171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
A
DESCRIPTION
The VDRM series of the MagI³C Power Modules
Family comprises a fully integrated current mode
DC/DC power supply with the switching power
stage, control circuitry and passives all in one
package. These devices also have a built-in
compensation circuitry and soft-start feature for a
smooth, safe power up. The small QFN package is
easy to solder onto a printed circuit board where a
low profile is demand. The MagI³C Power Module
requires as few as five external components and
eliminates loop compensation and magnetics part
selection process.
41
NF
BQ
B
FEATURES
The VDRM series offers high efficiency and delivers
up to 2.5A of output current with accurate regulated
output voltages. It operates from input voltage 7V to
50V.
The VDRM regulators also have on-board protection
circuitry to avoid thermal and electrical damage. The
MagI³C Power Module offers flexibility and the
feature of a discrete point-of-load design. This is
ideal for powering a wide area of systems and ICs.
C
Peak efficiency up to 96%
Current capability up to 2.5A
Wide input voltage range: 7V-50V
Regulated output voltages: 2.5V-15V
65V Line Transient Protection
Switching frequency range: 400kHz-1MHz
adjustable
External clock synchronisation
Built-in soft-start and tracking
Power Good signal and pre-bias output
Under voltage lockout protection (UVLO)
Voltage overshoot and over-current
protection
Over temperature and current protection
Operating ambient temperature: -40-85°C
EN55022 Class B compliant
APPLICATIONS
D
01P
Point of Load DC-DC applications
Servers, Data and Telecom
System power supplies
DSPs, FPGAs, MCUs and MPUs
I/O interface
TYPICAL APPLICATION CIRCUIT
VIN
VIN
VOUT
Module
RUVLO1
DL/UVLO
CIN
VOUT
RSET
VADJ
RUVLO2
COUT
RT/CLK
PG
SS/TRK SSCHO AGND PGND
VOUT(V)
3.3
RSET(kΩ) 31.6
RRT(kΩ)
OPEN
RUVLO1(kΩ) 174
RUVLO2(kΩ) 40.2
CIN(µF)min 4.7
COUT(µF)min 2x47
VIN(V)
7
to 36
fSW(kHz)
400
5.0
52.3
1100
174
31.6
2x2.2
2x47
8
to 50
500
12
140
267
174
15.4
2x2.2
2x47
15
to 50
800
01S
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
1/ 32
171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
19 PGND
20 PGND
21 PH
22 PH
23 PH
24 PH
25 DNC
26 VIN
27 DL/UVLO
28 SS/TRK
PACKAGE MARKING
29 SSCHO
E
DU125150
AGND 30
PGND
40
PH
41
RT/CLK 31
AGND 32
12X
ABCD X1
16 PGND
Second row: Logo & Code
Third row: Product code
13 VOUT
12 VOUT
VOUT 11
VOUT 10
GND_PT 8
PH 7
PH 6
AGND 5
AGND 4
DNC 3
AGND 1
VADJ 36
DNC 2
PH
38
PG 35
First row: Product number
14 VOUT
VOUT
39
GND_PT 9
AGND 34
17 PGND
15 VOUT
AGND
37
AGND 33
18 PGND
02P
Top View BQFN-41
F
PIN DESCRIPTION
PIN #
PIN
SYMBOL
26
10, 11,
12, 13,
14, 15,
39
1, 4, 5,
30, 32,
33, 34,
37
16, 17,
18, 19,
20, 40
VIN
PIN DESCRIPTION
1I Input power supply
VOUT
2I Output power supply
AGND
3I These pins are connected to the internal analog ground of the device.
PGND
4I This is the return current path for the power stage of the device.
8, 9
GND_PT
35
36
PG
VADJ
31
RT/CLK
27
28
29
6, 7,
21, 22,
23, 24,
38, 41
2, 3, 25
DL/UVLO
SS/TRK
SSCHO
PH
DNC
5I Ground point. Connect AGND to PGND at these pins as shown in the Layout
Considerations.
6I Power Good flag pin.
7I Sets the output voltage
8I These pin set the internal frequency over a resistor and can also use to synchronize to an
external clock.
9I Deadlock and UVLO adjust pin.
10I Soft-start or tracking pin.
11I Soft-start and track feature select.
12I Phase switch node.
Do Not Connect.
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
2/ 32
171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
G
ORDERING INFORMATION
ORDER CODE
PART DESCRIPTION
PACKAGE
PACKING UNIT
171021501
178021501
WPMDU1251501NT
WPMDU1251501NEV
BQFN-41
box
Tape and Reel with 250 Units
1
H
SALES INFORMATION
SALES CONTACTS
Würth Elektronik eiSos GmbH & Co. KG
EMC & Inductive Solutions
Max-Eyth-Str. 1
74638 Waldenburg
Germany
Tel. +49 (0) 79 42 945 - 0
www.we-online.com
powermodules@we-online.de
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
3/ 32
171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
I
ABSOLUTE MAXIMUM RATINGS
(1)
Preventive Caution: Exceeding the listed absolute maximum ratings below may affect the device negatively and may cause permanent damage. Therefore operating ratings are
conditions under which operation of the device is intended to be functional. All values are referenced to AGND. -40°C ≤ TA ≤ +85°C, VIN = 24 V, VOUT = 5.0 V, IOUT = 2.5 A, RT =
Open, CIN = 2 x 2.2 μF ceramic, COUT = 2 x 47 μF ceramic, unless otherwise specified.
SYMBOL
PARAMETER
VIN
DL/UVLO
VADJ
PG
SS/TRK
SSCHO
RT/CLK
PH
VOUT
VDIFF
RT/CLK
DL/UVLO
SS/TRK
PG
TJ
TST
TSOLR
Input voltage VIN
Under voltage lockout
Adjustable output voltage
Power Good
Soft Start/Tracking
Soft Start + Tracking Feature
Timer/ Clock
Phase switching node
Output voltage VOUT
GND to exposed thermal pad
Source current
Source current
Sink current
Sink current
Junction temperature
Storage temperature
(13)
Soldering temperature reflow, leads max. 30s
J
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VIN
VOUT
fSW
TA
K
LIMITS
UNIT
-0.3 to 65
-0.3 to 5
-0.3 to 3
-0.3 to 6
-0.3 to 3
-0.3 to 3
-0.3 to 3.6
-0.6 to 65
-0.6 to VIN
±200
100
100
200
10
(2)
-40 to 105
-65 to 150
245
V
V
V
V
V
V
V
V
V
mV
µA
µA
µA
mA
°C
°C
°C
(1)
PARAMETER
MIN
Input voltage
Output voltage
Switching Frequency
Ambient operating temperature
(6)
7
2.5
400
-40
TYP
(7)
-
MAX
(6)
50
15
1000
85
UNIT
V
V
kHz
°C
THERMAL SPECIFICATIONS
SYMBOL
θJA
ψJT
ψJB
TSD-HYST
TSD
PARAMETER
Thermal resistance junction to ambient
(4)
Thermal resistance junction to top
(5)
Thermal resistance junction to board
Thermal shut down hysteresis, falling
Thermal shut down
(3)
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
VALUE
UNIT
14
3.3
6.8
15
180
°C/W
°C/W
°C/W
°C
°C
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171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
L
ELECTRICAL SPECIFICATIONS
Preventive Caution: Exceeding the listed absolute maximum ratings below may affect the device negatively and may cause perman ent damage. Therefore operating
ratings are conditions under which operation of the device is intended to be functional. All values are referenced to AGND. -40°C ≤ TA ≤ +85°C, VIN = 24 V, VOUT = 5.0 V,
IOUT = 2.5 A, RT = Open, CIN = 2 x 2.2 μF ceramic, COUT = 2 x 47 μF ceramic, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
Specifications regarding input voltage pin VIN
Over output current
Input voltage range
VIN
range
Specifications regarding output voltage pin VOUT
VIN under voltage
No hysteresis, rising and
VUVLO
lockout
falling
Output voltage range
VOUT(adj)
Regulated output voltage
Over output current
Output current
IOUT
range
Set-point voltage
TA = 25°C; IOUT = 100mA
tolerance
Temperature variation
-40°C ≤ TA ≤ +85°C
Line regulation
Over input voltage range
VOUT
Over output current
Load regulation
range
Includes set-point, line,
Total output voltage
load, and temperature
variation
variation
20 MHz bandwidth,
Output voltage ripple
VPP%
0.25A ≤ IOUT ≤ 2.5A,
VOUT ≥3.3V
Current limit threshold
ILIM
Specifications regarding performance
VIN = 24 V, IOUT = 1.5 A,
VOUT = 5 V,
fSW = 500 kHz
Efficiency
ɳ
VIN = 48V IOUT = 1.5A,
VOUT = 5 V,
fSW = 500 kHz
System specifications
Transient response
1A/µs load step from 50
TTR
Recovery time
to 100%,
Transient response VOUT
1A/µs load step from 50
VTR
over/undershooter
to 100%,
Switching Frequency
fSW
RT/CLK pin open
Synchronization
fCLK
CLK Control
frequency
Duty cycle CLK
DCLK
CLK Control
High-Level Threshold
VCLK-H
CLK Control
CLK
Low-Level Threshold
VCLK-L
CLK Control
CLK
Specifications regarding Enable pin DL
Deadlock threshold
VDL
No hysteresis
current
VDL < 1.15 V
Deadlock Input current
IDL
VDL > 1.36 V
Shut Down current
ISD
VDL = 0 V
MIN
7
(6)
TYP
(8)
-
(7)
-
MAX
50
(6)
(9)
UNIT
V
2.5
-
V
-
15
V
0
-
2.5
A
-
-
-
±0.5
±0.1
±1.0
-
%
%
-
±0.4
-
%
-
-
±3.0
-
1
-
%
-
5.1
-
A
-
84
-
%
-
79
-
%
-
400
-
µs
-
90
-
mV
300
400
500
kHz
1000
kHz
2.5
(10)
300
±2.0
(11)
(11)
%
%
25
50
75
%
-
1.9
2.2
V
0.5
0.7
-
V
1.15
1.25
1.36
-
-0.9
-3.8
1.3
4
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
(12)
V
µA
µA
µA
5/ 32
171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
Preventive Caution: Exceeding the listed absolute maximum ratings below may affect the device negatively and may cause perman ent damage. Therefore operating
ratings are conditions under which operation of the device is intended to be functional. All values are referenced to AGND. -40°C ≤ TA ≤ +85°C, VIN = 24 V, VOUT = 5.0 V,
IOUT = 2.5 A, RT = Open, CIN = 2 x 2.2 μF ceramic, COUT = 2 x 47 μF ceramic, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
(6)
TYP
(7)
MAX
(6)
UNIT
Specifications regarding Power Good pin PG
VOUT rising
Power Good Thresholds
PG
VOUT falling
Power Good Low Voltage
I(PG) = 3.5mA
-
94
109
fault 91
good 106
0.2
good
fault
-
%
%
%
%
V
NOTES
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
(2)
See the temperature derating curves in the Typical Characteristics section for thermal information.
(3)
The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided, 4-layer PCB with 35µm. copper and
natural convection cooling. Additional airflow reduces θJA.
(4)
The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A
(sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device.
(5)
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD512A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device.
(6)
Min and Max limits are 100 % production tested at 25 °C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality
Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(7)
Typical numbers are at 25 °C and represent the most likely parametric norm.
(8)
For output voltages ≤ 12 V, the minimum input voltage is 7 V or (VOUT+ 3 V), whichever is greater. For output voltages > 12 V, the minimum input voltage is (1.33 x
VOUT).
(9)
The maximum input voltage is 50 V or (15 x V OUT), whichever is less.
(10)
Output voltages < 3.3 V are subject to reduced VIN(max) specifications and higher ripple magnitudes.
(11)
The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output
voltage tolerance is affected by the tolerance of the external R SET resistor.
(12)
Value when no voltage divider is present at the DL/UVLO pin.
(13)
JEDEC J-STD020
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
6/ 32
171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
M
TYPICAL PERFORMANCE CURVES
The electrical characteristic data has been developed from actual products tested at 25 °C. This data is considered typical for the converter. At light load the output voltage
ripple may increase due to pulse skipping. See Light-Load Behavior for more information. The temperature derating curves represent the conditions at which internal
components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB
with 35 mm copper.
Efficiency: VIN = 12V @ TAMB = 25°C
Power Loss: VIN = 12V @ TAMB = 25°C
6
100
VOUT = 5.0V, fSW =500 kHz
VOUT = 3.3V, fSW =400 kHz
VOUT = 2.5V, fSW =400 kHz
95
5
Power Loss [W]
Efficiency [%]
90
85
80
75
70
65
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
VOUT = 2.5V, fSW = 400 kHz
60
4
3
2
1
55
50
0
0
0.5
1.0
1.5
2.0
2.5
0
Output Current [A]
0.5
1.0
1.5
2.0
01D
05D
Efficiency: VIN = 24V @ TAMB = 25°C
Power Loss: VIN = 24V @ TAMB = 25°C
6
100
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
VOUT = 2.5V, fSW = 400 kHz
95
5
Power Loss [W]
Efficiency [%]
90
85
80
75
70
65
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
VOUT = 2.5V, fSW = 400 kHz
60
55
50
4
3
2
1
0
0
0.5
1.0
1.5
2.0
2.5
0
Output Current [A]
0.5
1.0
1.5
2.0
06D
Efficiency: VIN = 36V @ TAMB = 25°C
Power Loss: VIN = 36V @ TAMB = 25°C
6
100
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
VOUT = 2.5V, fSW = 400 kHz
95
5
Power Loss [W]
Efficiency [%]
90
85
80
75
70
65
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
VOUT = 2.5V, fSW = 400 kHz
60
55
2.5
Output Current [A]
02D
50
2.5
Output Current [A]
4
3
2
1
0
0
0.5
1.0
1.5
2.0
2.5
0
Output Current [A]
0.5
1.0
1.5
2.0
2.5
Output Current [A]
03D
07D
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
7/ 32
171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
TYPICAL PERFORMANCE CURVES
The electrical characteristic data has been developed from actual products tested at 25 °C. This data is considered typical for the converter. At light load the output voltage
ripple may increase due to pulse skipping. See Light-Load Behavior for more information. The temperature derating curves represent the conditions at which internal
components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB
with 35 mm copper.
Power Loss: VIN = 48V @ TAMB = 25°C
Efficiency: VIN = 48V @ TAMB = 25°C
6
100
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
95
5
Power Loss [W]
Efficiency [%]
90
85
80
75
70
65
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
60
55
50
4
3
2
1
0
0
1.0
0.5
1.5
2.0
0
2.5
0.5
1.0
1.5
2.0
04D
08D
Thermal Derating: VIN = 12V;
VOUT = all voltages
90
70
Ambient Temperature [°C]
Output Voltage Ripple [mV]
Output Voltage Ripple: VIN = 12V
@ TAMB = 25°C
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
VOUT = 2.5V, fSW = 400 kHz
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
80
70
60
50
40
30
Natural Convection
20
2.5
0
Output Current [A]
0.5
1.0
1.5
2.0
2.5
Output Current [A]
09D
11D
Output Voltage Ripple: VIN = 24V
@ TAMB = 25°C
Thermal Derating: VIN = 24V;
VOUT = all voltages
70
90
Ambient Temperature [°C]
Output Voltage Ripple [mV]
2.5
Output Current [A]
Output Current [A]
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
VOUT = 2.5V, fSW = 400 kHz
60
50
40
30
20
10
0
80
70
60
50
40
30
Natural Convection
20
0
0.5
1.0
1.5
2.0
2.5
0
Output Current [A]
0.5
1.0
1.5
2.0
2.5
Output Current [A]
10D
12D
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
8/ 32
171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
TYPICAL PERFORMANCE CURVES
The electrical characteristic data has been developed from actual products tested at 25 °C. This data is considered typical for the converter. At light load the output voltage
ripple may increase due to pulse skipping. See Light-Load Behavior for more information. The temperature derating curves represent the conditions at which internal
components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB
with 35 mm copper.
Thermal Derating: VIN = 36V;
VOUT = all voltages
90
70
Ambient Temperature [°C]
Output Voltage Ripple [mV]
Output Voltage Ripple: VIN = 36V
@ TAMB = 25°C
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
VOUT = 2.5V, fSW = 400 kHz
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
80
70
60
50
40
30
Natural Convection
20
2.5
0
Output Current [A]
0.5
1.0
1.5
2.0
Output Current [A]
13D
15D
Thermal Derating: VIN = 48V;
VOUT = all voltages
Output Voltage Ripple: VIN = 48V
@ TAMB = 25°C
90
70
Ambient Temperature [°C]
Output Voltage Ripple [mV]
2.5
VOUT = 15V, fSW = 1000 kHz
VOUT = 12V, fSW = 800 kHz
VOUT = 5.0V, fSW = 500 kHz
VOUT = 3.3V, fSW = 400 kHz
60
50
40
30
20
10
80
70
60
50
40
30
Natural Convection
20
0
0
0.5
1.0
1.5
2.0
0
2.5
0.5
1.0
1.5
2.0
2.5
Output Current [A]
Output Current [A]
14D
16D
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
9/ 32
171021501/WPMDU1251501NT
MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
TYPICAL PERFORMANCE CURVES
The electrical characteristic data has been developed from actual products tested at 25 °C. This data is considered typical for the converter. At light load the output voltage
ripple may increase due to pulse skipping. See Light-Load Behavior for more information. The temperature derating curves represent the conditions at which internal
components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB
with 35 mm copper.
40
120
30
90
30
90
20
60
10
30
0
0
-30
-10
Gain [dB]
120
Gain
Phase
-40
1
10
100
0
0
-10
-30
-60
-90
-30
-120
-40
Gain
Phase
1
300
-90
-120
10
100
300
Frequency [kHz]
Frequency [kHz]
18D
17D
Bode diagram: VIN = 48V; VOUT = 5V;
IOUT = 2A; COUT1 = 44µF ceramic; COUT2 = 56µF
electrolytic, fSW = 500kHz
120
40
120
30
90
30
90
20
60
20
60
10
30
10
30
0
0
-10
-30
0
0
-10
-30
-20
Gain
Phase
-30
-40
1
10
100
Gain [dB]
40
Phase [°]
Gain [dB]
Bode diagram: VIN = 36V; VOUT = 5V;
IOUT = 2A; COUT1 = 44µF ceramic; COUT2 = 56µF
electrolytic, fSW = 500kHz
-60
-20
-90
-30
-120
-40
-60
Gain
Phase
-90
-120
1
300
Phase [°]
-30
60
30
-20
-60
-20
20
10
Phase [°]
Bode diagram: VIN = 24V; VOUT = 5V;
IOUT = 2A; COUT1 = 44µF ceramic; COUT2 = 56µF
electrolytic, fSW = 500kHz
40
Phase [°]
Gain [dB]
Bode diagram: VIN = 12V; VOUT = 5V;
IOUT = 2A; COUT1 = 44µF ceramic; COUT2 = 56µF
electrolytic, fSW = 500kHz
10
100
300
Frequency [kHz]
Frequency [kHz]
20D
19D
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TYPICAL PERFORMANCE CURVES
The electrical characteristic data has been developed from actual products tested at 25 °C. This data is considered typical for the converter. At light load the output voltage
ripple may increase due to pulse skipping. See Light-Load Behavior for more information. The temperature derating curves represent the conditions at which internal
components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB
with 35 mm copper.
Deadlock shut-down IOUT = 2A
Deadlock start-up IOUT = 2A
VDL
5V/Div
5V/Div
VDL
VSS
1V/Div
VOUT
2V/Div
1V/Div
VSS
2V/Div
VOUT
100µs/Div
2ms/Div
22D
21D
Radiated Emissions EN55022 compliant:
VIN = 24V;VOUT = 5V Load = 2A
Radiated Emissions (dBV/m)
Startup VIN = 10V; IOUT = 2A
10V/Div
VIN
2V/Div
VOUT
5V/Div
VPG
2 ms/Div
100
EN 55022 Class A
EN 55022 Class B
EMI Vertical
EMI Horizontal
90
80
70
60
50
40
30
20
10
0
100
30
23D
1000
Freqency (MHz)
24D
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N
CIRCUIT DESCRIPTION
N1
MagI³C 6 Steps to design the power application
The next 6 simple steps will show how to select the external components to design your power application:
1.
2.
3.
4.
5.
6.
Program output voltage
Program under voltage lockout divider
Set operating frequency
Select Input Capacitor
Select Output Capacitor
Layout considerations
The Typical Basic Schematic below shows a MagI³C Power Module schematic with the key parameter-setting
resistors labeled.
VIN
VIN
VOUT
Module
RUVLO1
DL/UVLO
2.
CIN
VOUT
6.
RSET
1.
VADJ
RUVLO2
COUT
RT/CLK
4.
PG
5.
RRT
SS/TRK SSCHO AGND PGND
3.
02S
Figure 1. Typical Basic Schematic
Step 1. Program output voltage (RSET)
The MagI³C Power Module is designed to provide output voltages from 2.5 V to 15 V. The output voltage is
determined by the value of RSET, which must be connected between the VOUT node and the VADJ pin (Pin 36). For
output voltages higher than 5 V, improved operating performance can be obtained by increasing the operating
frequency. This adjustment requires the addition of RRT between RT/CLK (Pin 31) and AGND (Pin 30). See the
Step 3 Set operating frequency section for more details. Table 1 gives the standard external RSET resistor for a
number of common bus voltages and also includes the recommended R RT resistor for output voltages above 5 V.
Table 1: Recommended standard output voltages
VOUT
RSET
RRT
fSW
2.5V
21.5kΩ
Open
400kHz
3.3V
31.6kΩ
Open
400kHz
5V
52.3kΩ
1.1MΩ
500kHz
9V
102kΩ
365kΩ
700kHz
12V
140kΩ
267kΩ
800kHz
15V
178kΩ
178kΩ
1000kHz
For other output voltages the value of RSET can be calculated using the following formula.
(
)
(1)
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Step 2. Program under voltage lockout divider (RUVLO1 and RUVLO2)
At turn-on, the VON UVLO threshold determines the input voltage level where the device begins power conversion.
During the power-down sequence, the VOFF UVLO threshold determines the input voltage where power conversion
ceases. The turn-on and turn-off thresholds are set by two resistors, RUVLO1 and RUVLO2 as shown in Figure 2. The
VON UVLO threshold must be set to at least (VOUT + 3 V) or 6.5 V whichever is higher to insure proper startup and
reduce current surges on the host input supply as the voltage rises. If possible, it is recommended to set the UVLO
threshold to approximately 80 to 85% of the minimum expected input voltage.
Use Equation 2 and Equation 3 to calculate the values of RUVLO1 and RUVLO2. VON is the voltage threshold during
power-up when the input voltage is rising. VOFF is the voltage threshold during power-down when the input voltage is
decreasing. VOFF should be selected to be at least 500 mV less than VON. Table 2 lists standard resistor values for
RUVLO1 and RUVLO2 for adjusting the VON UVLO threshold for several input voltages.
(
(
(
VIN
)
(2)
)
)
(3)
VIN
RUVLO1
DL/UVLO
RUVLO2
SSCHO
AGND
03S
Figure 2. Under voltage Lockout (UVLO) Schematic
Table 2: Standard VON Threshold Values
VON Threshold
RUVLO1
RUVLO2
6.5V
40.2kΩ
10V
24.3kΩ
15V
15.8kΩ
20V
11.5kΩ
25V
9.09kΩ
174kΩ
30V
7.5kΩ
35V
6.34kΩ
40V
5.62kΩ
45V
4.99kΩ
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Step 3. Set operating frequency
Nominal switching frequency of the MagI³C Power Module is set from the factory at 400 kHz. This switching
frequency is optimized for output voltages below 5 V. For output voltages of 5 V and above, better operating
performance can be obtained raising the operating frequency. This is easily done by adding a resistor, R RT in , from
the RT/CLK pin (Pin 31) to the AGND pin (Pin 30). Raising the operating frequency reduces output voltage ripple,
lowers the load current threshold where pulse skipping begins, and improves transient response. The recommended
switching frequency for typical output voltages is listed in Table 1.
For the maximum recommended output voltage value of 15 V, the switching frequency computes to 1 MHz. Operation
above 1 MHz is not recommended. Use Table 3 below to select the value of the timing resistor for the given values of
switching frequencies.
VOUT
2.5V
Table 3: Standard Switching Frequencies
fSW
RRT
400kHz
Open
3.3V
400kHz
Open
5V
500kHz
1,1MΩ
9V
700kHz
365kΩ
12V
800kHz
267kΩ
15V
1MHz
178kΩ
It is also possible to synchronize the switching frequency to an external clock signal. See the Step E Synchronization
CLK option section for further details. While it is possible to set the operating frequency higher than 400 kHz when
using the device at output voltages of 5 V or less, minimum duty cycle and pulse skipping issues restrict the
maximum recommended input voltage under these conditions. The recommended operating conditions for the
MagI³C Power Module can be summarized by Figure 3. The graph shows the maximum input voltage vs. output
voltage restriction for several operating frequencies. The lower boundary of the graph shows the minimum input
voltage as a function of the output voltage.
60
Input Voltage [V]
50
fSW = 400kHz
fSW = 600kHz
fSW = 800kHz
fSW = 1MHz
VIN (min)
Recommended
Operating Area
40
30
20
10
0
2.5
5
7.5
10
12.5
15
Output Voltage [V]
26D
Figure 3. Input Voltage vs. Output Voltage Operating Area
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Step 4. Select Input Capacitor (CIN)
The MagI³C Power Module requires a minimum input capacitance of 4.4 μF of ceramic type. The voltage rating of
input capacitors must be higher than the maximum input voltage. The ripple current rating of the capacitor must be at
least 450 mArms. Table 4 includes a preferred list of capacitors.
(1)
Table 4: Recommended input and output capacitors :
Series
Description
X5R
4.7µF; 50V; ±10%
X5R
22µF; 16V; ±10%
X5R
47µF; 6.3V; ±20%
POSCAP
68µF; 16V; POSCAP
POSCAP
100µF; 6.3V;
T530
220µF; 6.3V;
(2)
Case Size
1206
1210
1210
ESR
2
2
2
50
25
6
mΩ
(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status,
and manufacturing process requirements for any capacitors identified in this table.
(2) Maximum ESR @ 100 kHz, 25°C.
Step 5. Select Output Capacitor (COUT)
The output capacitance of the MagI³C Power Module can be comprised of either all ceramic capacitors, or a
combination of ceramic and bulk capacitors. The required output capacitance must include at least 100 μF of ceramic
type (or 2 x 47 μF). When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones
recommended in Table 4 are required. Additional capacitance above the minimum is determined by actual transient
deviation requirements. Table 4 includes a preferred list of capacitors.
Step 6. Layout considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 4 and Figure 5
show two layers of a typical PCB layout. Some considerations for an optimized layout are:
1. Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
2. Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.
3. Locate additional output capacitors between the ceramic capacitor and the load.
4. Place a dedicated AGND copper area beneath the MagI³C Power Module.
5. Isolate the PH copper area from the VOUT copper area using the PGND copper area.
6. Connect the AGND and PGND copper area at one point; at pins 8 & 9.
7. Place RSET, RRT, and CSS as close as possible to their respective pins.
8. Use multiple vias to connect the power planes to internal layers.
9. Use a dedicated sense line to connect RSET to VOUT near the load for best regulation.
AGND to PGND
Connection
RSET
VOUT sense
Via
PH
Thermal
Vias
COUT1
CIN1
COUT2
PGND
Plane
VOUT
PGND
VIN
AGND
LOAD
VOUT sense
Via
04P
03P
Figure 4. Layout top layer
Figure 5. Layout bottom layer
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N2
MagI³C optional Features:
The MagI³C Power Module can operate over a wide input voltage range of 7 V to 50 V and produce output
voltages from 2.5 V to 15 V. The performance of the device varies over this wide operating range. There are
some important considerations when operated near the boundary limits. This section offers guidance in selecting
the optimum components depending on the application and operating conditions.
A
B
C
D
Select soft-start capacitor
Output On/Off Deadlock
Synchronization CLK option
Power Good
VIN
VIN
VOUT
Module
RUVLO1
DL/UVLO
VADJ
COUT2
RT/CLK
B.
RSET
1kΩ
RUVLO2
CIN
PG
D.
Q1
DL
Control
VOUT
470pF
C.
RRT
SS/TRK SSCHO AGND PGND
A.
CSS
11S
Figure 6. Schematic for optional functions
Step A. Select soft-start capacitor (CSS)
For output voltages of 5 V or less, the slow start capacitance built into the MagI³C Power Module is sufficient for a
turn-on ramp rate that does not induce large surge currents while charging the output capacitors. Connecting the
SSCHO pin (Pin 29) to AGND while leaving SS pin (Pin 28) open enables the internal SS capacitor with a slow
start interval of approximately 5ms. For output voltages higher than 5 V, additional a slow start capacitance is
recommended. For 12 V to 15 V output voltages, a 22 nF capacitor should be connected between the SS/TRK pin
(Pin 28) and AGND, while connecting the SSCHO pin (Pin 29) to AGND as well. Figure 7 shows an additional SS
capacitor connected to the SS pin and the SSCHO pin connected to AGND. See Table 5 below for SS capacitor
values and timing interval.
SS/TRK
CSS opt
SSCHO
AGND
04S
Figure 7. Soft-Start Capacitor Css and SSCHO connection
Table 5: Recommended Soft-Start Capacitors for typical Start times
Soft Start Time
Capacitor CSS
5msec
Open
7msec
4.7nF
10msec
10nF
13msec
15nF
17msec
22nF
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Step B. Output On/Off Deadlock (DL)
The DL pin provides electrical on/off control of the device. Once the DL pin voltage exceeds the threshold voltage,
the device starts operation. If the DL pin voltage is pulled below the threshold voltage, the regulator stops
switching and enters low quiescent current state.
The DL pin has an internal pull-up current source, allowing the user to float the DL pin for enabling the device. If
an application requires controlling the DL pin, use an open drain/collector device, or a suitable logic gate to
interface with the pin.
Figure 8 shows the typical application of the deadlock function. The deadlock control has its own internal pull-up
to VIN potential. An open-collector or open-drain device is recommended to control this input.
Turning Q1 on applies a low voltage to the deadlock control (DL) pin and disables the output of the supply, shown
in Figure 10. If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in Figure 9. A
regulated output voltage is produced within 5 ms.
VIN
VIN
RUVLO1
DL/UVLO
Q1
RUVLO2
DL
Control
SSCHO
AGND
05S
Figure 8. Typical Deadlock Control
5V/Div
VDL
1V/Div
VSS
2V/Div
VOUT
VDL
5V/Div
1V/Div
VSS
VOUT
2V/Div
100µs/Div
2ms/Div
22D
21D
Figure 9. Deadlock start-up IOUT = 2A
Figure 10. Deadlock shut-down IOUT = 2A
Step C. Synchronization CLK option
An internal phase locked loop (PLL) allows synchronization between 300 kHz and 1 MHz, and to easily switch
from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to
the RT/CLK pin with a duty cycle between 20 % to 80 %. The clock signal amplitude must transition lower than
0.8 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In
applications where both RT mode and CLK mode are needed, the device can be configured as shown in
Figure 11.
Before the external clock is present, the device works in RT mode where the switching frequency is set by the R RT
resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is
pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not
recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to
100 kHz first before returning to the switching frequency set by the R RT resistor.
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470pF
1 kΩ
RT/CLK
External Clock
300kHz to 1MHz
RRT
SSCHO
AGND
06S
Figure 11. Synchronization Configuration
Step D. Power Good (PG)
The PG pin is an open drain output. Once the output voltage is between 94 % and 106 % of the set voltage, the
PG pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 kΩ and
100 kΩ to a voltage source that is 5.5 V or less. The PG pin is in a defined state once VIN is higher than 1.0 V, but
with reduced current sinking capability. The PG pin achieves full current sinking capability once the V IN pin is
above 4.5 V. The PG pin is pulled low when the output voltage is lower than 91 % or higher than 109 % of the
nominal set voltage. Also, the PG pin is pulled low if the input UVLO or thermal shutdown is asserted, the DL pin
is pulled low, or the SS/TRK pin is below 1.4 V.
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N3
MagI³C inherent Characteristics:
The MagI³C Power Module can operate over a wide input voltage range of 7 V to 50 V and produce output
voltages from 2.5 V to 15 V. The performance of the device varies over this wide operating range. There are
some important considerations when operated near the boundary limits. This section offers guidance in selecting
the optimum components depending on the application and operating conditions.
E
F
G
H
Input voltage
Power up characteristic
Light load behaviour
EMI
VIN
VIN
E.
VOUT
Module
G.
RUVLO1
DL/UVLO
RSET
VADJ
1kΩ
RUVLO2
CIN
H.
COUT2
RT/CLK
Q1
DL
Control
470pF
RRT
VOUT
PG
C.
SS/TRK SSCHO AGND PGND
CSS
11S
Figure 12. Schematic for inherent Characteristics
Step E. Input Voltage (VIN)
The MagI³C Power Module operates over the input voltage range of 7 V to 50 V. For reliable start-up and
operation at light loads, the minimum input voltage depends on the output voltage. For output voltages ≤ 12 V,
the minimum input voltage is 7 V or (VOUT + 3 V), whichever is higher. For output voltages > 12 V, the minimum
input voltage is (1.33 x VOUT).
The maximum input voltage is (15 x V OUT) or 50 V, whichever is less. While the device can safely handle input
surge voltages up to 65 V, sustained operation at input voltages above 50 V is not recommended. See the Step 2.
Under voltage Lockout (UVLO) Threshold section of this datasheet for more information.
Step F. Power-Up Characteristics
When configured as shown in the typical application on the front page, the MagI³C Power Module produces a
regulated output voltage following the application of a valid input voltage. During the power-up, internal soft-start
circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be
drawn from the input source. The soft-start circuitry introduces a short time delay from the point that a valid input
voltage is recognized. Figure 13 shows the start-up waveforms for a MagI³C Power Module, operating from a
24 V input and the output voltage adjusted to 5 V.
10V/Div
VIN
2V/Div
VOUT
5V/Div
VPG
2 ms/Div
23D
Figure 13. Startup VIN=10V; IOUT=2A
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Step G. Light load behaviour
The MagI³C Power Module is a non-synchronous converter. One of the characteristics of a non-synchronous
converter is that as the load current on the output is decreased, a point is reached where the energy delivered by
a single switching pulse is more than the load can absorb. This causes the output voltage to rise slightly. This rise
in output voltage is sensed by the feedback loop and the device responds by skipping one or more switching
cycles until the output voltages falls back to the set point. At very light loads or no load, many switching cycles are
skipped. The observed effect during this pulse skipping mode of operation is an increase in the peak to peak
ripple voltage, and a decrease in the ripple frequency. The load current at which pulse skipping begins is a
function of the input voltage, the output voltage, and the switching frequency. A plot of the pulse skipping
threshold current as a function of input voltage is given in Figure 14 for a number of popular output voltage and
switching frequency combinations.
900
2.5V/400kHz
3.3V/400kHz
5.0V/400kHz
9V/600kHz
12V/800kHz
15V/1MHz
Output Current (mA)
800
700
600
500
400
300
200
100
0
10
15
20
25
30
35
40
45
50
Input Voltage (V)
27D
Figure 14. Pulse Skipping Load Threshold
Radiated Emissions (dBV/m)
Step H. Electromagnetic Interference
100
EN 55022 Class A
EN 55022 Class B
EMI Vertical
EMI Horizontal
90
80
70
60
50
40
30
20
10
0
30
100
1000
Freqency (MHz)
24D
Figure 15. Radiated Emissions EN55022 complaint: VIN = 24V; VOUT = 5V ; Load 2A
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O
BLOCK DIAGRAM
Power Module
AGND
PGND
VOUT
OSC
w/PLL
Controller/
Power
Control
RT/CLK
SSCHO
VREF
Comp
+
+
-
SS/TR
PH
VIN
DL/UVLO
VIN
UVLO
OCP
Shutdown
Logic
VADJ
PG
Logic
PG
Thermal
Shutdown
10S
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PH
41
AGND 30
19 PGND
20 PGND
21 PH
22 PH
23 PH
24 PH
25 DNC
26 VIN
27 DL/UVLO
28 SS/TRK
29 SSCHO
PIN CONFIGURATION
PGND
40
RT/CLK 31
18 PGND
17 PGND
16 PGND
AGND 32
AGND 33
15 VOUT
AGND
37
AGND 34
PG 35
14 VOUT
VOUT
39
PH
38
13 VOUT
12 VOUT
VOUT 11
VOUT 10
GND_PT 9
GND_PT 8
PH 7
PH 6
AGND 5
AGND 4
DNC 3
DNC 2
VADJ 36
AGND 1
P
05P
Bottom view mirrored BQFN 41 (page 22 detail PIN description)
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Q
DETAILED PIN DESCRIPTION
PIN #
PIN
SYMBOL
PIN DESCRIPTION
26
VIN
1I Input voltage. This pin supplies all power to the converter. Connect this pin to the input
supply and connect bypass capacitors between this pin and PGND.
10, 11,
12, 13,
14, 15,
39
VOUT
2I Output voltage. These pins are connected to the internal output inductor. Connect these pins
to the output load and connect external bypass capacitors between these pins and PGND.
Connect a resistor from these pins to VADJ to set the output voltage.
3I These pins are connected to the internal analog ground (AGND) of the device. This node
should be treated as the zero volt ground reference for the analog control circuitry. Pad 37
should be connected to PCB ground planes using multiple vias for good thermal performance.
Not all pins are connected together internally. All pins must be connected together externally
with a copper plane or pour directly under the module. Connect AGND to PGND at a single
point (GND_PT; pins 8 & 9). See Layout Recommendations.
4I This is the return current path for the power stage of the device. Connect these pins to the
load and to the bypass capacitors associated with VIN and VOUT. Pad 40 should be
connected to PCB ground planes using multiple vias for good thermal performance.
5I Ground Point. Connect AGND to PGND at these pins as shown in the Step 6. Layout
Considerations. These pins GND_PT are not connected to internal circuitry, and are not
connected to one another.
6I Power Good flag pin. This open drain output asserts low if the output voltage is more than
approximately ±6% out of regulation. A pull-up resistor is required.
7I Connecting a resistor between this pin and VOUT sets the output voltage.
8I This pin is connected to an internal frequency setting resistor which sets the default
switching frequency. An external resistor can be connected from this pin to AGND to increase
the frequency. This pin can also be used to synchronize to an external clock.
9I Deadlock and UVLO adjust pin. Use an open drain or open collector logic device to ground
this pin to control the INH function. A resistor divider between this pin, AGND, and VIN sets the
UVLO voltage.
10I Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output
voltage rise time. A voltage applied to this pin allows for tracking and sequencing control.
11I Slow-start or track feature select. Connect this pin to AGND to enable the internal SS
capacitor. Leave this pin open to enable the TR feature.
1, 4, 5,
30, 32,
33, 34,
37
AGND
16, 17,
18, 19,
20, 40
PGND
8, 9
GND_PT
35
PG
36
VADJ
31
RT/CLK
27
DL/UVLO
28
SS/TRK
29
SSCHO
6, 7,
21, 22,
23, 24,
38, 41
PH
12I Phase switch node. Do not place any external component on these pins or tie them to a pin
of another function.
2, 3, 25
DNC
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other
voltage. These pins are connected to internal circuitry. Each pin must be soldered to an
isolated pad.
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PROTECTIVE FEATURES
Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature
exceeds 180 °C typically. The device reinitiates the power up sequence when the junction temperature
drops below 165 °C typically.
Overcurrent Protection
For protection against load faults, the MagI³C Power Module incorporates cycle-by-cycle current limiting.
During an overcurrent condition the output current is limited and the output voltage is reduced, as
shown in Figure 15. As the output voltage drops more than 8% below the set point, the PG signal is
pulled low. If the output voltage drops more than 25%, the switching frequency is reduced to reduce
power dissipation within the device. When the overcurrent condition is removed, the output voltage
returns to the established voltage. The MagI³C Power Module is not designed to endure a sustained
short circuit condition. The use of an output fuse, voltage supervisor circuit, or other overcurrent
protection circuit is recommended. A recommended overcurrent protection circuit is shown in
Figure 16. This circuit uses the PG signal as an indication of an overcurrent condition. As PG remains
low, the TLC555 timer operates as a low frequency oscillator, driving the DL/UVLO pin low for
approximately 400ms, halting the power conversion of the device. After the inhibit interval, the
DL/UVLO pin is released and the MagI³C Power Module restarts. If the overcurrent condition is removed,
the PG signal goes high, resetting the oscillator and power conversion resumes, otherwise the inhibit
cycle repeats.
5A/Div
IOUT
VOUT
2V/Div
VPWRGD
5V/Div
100µs/Div
28D
Figure 15. Overcurrent Limiting
3.3V/5V
475kΩ
VDD
DIS
CONT
47.5kΩ
To DL/UVLO
Pin 27
TLC555
THRS
BSS138
TRIG
3.3V/5V
OUT
1µF
100kΩ
100kΩ
RST
From PWRGD
Pin 35
GND
BSS138
07S
Figure 16. Over-Current Protection Circuit
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
PRELIMINARY
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VDRM - Variable Step Down Regulator Module
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APPLICATIONS
The MagI³C Power Module for high output voltage is easy-to-use DC-DC solutions capable of driving up to a 2.5A
load with exceptional power conversion efficiency, output voltage accuracy, line and load regulation. They are
available in an innovative package that enhances thermal performance. Following application circuits show
possible operating configurations.
S1
APPLICATION CIRCUIT
VIN
VIN
VOUT
Module
RUVLO1
RSET
DL/UVLO
CIN1
VADJ
RUVLO2
COUT1
RT/CLK
RRT
CIN2
VOUT
PG
CSS
COUT2
SS/TRK SSCHO AGND PGND
08S
S1a
Recommended Parameters for Design Example:
Recommended component values: TA = 25°C
VOUT
3.3V
5V
12V
VIN
7V to 36V
8V to 50V
15V to 50V
RSET
31.6kΩ
52.3kΩ
140kΩ
RUVLO1
174kΩ
174kΩ
174kΩ
RUVLO2
40.2kΩ
31.6kΩ
15.4kΩ
RRT
Open
1.1MΩ
267kΩ
CIN1 min
4.7µF; 50V
2.2µF; 100V
2.2µF; 100V
CIN2
Open
2.2µF; 100V
2.2µF; 100V
COUT1 min
47µF; 6.3V
47µF; 6.3V
47µF; 16V
COUT2
47µF; 6.3V
47µF; 6.3V
47µF; 16V
CSS
Open
Open
22nF
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
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VDRM - Variable Step Down Regulator Module
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PHYSICAL DIMENSIONS (mm)
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
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MagI³C Power Module Product Family
VDRM - Variable Step Down Regulator Module
recommended soldering pad
solder past recommendation 150 µm
Data Sheet
Würth Elektronik eiSos GmbH & Co. KG - REV 0.1
©2014
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VDRM - Variable Step Down Regulator Module
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Packaging
U1
Reel (mm)
20P
Data Sheet
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©2014
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VDRM - Variable Step Down Regulator Module
U2
Tape (mm)
21P
BQFN-41
±0,1
±0,1
±0,05
±0,1
±0,05
9,35
11,35
0,30
3,10
1,55
±0,10
Marking
Marking
Marking
Marking
Marking
Marking
22P
Data Sheet
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DOCUMENT HISTORY
DOCUMENT HISTORY
Revision
0.1
Date
15.04.2014
Description
First draft
Responsible
Michael Berger
Data Sheet
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©2014
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VDRM - Variable Step Down Regulator Module
CAUTIONS AND WARNINGS
The following conditions apply to all goods within the product series of MagI³C
of Würth Elektronik eiSos GmbH & Co. KG:
General:
All recommendations according to the general technical specifications of the data-sheet have to be complied with.
The disposal and operation of the product within ambient conditions which probably alloy or harm the component
surface has to be avoided.
If the product is potted in customer applications, the potting material might shrink during and after hardening.
Accordingly to this the product is exposed to the pressure of the potting material with the effect that the body and
termination is possibly damaged by this pressure and so the electrical as well as the mechanical characteristics are
endanger to be affected. After the potting material is cured, the body and termination of the product have to be
checked if any reduced electrical or mechanical functions or destructions have occurred.
The responsibility for the applicability of customer specific products and use in a particular customer design is always
within the authority of the customer. All technical specifications for standard products do also apply for customer
specific products.
Washing varnish agent that is used during the production to clean the application might damage or change the
characteristics of the body, pins or termination. The washing varnish agent could have a negative effect on the long
turn function of the product.
Direct mechanical impact to the product shall be prevented as the material of the body, pins or termination could flake
or in the worst case it could break. As these devices are sensitive to electrostatic discharge customer shall follow
proper IC Handling Procedures.
Customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safetyrelated requirements concerning its products, and any use of Würth Elektronik eiSos GmbH & Co. KG components in
its applications, notwithstanding any applications-related information or support that may be provided by Würth
Elektronik eiSos GmbH & Co. KG. Customer represents and agrees that it has all the necessary expertise to create
and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their
consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions.
Customer will fully indemnify Würth Elektronik eiSos and its representatives against any damages arising out of the
use of any Würth Elektronik eiSos GmbH & Co. KG components in safety-critical applications.
Product specific:
Follow all instructions mentioned in the datasheet, especially:
The solder profile has to be complied with according to the technical reflow/ or wave soldering specification,
otherwise no warranty will be sustained.
All products are supposed to be used before the end of the period of 12 months based on the product datecode, if not a 100% solderability can´t be warranted.
Violation of the technical product specifications such as exceeding the absolute maximum ratings will result
in the loss of warranty.
It is also recommended to return the body to the original moisture proof bag and reseal the moisture proof
bag again.
ESD prevention methods need to be followed for manual handling and processing by machinery.
Data Sheet
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©2014
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VDRM - Variable Step Down Regulator Module
IMPORTANT NOTES
The following conditions apply to all goods within the product range of
Würth Elektronik eiSos GmbH & Co. KG:
1. General Customer Responsibility
Some goods within the product range of Würth Elektronik eiSos GmbH & Co. KG contain statements regarding
general suitability for certain application areas. These statements about suitability are based on our knowledge and
experience of typical requirements concerning the areas, serve as general guidance and cannot be estimated as
binding statements about the suitability for a customer application. The responsibility for the applicability and use in a
particular customer design is always solely within the authority of the customer. Due to this fact it is up to the customer
to evaluate, where appropriate to investigate and decide whether the device with the specific product characteristics
described in the product specification is valid and suitable for the respective customer application or not. Accordingly,
the customer is cautioned to verify that datasheet are current before placing orders.
2. Customer Responsibility related to Specific, in particular Safety-Relevant Applications
It has to be clearly pointed out that the possibility of a malfunction of electronic components or failure before the end of
the usual lifetime cannot be completely eliminated in the current state of the art, even if the products are operated
within the range of the specifications. In certain customer applications requiring a very high level of safety and
especially in customer applications in which the malfunction or failure of an electronic component could endanger
human life or health it must be ensured by most advanced technological aid of suitable design of the customer
application that no injury or damage is caused to third parties in the event of malfunction or failure of an electronic
component.
3. Best Care and Attention
Any product-specific notes, warnings and cautions must be strictly observed.
4. Customer Support for Product Specifications
Some products within the product range may contain substances which are subject to restrictions in certain
jurisdictions in order to serve specific technical requirements. Necessary information is available on request. In this
case the field sales engineer or the internal sales person in charge should be contacted who will be happy to support
in this matter.
5. Product R&D
Due to constant product improvement product specifications may change from time to time. As a standard reporting
procedure of the Product Change Notification (PCN) according to the JEDEC-Standard inform about minor and major
changes. In case of further queries regarding the PCN, the field sales engineer or the internal sales person in charge
should be contacted. The basic responsibility of the customer as per Section 1 and 2 remains unaffected.
6. Product Life Cycle
Due to technical progress and economical evaluation we also reserve the right to discontinue production and delivery
of products. As a standard reporting procedure of the Product Termination Notification (PTN) according to the JEDECStandard we will inform at an early stage about inevitable product discontinuance. According to this we cannot
guarantee that all products within our product range will always be available. Therefore it needs to be verified with the
field sales engineer or the internal sales person in charge about the current product availability expectancy before or
when the product for application design-in disposal is considered. The approach named above does not apply in the
case of individual agreements deviating from the foregoing for customer-specific products.
7. Property Rights
All the rights for contractual products produced by Würth Elektronik eiSos GmbH & Co. KG on the basis of ideas,
development contracts as well as models or templates that are subject to copyright, patent or commercial protection
supplied to the customer will remain with Würth Elektronik eiSos GmbH & Co. KG. Würth Elektronik eiSos GmbH &
Co. KG does not warrant or represent that any license, either expressed or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right relating to any combination, application, or process in
which Würth Elektronik eiSos GmbH & Co. KG components or services are used.
8. General Terms and Conditions
Unless otherwise agreed in individual contracts, all orders are subject to the current version of the “General Terms
and Conditions of Würth Elektronik eiSos Group”, last version available at www.we-online.com.
Data Sheet
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©2014
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