WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
6V – 42V / 1A / 0.8V – 6V Output
DESCRIPTION
FEATURES
The VDRM series of the MagI³C Power Module family
provides a fully integrated DC-DC power supply including
the buck switching regulator and inductor in a package.
The 171010601 offers high efficiency and delivers up to
1A of output current. It operates from 6V input voltage up
to 42V. It is designed for fast transient response.
It is available in an innovative industrial high power
density TO263-7EP (10.16 x 13.77 x 4.57mm) package
that enhances thermal performance and allows for hand
or machine soldering.
The VDRM regulators have an integrated protection
circuit that guards against thermal overstress and
electrical damage by using thermal shut-down,
overcurrent, short-circuit, overvoltage and undervoltage
protection.
TYPICAL APPLICATIONS
Point-of-Load DC-DC applications from 9V, 12V, 18V
and 24V industrial rails
Industrial, test & measurement, medical applications
System power supplies
DSPs, FPGAs, MCUs and MPUs supply
I/O interface power supply
Peak efficiency above 90%
Current capability up to 1A
Input voltage range: 6V to 42V
Output voltage range: 0.8V to 6V
Reference accuracy: ±2%
No minimum load required
Integrated shielded inductor solution for quick time to
market and ease of use
Single exposed pad for best-in-class thermal
performance
Low output voltage ripple (< 10mVpp)
Adjustable switching frequency: 0.2 to 0.8 MHz
Low ripple Constant On-Time control
Synchronous operation
Automatic power saving operation at light load
Undervoltage lockout protection (UVLO)
Adjustable soft-start
Thermal shutdown
Short circuit protection
Cycle-by-cycle current limit
Output overvoltage protection
Pin compatible with 171012401, 171012402,
171032401, 171020601 and 171030601
Operating ambient temperature up to 105°C
RoHS and REACh compliant
Operating junction temp. range: -40 to 125°C
Mold compound UL 94 Class V0 (flammability
testing) certified
Complies with EN55022 class B radiated emissions
standard
2
TO
P
-7E
63
TYPICAL CIRCUIT DIAGRAM
1
VIN
VIN
RON
VOUT
7
RFBT
Module
2
RON
FB
CIN
AGND
3
EN
VOUT
PGND
SS
EP
5
CFF
6
COUT
4
CSS
RFBB
GND
GND
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
PACKAGE
EP
Exposed Pad = PGND
6
7
7
6
5
4
Top View
SS
AGND
FB
VOUT
7
FB
7
VOUT
6
3
2
1
VIN
5
6
EN
4
SS
EN
3
AGND
VIN
2
RON
1
RON
YMLLLLSG3
MagI3C
171010601
Bottom View
MARKING DESCRIPTION
Marking
WE
Y
M
LLLL
S
G3
MagI3C
171010601
Description
Würth Elektronik tradename
Year
Month
Assembly lot code
Assembly site code per QSS 050-120
Lead finish code per Jedec Norm (green 3 mat sin)
MagI³C logo
Order code
PIN DESCRIPTION
SYMBOL
NUMBER
TYPE
DESCRIPTION
VIN
1
Power
The supply input pin is a terminal for an unregulated input voltage source. It is required
to place the input capacitor nearby the VIN pin and PGND.
RON
2
Input
An external resistor from RON to VIN pin sets the on-time and frequency of the
application.
EN
3
Input
Connecting this pin to GND disables the device. Connecting this pin to a voltage
higher than 1.18V typ. (but 0.8V,
TJ=25°C,
IOUT = 10mA
VSS>0.8V,
-40°C≤TJ≤125°C,
IOUT = 1A
Load regulation
Output voltage ripple
VIN = 12V to 42V
IOUT=1A
VIN = 24V
IOUT = 0A to 1A
VOUT=5V
COUT=100μF 6.3V X7R
20MHz BWL
Protections
VFB-OVP
fSW
tON-MIN
tOFF-MIN
Feedback overvoltage
protection threshold
Switching frequency
Switching frequency
Continuous Conduction Mode
(CCM)
ON timer minimum pulse
width
OFF timer minimum pulse
width
Enable
VENABLE
EN threshold trip point
VEN rising
1.10
1.18
1.25
V
EN threshold hysteresis
VEN falling
-
90
-
mV
2.2
-
ms
Soft-Start
tSS
Soft-start time
CSS = 0.022µF
-
ISS
SS pin source current
VSS = 0V
5
8
11
µA
ISS-DIS
SS discharge current
-
-200
-
µA
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
ELECTRICAL SPECIFICATIONS
MIN and MAX limits are valid for the recommended junction temperature range of -40°C to 125°C. Typical values represents
statistically the utmost probability at following conditions: V IN = 24V, VOUT = 3.3V, TA = 25°C, unless otherwise specified.
SYMBOL
η
PARAMETER
TEST CONDITIONS
Efficiency
VIN = 24V, VOUT = 3.3V,
IOUT = 0.5A, fSW = 500kHz
VIN = 24V, VOUT = 3.3V,
IOUT = 1A, fSW = 500kHz
VIN = 24V, VOUT = 5V,
IOUT = 0.5A, fSW = 500kHz
VIN = 24V, VOUT = 5V,
IOUT = 1A, fSW = 500kHz
Input current
Efficiency
MIN (1)
TYP (4)
MAX (1)
UNIT
-
83
-
%
-
86
-
%
-
85
-
%
-
89
-
%
IQ
Input quiescent current
VFB = 0.86V (7)
-
1
-
mA
ISD
Shutdown quiescent input
current
VENABLE = 0V
-
25
-
µA
MIN (1)
TYP (4)
MAX (1)
UNIT
RELIABILITY
SYMBOL
MTBF(8)
PARAMETER
Mean Time Between
Failures
-
TEST CONDITIONS
Confidence level 60%
Test temperature: 125°C
Usage temperature: 55°C
Activation energy: 0.7eV
Test duration: 1000 hours
Sample size: 6471
Fail: 0
5.54·108
h
RoHS, REACh
RoHS
directive
Directive 2011/65/EU of the European Parliament and the Council of June
8th, 2011 on the restriction of the use of certain hazardous substances in
electrical and electronic equipment.
REACh
directive
Directive 1907/2006/EU of the European Parliament and the Council of
June 1st, 2007 regarding the Registration, Evaluation, Authorization and
Restriction of Chemicals (REACh).
PACKAGE SPECIFICATIONS
MOLD COMPOUND
Part Number
Material
171020601
EME-G760
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WEIGHT
UL Class
UL94V-0
Certificate Number
E41429
0.54g
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
NOTES
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed
through correlation using Statistical Quality Control (SQC) methods.
(2) The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per
JESD-22-114.
(3) JEDEC J-STD020
(4) Typical numbers are valid at 25°C ambient temperature and represent statistically the utmost probability assuming the
Gaussian distribution.
(5) Depending on heat sink design, number of PCB layers, copper thickness and air flow.
(6) Measured on a 8cm x 8cm four layer PCB, 35µm copper, thirty-six 10mil (254µm) thermal vias, no air flow (see
“OUTPUT POWER DERATING” section on page 13).
(7) Module ON (Enable floating or high), feedback voltage applied by external source no PWM switching
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
TYPICAL PERFORMANCE CURVES
If not otherwise specified, the following conditions apply: V IN = 24V; CIN = 10µF X7R ceramic; COUT = 100µF X7R ceramic,
TAMB = 25°C.
RADIATED AND CONDUCTED EMISSIONS
70
Radiated Emissions 171010601 (3m Antenna Distance)
VIN = 24V, VOUT = 5V, ILOAD = 1A with input filter 1µF(885012209047) and 10µH(7447462100)
Horizontal
Vertical
Radiated Emissions [dBµV/m]
60
50 EN55022 Class A limit
40
EN55022 Class B limit
30
20
10
0
30
80
70
100
Frequency [MHz]
1
Conducted Emissions 171010601
VIN = 24V, VOUT = 5V, ILOAD = 1A with input filter 4.7µF and 10µH(7447462100)
Average Quasi peak
60
Conducted Emissions [dBµV]
1000
EN55022 Class B Quasi Peak limit
50
EN55022 Class B Average limit
40
30
20
10
0
-10
0.15
0.5
1
10
30
Frequency [MHz]
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
EFFICIENCY
171010601 VIN = 12V, fSW =500kHz, TA = 25°C
100
95
90
Efficiency [%]
85
80
Vout = 5V
75
Vout = 3.3V
70
Vout = 2.5V
65
Vout = 1.8V
60
55
50
0
0,25
0,5
Output Current [A]
0,75
1
171010601 VIN = 12V, fSW =500kHz, TA = 85°C
100
95
90
Efficiency [%]
85
80
Vout = 5V
75
Vout = 3.3V
70
Vout = 2.5V
65
Vout = 1.8V
60
55
50
0
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0,25
0,5
Output Current [A]
0,75
1
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
EFFICIENCY
171010601 VIN = 24V, fSW =500kHz, TA = 25°C
100
95
90
Efficiency [%]
85
80
Vout = 5V
75
Vout = 3.3V
70
Vout = 2.5V
65
Vout = 1.8V
60
55
50
0
0,25
0,5
Output Current [A]
0,75
1
171010601 VIN = 24V, fSW =500kHz, TA = 25°C
100
95
90
Efficiency [%]
85
80
Vout = 5V
75
Vout = 3.3V
70
Vout = 2.5V
65
Vout = 1.8V
60
55
50
0
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0,25
0,5
Output Current [A]
0,75
1
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
POWER DISSIPATION
171010601 VIN = 12V, fSW =500kHz, TA = 25°C
Power Dissipation [W]
0,80
0,60
Vout = 5V
0,40
Vout = 3.3V
Vout = 2.5V
Vout = 1.8V
0,20
0,00
0
0,25
0,5
Output Current [A]
0,75
1
171010601 VIN = 12V, fSW =500kHz, TA = 85°C
Power Dissipation [W]
0,80
0,60
Vout = 5V
0,40
Vout = 3.3V
Vout = 2.5V
Vout = 1.8V
0,20
0,00
0
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0,25
0,5
Output Current [A]
0,75
1
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
POWER DISSIPATION
171010601 VIN = 24V, fSW =500kHz, TA = 25°C
Power Dissipation [W]
0,80
0,60
Vout = 5V
0,40
Vout = 3.3V
Vout = 2.5V
Vout = 1.8V
0,20
0,00
0
0,25
0,5
Output Current [A]
0,75
1
171010601 VIN = 24V, fSW =500kHz, TA = 85°C
Power Dissipation [W]
0,80
0,60
Vout = 5V
0,40
Vout = 3.3V
Vout = 2.5V
Vout = 1.8V
0,20
0,00
0
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0,25
0,5
Output Current [A]
0,75
1
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
OUTPUT POWER DERATING
171010601 Current Thermal Derating
VIN = 12V, VOUT = 3.3V, fSW = 500kHz, θJA = 19.3°C/W
1,2
Output current [A]
1,0
0,8
0,6
0,4
0,2
125°C
118°C
0,0
0
10
20
30
40
50
60
70
80
Ambient Temperature [°C]
90
100
110
120
130
171010601 Current Thermal Derating
VIN = 12V, VOUT = 5V, fSW = 500kHz, θJA = 19.3°C/W
1,2
Output current [A]
1,0
0,8
0,6
0,4
0,2
125°C
117°C
0,0
0
10
20
30
40
50
60
70
80
Ambient Temperature [°C]
90
100
110
120
130
The ambient temperature and the power limits of the derating curve represent the operation at the max junction temperature
specified in the “Operating Conditions” section on page 4.
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
171010601 Current Thermal Derating
VIN = 24V, VOUT = 3.3V, fSW = 500kHz, θJA = 19.3°C/W
1,2
Output current [A]
1,0
0,8
0,6
0,4
0,2
114°C 125°C
0,0
0
10
20
30
40
50
60
70
80
Ambient Temperature [°C]
90
100
110
120
130
171010601 Current Thermal Derating
VIN = 24V, VOUT = 5V, fSW = 500kHz, θJA = 19.3°C/W
1,2
Output current [A]
1,0
0,8
0,6
0,4
0,2
113°C
125°C
0,0
0
10
20
30
40
50
60
70
80
Ambient Temperature [°C]
90
100
110
120
130
The ambient temperature and the power limits of the derating curve represent the operation at the max junction temperature
specified in the “Operating Conditions” section on page 4.
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
LINE AND LOAD REGULATION
171010601 Line Regulation VOUT = 3.3V, IOUT = 1A, TA = 25°C
3,4
Output voltage [V]
3,35
3,3
3,25
3,2
6
9
12
15
18
21
24
27
Input Voltage [V]
30
33
36
39
42
171010601 Load Regulation VIN = 24V, VOUT = 3.3V, TA = 25°C
3,4
DCM
operation
CCM
operation
Output Voltage [V]
3,35
3,3
3,25
3,2
0
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0,25
0,5
Output Current [A]
0,75
1
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
BLOCK DIAGRAM
Power Module
Linear
Regulator
CVCC
CBST
10µH
1 VIN
VIN
VOUT 7
VOUT
HSS
0.47µF
CIN
RFBT
RON
VIN
UVLO
CSS
AGND
2
RON
5
SS
Controller/
Power Control/
Protection Circuitry
CFF
COUT
LSS
Comparator
EN
AGND
PGND
3
4
EP
VREF
0.8V
FB 6
RFBB
AGND
CIRCUIT DESCRIPTION
The MagI³C Power Module 171010601 is based on a synchronous step-down regulator with integrated MOSFETs and a
power inductor. The control scheme uses a Constant On-Time (COT) low ripple hysteretic regulation loop.
The VOUT of the regulator is divided by the feedback resistor network RFBT and RFBB and fed into the FB pin. The internal
comparator compares this signal with the internal 0.8V reference. If the feedback voltage is below the reference, the high
side MOSFET is turned on for a fixed on-time.
To achieve a regulated output voltage the off-time is modulated. At stable VIN to VOUT condition the relation between on-time
and off-time is constant. The on-time is preset by the value of the RON resistor. The switching frequency is directly
proportional to this value. The connection of the RON resistor to VIN results into an additional compensation of VIN variations,
(VIN feed-forward) so the switching frequency will remain almost constant even during VIN transients.
A load current transient (low to high current) allows the off-time to immediately transition to the minimum of 260 ns. This
results in a short term higher switching frequency which ensures an extremely quick regulation response. As soon as the
output capacitor is recharged to the nominal output voltage the switching frequency will return to the original value even
though the load current is higher.
The constant on-time control scheme does not require compensation circuitry which makes the overall design very simple.
Nevertheless, it requires a certain minimum ripple at the feedback pin. The MagI³C Power Module 171010601 generates this
ripple internally and is supported by the C FF capacitor which bypasses AC ripple directly to the feedback pin from the output.
With this architecture very small output ripple values of around 10mV (similar to current or voltage mode devices) are
achieved.
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
DESIGN FLOW
The next 7 simple steps show how to select the external components to design your power application.
Essential Steps
1.
2.
3.
4.
5.
6.
Set the output voltage
Set the operating frequency with RON
Select the input capacitor
Select the output capacitor
Select the feed forward capacitor
Select the soft-start capacitor
Optional Steps
7.
Select the undervoltage lockout divider
1
VIN
RON
2.
3.
RON
3
EN
PGND
SS
EP
5
CFF
5.
6
4.
COUT
4
AGND
7.
VOUT
RFBT
FB
RENT
RENB
7
VOUT
Module
2
CIN
VIN
1.
CSS
RFBB
6.
GND
GND
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
Step 1 Set the output voltage (VOUT)
The output voltage is determined by a divider of two resistors connected between VOUT and ground. The midpoint of the
divider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal operation, an ontime cycle is initiated when the voltage on the FB pin falls below 0.8V. The high-side MOSFET on-time cycle causes the
output voltage to rise and the voltage at the FB to exceed 0.8V. As long as the voltage at FB is above 0.8V, on time cycles
will not occur.
The ratio of the feedback resistors for the desired output voltage is:
RFBT
VOUT
= (
) -1
RFBB
VFB
(1)
These resistors should be chosen from values in the range of 1kΩ to 20kΩ.
A table of values for RFBT, RFBB, and RON is included in the “TYPICAL SCHEMATIC” section (page 38).
Step 2 Set the operating frequency (fSW) with RON
Many designs begin with a desired switching frequency in mind. For that purpose the following equation can be used:
RON ≊
VOUT
(k ∙ fSW(CCM) )
(2)
where k = 1.3·10-10 C and fSW(CCM) is the switching frequency when the device is working in CCM (Continuous Conduction
Mode). While selecting the RON and the fSW(CCM), the limitations in terms of minimum on-time and off-time must be taken into
account. The on-time of the MagI³C power module timer is determined by the resistor RON and the input voltage VIN. It is
calculated as follows:
tON =
(k ∙ RON )
VIN
(3)
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. The TON is internally
limited to a minimum value of 150ns. Therefore RON should be selected such that the on-time at maximum VIN is greater than
150ns, as the following formula describes:
RON ≥
VIN(MAX) ∙ tON-MIN
k
(4)
This limits the maximum operating frequency, which is governed by the following equation:
fSW(MAX) =
VOUT
(VIN(MAX) ∙tON-MIN )
(5)
If the RON calculated in equation (2) is less than the minimum value determined in equation (4) a lower frequency should be
selected. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged.
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
All considerations mentioned above are summarized in the diagram below. The curves depict the relation between the
switching frequency and the RON for some typical output voltages. For the switching frequency, only the range indicated in
the “ELECTRICAL SPECIFICATIONS” section on page 5 (from 200kHz to 800kHz) is considered. Due to the minimum ontime previously mentioned, under low duty cycle conditions, there are some limitations in the minimum selectable R ON.
These limits are shown below with a dotted line and they refer to some typical input voltages (24V, 36V and the maximum
operating voltage of 42V).
As stated above, the off-time is also limited to a minimum value of 260 ns, which limits the maximum duty cycle. Larger RON
(lower FSW) should be selected in any application requiring large duty ratio.
The choice of the switching frequency influences the efficiency of the system, especially at low currents, as the picture below
depicts.
Efficiency vs Frequency, VIN = 12V, VOUT = 5V, TA = 25°C
100
95
90
Efficiency [%]
85
80
75
70
65
fsw = 200kHz
60
fsw = 500kHz
55
fsw = 800kHz
50
0
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0,2
0,4
0,6
Output Current [A]
0,8
1
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WPMDH1100601 / 171010601
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
Step 3 Select the input capacitor (CIN)
The MagI³C power module contains an internal 0.47μF input ceramic capacitor. The module requires additional, external
input capacitance to handle the input current ripple. This input capacitance should be located as close as possible to the
MagI³C power module. Input capacitor selection is generally based on different requirements. The first criteria is the input
current ripple. Worst case input current ripple rating is dictated by the equation:
ICINRMS ≈
1
D
∙I
∙√
2 OUT 1-D
(6)
where
D≈
VOUT
VIN
As a point of reference, the worst case current ripple will occur when the module is presented with full load current and when
VIN = 2 x VOUT.
Recommended minimum input capacitance is 10µF (including derating) ceramic with a voltage rating at least 25% higher
than the maximum applied input voltage for the application. It is strongly recommended to pay attention to the voltage and
temperature deratings of the capacitor selected. It should be noted that current ripple rating of ceramic capacitors may be
missing from the capacitor data sheet and you may have to contact the capacitor manufacturer for this rating.
The second criteria is the input voltage ripple.
If the system design requires a certain minimum value of peak-to-peak input voltage ripple (VIN
equation may be used:
CIN ≥
ripple)
IOUT ∙ D ∙ (1-D)
fSW(CCM) ∙ VIN ripple
then the following
(7)
As example, if ΔVIN is 1% of VIN for a 24V input to 3.3V output application, and fSW = 400 kHz this leads:
CIN ≥
3.3V
3.3V
∙ (1–
)
24V
24V
400000 ∙ 0.240V
1A ∙
CIN ≥1.25μF
Additional bulk capacitance with higher ESR may be required to damp any resonant effects between the input capacitance
and parasitic inductance of the incoming supply lines.
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Step 4 Select output capacitor (COUT)
L
HS Mosfet
IL
Iout
VCOUT
VIN
COUT
CIN
VOUT
LS Mosfet
VES R
RLoad
ESR
None of the required output capacitors are integrated within the module. A general recommendation in order to guarantee a
stable behavior is to place at least a capacitance of 10µF (MLCC recommended) at the output.
The output capacitor must meet the worst case RMS current rating, as calculated by equation (8):
ICOUTRMS =
∆IL
(8)
√12
where ∆IL is the inductor current ripple calculated with the equation (9)
∆IL =
VOUT ∙ (VIN -VOUT )
fSW ∙ L ∙ VIN
(9)
Selection by output voltage ripple requirements
The output capacitor should be selected in order to minimize the output voltage ripple and provide a stable voltage at the
output. Under steady state conditions, the voltage ripple observed at the output can be defined as:
VOUT ripple =∆IL ∙ ESR+∆IL ∙
1
8∙fSW ∙COUT
(10)
Very low ESR capacitors, like ceramic and polymer electrolytic, are recommended. If a low ESR capacitor is selected,
equation (10) can be simplified and a first condition for the minimum capacitance value can be derived:
COUT ≥
∆IL
8 ∙ VOUT ripple ∙ fSW
(11)
Beyond that, the additional capacitance will reduce the output voltage ripple as long as the ESR is low enough to permit it.
Please consider the derating of the nominal capacitance value due to temperature, aging and applied DC voltage (e.g.
MLCC X7R up to -50%).
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The use of very low ESR capacitors leads to an output voltage ripple as shown below (generic waveform):
Output voltage ripple with low ESR capacitors
Output voltage ripple [mV]
10
5
0
-5
-10
0
1
2
3
time [µs]
When capacitors with slightly higher ESR are utilized, the dominant parameter that influences the output voltage ripple is just
the ESR:
ESR≤
VOUT ripple
∆IL
(12)
Consequently, the shape of the output voltage ripple changes as shown below (generic waveform):
Output voltage ripple with high ESR capacitors
Output voltage ripple [mV]
100
50
0
-50
-100
0
1
2
3
time [µs]
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Selection by load step requirements
The output voltage is also affected by load transients (see picture below). The constant on-time control scheme generally
provides faster response than the other control loops.
When the output current transitions from a low to a high value, the voltage at the output capacitor (VOUT) drops due to two
contributing factors. One is caused by the voltage drop across the ESR (V ESR) and depends on the slope of the rising edge
of the current step (trise). For low ESR values and small load currents, this is often negligible. It can be calculated as follows:
VESR =ESR∙∆IOUT
(13)
where ∆IOUT is the load step, as shown in the picture below (simplified: no voltage ripple is shown).
IOUT
∆IOUT
0
trise
t
VOUT
VESR
∆VOUT
Vdischarge
0
t
td
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VDRM – Variable Step Down Regulator Module
The second contributing factor is the voltage drop due to the discharge of the output capacitor. In order to estimate this
contribution, the behavior of the inductor current during the transient should be analyzed (see picture below, ESR
contribution neglected).
At the transition, the device tries to reach the new steady state as fast as possible by increasing the inductor current. This
can be achieved only by modulating the off-time tOFF since the on-time is fixed and defined by RON. The device has a
minimum tOFF (tOFF-MIN = 260ns typ.). Therefore, as long as the new steady state is not achieved, the inductor current
increases by performing consecutive cycles of tON and tOFF-MIN. During the transition to the new output current, the load
demand is supported by the energy stored in the output capacitor. For that reason, the output voltage drops until the
average inductor current reaches the new output current. The time for reaching this condition (t d) can be calculated as
follows:
td =
∆IL
)∙L∙(tON +tOFF-MIN )
2
VIN ∙tON -VOUT ∙(tON +tOFF-MIN )
(∆IOUT +
(14)
The td calculated above represents the worst case, i.e. it is supposed that the load transient occurs when the inductor
current has its minimum value (IOUT −
∆IL
2
).
IL, 200
VOUT
3
150
2,5
100
LOAD
TRANSITION
50
0
VOUT
IOUT2
2
tOFFmin
1,5
∆VOUT
-50
IL
1
-100
IOUT10,5
-150
tON
-200
0
t
td
The selection of the COUT is related to the td as well as to the current step ∆IOUT and the max allowed voltage drop ∆V OUT, as
shown by the following equation:
COUT ≥
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(∆IOUT +
∆IL
)∙t
2 d
2∙∆VOUT
(15)
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The same equation can be used for calculating the minimum required capacitance for an output current transition from high
to low (see picture below). Since the inductor current must reach the new steady state with a lower value than before, there
is no need to trigger a new on-time cycle. Instead, the off-time is extended until the average inductor current reaches the
new load current value. The excess of current during this time charges the output capacitor. This causes the output voltage
to increase and an overshoot occurs. The time td for reaching the new steady state can be calculated for a negative load
transient with the following equation:
td =
L
∆IL
∙(
+∆IOUT ) +tON
VOUT 2
The equation (16) shows the worst case in terms of the current (IOUT +
(16)
∆IL
2
) as well as in terms of time. The inclusion of tON in
the formula takes into account a new on-time triggered in case the load transient occurs at the end of the off-time. Under this
condition a new on-time is generated because the device has not yet reacted to the transient and to the consequent
deviation of VOUT from its steady state value (see figure below).
IL, VOUT
tON
200
3
tOFF
IL
150
2,5
IOUT1
100
50
VOUT
∆VOUT
1,5
∆IOUT0
LOAD
TRANSITION
-50
1
0,5
IOUT2
-100
0
-150
-200
-0,5
0
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2
10
20
td
30
t
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Example
The following application conditions are used as an example to show how to calculate a suitable C OUT value:
-
VIN = 24V
VOUT = 5V
RON = 75kΩ
load transient from 0.5A to 1A and vice versa (∆IOUT = 0.5A)
max allowed undershoot or overshoot ∆VOUT = 100mV
The COUT can be calculated using the equation (15) on page 24. This equation provides two possible values depending on
whether td is calculated for a positive load transient (generating a V OUT drop) or for a negative load transient (resulting in a
VOUT overshoot).
In case of positive load transient: td = 920ns and COUT ≥ 4.1µF
In case of negative load transient: td = 2.18µs and COUT ≥ 9.6µF
A combination of 10µF (Würth Elektronik, part number 885012109008) + 4.7µF (885012109008) MLCC are selected. Some
margin from the calculated COUT value is recommended in order to take into account:
-
Approximations within the equations to estimate td and COUT itself;
Tolerances and variations of some components and parameters involved in those equations (e.g. RON, tOFF-MIN, L, k,
etc.)
Derating of the capacitors with DC applied voltage and temperature
The use of two MLCCs in parallel contributes to the further reduction of the total ESR.
The load transients with the selected COUT can be tested using the setup depicted below:
VIN
VIN
VOUT
MagI³C Power
Module
COUT
RLoad1
10Ω
RLoad2
10Ω
GND
IOUT1
IOUT2
Q1
GND
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The results of the load transient tests with the selected COUT are shown below:
Load Transient from 0.5A to 1A
4
200
Output Current [A]
3
100
50
VOUT
2
0
∆VOUT = 30mV
-50
IOUT2
1
-100
IOUT1
Output Voltage AC [mV]
150
-150
0
-200
0
10
20
30
40
50
60
70
Time [µs]
80
90
100
110
120
Load Transient from 1A to 0.5A
4
200
150
100
∆VOUT = 55mV
2
50
VOUT
IOUT1
0
-50
1
-100
IOUT2
Output Voltage AC [mV]
Output Current [A]
3
-150
0
-200
0
10
20
30
40
50
60
70
Time [µs]
80
90
100
110
120
In both the positive and the negative transition, the ∆V OUT is significantly below the target (100mV). The explanation of the
strong reduction of the ∆VOUT lies in the use of a capacitance value higher than the one calculated.
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Step 5 Select the feed forward capacitor (CFF)
A feed-forward capacitor CFF is placed in parallel with RFBT that bypasses AC ripple directly to the feedback pin from the
output to support the internal ripple generator. This capacitor also affects the load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM and adjusting for best transient response and
minimum output ripple. A value of 22nF has been practically evaluated as the best choice. The feed forward capacitor CFF
should be located close to the FB pin.
Step 6 Select soft-start capacitor (CSS)
A minimum soft-start capacitance of 22nF is required. Programmable soft-start permits the regulator to slowly ramp up to its
steady state operating point after being enabled, thereby reducing the input current at start-up and slowing the output
voltage rise-time to prevent overshoot. Upon turn-on, after all UVLO conditions have been passed, an internal 8µA current
source begins charging the external soft-start capacitor. The soft-start capacitor can be calculated with:
CSS = tSS ∙
8μA
0.8V
(17)
Where tSS in the desired soft-start time in milliseconds. The use of a 22nF capacitor results in 2.2ms soft-start duration.
As the soft-start input exceeds 0.8V the output of the power stage will be in regulation. The soft-start capacitor continues
charging until it reaches approximately 3.8V on the SS pin. Voltage levels between 0.8V and 3.8V do not influence the
regulation of the output voltage.
The picture below shows the output voltage under three different soft-start conditions:
Output Voltage at Start Up with Different Soft-Start Capacitors at VOUT = 5V
6,0
5,5
Enable
Output Voltage [V]
5,0
Css = 22nF
4,5
Css = 47nF
4,0
Css = 68nF
3,5
3,0
2,5
2,0
1,5
1,0
0,5
0,0
0
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2
4
6
Time [ms]
8
10
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Note that high values of the CSS capacitance will cause more output voltage droop when a load transient goes across the
DCM-CCM boundary. Use equation (22) in the “LIGHT LOAD OPERATION” section (page 33) to find the DCM-CCM load
current boundary for the specific operating conditions. If a fast load transient response is desired for steps between DCM
and CCM mode the soft-start capacitor value should be less than 0.018μF. Note that the following conditions will reset the
soft-start capacitor by discharging the SS input to ground with an internal 200μA current sink:
1.
2.
3.
4.
The enable input being “pulled low”
Thermal shutdown condition
Overcurrent fault
Internal UVLO at input
Step 7 Optional: select enable divider, RENT, RENB (external UVLO)
The enable input provides a precise 1.18V reference threshold to allow a direct logic drive or connection to a voltage divider
from a higher voltage such as VIN. The enable input also incorporates 90mV (typ.) of hysteresis resulting in a falling threshold
of 1.09V. The maximum recommended voltage into the EN pin is 6.5V. For applications where the midpoint of the enable
divider exceeds 6.5V, a small zener diode can be added to limit this voltage.
The function of the RENT and RENB divider shown in the application block diagram is to allow the designer to choose an input
voltage below which the circuit will be disabled. This implements the feature of programmable external under voltage
lockout. This is often used in battery powered systems to prevent deep discharge of the system battery. It is also useful in
system designs for sequencing of output rails or to prevent early turn-on of the supply as the main input voltage rail rises at
power-up. Most systems will benefit by using the precision Enable threshold to establish a system under voltage lockout.
Without an external enable divider the device would attempt to turn on around V IN = 3.5V. In case of output voltages higher
than this turn on threshold, the VOUT follows the VIN as long as VIN
