WPMDL1201801 / 171021801
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
4V – 18V / 2A / 0.8V – 17V Output
DESCRIPTION
FEATURES
The VDRM series of the MagI³C Power Module family
provides a fully integrated DC-DC power supply including
the buck switching regulator, inductor, input and output
capacitors in a package, allowing a minimum external
components count solution, quick time to market and
ease of use.
The 171021801 family offers high efficiency and delivers
up to 2A of output current. It operates from 4V input
voltage up to 18V. It is designed for fast transient
response.
It is available in an innovative industrial high power
density LGA-16EP (9 x 9 x 3mm) package that enhances
thermal performance.
The VDRM regulators have an integrated protection
circuit that guards against thermal overstress and
electrical damage by using thermal shut-down,
overcurrent, short-circuit, and undervoltage protection.
TYPICAL APPLICATIONS
Point-of-Load DC-DC applications from 5V, 9V and
12V industrial rails
Industrial, test & measurement, medical applications
System power supplies
DSPs, FPGAs, MCUs and MPUs supply
I/O interface power supply
Peak efficiency up to 95%
Current capability: 2A
Input voltage range: 4V to 18V
Output voltage range: 0.8V to 17V
Reference accuracy: ±1.5%
No minimum load required
Integrated input and output capacitors
Integrated shielded inductor
Exposed pads for best-in-class thermal performance
Low output voltage ripple (< 20mVpp)
Fixed switching frequency: 850kHz
Peak Current Mode control
Internal soft-start
Synchronous operation
Automatic power saving operation at light load
Undervoltage lockout protection (UVLO)
Thermal shutdown
Short circuit protection
Cycle-by-cycle current limit
Operating ambient temperature up to 85°C
RoHS and REACh compliant
Operating junction temp. range: -40 to 125°C
Mold compound UL 94 Class V0 (flammability
testing) certified
Complies with EN55022 class B radiated emissions
standard
TYPICAL CIRCUIT DIAGRAM
VIN
1,2,3,4
VIN
VOUT
9,10,11,12
RFBT
Module
NO NEED FOR CIN
16 EN
VOUT
FB
NO NEED FOR COUT
13
GND
17
RFBB
GND
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GND
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WPMDL1201801 / 171021801
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
VOUT 10
9 VOUT
VOUT 9
16 EN
15 NC
PGND
EP
PGND
EP
Top View
1 VIN
2 VIN
3 VIN
4 VIN
NC 5
10 VOUT
PGND
EP
NC 6
VOUT 11
PGND
EP
NC 7
11 VOUT
14 NC
13 FB
13 FB
14 NC
PGND
EP
VOUT 12
NC 8
VIN 4
PGND
EP
12 VOUT
NC 8
VIN 3
PGND
EP
NC 7
VIN 2
PGND
EP
NC 6
VIN 1
NC 5
16 EN
15 NC
PACKAGE
Bottom View
MARKING DESCRIPTION
Marking
WE
MagI³C
171021801
YYWW
XXXX
E4
Description
Würth Elektronik tradename
MagI³C Logo
Order Code
Date Code
Tracking Code
Lead finish code per Jedec
PIN DESCRIPTION
SYMBOL
NUMBER
TYPE
DESCRIPTION
VIN
1,2,3,4
Power
The supply input pins are a terminal for an unregulated input voltage source.
These pins are internally connected together. Connect externally all together
with a single PCB track.
VOUT
9,10,11,12
Power
The output voltage pins are connected to the internal inductor. These pins are
internally connected together. Connect externally all together with a single PCB
track.
FB
13
Input
The feedback pin is internally connected to the regulation circuitry. The
regulation reference point is 0.8V at this input pin. Connect the feedback
resistor divider between the output and GND to set the output voltage.
EN
16
Input
Connecting this pin to a voltage lower than 0.4V (e.g. GND) disables the
device. Connecting this pin to a voltage higher than 1.2V enables the device.
This pin is connected to ground through an internal pull-down resistor.
Therefore leaving this pin open disables the device.
PGND
EP
Exposed
Pads
These pins are the ground connection of the device. All pins must be
connected together externally with a copper plane for heat sinking
NC
5,6,7,8,14,15
Not
connected
These pins are not connected to the internal circuitry and are not connected to
each other. They can be left floating
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WPMDL1201801 / 171021801
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
ORDERING INFORMATION
ORDER CODE
PART DESCRIPTION
SPECIFICATIONS
PACKAGE
PACKAGING UNIT
171021801
WPMDL1201801LD
178021801
WPMDL1201801JEV
2A / 0.8-17Vout
LGA-16EP
Tape and Reel, 1000 pieces
2A / 0.8-17Vout
Eval Board
1
PIN COMPATIBLE FAMILY MEMBERS
ORDER CODE
PART DESCRIPTION
SPECIFICATIONS
PACKAGE
PACKAGING UNIT
171011801
WPMDL1101801LD
1A / 0.8-17Vout
LGA-16EP
Tape and Reel, 1000 pieces
178011801
WPMDL1101801JEV
1A / 0.8-17Vout
Eval Board
1
171031801
WPMDL1301801LD
3A / 0.8-17Vout
LGA-16EP
Tape and Reel, 1000 pieces
178031801
WPMDL1301801JEV
3A / 0.8-17Vout
Eval Board
1
SALES INFORMATION
SALES CONTACTS
Würth Elektronik eiSos GmbH & Co. KG
EMC & Inductive Solutions
Max-Eyth-Str. 1
74638 Waldenburg
Germany
Tel. +49 (0) 7942 945 0
www.we-online.com
powermodules@we-online.com
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WPMDL1201801 / 171021801
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
ABSOLUTE MAXIMUM RATINGS
Caution:
Exceeding the listed absolute maximum ratings may affect the device negatively and may cause permanent damage.
SYMBOL
VIN
VOUT
Output voltage
FB input voltage
EN
EN input voltage
TJ
MIN(1)
Input voltage
FB
VESD
LIMITS
PARAMETER
ESD voltage (Human Body Model), according to EN61000-4-2
(2)
Junction temperature
Tstorage
TSOLDER
Assembled, non-operating storage temperature
Peak case/leads temperature during reflow soldering, max.20sec
(3)
MAX(1)
UNIT
-0.3
20
V
-1
VIN
V
-0.3
2.5
V
-0.3
VIN
-
±2000
V
-40
150
°C
-55
150
°C
230
240
°C
OPERATING CONDITIONS
Operating conditions are conditions under which the device is intended to be functional. All values are referenced to GND.
SYMBOL
VIN
PARAMETER
MIN(1)
TYP(4)
MAX(1)
UNIT
4
-
18
V
0.8
-
17
V
-
-
2
A
°C
°C
Input voltage
VOUT
Regulated output voltage
IOUT
Nominal output current
TA
Ambient temperature range
-40
-
85(5)
TJ
Junction temperature range
-40
-
125
THERMAL SPECIFICATIONS
SYMBOL
ӨJA
TSD
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TYP (4)
UNIT
22
°C/W
Thermal shutdown, rising
150
°C
Thermal shutdown hysteresis, falling
15
°C
PARAMETER
Junction-to-ambient thermal resistance
(6)
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WPMDL1201801 / 171021801
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
ELECTRICAL SPECIFICATIONS
MIN and MAX limits are valid for the recommended junction temperature range of -40°C to 125°C. Typical values represents
statistically the utmost probable values at the following conditions: VIN = 12V, TA = 25°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (4)
MAX (1)
UNIT
-
4
-
A
0.784
0.8
0.816
V
0.776
0.8
0.824
V
Output current
ICL
Current limit threshold
TA = 25°C
Output voltage
Reference voltage
TA = 25°C
VFB
Reference voltage over
temperature
IFB
Feedback input bias current
TA = 25°C
-
50
-
nA
Line regulation
VIN = 4V to 18V, TA = 25°C
-
0.4
-
%/V
Load regulation
IOUT = 10mA to ICL, TA = 25°C
VOUT = 3.3V, IOUT = 2A,
TA = 25°C, 20MHz BWL
-
0.5
-
%/A
-
15
-
mVpp
VOUT
Output voltage ripple
Switching frequency
fSW
Switching frequency
TA = 25°C
0.7
0.85
1
MHz
DMAX
Maximum duty-cycle
TA = 25°C
100
-
-
%
-
2.9
-
V
-
0.25
-
V
1.2
-
-
V
-
-
0.4
V
-
2
-
µA
-
1
-
ms
-
88
-
%
-
91
-
%
-
94
-
%
-
89
-
%
Enable and undervoltage lockout
VUVLO
VENABLE
IENABLE
VIN undervoltage threshold
VIN increasing
VIN undervoltage hysteresis
EN threshold trip point
EN pin input current
Enable logic high voltage
TA = 25°C
Enable logic low voltage
TA = 25°C
TA = 25°C
Soft-Start
tSS
η
Soft-start time
Efficiency
VIN = 12V, VOUT = 3.3V,
IOUT = 2A, TA = 25°C
VIN = 12V, VOUT = 5V,
IOUT = 2A, TA = 25°C
VIN = 5V, VOUT = 3.3V,
IOUT = 500mA, TA = 25°C
VIN = 5V, VOUT = 3.3V,
IOUT = 2A, TA = 25°C
Input current
Efficiency
IQ
Input quiescent current
Switching, no load,
VIN = 12V, VOUT = 5V, TA = 25°C
-
2
-
mA
ISD
Shutdown quiescent input
current
EN = 0, TA = 25°C
-
2.1
-
µA
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WPMDL1201801 / 171021801
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
RELIABILITY
SYMBOL
MTBF
PARAMETER
Mean Time Between
Failures
-
TEST CONDITIONS
Confidence level 60%
Test temperature: 125°C
Usage temperature: 55°C
Activation energy: 1eV
Test duration: 1000 hours
Sample size: 62342
Fail: 0
MIN (1)
TYP (4)
MAX (1)
3.41·1010
UNIT
h
RoHS, REACh
RoHS
directive
Directive 2011/65/EU of the European Parliament and the Council of June
8th, 2011 on the restriction of the use of certain hazardous substances in
electrical and electronic equipment.
REACh
directive
Directive 1907/2006/EU of the European Parliament and the Council of
June 1st, 2007 regarding the Registration, Evaluation, Authorisation and
Restriction of Chemicals (REACh).
PACKAGE SPECIFICATIONS
MOLD COMPOUND
Part Number
Material
171021801
EME-G760L
WEIGHT
UL Class
UL94V-0
Certificate Number
E41429
0.8 g
NOTES
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed
through correlation using Statistical Quality Control (SQC) methods.
(2) The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per
JESD-22-114.
(3) JEDEC J-STD020
(4) Typical numbers are valid at 25°C ambient temperature and represent statistically the utmost probability assuming the
Gaussian distribution.
(5) Depending on heat sink design, number of PCB layers, copper thickness and air flow.
(6) Measured on a 8cm x 8cm four layer PCB, 35µm copper, thirty-six 10mil (254µm) thermal vias, no air flow (see
“OUTPUT POWER DERATING” section on page 12).
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
TYPICAL PERFORMANCE CURVES
If not otherwise specified, the following conditions apply: V IN = 12V, TAMB = 25°C.
RADIATED AND CONDUCTED EMISSIONS
70
Radiated Emissions 171021801 (3m Antenna Distance)
VIN = 12V, VOUT = 3.3V, ILOAD = 2A
with input filter 10µF (885012108021) and 10µH (74477510)
Horizontal
Vertical
Radiated Emissions [dBµV/m]
60
50 EN55022 Class A limit
40
EN55022 Class B limit
30
20
10
0
80
70
30
100
Frequency [MHz]
Conducted Emissions 171021801
VIN = 12V, VOUT = 3.3V, ILOAD = 2A with input filter 10µF (885012108021) and 10µH (74477510)
Average Quasi peak
60
Conducted Emissions [dBµV]
1000
EN55022 Class B Quasi Peak limit
50
EN55022 Class B Average limit
40
30
20
10
0
-10
0.15
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0.5
1
Frequency [MHz]
10
30
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WPMDL1201801 / 171021801
MagI3C Power Module
VDRM – Variable Step Down Regulator Module
EFFICIENCY
171021801 VIN = 12V, TA = 25 C
100
95
90
Efficiency [%]
85
80
Vout = 5V
75
Vout = 3.3V
70
Vout = 2.5V
65
Vout = 1.8V
60
55
50
0,00
0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
171021801 VIN = 12V, TA = 85 C
100
95
90
Efficiency [%]
85
80
Vout = 5V
75
Vout = 3.3V
70
Vout = 2.5V
65
Vout = 1.8V
60
55
50
0,00
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0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
EFFICIENCY
171021801 VIN = 5V, TA = 25 C
100
95
90
Efficiency [%]
85
80
75
Vout = 3.3V
70
Vout = 2.5V
Vout = 1.8V
65
60
55
50
0,00
0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
171021801 VIN = 5V, TA = 85 C
100
95
90
Efficiency [%]
85
80
75
Vout = 3.3V
70
Vout = 2.5V
Vout = 1.8V
65
60
55
50
0,00
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0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
POWER DISSIPATION
171021801 VIN = 12V, TA = 25 C
1,50
Power Dissipation [W]
1,25
1,00
Vout = 5V
0,75
Vout = 3.3V
Vout = 2.5V
0,50
Vout = 1.8V
0,25
0,00
0,00
0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
171021801 VIN = 12V, TA = 85 C
1,50
Power Dissipation [W]
1,25
1,00
Vout = 5V
0,75
Vout = 3.3V
Vout = 2.5V
0,50
Vout = 1.8V
0,25
0,00
0,00
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0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
POWER DISSIPATION
171021801 VIN = 5V, TA = 25 C
1,50
Power Dissipation [W]
1,25
1,00
Vout = 3.3V
0,75
Vout = 2.5V
Vout = 1.8V
0,50
0,25
0,00
0,00
0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
171021801 VIN = 5V, TA = 85 C
1,50
Power Dissipation [W]
1,25
1,00
Vout = 3.3V
0,75
Vout = 2.5V
Vout = 1.8V
0,50
0,25
0,00
0,00
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0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
OUTPUT POWER DERATING
171021801 Current Thermal Derating
VIN = 12V, VOUT = 5V, θJA = 22 C/W
2,5
Output current [A]
2,0
1,5
1,0
0,5
125 C
103 C
0,0
0
10
20
30
40
50
60
70
80
Ambient Temperature [ C]
90
100
110
120
130
171021801 Current Thermal Derating
VIN = 12V, VOUT = 3.3V, θJA = 22 C/W
2,5
Output current [A]
2,0
1,5
1,0
0,5
104 C
125 C
0,0
0
10
20
30
40
50
60
70
80
Ambient Temperature [ C]
90
100
110
120
130
The ambient temperature and the power limits of the derating curve represent the operation at the max junction temperature
specified in the “Operating Conditions” section on page 4.
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VDRM – Variable Step Down Regulator Module
LINE AND LOAD REGULATION
171021801 Line Regulation VOUT = 3.3V, IOUT = 2A , TA = 25 C
3,35
Output voltage [V]
3,34
3,33
3,32
3,31
3,30
4
6
8
10
12
Input Voltage [V]
14
16
18
171021801 Load Regulation VIN = 12V, VOUT = 5V, TA = 25 C
3,35
Output voltage [V]
3,34
3,33
3,32
3,31
3,30
0,0
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0,5
1,0
Output Current [A]
1,5
2,0
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VDRM – Variable Step Down Regulator Module
BLOCK DIAGRAM
VIN
1,2,3,4
3.3µH
VIN
10µF
VOUT
100nF
10µF
9,10,11,12
VOUT
10µF
PWM Modulator
Drivers
RFBT
Logic circuitries
OCP
ref.
UVLO
SS
OCP
detect
OTP
SS
FB
SHUT
SS
DOWN
SS
16 EN
13
EA
& comp.
network
COMP
OSCILLATOR
SS
SS
VREF
0.8V
RFBB
PGND
EP
CIRCUIT DESCRIPTION
The MagI³C Power Module series 171021801 is based on a synchronous step down regulator with integrated MOSFETs,
power inductor and both the input and the output capacitors. The control scheme is based on a peak Current Mode (CM)
regulation loop.
The VOUT of the regulator is divided by the feedback resistor divider and fed into the FB pin. The error amplifier compares
this signal with the internal 0.8V reference. The error signal is amplified and controls the on-time of a fixed frequency pulse
width generator. This signal drives the power MOSFETs.
The Current Mode architecture features a constant frequency during load steps. Only the on-time is modulated. It is
internally compensated and requires no additional external compensation network.
This architecture supports fast transient response and very small output ripple values (less than 15mV) are achieved only
relying on the integrated output capacitors.
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VDRM – Variable Step Down Regulator Module
DESIGN FLOW
The design flow for 171021801 consist of a single step: setting the output voltage trough the external resistor divider.
External input and output capacitors are not necessary
Essential Step
1.
Set the output voltage
VIN
1,2,3,4
VIN
VOUT
9,10,11,12
VOUT
RFBT
Module
1
NO NEED FOR CIN
16 EN
FB
13
NO NEED FOR COUT
PGND
EP
RFBB
GND
GND
Step 1 Set the output voltage (VOUT)
The output voltage is determined by a divider of two resistors connected between VOUT and ground. The midpoint of the
divider is connected to the FB input. The output voltage adjustment range is from 0.8V to 17V.
The ratio of the feedback resistors for the desired output voltage is:
RFBT
VOUT
= (
) -1
RFBB
VFB
(1)
A table of values for RFBT and RFBB, is included in the “TYPICAL SCHEMATIC” section (page 35).
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
Optional Steps
2.
3.
Add external input capacitors (in case an input voltage ripple reduction is required)
Add external output capacitors (in case an output voltage ripple reduction or output voltage under- or overshoot
reduction load transient are required)
1,2,3,4
VIN
VIN
VOUT
9,10,11,12
RFBT
Module
16 EN
C1
VOUT
FB
13
C2
2
3
PGND
EP
GND
RFBB
GND
C1 and C2 normally not necessary
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MagI3C Power Module
VDRM – Variable Step Down Regulator Module
Step 2 Select the input capacitor (CIN)
The 171021801 integrates already a 10µF MLCC as input capacitor in parallel with a 100nF MLCC. These capacitors are
enough to fulfil the targeted steady state and transient response under all operating conditions.
The resulting input voltage ripple with the internal input capacitors (VIN ripple,INT) is shown in the figure below:
VIN = 12V, VOUT = 3.3V, IOUT = 2A
300
250
200
Input Voltage Ripple [mV]
150
100
50
0
-50
-100
150mV
-150
-200
-250
-300
0
2
4
6
Time [µs]
8
10
12
If the application has more demanding requirements in terms of input voltage ripple, an external input capacitor can be
placed.
The input capacitor selection is generally based on different requirements. The first criterion is the input current ripple. Worst
case input current ripple rating is dictated by the equation:
ICINRMS ≈
1
D
∙I
∙√
2 OUT 1-D
(2)
where
D≈
VOUT
VIN
As a point of reference, the worst case current ripple will occur when the module is presented with full load current and when
VIN = 2 x VOUT.
The second criterion is the input voltage ripple. If the system design requires a certain minimum value of peak-to-peak input
voltage ripple then the following equation may be used:
CIN ≥
fSW(CCM)
IOUT ∙ D ∙ (1-D)
∙ (VIN ripple − ESR∙IOUT ∙ D )
(3)
The value of the additional external input capacitor (C IN,EXT) in case a further reduction of the input voltage ripple is required
can be calculated with the following equation:
CIN,EXT ≥
IOUT ∙ D ∙ (1-D)
- CIN,INT
fSW(CCM) ∙ (VIN ripple − ESR∙IOUT ∙ D )
(4)
where the VIN ripple is the required input voltage ripple and CIN,INT represents the total integrated input capacitance (in this
case 10µF+100nF).It is always strongly recommended to pay attention to the voltage and temperature derating of the
selected capacitor.
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Example
VIN = 12V, VOUT = 3.3V, IOUT = 2A, VIN ripple ≤ 90mV.
The duty cycle is theoretically defined as the ratio between the output and the input voltage. Actually, a correct estimate of
the duty cycle should consider also the efficiency, as shown by the following formula:
D=
VOUT
VIN ∙ 𝜂
(5)
where 𝜂 represents the efficiency and its value under the specified conditions can be read on the diagram on page 8 (88%).
The equation (4) can be used to calculate the additional external capacitor to achieve the target input voltage ripple.
The actual value of the integrated capacitance (CIN,INT) can be estimated by using capacitance derating diagram of the
internal capacitor shown below.
12
11
Actual Input Capacitance [µF]
10
9
8
7
6
4.7µF
5
4
3
2
1
0
0
3
6
9
Input Voltage [V]
12
15
18
From the diagram above, the actual capacitance value of 4.7µF can be read.
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Now equation (4) can be finally used to calculate the required external input capacitor to fulfil the input voltage ripple
requirements, assuming ESR = 5mΩ:
CIN,EXT =
2A∙0.312∙(1-0.312)
- 4.7μF = 1.1μF
850kHz ∙(0.09V- 0.005Ω∙2A∙0.312)
Some margin from the calculated CIN,ext value is recommended in order to take into account:
-
Approximations within the equations to calculate CIN;
Tolerances and variations of some components and parameters involved in those equations (e.g. fSW, ESR, etc.)
Derating of the capacitors with DC applied voltage and temperature
A 4.7µF MLCC (Würth Elektronik 885012109012) is selected as CIN,EXT. The resulting input voltage ripple using the
additional input capacitor is depicted by the figure below.
VIN = 12V, VOUT = 3.3V, IOUT = 2A
300
250
200
Intput Voltage Ripple [mV]
150
100
50
0
-50
85mV
-100
-150
-200
-250
-300
0
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2
4
6
Time [µs]
8
10
12
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Step 3 Select output capacitor (COUT)
The output capacitance determines the performance in terms of output voltage ripple as well as load transient response.
The 171021801 integrates already two MLCC of 10µF as output capacitors, which are enough to operate under all
conditions. Therefore no external additional output capacitor is necessary.
Output voltage ripple
The output capacitor should be selected in order to minimize the output voltage ripple and provide a stable voltage at the
output. In general, under steady state conditions the output voltage ripple observed at the output can be defined as:
VOUTripple =∆IL ∙ ESR+∆IL ∙
1
8∙fSW ∙COUT
(6)
where ∆IL is the inductor current ripple, calculated with the following equation:
∆IL =
VOUT ∙ (VIN -VOUT )
fSW ∙ L ∙ VIN
(7)
The output voltage ripple achievable with the integrated output capacitors only (VOUTripple, int) is around 15mV, as shown by
the figure below.
VIN = 12V, VOUT = 3.3V, IOUT = 2A
30
Output Voltage Ripple [mV]
20
10
0
15mV
-10
-20
-30
0
1
2
3
Time [µs]
4
5
6
In case the application has more demanding requirements in terms of output voltage ripple, additional external capacitors
should be used. The value of the external additional capacitance (COUT,INT) can be calculated using the following equation:
COUT,EXT ≥
∆IL
− COUT, INT
8 ∙ (VOUTripple - ESR∙∆IL ) ∙ fSW
(8)
where VOUTripple represents the target output voltage ripple whereas COUT,INT indicates the total amount of the integrated
capacitance (20µF).
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Example
VIN = 12V, VOUT = 3.3V, IOUT = 2A (this parameter does not influence the output voltage ripple).
First of all the actual value of the integrated output capacitance must be estimated, using the derating curve below:
12
11
Actual Output Capacitance [µF]
10
10.4µF
9
8
7
6
5
4
3
2
1
3.3V
0
0
3
6
9
Output Voltage [V]
12
15
18
At VOUT = 3.3V the value of the output capacitance is not reduced due to the voltage, it is instead slightly higher.
Nevertheless, a total value of 20µF can be considered for COUT, INT.
Assuming that the application requires an output voltage ripple less than 10mV, the additional external capacitance should
be at least 2µF, according to equation (8):
COUT,EXT ≥
0.853A
- 20μF = 2μF
8 ∙(0.01V - 0.005Ω∙0.853A) ∙ 0.85 MHz
where a value of ESR of 5mΩ is assumed and ∆IL = 0.853A is the inductor current ripple calculated with the equation (7).
Some margin from the calculated COUT,ext value is recommended in order to take into account:
-
Approximations within the equations to calculate COUT;
Tolerances and variations of some components and parameters involved in those equations (e.g. f SW, ESR, etc.)
Derating of the capacitors with DC applied voltage and temperature
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An additional external capacitor of 10µF (Würth Elektronik 885012208069) has been selected as the best performing.
The resulting output voltage ripple is shown in the figure below.
VIN = 12V, VOUT = 3.3V, IOUT = 2A
30
Output Voltage Ripple [mV]
20
10
0
9mV
-10
-20
-30
0
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1
2
3
Time [µs]
4
5
6
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Load transient response
The output voltage is also affected by load transients (see picture below).
When the output current transitions from a low to a high value, the voltage at the output capacitor (VOUT) drops. This involves
two contributing factors. One is caused by the voltage drop across the ESR (V ESR) and depends on the slope of the rising
edge of the current step (trise). For low ESR values and small load current trasnients, this is often negligible. It can be
calculated as follows:
VESR = ESR ∙ ∆IOUT
(9)
where ∆IOUT is the load step, as shown in the picture below (simplified: no voltage ripple is shown).
IOUT
∆IOUT
0
trise
t
VOUT
VESR
∆VOUT
Vdischarge
0
t
td
treg
The second contributing factor is the voltage drop due to discharge of the output capacitor, which can be estimated as:
Vdischarge =
∆IOUT ∙ td
2 ∙ COUT
(10)
In a current mode architecture the td is strictly related to the bandwidth of the regulation loop and influenced by the C OUT
(increasing COUT, the td increases as well).
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The figures below show the load transient response achieved with the integrated capacitors only.
Load Transient from 0.5A to 2A
3
300
IOUT2
2
100
VOUT
0
∆VOUT = 110mV
1
-100
IOUT1
-200
Output Voltage AC [mV]
Output Current [A]
200
td = 4.8µs
0
-300
0
40
80
120
Time [µs]
160
200
240
Load Transient from 2A to 0.5A
3
300
200
IOUT1
2
100
∆VOUT = 120mV
VOUT
0
1
-100
IOUT2
Output Voltage AC [mV]
Output Current [A]
td = 4.8µs
-200
0
-300
0
40
80
120
Time [µs]
160
200
240
If the application demands a lower undershoot or overshoot, an additional external capacitance is necessary. In order to
choose the value of the external output capacitor COUT,EXT, the following steps should be utilized:
1.
2.
3.
Measure td.
Calculate the appropriate value of COUT,EXT for the maximum voltage drop Vdischarge allowed at a defined load step,
using the following equation (11), derived from equation (10).
As mentioned above, changing COUT affects also td. Therefore, a new measurement should be performed and, if
necessary, the step 1 and 2 should be repeated (it is an iterative process and few steps could be required).
COUT,EXT ≥
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∆IOUT ∙ td
- COUT,INT
2 ∙ Vdischarge
(11)
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Example
The following application conditions are used as an example to show how to calculate a suitable COUT,EXT value, in case the
application requirements demand a further reduction of the overshoot and undershoot of the output voltage after the load
transient.
-
VIN = 12V
VOUT = 3.3V
load transient from 0.5A to 2A and vice versa (∆IOUT = 1.5A)
max allowed undershoot or overshoot ∆VOUT = 100mV
Using equation (11), the value of the additional capacitor COUT,EXT can be calculated. As explained above, some iterations
are necessary in order to find the most suitable value because any change in the output capacitance affects td, which is in
turn involved in determining the value of COUT,EXT, and so on.
A combination of two MLCC of 22µF (Würth Elektronik 885012109014) are selected.
The load transients with the selected COUT,EXT can be tested using the setup depicted below:
VIN
VIN
VOUT
MagI³C Power
Module
COUT,EXT
RLoad1
6.6Ω
RLoad2
2.2Ω
GND
IOUT1
IOUT2
Q1
GND
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The load transient response results with the additional external C OUT,EXT = 2x22µF are shown below. For both the positive
(from 0.5A to 2A) and negative (from 0.5A to 2A) load transients the undershoot and the overshoot respectively are within
the target defined for this example.
Load Transient from 0.5A to 2A
3
300
IOUT2
2
100
VOUT
0
∆VOUT = 95mV
1
-100
IOUT1
-200
0
Output Voltage AC [mV]
Output Current [A]
200
-300
0
40
80
120
Time [µs]
160
200
240
Load Transient from 2A to 0.5A
3
300
IOUT1
2
100
∆VOUT = 100mV
VOUT
0
1
-100
IOUT2
-200
0
-300
0
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Output Voltage AC [mV]
Output Current [A]
200
40
80
120
Time [µs]
160
200
240
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ENABLE
The enable function allows the device to be put into shutdown mode. Driving the EN pin with a voltage lower than 0.4V
disables the device and reduces dramatically the input current consumption (typ 2.1µA), while driving the EN pin with a
voltage higher than 1.2V enables the device. An internal pull-down resistor ensures that the device is disabled also when the
EN pin is left floating. The EN pin is also VIN compatible.
1,2,3,4
VIN
1,2,3,4
VIN
VIN
Module
1,2,3,4
VIN
VIN
Module
J1
Module
J1
16 EN
Jumper to VIN
VIN
J1
16 EN
16 EN
No jumper
(EN floating)
Jumper to GND
GND
GND
GND
17
17
17
GND
GND
GND
MODULE ENABLED
MODULE DISABLED
MODULE DISABLED
SOFT-START
The 171021801 implements an internal soft-start (see figure below) in order to limit the inrush current and avoid output
voltage overshoot during start-up.
The soft-start is implemented by ramping the reference voltage (non-inverting input of the error amplifier) from 0V to 0.8V in
around 1ms (typical duration of the soft-start).
Output Voltage at Start Up - VIN = 12V, VOUT = 3.3V
6,0
6,0
ENABLE
5,0
4,0
4,0
VOUT
3,0
3,0
2,0
2,0
1,0
Output Voltage [V]
EN pin Voltage [V]
5,0
1,0
tSS
0,0
0,0
0
1
2
3
4
5
Time [ms]
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LIGHT LOAD OPERATION
Under light load operation, the device switch from in Continuous Conduction Mode (CCM) to Discontinuous Conduction
Mode (DCM). The load current where the transition between DCM and CCM takes place can be estimated using the
following formula:
IOUT(DCM) =
VOUT
)
VIN
2∙fSW ∙L
VOUT ∙ (1-
(12)
The figures below show the device working in CCM and DCM.
Inductor Current Ripple VIN = 12V, VOUT = 3.3V, IOUT = 500mA, CCM Operation
1,50
Inductor Current [A]
1,25
1.2µs → 850kHz
1,00
0,75
0,50
0,25
0,00
-0,25
-0,50
0
2
4
6
Time [µs]
8
10
12
10
12
Inductor Current Ripple VIN = 12V, VOUT = 3.3V, IOUT = 200mA, DCM Operation
1,00
Inductor Current [A]
0,75
1.2µs → 850kHz
0,50
0,25
0,00
-0,25
-0,50
0
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2
4
6
Time [µs]
8
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If the load current is further reduced, the device decreases the switching frequency in order to limit the energy transferred to
the output (to both capacitor and load) and therefore keeping the output voltage regulated. The frequency reduction is shown
in the figures below.
Inductor Current Ripple VIN = 12V, VOUT = 3.3V, IOUT = 40mA, DCM Operation
1,00
Inductor Current [A]
0,75
0,50
2.3µs → 440kHz
0,25
0,00
-0,25
-0,50
0
2
4
6
Time [µs]
8
10
12
10
12
Inductor Current Ripple VIN = 12V, VOUT = 3.3V, IOUT = 20mA, DCM Operation
1,00
Inductor Current [A]
0,75
0,50
4.6µs → 220kHz
0,25
0,00
-0,25
-0,50
0
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2
4
6
Time [µs]
8
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DROPOUT OPERATION
The dropout voltage is generally defined as the minimum voltage drop between the input and the output voltages necessary
to keep the output voltage regulated. It is usually defined for linear regulators, but it applies also to DC-DC converters when
they operate at 100% duty cycle.
The 171021801 integrates a p-channel MOSFET as high-side switch. Therefore this module does not need any bootstrap
circuitry to create the gate voltage used for driving an n-channel MOSFET. The implementation of a p-channel MOSFET as
high-side results in:
-
there is no minimum off-time, normally necessary to provide the bootstrap circuitry with sufficient voltage
the duty cycle can reach 100%, allowing the output voltage regulation even with a very limited voltage dropout
As the input voltage decreases and becomes closer to the output voltage, the duty-cycle rises and reaches then 100%.
The voltage dropout in case of 100% duty cycle operation depends fundamentally on the RDSon (resistance of the MOSFET
when turned on) of the high-side MOSFET,on the DC resistance of the inductor (DCR) and on the load current.
The curve below shows the relation between the dropout voltage and the load current.
VOUT = 12V, VOUT = 5V
500
Dropout voltage [mV]
400
300
200
100
Ta = 25°C
0
0,00
Ta = 85°C
0,50
1,00
1,50
2,00
Output current [A]
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PROTECTING FEATURES
Overcurrent protection (OCP)
The overcurrent protection is implemented by sensing the peak current in the high-side power MOSFET during the on-time.
When the peak current exceeds the current limit threshold (I CL, see ELECTRICAL SPECIFICATIONS on page 5) the highside MOSFET is immediately turned off. The current flows through the low-side MOSFET for the remaining time of the
period (see figure below).
IL
IC L
IO UT _M AX
IO UT
over curr ent e vent
t
During overcurrent condition, the duty cycle is no longer determined by the control loop, it is instead limited by the current
limit threshold. Therefore, the output voltage is out of regulation and drops (see figure below).
If the voltage at the feedback pin falls below 0.3V, the switching frequency (typ. 850kHz) is reduced to one fourth of the
default value and the current limit threshold is folded back to 2A. This additional countermeasure prevents the module and
the load from being overstressed by a severe overload condition.
The overcurrent threshold foldback is inhibited during the startup, hence allowing the output voltage to properly rise even in
case of big output capacitors, which require a high current to be charged.
Foldback of
the current
limit
Overcurrent
protection
IOUT
VOUT drops due to
the reduced duty
cycle operation
VOUT
switch node
t
Normal operation
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Reduced duty
cycle operation
Reduced f SW operation
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Short circuit protection
In case of short circuit condition, the module is protected by the current protection mechanism explained in the previous
section. Since a short circuit is present at the output, the voltage at the feedback pin is surely below 0.3V. Therefore the
current fold-back and the switching frequency reduction described above will take place after few switching cycles, as shown
in the figure below.
Current limit
threshold
Current limit
reduced to 2A
Short circuit
event
IL
VOUT
VOUT value
corresponding to
VFB=0.3V
t
Overtemperature protection (OTP)
The overtemperature protection helps to prevent catastrophic failures in case of accidental device overheating.
The junction temperature of the 171021801 should not be allowed to exceed its maximum rating. Thermal protection is
implemented by an internal thermal shutdown circuit which activates at 150°C (typ.) causing the device to stop switching. In
this state the VOUT drops and additionally the internal soft-start capacitor is discharged. When the junction temperature falls
back below approximately 135°C (typical hysteresis = 15°C) the soft-start circuitry is re-activated, VOUT rises smoothly, and
normal operation resumes.
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DETERMINE POWER LOSSES AND THERMAL REQUIREMENTS OF THE BOARD
This section provides an example of estimation of power losses and definition of the thermal performance of the board.
As a starting point, the following application conditions can be considered:
VIN =12V, VOUT =3.3V, IOUT =2A, TA(MAX) =85 C and TJ(MAX) =125 C
where TA is the maximum air temperature surrounding the module and TJ(MAX) is the maximum value of the junction
temperature according to the limits in the “OPERATING CONDITIONS” section on page 4.
The goal of the calculation is to determine the junction to ambient thermal resistance (θJA ) that can be used to define the
characteristics of the PCB on which the device will be mounted.
The basic formula for calculating the operating junction temperature TJ of a semiconductor device is as follows:
TJ = PLOSS_TOT ∙ θJA + TA
(13)
PLOSS_TOT are the total power losses within the module and are related to the operating conditions and ƟJA is the junction to
ambient thermal resistance, defined as:
θJA = θJC + θCA
(14)
where ƟJC is the junction to case thermal resistance and ƟCA is the case to ambient thermal resistance.
From equation (13) the target junction to ambient thermal resistance can be derived:
θJA(MAX) <
TJ(MAX) -TA(MAX)
PLOSS_TOT
(15)
From the power dissipation´s diagram on page 10 (here below reported) a power loss of 1.16W is read.
171021801 VIN = 12V, TA = 85 C
1,50
Power Dissipation [W]
1,25
1.16W
1,00
Vout = 5V
0,75
Vout = 3.3V
Vout = 2.5V
0,50
Vout = 1.8V
0,25
0,00
0,00
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0,25
0,50
0,75
1,00
1,25
Output Current [A]
1,50
1,75
2,00
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Entering the values in formula (15) results in:
θJA(MAX) <
125 C-85 C
= 34.5 C/W
1.16W
In order to fulfil the application conditions mentioned above, the PCB should at least provide a junction to ambient thermal
resistance of 34.5°C/W.
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TYPICAL SCHEMATIC
1,2,3,4
VIN
VIN
VOUT
9,10,11,12
RFBT
Module
16 EN
VOUT
FB
13
GND
RFBB
17
GND
GND
Quick setup guide
Conditions: TA = 25°C, IOUT = 2A
Recommended component values
VOUT
12V
9V
5V
3.3V
2.5V
1.8V
RFBT
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
RFBB (E96 series)
715Ω
976
1.87kΩ
3.16kΩ
4.64kΩ
7.87kΩ
VIN
12.7V – 18V
9.7V – 18V
5.7V – 18V
4V – 18V
4V – 18V
4V – 18V
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LAYOUT RECOMMENDATION
PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC
converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These
can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. A good layout can be
implemented by following simple design rules.
Due to the integration of both the input and the output capacitors the user does not need to take care anymore of the
switched current loops. The most critical paths, due to discontinuous current flows, are within the module and are already
optimized in terms of EMI.
VIN
1,2,3,4
VIN
VOUT
9,10,11,12
Module
VOUT
RFB T
FB 13
EN
PGND
16
EP
RFB B
GND
GND
The only external components necessary to operate the 171021801 that must be placed on the PCB are the resistors of the
output voltage divider, as shown in the picture above.
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1: Feedback layout
Bottom
GROUND PLANE
VIN
RFBB
VIN
1
VIN
2
VIN
3
VIN
4
RFBT
EN
NC
NC
FB
16
15
14
13
PGND
PGND
PGND
PGND
5
6
7
8
NC
NC
3
NC
NC
GND
12
VOUT
11
VOUT
10
VOUT
9
VOUT
VOUT
GND
MagI C Module
PCB color coding:
Top layer
Bottom layer
The resistor divider (RFBT and RFBB) should be located close to the FB pin. Since the FB node is high impedance, the trace
thickness should be kept small. The traces from the FB pin to the middle point of the resistor divider should be as short as
possible. The upper terminal of the output resistor divider (where the V OUT is applied) should have a short connection to the
VOUT pins, where internally are integrated the output capacitors.
2: Ground (PGND) connection of the resistor divider
Bottom
GROUND PLANE
VIN
VIN
GND
RFBB
1
RFBT
EN
NC
NC
FB
16
15
14
13
PGND
PGND
12
VOUT
VIN
2
11
VOUT
VIN
3
10
VOUT
VIN
4
9
VOUT
PGND
PGND
5
6
7
8
NC
NC
3
NC
NC
VOUT
GND
MagI C Module
The ground connection of the lower resistor of the output voltage divider (RFBB) should be routed to the PGND pins of the
device. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple
behavior.
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3: Make input and output bus connections as wide as possible
Bottom
GROUND PLANE
VIN
GND
RFBB
VIN
1
VIN
2
VIN
3
VIN
4
RFBT
EN
NC
NC
FB
16
15
14
13
PGND
PGND
PGND
PGND
5
6
7
8
NC
NC
3
NC
NC
12
VOUT
11
VOUT
10
VOUT
9
VOUT
VOUT
GND
MagI C Module
This reduces any voltage drops on the input or output of the converter and maximizes efficiency.
4: Place array of heat-sinking vias
Use an array of heat-sinking vias to connect the PGND pad to the ground plane on the bottom PCB layer. If the PCB has
multiple of copper layers, these thermal vias can also be used to make a connection to the heat-spreading ground planes
located on inner layers.
0.762
0.762
0.55
0.3
All dimension are in mm
For best result, use a thermal via array as proposed in the picture above with drill of max 300µm, spaced 762µm apart.
Ensure enough copper area is used for heat-sinking, to keep the junction temperature below 125°C.
Connecting the NC pins (5,6,7,8) to the the GND layer helps dissipating the heat.
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5: Isolate high noise areas
Bottom
GROUND PLANE
RFBB RFBT
VIN
1
VIN
2
VIN
3
VIN
4
EN
NC
NC
FB
16
15
14
13
PGND
PGND
PGND
PGND
5
6
7
8
NC
NC
NC
NC
12
VOUT
11
VOUT
10
VOUT
9
VOUT
MagI3C Module
Place a dedicated solid ground copper area beneath the MagI³C Power Module.
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EVALUATION BOARD SCHEMATIC (178021801 v.1.0)
Lf
1,2,3,4
VIN
R1
VIN
VOUT
9,10,11,12
VOUT
RFBT
Module
J1
C1
+
Cf
C2
16 EN
FB
13
C5
optiona l
optiona l
+
C6
+
optiona l
C7
optiona l
GND
RFBB
17
GND
GND
Optional input filter
The 171021801 integrates both the input and output capacitors. Therefore, additional external input/output capacitors are
normally not required.
The additional 220µF aluminum electrolytic capacitor C1 is mounted as termination of the supply line and provides a slight
damping of possible oscillations of the series resonance circuit represented by the inductance of the supply line and the
input capacitance.
The additional MLCC Cf is part of the input filter and is not mounted on the board. The inductor Lf is not mounted too (see
recommended part number in the table below). A zero ohm resistor (R1) is mounted in parallel with L f. In case the input filter
is placed, R1 must be removed and an appropriate Lf mounted.
Although the 171021801 do not need any external output capacitor, in case particular application requirements are
demanding additional capacitance, the evaluation board gives the possibility to place further capacitors at the output: C5
(MLCC), C6 (surface mounted electrolytic) and C7 (through hole electrolytic).
Bill of Material
Designator
IC1
C1
C2
C5
C6
C7
Cf
Lf
R1
RFBT
RFBB
Description
MagI3C Power Module
Aluminum electrolytic capacitor, ATG5 family, 220μF/25V
Ceramic chip capacitor (not mounted)
Ceramic chip capacitor (not mounted)
Surface mounted electrolytic (not mounted)
Through hole electrolytic (not mounted)
Ceramic chip capacitor 10µF/25V X5R, 1206 (not mounted)
Filter inductor, 10µH, PD2 (not mounted)
SMD bridge 0Ω resistance
10kΩ
715 Ω for VOUT = 12V
976 Ω for VOUT = 9V
1.87 kΩ for VOUT = 5V
Set
3.16 kΩ for VOUT = 3.3V
by
4.64 kΩ for VOUT = 2.5V
jumper
7.87 kΩ for VOUT = 1.8V
For adjustable VOUT: RFBB =
J1
RFBT ∙0.8V
VOUT -0.8V
Jumper for ENABLE connection to either VIN or GND
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Quantity
1
1
optional
optional
optional
optional
optional
optional
1
1
1
1
1
1
1
1
Order Code
171021801
860020474012
Manufacturer
Würth Elektronik
Würth Elektronik
885012108021
74477510
Würth Elektronik
Würth Elektronik
optional
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Filter suggestion for conducted EMI
The input filter shown in the schematic below is recommended to achieve conducted compliance according to EN55022
Class B (see results on page 7).
For radiated EMI the input filter is not necessary. It is only used to comply with the setup recommended by the norms.
Lf
VIN
VIN
Power Module
Cf
GND
GND
Input LC Filter
Bill of Material of the Input LC Filter
Designator
Description
Order Code
Manufacturer
Cf
Filter ceramic chip capacitor 10μF/25V X5R, 1206
885012108021
Würth Elektronik
Lf
Filter inductor, 10µH, PD2 family
74477510
Würth Elektronik
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HANDLING RECOMMENDATIONS
1.
The power module is classified as MSL3 (JEDEC Moisture Sensitivity Level 3) and requires special handling due to
moisture sensitivity (JEDEC J-STD033).
The parts are delivered in a sealed bag (Moisture Barrier Bags = MBB) and should be processed within one year.
When opening the moisture barrier bag check the Humidity Indicator Card (HIC) for color status. Bake parts prior to
soldering in case indicator color has changed according to the notes on the card.
Parts must be processed after 168 hour (7 days) of floor life. Once this time has been exceeded, bake parts prior to
soldering per JEDEC J-STD033 recommendation.
2.
3.
4.
SOLDER PROFILE
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Only Pb-Free assembly is recommended according to JEDEC J-STD020.
Measure the peak reflow temperature of the MagI³C power module in the middle of the top view.
Ensure that the peak reflow temperature does not exceed 235°C ±5°C as per JEDEC J-STD020.
The reflow time period during peak temperature of 235°C ±5°C must not exceed 20 seconds.
Reflow time above liquidus (217°C) must not exceed 60 seconds.
Maximum ramp up is rate 3°C per second
Maximum ramp down rate is 3°C per second
Reflow time from room (25°C) to peak must not exceed 8 minutes as per JEDEC J-STD020.
Maximum numbers of reflow cycles is two.
For minimum risk, solder the module in the last reflow cycle of the PCB production.
For soldering process please consider lead material copper (Cu) and lead finish tin (Sn).
For solder paste use a standard SAC Alloy such as SAC 305, type 3 or higher.
Below profile is valid for convection reflow only
Other soldering methods (e.g.vapor phase) are not verified and have to be validated by the customer on his own
risk
Temperature [°C]
Max 240
217
Max 20 sec
Peak
Ramp Up Rate
Max 3°C/sec
Liquidus
Ramp Down Rate
Max 3°C/sec
Max 60 sec
Min 40 sec
200
150
235°C
Preheat
Max 90 sec
Min 60 sec
Max 2 solder cycles !
Time [sec]
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PHYSICAL DIMENSIONS
Package type: LGA-16EP
All dimensions are in mm
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RECOMMENDED LAND PATTERN DESIGN
All dimensions are in mm
RECOMMENDED SOLDER STENCIL DESIGN
All dimensions are in mm
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PACKAGING
Reel (mm)
20P
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Tape (mm)
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DOCUMENT HISTORY
Revision
Date
Description
1.0
January 2018
Release of the final version
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CAUTIONS AND WARNINGS
The following conditions apply to all goods within the product series of MagI³C of
Würth Elektronik eiSos GmbH & Co. KG:
General:
All recommendations according to the general technical specifications of the datasheet have to be complied with.
The usage and operation of the product within ambient conditions which probably alloy or harm the component surface has
to be avoided.
The responsibility for the applicability of customer specific products and use in a particular customer design is always within
the authority of the customer. All technical specifications for standard products do also apply for customer specific products.
Residual washing varnish agent that is used during the production to clean the application might change the characteristics
of the body, pins or termination. The washing varnish agent could have a negative effect on the long term function of the
product.
Direct mechanical impact to the product shall be prevented as the material of the body, pins or termination could flake or in
the worst case it could break. As these devices are sensitive to electrostatic discharge customer shall follow proper IC
Handling Procedures.
Customer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related
requirements concerning its products, and any use of Würth Elektronik eiSos GmbH & Co. KG components in its
applications, notwithstanding any applications-related information or support that may be provided by Würth Elektronik eiSos
GmbH & Co. KG. Customer represents and agrees that it has all the necessary expertise to create and implement
safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences lessen the
likelihood of failures that might cause harm and take appropriate remedial actions. Customer will fully indemnify Würth
Elektronik eiSos and its representatives against any damages arising out of the use of any Würth Elektronik eiSos GmbH &
Co. KG components in safety-critical applications.
Product specific:
Follow all instructions mentioned in the datasheet, especially:
The solder profile has to comply with the technical reflow or wave soldering specification, otherwise this will void the
warranty.
All products are supposed to be used before the end of the period of 12 months based on the product date-code.
Violation of the technical product specifications such as exceeding the absolute maximum ratings will void the warranty.
It is also recommended to return the body to the original moisture proof bag and reseal the moisture proof bag again.
ESD prevention methods need to be followed for manual handling and processing by machinery.
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IMPORTANT NOTES
The following conditions apply to all goods within the product range of Würth Elektronik eiSos GmbH & Co. KG:
1. General Customer Responsibility
Some goods within the product range of Würth Elektronik eiSos GmbH & Co. KG contain statements regarding general
suitability for certain application areas. These statements about suitability are based on our knowledge and experience of
typical requirements concerning the areas, serve as general guidance and cannot be estimated as binding statements about
the suitability for a customer application. The responsibility for the applicability and use in a particular customer design is
always solely within the authority of the customer. Due to this fact it is up to the customer to evaluate, where appropriate to
investigate and decide whether the device with the specific product characteristics described in the product specification is
valid and suitable for the respective customer application or not. Accordingly, the customer is cautioned to verify that the
datasheet is current before placing orders.
2. Customer Responsibility related to Specific, in particular Safety-Relevant Applications
It has to be clearly pointed out that the possibility of a malfunction of electronic components or failure before the end of the
usual lifetime cannot be completely eliminated in the current state of the art, even if the products are operated within the
range of the specifications. In certain customer applications requiring a very high level of safety and especially in customer
applications in which the malfunction or failure of an electronic component could endanger human life or health it must be
ensured by most advanced technological aid of suitable design of the customer application that no injury or damage is
caused to third parties in the event of malfunction or failure of an electronic component.
3. Best Care and Attention
Any product-specific notes, warnings and cautions must be strictly observed.
4. Customer Support for Product Specifications
Some products within the product range may contain substances which are subject to restrictions in certain jurisdictions in
order to serve specific technical requirements. Necessary information is available on request. In this case the field sales
engineer or the internal sales person in charge should be contacted who will be happy to support in this matter.
5. Product R&D
Due to constant product improvement product specifications may change from time to time. As a standard reporting
procedure of the Product Change Notification (PCN) according to the JEDEC-Standard we inform about minor and major
changes. In case of further queries regarding the PCN, the field sales engineer or the internal sales person in charge should
be contacted. The basic responsibility of the customer as per Section 1 and 2 remains unaffected.
6. Product Life Cycle
Due to technical progress and economical evaluation we also reserve the right to discontinue production and delivery of
products. As a standard reporting procedure of the Product Termination Notification (PTN) according to the JEDECStandard we will inform at an early stage about inevitable product discontinuance. According to this we cannot guarantee
that all products within our product range will always be available. Therefore it needs to be verified with the field sales
engineer or the internal sales person in charge about the current product availability expectancy before or when the product
for application design-in disposal is considered. The approach named above does not apply in the case of individual
agreements deviating from the foregoing for customer-specific products.
7. Property Rights
All the rights for contractual products produced by Würth Elektronik eiSos GmbH & Co. KG on the basis of ideas,
development contracts as well as models or templates that are subject to copyright, patent or commercial protection
supplied to the customer will remain with Würth Elektronik eiSos GmbH & Co. KG. Würth Elektronik eiSos GmbH & Co. KG
does not warrant or represent that any license, either expressed or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right relating to any combination, application, or process in which Würth
Elektronik eiSos GmbH & Co. KG components or services are used.
8. General Terms and Conditions
Unless otherwise agreed in individual contracts, all orders are subject to the current version of the “General Terms and
Conditions of Würth Elektronik eiSos Group”, last version available a
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