X88064

APPLICATION NOTE A V A I LABLE Application Brief iAPX88/188, MCS 196, MCS51 Compatible* 64K X88064 E2 Microcontroller Peripheral 8192 x 8 Bit • Block Lock Write Control —Eight 1K Byte Blocks - Lockable Independently or in Combination • Multiplexed Address/Data Bus —Direct Interface to Popular Microcontrollers • High Performance CMOS —Fast Access Times, 60ns and 80 ns —Low Power - 30mA Active Maximum - 150µ A Standby Maximum • Software Data Protection • Toggle Bit Polling —Early End of Write Detection • Page Mode Write —Allows up to 32 Bytes to be Written in One Write Cycle DESCRIPTION The X88064 is a high speed byte wide microperipheral device with eight 1K byte blocks of E2PROM and can be directly connected to industry standard high performance microprocessors. This peripheral provides two levels of memory write control, the standard Software Data Program (SDP) control and Block Lock. Block Lock provides a higher level of memory write control above SDP. This allows the software developer to partition any or all of the eight 1K byte blocks as In-Circuit Programmable ROM (ICPROM). Once locked, a block of memory must first be unlocked before being written. Not even a write operation using the SDP sequence will change the contents of a locked block. Since a distinct, 6 byte, software command sequence locks and unlocks the memory, the software developer has complete control of the memory contents. BLOCK LOCK CONTROL LOGIC INDIVIDUALLY LOCKABLE A/D0–A/D7 L A T C H D E C O D E R E2 PROM ARRAY A8–A12 ALE 1Kx8 BLOCKS WR RD PSEN CE WC INTERFACE CONTROL SOFTWARE DATA PROTECT (SDP) WE OE BUS TRANSCEIVER POWER-ON RESET AND VCC SENSE A/D0–A/D7 ©Xicor, Inc. 1994, 1995, 1996 Patents Pending * All other brand and product names may be trademarks or registered trademarks of their respective companies. 7023-2.3 1/29/97 T0/C2/D0 SH 1 Characteristics subject to change without notice X88064 Software Data Program Control provides a lower level of memory write management. SDP controls write operations to the entire memory. When enabled, the host microprocessor must send a special 3 byte command sequence before any byte or page writes to unlocked locations in the memory. Pin configuration DIP/SOIC NC A12 NC NC WC PSEN A/D0 A/D1 A/D2 A/D3 A/D4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 X88064 24 23 22 21 20 19 18 17 16 15 14 13 VCC WR ALE A8 A9 A11 RD A10 CE A/D7 A/D6 A/D5 7023 FRM F02 PIN NAMES PIN NAME PSEN I/O I DESCRIPTION Content of E2 memory can be read by lowering the PSEN and holding both RD and WR HIGH. The device then places on the data bus (AD0–AD7) the contents of E2 memory at the latched address. Non-multiplexed high-order Address Bus inputs for the upper byte of the address. Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a HIGH to LOW transition. During a byte/page write cycle WR is brought LOW while RD is held HIGH and the data is placed on the bus. The rising edge of WR latches data into the device. The RD input is active LOW and is used to read content of the E2 memory at the latched address. Both PSEN an WR signals must be held HIGH during RD controlled read operation. WC input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to disable write to the E2 memory. Taking WC HIGH prior to tBLC (100ns, the time delay from the last write cycle to the start of internal programming cycle) will inhibit the write operation. The device select (CE) is an active LOW input. This signal has to be asserted prior to ALE HIGH to LOW transition in order to generate a valid internal device select signal. Holding this pin HIGH and ALE LOW will place the device in standby mode. Address Latch Enable input is used to latch the addresses present on the address lines A8–A12 and AD0–AD7 into the device. The addresses are latched when ALE transitions from HIGH to LOW. A8–A12 AD0–AD7 WR RD WC I I/O I I I CE I ALE I 2 X88064 PRINCIPLES OF OPERATION The X88064 is a highly integrated peripheral device for a wide variety of single-chip microcontrollers. The X88064 provides 8K bytes of E2PROM which can be used either for Program Storage, Data Storage, or a combination of both, in systems based upon Harvard (80XX) architectures. The X88064 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the Address/Data bus to provide a “Seamless” interface. The interface inputs on the X88064 are configured such that it is possible to directly connect them to the proper interface signals of the appropriate single-chip microcontroller. In the Harvard type system, the reading of data from the chip is controlled either by the PSEN or the RD signal, which essentially maps the X88064 into both the Program and the Data Memory address map. The X88064 also features an advanced implementation of the Software Data Protection scheme, called Block Lock, which allows the device to be broken into 8 independent sections of 1K bytes. Each of these sections can be independently enabled for write operations; thereby allowing certain sections of the device to be secured so that updates can only occur in a controlled environment (e.g. in an automotive application, only at an authorized service center). The desired set-up configuration is stored in a nonvolatile register, ensuring the configuration data will be maintained after the device is powered down. The X88064 also features a Write Control input (WC), which serves as an external control over the completion of a previously initiated page load cycle. The X88064 also features the industry standard E2PROM characteristics such as byte or page mode write and Toggle Bit Polling. DEVICE OPERATION MODES Mixed Program/Data Memory By properly assigning the address space, a single X88064 can be used as both the Program and Data Memory. This would be accomplished by connecting all of the Microcontroller control outputs to the corresponding inputs of the X88064. The Data Storage can be fully protected by enabling Block Lock Control. Program Memory Mode This mode of operation is read-only. The PSEN and ALE inputs of the X88064 are tied directly to the PSEN and ALE outputs of the microcontroller. The RD and WR inputs are tied HIGH. When ALE is HIGH, the A/D0–A/D7 and A8–A12 addresses flow into the device. The addresses, both low and high order, are latched when ALE transitions LOW (VIL). PSEN will then go LOW and after tPLDV, valid data is presented on the A/D0–A/D7 pins. CE must be LOW during the entire operation. Data Memory Mode This mode of operation allows both read and write functions. The PSEN input is tied to VIH or to VCC through a pull-up resistor. The ALE, RD, and WR inputs are tied directly to the microcontroller’s ALE, RD, and WR outputs. Read This operation is quite similar to the Program Memory read. A HIGH to LOW transition on ALE latches the addresses and the data will be output on the A/D pins after RD goes LOW (tRLDV). Write A write is performed by latching the addresses on the falling edge of ALE. Then WR is strobed LOW followed by valid data being presented at the A/D0–A/D7 pins. The data will be latched into the X88064 on the rising edge of WR. To write to the X88064, with the SDP feature enabled, a three-byte command sequence must precede the byte(s) being written. (See Software Data Protection.) 3 X88064 MODE SELECTION CE VCC HIGH LOW LOW LOW PSEN X X LOW HIGH HIGH RD X X HIGH LOW HIGH WR X X HIGH HIGH Mode Standby Standby Program Fetch Data Read Write I/O High Z High Z DOUT DOUT DIN Power Standby (CMOS) Standby (TTL) Active Active Active 7023 FRM T02 TYPICAL APPLICATIONS U4 U3 LATCH RAM EA/VP A/D0–A/D7 VCC A/D0–A/D7 X1 U2 LCS A/D0–A/D7 A/D8–A/D15 A/D0–A/D7 U1 A8–A12 X2 A8–A12 X1 A8–A12 WC PSEN VCC WC X2 UCS ALE/QS0 WR/QS1 RD/QSMD CE ALE WR RD X88064 PSEN ALE RD WR P2.7 PSEN ALE RD WR CE 80188 188 Interface 80C51 µ C Family X88064 U2 X1 A/D0–A/D7 U1 A/D0–A/D7 X2 A/D8–A/D15 A8–A12 WC PSEN VCC EA BUSWIDTH ALE WR RD CE ALE WR RD X88064 8X196 KC/KD 196 Interface 7023 FRM F03 4 X88064 PAGE WRITE OPERATION Regardless of the microcontroller employed, the X88064 supports page mode write operations. This allows the microcontroller to write from one to thirty-two bytes of data to the X88064. Each individual write within a page write operation must conform to the byte write timing requirements. The falling edge of WR starts a timer delaying the internal programming cycle 100µs. Therefore, each successive write operation must begin within 100µs of the last byte written. The following waveforms illustrate the sequence and timing requirements. Page Write Timing Sequence for WR Controller Operation OPERATION BYTE 0 BYTE 1 BYTE 2 LAST BYTE READ (1) AFTER tWC READY FOR NEXT WRITE OPERATION CE ALE A/D0 –A/D 7 AIN D IN AIN D IN AIN D IN AIN D IN AIN D OUT AIN AIN A8 –A12 A12=n A12=n A12=n A12=n A12=x ADDR Next Address WR PSEN(RD) t BLC tWC 7023 FRM F04 Notes: (1) For each successive write within a page write cycle A5–A12 must be the same. 5 X88064 TOGGLE BIT POLLING Because the X88064 typical nonvolatile write cycle time is less than the specified 5ms, Toggle Bit Polling has been provided to determine the early completion of write. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete, the toggling will cease and the device will be accessible for additional read or write operations. Toggle Bit Polling RD/WR Control OPERATION LAST BYTE • WRITTEN I/O6=X I/O6=X I/O6=X I/O6=X X88064 READ Y FOR NEXT OPERATION CE ALE A/D0 –A/D7 AIN D IN AIN DOUT AIN DOUT AIN DOUT AIN D OUT AIN A8 –A12 A12=n A12=n A12=n A12=n A12=n ADDR WR RD 7023 FRM F05 Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 6 X88064 DATA PROTECTION The X88064 provides two levels of data protection through software control. There is a global software data protection feature similar to the industry standard for E2PROMs and a new Block Lock Control providing a secondary level of data security. SOFTWARE DATA PROTECTION The X88064 offers a software controlled data protection feature. The X88064 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host then has open read and write access of the device once VCC is stable. The X88064 can be automatically protected during power-up/down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the SDP deactivation command is issued. Once the software protection is enabled, the X88064 is also protected from inadvertent and accidental writes in the powered-up state. That is, the SDP software algorithm must be issued prior to writing additional data to the device. WRITE A0 TO X555 Writing with SDP Enabled WRITE AA TO X555 WRITE 55 TO XAAA PERFORM BYTE OR PAGE WRITE OPERATIONS X = Address bit (A12) of the byte being updated. WAIT tWC EXIT ROUTINE 7023 FRM F06 SEQUENCE TO DEACTIVATE SOFTWARE DATA PROTECTION WRITE AA to 555 WRITE 55 to AAA WRITE A0 to 555 WRITE AA to 555 WRITE 80 to AAA WAIT OF twc EXIT ROUTINE 7 X88064 Block Lock Write Control The X88064 provides a secondary level of data security referred to as Block Lock Control. This is accessed through an extension of the SDP command sequence. Block Lock allows the user to inhibit writes to any 1K x 8 blocks of memory. Unlike SDP which prevents inadvertent writes, but still allows easy system access to writing the memory, Block Lock will inhibit all attempts unless it is specifically disabled by the host. This could be used to set a higher level of protection in a system where a portion of the memory is used for Program Storage and another portion is used as Data Storage. Setting write lockout is accomplished by writing a fivebyte command sequence, opening access to the Block Lock Register (BLR). After the fifth byte is written, the user writes to the BLR, selecting which blocks to protect or unprotect. All write operations, both the command sequence and writing the data to the BLR, must conform to the page write timing requirements. Block Lock Register Format MSB 7 6 5 4 3 2 1 LSB 0 BLOCK ADDRESS 0000–03FF 0400–07FF 0800–0BFF 0C00–0FFF 1000–13FF 1400–17FF 1800–1BFF 1C00–1FFF 1 = Locked, 0 = Unlocked 7023 FRM F07 Setting Block Lock Register Sequence WRITE AA TO 555 WRITE 55 TO AAA WRITE A0 TO 555 WRITE AA TO 555 WRITE C0 TO AAA WRITE BLR MASK VALUE TO XXXX WAIT tWC (BLR SET) EXIT ROUTINE 7023 FRM F08 8 X88064 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias.......................–65°C to +135°C Storage Temperature ...........................–65°C to +150°C Voltage on any Pin with Respect to VSS .......................................... –1V to +7V D.C. Output Current.................................................5 mA Lead Temperature (Soldering, 10 seconds)300°C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Min. 0°C –40°C Max. +70°C +85°C 7023 FRM T03 Supply Voltage X88064 X88064-60 Limits 5V ±10% 5V ±10% 7023 FRM T04 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol ICC ISB1(CMOS) ISB2(TTL) ILI ILO VlL(3) VIH(3) VOL VOH Parameter VCC Current (Active) VCC Current (Standby) VCC Current (Standby) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Min. Max. 30 150 2.5 10 10 Units mA µA mA µA µA V V V V Test Conditions CE = RD = VIL, All I/O’s = Open, Other Inputs = VCC CE = VCC – 0.3V, All I/O’s = Open, Other Inputs = VCC – 0.3V, ALE = VIL CE = VIH, All I/O’s = Open, Other Inputs = VIH, ALE = VIL VIN = VSS to VCC VOUT = VSS to VCC, RD = VIH = PSEN –1 2 2.4 0.8 VCC + 0.5 0.4 IOL = 2.1 mA IOH = –400 µA 7023 FRM T05 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol CI/O(4) CIN(4) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V 7023 FRM T06 POWER-UP TIMING Symbol tPUR(4) tPUW(4) Parameter Power-Up to Read Power-Up to Write Max. 1 5 Units ms ms 7032 FRM T07 Notes: (3) VIL min. and VIH max. are for reference only and are not tested. (4) This parameter is periodically sampled and not 100% tested. 9 X88064 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 0V to 3V 10ns 1.5V 7023 FRM T08 EQUIVALENT A.C. TEST CIRCUIT 5V 1.92KΩ OUTPUT 1.37KΩ 100pF 7023 FRM F09 PSEN Controlled Read Cycle X88064 – 60 Symbol tLHLL tAVLL tLLAX tPLDV tPHDX tELLL PWPL tPS tPH tPHDZ (5) tPLDX (5) X88064 Min. 80 10 20 Parameter ALE Pulse Width Address Setup Time Address Hold Time PSEN Read Access Time Data Hold Time Chip Enable Setup Time PSEN Pulse Width PSEN Setup Time PSEN Hold Time PSEN Disable to Output in High Z PSEN to Output in Low Z Min. 60 10 20 Max. Max. Units ns ns ns 45 0 7 100 20 20 20 10 10 0 7 140 30 20 80 ns ns ns ns ns ns 30 ns ns 7023 FRM T09 PSEN Controlled Read Timing Diagram tPH CE t ELLL tLHLL ALE tAVLL A/D0 –A/D7 AIN tPLDX tPLDV A8 –A12 tPS PSEN 7023 FRM F10 tPH tLLAX DOUT tPHDX tPHDZ ADDRESS PWPL 10 X88064 RD Controlled Read Cycle X88064 – 60 Symbol tLHLL tAVLL tLLAX tRLDV tRHDX tELLL PWRL tRDS tRDH tRHDZ (6) tRLDX (6) X88064 Min. 80 10 20 Parameter ALE Pulse Width Address Setup Time Address Hold Time RD Read Access Time Data Hold Time Chip Enable Setup Time RD Pulse Width RD Setup Time RD Hold Time RD Disable to Output in High Z RD to Output in Low Z Min. 60 10 20 Max. Max. Units ns ns ns 60 0 7 120 20 20 20 0 0 0 7 150 30 20 80 ns ns ns ns ns ns 30 ns ns 7023 FRM T10 RD Controlled Read Timing Diagram tRDH CE tLHLL ALE tAVLL A/D0 –A/D7 AIN tRLDX tRLDV A8 –A12 tRDS RD PWRL tLLAX DOUT tRHDX tRHDZ ADDRESS tELLL tRDH 7023 FRM F11 Notes: (6) This parameter is periodically sampled and not 100% tested. 11 X88064 WR Controlled Write Cycle X88064 – 60 Symbol tLHLL tAVLL tLLAX tDVWH tWHDX tELLL tWLWH tWRS tWRH tBLC tWC (7) X88064 Min. 80 10 20 50 30 7 120 30 20 Parameter ALE Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Enable Setup Time WR Pulse Width WR Setup Time WR Hold Time Byte Load Time (Page Write) Write Cycle Time Min. 60 10 20 50 30 7 100 20 20 0.5 Max. Max. Units ns ns ns ns ns ns ns ns ns 100 5 0.5 100 5 µs ms 7023 FRM T11 WR Controlled Write Timing Diagram WRH t CE tLHLL ALE tAVLL A/D0 –A/D7 AIN tLLAX DIN tDVWH A8 –A12 tWRS tWLWH tWHDX ADDRESS tELLL tWRH WR 7023 FRM T12 Notes: (7) TWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 12 X88064 PACKAGING INFORMATION 24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.265 (32.13) 1.230 (31.24) 0.557 (14.15) 0.530 (13.46) PIN 1 INDEX PIN 1 1.100 (27.94) REF. 0.080 (2.03) 0.065 (1.65) SEATING PLANE 0.150 (3.81) 0.125 (3.18) 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) 0.110 (2.79) 0.090 (2.29) 0.065 (1.65) 0.040 (1.02) 0.022 (0.56) 0.014 (0.36) 0.625 (15.87) 0.600 (15.24) TYP. 0.010 (0.25) 0° 15 ° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 7023 FRM F13 13 X88064 PACKAGING INFORMATION 24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.290 (7.37) 0.299 (7.60) PIN 1 INDEX 0.393 (10.00) 0.420 (10.65) PIN 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.050 (1.27) 0.003 (0.10) 0.012 (0.30) 0.050" TYPICAL 0.010 (0.25) X 45° 0.020 (0.50) 0° – 8° 0.009 (0.22) 0.013 (0.33) 0.015 (0.40) 0.050 (1.27) 0.050" TYPICAL 0.420" FOOTPRINT 0.030" TYPICAL 24 PLACES NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 7023 FRM F14 14 X88064 ORDERING INFORMATION X88064 Device X X XX Access Time Blank = 80 ns -60 = 60 ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Packages: P = 24-Lead Plastic DIP S = 24-Lead SOIC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 15