X88C64SI

APPLICATION NOTE AVAILABLE AN63 X88C64 8051 Microcontroller Family Compatible SLIC 64K X88C64 E2 Micro-Peripheral DESCRIPTION 8192 x 8 Bit FEATURES • • • • • • • • CONCURRENT READ WRITE™ —Dual Plane Architecture —Isolates Read/Write Functions Between Planes —Allows Continuous Execution of Code From One Plane While Writing in the Other Plane Multiplexed Address/Data Bus —Direct Interface to Popular 8051 Family High Performance CMOS —Fast Access Time, 120ns —Low Power —60mA Active Maximum —500µA Standby Maximum Software Data Protection Block Protect Register —Individually Set Write Lock Out in 1K Blocks Toggle Bit Polling —Early End of Write Detection Page Mode Write —Allows up to 32 Bytes to be Written in One Write Cycle High Reliability —Endurance: 100,000 Write Cycle —Data Retention: 100 Years The X88C64 is an 8K x 8 E2PROM fabricated with advanced CMOS Textured Poly Floating Gate Technology. The X88C64 features a Multiplexed Address and Data bus allowing a direct interface to a variety of popular single-chip microcontrollers operating in expanded multiplexed mode without the need for additional interface circuitry. The X88C64 is internally configured as two independent 4K x 8 memory arrays. This feature provides the ability to perform nonvolatile memory updates in one array and continue operation out of code stored in the other array; effectively eliminating the need for an auxiliary memory device for code storage. To write to the X88C64, a three-byte command sequence must precede the byte(s) being written. The X88C64 also provides a second generation software data protection scheme called Block Protect. Block Protect can provide write lockout of the entire device or selected 1K blocks. There are eight 1K x 8 blocks that can be write protected individually in any combination required by the user. Block Protect, in addition to Write Control input, allows the different segments of the memory to have varying degrees of alterability in normal system operation. FUNCTIONAL DIAGRAM WC CE WR RD PSEN A8–A11 CONTROL LOGIC X D E C O D E SOFTWARE DATA PROTECT A12 1K BYTES 1K BYTES 1K BYTES 1K BYTES A12 M U X 1K BYTES 1K BYTES 1K BYTES 1K BYTES A12 ALE L A T C H E S Y DECODE I/O & ADDRESS LATCHES AND BUFFERS A/D0–A/D7 CONCURRENT READ WRITE™ is a trademark of Xicor, Inc. © Xicor, Inc. 1994, 1995, 1996 Patents Pending 3867-1.5 7/9/96 T0/C2/D0 NS 3867 FHD F02 1 Characteristics subject to change without notice X88C64 PIN DESCRIPTIONS Address/Data (A/D0–A/D7) Multiplexed low-order addresses and data. The Addresses flow into the device while ALE is HIGH. After ALE transitions from a HIGH to LOW the addresses are latched. Once the addresses are latched these pins input data or output data depending on RD, WR, PSEN, and CE. Addresses (A8–A12) High order addresses flow into the device when ALE is HIGH and are latched when ALE goes LOW. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH and ALE is LOW, the X88C64 is placed in the low power standby mode. Program Store Enable (PSEN) When the X88C64 is to be used in a 8051 based system, PSEN is tied directly to the microcontroller’s PSEN output. Read (RD) When the X88C64 is to be used in a 8051 based system, RD is tied directly to the microcontroller’s RD output. Write (WR) When the X88C64 is to be used in a 8051 based system, WR is tied directly to the microcontroller’s WR output. Address Latch Enable (ALE) Addresses flow through the latches to address decoders when ALE is HIGH and are latched when ALE transitions from a HIGH to LOW. Write Control (WC) The Write Control allows external circuitry to abort a page load cycle once it has been initiated. This input is useful in applications in which a power failure or processor RESET could interrupt a page load cycle. In this case, the microcontroller might drive all signals HIGH, causing bad data to be latched into the E2PROM. If the Write Control input is driven HIGH (before tBLC Max) after Write (WR) goes HIGH, the write cycle will be aborted. PIN NAMES Symbol ALE A/D0–A/D7 A8–A12 RD WR PSEN CE WC VSS VCC NC Description Address Latch Enable Address Inputs/Data I/O Address Inputs Read Input Write Input Program Store Enable Input Chip Enable Write Control Ground Supply Voltage No Connect 3867 PGM T01.1 When WC is LOW (tied to VSS) the X88C64 will be enabled to perform write operations. When WC is HIGH normal read operations may be performed, but all attempts to write to the device will be disabled. PIN CONFIGURATION DIP/SOIC NC A12 NC NC WC PSEN A/D0 A/D1 A/D2 A/D3 A/D4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 X88C64 24 23 22 21 20 19 18 17 16 15 14 13 VCC WR ALE A8 A9 A11 RD A10 CE A/D7 A/D6 A/D5 3867 FHD F01 2 X88C64 PRINCIPLES OF OPERATION The X88C64 is a highly integrated peripheral device for a wide variety of single-chip microcontrollers. The X88C64 provides 8K bytes of E2PROM which can be used either for Program Storage, Data Storage, or a combination of both in systems based upon Harvard (80XX) architectures. The X88C64 incorporates the interface circuitry normally needed to decode the control signals and demultiplex the Address/Data bus to provide a “Seamless” interface. The interface inputs on the X88C64 are configured such that it is possible to directly connect them to the proper interface signals of the appropriate single-chip microcontroller. In the Harvard type system, the reading of data from the chip is controlled either by the PSEN or the RD signal, which essentially maps the X88C64 into both the Program and the Data Memory address map. The X88C64 is internally organized as two independent planes of 4K bytes of memory with the A12 input selecting which of the two planes of memory are to be accessed. While the processor is executing code out of one plane, write operations can take place in the other plane, allowing the processor to continue execution of code out of the X88C64 during a byte or page write to the device. The X88C64 also features an advanced implementation of the Software Data Protection scheme, called Block Protect, which allows the device to be broken into 8 independent sections of 1K bytes. Each of these sections can be independently enabled for write operations; thereby allowing certain sections of the device to be secured so that updates can only occur in a controlled environment (e.g. in an automotive application, only at an authorized service center). The desired set-up configuration is stored in a nonvolatile register, ensuring the configuration data will be maintained after the device is powered down. The X88C64 also features a Write Control input (WC), which serves as an external control over the completion of a previously initiated page load cycle. The X88C64 also features the industry standard E2PROM characteristics such as byte or page mode write and Toggle Bit Polling. DEVICE OPERATION MODES Mixed Program/Data Memory By properly assigning the address spaces, a single X88C64 can be used as both the Program and Data Memory. This would be accomplished by connecting all of the 8051 control outputs to the corresponding inputs of the X88C64. In this configuration, one plane of memory could be dedicated to Program Storage and the other plane dedicated to Data Storage. The Data Storage can be fully protected by enabling block protect write lockout. TYPICAL APPLICATION 31 EA/VP 19 X1 18 X2 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 PSEN ALE RD WR P2.7 80C31 39 38 37 36 35 34 33 32 21 22 23 24 25 29 30 17 16 7 8 9 10 11 13 14 15 21 20 17 19 2 5 6 22 18 23 16 A/D0 A/D1 A/D2 A/D3 A/D4 A/D5 A/D6 A/D7 A8 A9 A10 A11 A12 WC PSEN ALE RD WR CE 24 VCC X88C64 3867 FHD F03 Program Memory Mode This mode of operation is read-only. The PSEN and ALE inputs of the X88C64 are tied directly to the PSEN and ALE outputs of the microcontroller. The RD and WR inputs are tied HIGH. When ALE is HIGH, the A/D0–A/D7 and A8–A12 addresses flow into the device. The addresses, both low and high order, are latched when ALE transitions LOW (VIL). PSEN will then go LOW and after tPLDV, valid data is presented on the A/D0–A/D7 pins. CE must be LOW during the entire operation. 3 X88C64 Data Memory Mode This mode of operation allows both read and write functions. The PSEN input is tied to VIH or to VCC through a pull-up resistor. The ALE, RD, and WR inputs are tied directly to the microcontroller’s ALE, RD, and WR outputs. Read This operation is quite similar to the Program Memory read. A HIGH to LOW transition on ALE latches the MODE SELECTION CE VCC HIGH LOW LOW LOW PSEN X X LOW HIGH HIGH RD X X HIGH LOW HIGH WR X X HIGH HIGH Mode Standby Standby Program Fetch Data Read Write I/O High Z High Z DOUT DOUT DIN Power Standby (CMOS) Standby (TTL) Active Active Active 3867 PGM T02.2 addresses and the data will be output on the AD pins after RD goes LOW (tRLDV). Write A write is performed by latching the addresses on the falling edge of ALE. Then WR is strobed LOW followed by valid data being presented at the A/D0–A/D7 pins. The data will be latched into the X88C64 on the rising edge of WR. To write to the X88C64, a three-byte command sequence must precede the byte(s) being written. (See Software Data Protection.) 4 X88C64 PAGE WRITE OPERATION Regardless of the microcontroller employed, the X88C64 supports page mode write operations. This allows the microcontroller to write from one to thirty-two bytes of data to the X88C64. Each individual write within a page write operation must conform to the byte write timing requirements. The falling edge of WR starts a timer delaying the internal programming cycle 100µs. Therefore, each successive write operation must begin within 100µs of the last byte written. The following waveforms illustrate the sequence and timing requirements. Page Write Timing Sequence for WR Controlled Operation OPERATION BYTE 0 BYTE 1 BYTE 2 LAST BYTE READ (1)(2) AFTER tWC READY FOR NEXT WRITE OPERATION CE ALE A/D0–A/D7 AIN DIN AIN DIN AIN DIN AIN DIN AIN DOUT AIN AIN A8–A12 A12=n A12=n A12=n A12=n A12=x ADDR Next Address WR PSEN(RD) tBLC tWC 3867 FHD F08 Notes: (1) For each successive write within a page write cycle A5–A12 must be the same. (2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page write operation. Two responses are possible: a. Reading from the same plane being written (A12 of Read = A12 of Write) is effectively a Toggle Bit Polling operation. b. Reading from the opposite plane being written (A12 of Read ≠ A12 of Write) true data will be returned, facilitating the use of a single memory component as both program and data storage. 5 X88C64 TOGGLE BIT POLLING Because the X88C64 typical nonvolatile write cycle time is less than the specified 5ms, Toggle Bit Polling has been provided to determine the early completion of write. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subseToggle Bit Polling RD/WR Control quent attempts to read the device. When the internal cycle is complete, the toggling will cease and the device will be accessible for additional read or write operations. Due to the dual plane architecture, reads for polling must occur in the plane that was written; that is, the state of A12 during a write must match the state of A12 during Toggle Bit Polling. OPERATION LAST BYTE WRITTEN I/O6=X I/O6=X I/O6=X I/O6=X X88C64 READY FOR NEXT OPERATION CE ALE A/D0–A/D7 AIN DIN AIN DOUT AIN DOUT AIN DOUT AIN DOUT AIN A8–A12 A12=n A12=n A12=n A12=n A12=x ADDR WR RD 3867 FHD F09 SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 6 X88C64 DATA PROTECTION The X88C64 provides two levels of data protection through software control. There is a global software data protection feature similar to the industry standard for E2PROMs and a new Block Protect write lockout protection providing a secondary level of data security. SOFTWARE DATA PROTECTION Software Data Protection (SDP) is employed to protect the entire array against inadvertent writes. To write to the X88C64, a three-byte command sequence must precede the byte(s) being written. All write operations, both the command sequence and any data write operations, must conform to the page write timing requirements. Writing with SDP WRITE AA TO X555 Setting write lockout is accomplished by writing a fivebyte command sequence, opening access to the Block Protect Register (BPR). After the fifth byte is written, the user writes to the BPR, selecting which blocks to protect or unprotect. All write operations, both the command sequence and writing the data to the BPR, must conform to the page write timing requirements. Block Protect Register Format MSB 7 6 5 4 3 2 1 LSB 0 BLOCK ADDRESS 0000–03FF 0400–07FF 0800–0BFF 0C00–0FFF 1000–13FF 1400–17FF 1800–1BFF 1C00–1FFF 1 = Protect, 0 = Unprotect Block Specified 3867 FHD F12 WRITE 55 TO XAAA Setting BPR Sequence WRITE A0 TO X555 WRITE AA TO X555 WRITE C0 TO XAAA PERFORM BYTE OR PAGE WRITE OPERATIONS X = A12 : WAIT tWC A12 = 1 IF DATA TO BE WRITTEN IS WITHIN ADDRESS 1000 TO 1FFF. A12 = 0 IF DATA TO BE WRITTEN IS WITHIN ADDRESS 0000 TO 0FFF. WRITE 55 TO XAAA WRITE BPR MASK VALUE TO ANY ADDRESS EXIT ROUTINE 3867 FHD F10 WRITE A0 TO X555 WAIT tWC (BPR REGISTER SET) Block Protect Write Lockout The X88C64 provides a secondary level of data security referred to as Block Protect write lockout. This is accessed through an extension of the SDP command sequence. Block Protect allows the user to lockout writes to any 1K x 8 blocks of memory. Unlike SDP which prevents inadvertent writes, but still allows easy system access to writing the memory, Block Protect will lockout all attempts unless it is specifically disabled by the host. This could be used to set a higher level of protection in a system where a portion of the memory is used for Program Storage and another portion is used as Data Storage. 7 WRITE AA TO X555 EXIT ROUTINE X = A12: A12 = 1 IF PROGRAM BEING EXECUTED RESIDES WITHIN ADDRESS 0000 TO 0FFF. A12 = 0 IF PROGRAM BEING EXECUTED RESIDES WITHIN ADDRESS 1000 TO 1FFF. 3867 FHD F13 X88C64 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS .................................. –1V to +7V D.C. Output Current ............................................ 5 mA Lead Temperature (Soldering, 10 seconds) .............................. 300°C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0°C –40°C –55°C Max. +70°C +85°C +125°C 3867 PGM T03.1 *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X88C64 Limits 5V ± 10% 3867 PGM T04.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol ICC ISB1(CMOS) Parameter VCC Current (Active) VCC Current (Standby) Min. Max. 60 500 Units mA µA Test Conditions CE = RD = VIL, All I/O’s = Open,Other Inputs = VCC CE = VCC – 0.3V, All I/O’s = Open,Other Inputs = VCC – 0.3V, ALE = VIL CE = VIH, All I/O’s = Open, Other Inputs = VIH, ALE = VIL VIN = VSS to VCC VOUT = VSS to VCC, RD = VIH = PSEN ISB2(TTL) ILI ILO VlL(3) VIH(3) VOL VOH VCC Current (Standby) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage –1 2 2.4 6 10 10 0.8 VCC + 0.5 0.4 mA µA µA V V V V IOL = 2.1 mA IOH = –400 µA 3867 PGM T05.2 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol CI/O(4) CIN(4) POWER-UP TIMING Symbol tPUR(4) tPUW(4) Parameter Power-Up to Read Power-Up to Write Max. 1 5 Units ms ms 3867 PGM T07 Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V 3867 PGM T06 Notes: (3) VIL min. and VIH max. are for reference only and are not tested. (4) This parameter is periodically sampled and not 100% tested. 8 X88C64 A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 0V to 3V 10ns 1.5V 3867 PGM T08.1 EQUIVALENT A.C. TEST CIRCUIT 5V 1.92KΩ OUTPUT 1.37KΩ 100pF 3867 FHD F04.3 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) PSEN Controlled Read Cycle Symbol tLHLL tAVLL tLLAX tPLDV tPHDX tELLL PWPL tPS tPH tPHDZ (5) tPLDX (5) Parameter ALE Pulse Width Address Setup Time Address Hold Time PSEN Read Access Time Data Hold Time Chip Enable Setup Time PSEN Pulse Width PSEN Setup Time PSEN Hold Time PSEN Disable to Output in High Z PSEN to Output in Low Z Min. 80 20 30 120 0 7 150 30 20 50 10 Max. Units ns ns ns ns ns ns ns ns ns ns ns 3867 PGM T09 PSEN Controlled Read Timing Diagram tPH CE tLHLL ALE tAVLL A/D0–A/D7 AIN tPLDX tPLDV A8–A12 tPS PSEN 3867 FHD F05 tELLL tPH tLLAX DOUT tPHDX tPHDZ ADDRESS PWPL Note: (5) This parameter is periodically sampled and not 100% tested. 9 X88C64 RD Controlled Read Cycle Symbol tLHLL tAVLL tLLAX tRLDV tRHDX tELLL PWRL tRDS tRDH tRHDZ (6) tRLDX (6) Parameter ALE Pulse Width Address Setup Time Address Hold Time RD Read Access Time Data Hold Time Chip Enable Setup Time RD Pulse Width RD Setup Time RD Hold Time RD Disable to Output in High Z RD to Output in Low Z Min. 80 20 30 120 0 7 150 30 20 50 0 Max. Units ns ns ns ns ns ns ns ns ns ns ns 3867 PGM T10 RD Controlled Read Timing Diagram tRDH CE tLHLL ALE tAVLL A/D0–A/D7 AIN tRLDX tRLDV A8–A12 tRDS RD 3867 FHD F06 tELLL tRDH tLLAX DOUT tRHDX tRHDZ ADDRESS PWRL Note: (6) This parameter is periodically sampled and not 100% tested. 10 X88C64 WR Controlled Write Cycle Symbol tLHLL tAVLL tLLAX tDVWH tWHDX tELLL tWLWH tWRS tWRH tBLC tWC (7) Parameter ALE Pulse Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Enable Setup Time WR Pulse Width WR Setup Time WR Hold Time Byte Load Time (Page Write) Write Cycle Time Min. 80 20 30 50 30 7 120 30 20 0.5 Max. Units ns ns ns ns ns ns ns ns ns µs ms 3867 PGM T11 100 5 WR Controlled Write Timing Diagram tWRH CE tLHLL ALE tAVLL A/D0–A/D7 AIN tLLAX DIN tDVWH A8–A12 tWRS WR 3867 FHD F07 tELLL tWRH tWHDX ADDRESS tWLWH Note: (7) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 11 X88C64 PACKAGING INFORMATION 24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.265 (32.13) 1.230 (31.24) 0.557 (14.15) 0.530 (13.46) PIN 1 INDEX PIN 1 1.100 (27.94) REF. 0.080 (2.03) 0.065 (1.65) SEATING PLANE 0.150 (3.81) 0.125 (3.18) 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) 0.110 (2.79) 0.090 (2.29) 0.065 (1.65) 0.040 (1.02) 0.022 (0.56) 0.014 (0.36) 0.625 (15.87) 0.600 (15.24) TYP. 0.010 (0.25) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F03 12 X88C64 PACKAGING INFORMATION 24-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.290 (7.37) 0.299 (7.60) PIN 1 INDEX 0.393 (10.00) 0.420 (10.65) PIN 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.050 (1.27) 0.003 (0.10) 0.012 (0.30) 0.050" TYPICAL 0.010 (0.25) X 45° 0.020 (0.50) 0.050" TYPICAL 0.009 (0.22) 0.013 (0.33) 0.015 (0.40) 0.050 (1.27) 0.420" 0° – 8° FOOTPRINT 0.030" TYPICAL 24 PLACES NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 3926 FHD F24 13 X88C64 ORDERING INFORMATION X88C64 Device X X Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C MB = MIL-STD-883 Package P = 24-Lead Plastic DIP S = 24-Lead SOIC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 14