17512LJC

0 ® XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs 0 5* December 10, 1997 (Version 1.1) Product Specification Features • On-chip address counter, incremented by each rising edge on the clock input • Simple interface to the FPGA; requires only one user I/O pin • Cascadable for storing longer or multiple bitstreams • Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions • Supports XC4000EX/XL fast configuration mode (15.0 MHz) • Low-power CMOS Floating Gate process • Available in 5 V and 3.3 V versions • Available in compact plastic packages: 8-pin PDIP, 20-pin SOIC, and 20-pin PLCC. • Programming support by leading programmer manufacturers. • Design support using the Xilinx Alliance and Foundation series software packages. Description The XC1701L, XC1701 and XC17512L serial configuration PROMs (SCPs) provide an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in master serial mode, it generates a configuration clock that drives the SCP. A short access time after the rising clock edge, data appears on the SCP DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the SCP. When the FPGA is in slave mode, the SCP and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SCPs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to the programmer. VCC VPP GND CE RESET/ OE or OE/ RESET CLK Address Counter TC CEO EPROM Cell Matrix Output OE DATA X3185 Figure 1: Simplified Block Diagram (does not show programming circuit) December 10, 1997 (Version 1.1) 5-1 XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs Pin Description DATA Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. Serial PROM Pinouts Pin Name DATA CLK RESET/OE (OE/RESET) CE GND CEO VPP VCC 8-Pin PDIP 1 2 3 4 5 6 7 8 20-Pin SOIC 1 3 8 10 11 13 18 20 20-Pin PLCC 2 4 6 8 10 14 17 20 CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGA’s INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW130 Programmer. Third-party programmers have different methods to invert this pin. Capacity Device XC1701L XC1701 XC17512L Configuration Bits 1,048,576 1,048,576 524,288 Number of Configuration Bits, Including Header for all Xilinx FPGAs and Compatible SCP Type Device XC4010XL XC4013XL XC4020E XC4020XL XC4025E XC4028XL XC4028EX XC4036EX XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL Configuration Bits 283,424 393,623 329,312 521,880 422,176 668,184 668,184 832,528 832,528 1,014,928 1,215,368 1,433,864 1,924,992 SPROM XC17512L XC17512L XC1701 XC17512L XC1701 XC1701L XC1701 XC1701 XC1701L XC1701L XC1701L + XC17256L XC1701L + XC17512L 2 x XC1701L CE When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC standby mode. CEO Chip Enable output, to be connected to the CE input of the next SCP in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. VPP Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating! VCC and GND Positive supply and ground pins. 5-2 December 10, 1997 (Version 1.1) Controlling Serial PROMs Most connections between the FPGA device and the Serial PROM are simple and self-explanatory. • • • • The DATA output(s) of the of the Serial PROM(s) drives the DIN input of the lead FPGA device. The master FPGA CCLK output drives the CLK input(s) of the Serial PROM(s). The CEO output of a Serial PROM drives the CE input of the next Serial PROM in a daisy chain (if any). The RESET/OE input of all Serial PROMs is best driven by the INIT output of the XC3000 or XC4000 lead FPGA device. This connection assures that the Serial PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods – such as driving RESET/OE from LDC or system reset – assume that the Serial PROM internal power-on-reset is always in step with the FPGA’s internal power-on-reset, which may not be a safe assumption. The CE input of the lead (or only) Serial PROM is driven by the DONE/PRGM or DONE output of the lead FPGA device, provided that DONE/PRGM is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The XC3000 and XC4000 families take care of this automatically with an onchip default pull-up resistor. Programming the FPGA With Counters Unchanged Upon Completion When multiple FPGA-configurations for a single FPGA are stored in a Serial Configuration PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the D/P line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the Serial PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (24) and D/P goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. • FPGA Master Serial Mode Summary The I/O and logic functions of the Logic Cell Array and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration PROM has been designed for compatibility with the Master Serial Mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial Mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the Serial Configuration PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the Serial Configuration PROM is read sequentially, accessed via the Cascading Serial Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded SCPs provide additional memory. After the last bit from the first SCP is read, the next clock signal to the SCP asserts its CEO output Low and disables its DATA line. The second SCP recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded SCPs are reset if the FPGA RESET pin goes Low, assuming the SCP reset polarity option has been inverted. To reprogram the FPGA with another program, the D/P line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN. December 10, 1997 (Version 1.1) 5-3 XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs * If Readback is Activated, a 3.3-kΩ Resistor is Required in Series With M1 During Configuration the 3.3 kΩ M2 Pull-Down Resistor Overcomes the Internal Pull-Up, but it Allows M2 to be User I/O. * Vcc M0 M1 PWRDWN DOUT M2 HDC GeneralPurpose User I/O Pins LDC INIT • • • • • OPTIONAL Daisy-chained FPGAs with Different Configurations Other I/O Pins OPTIONAL Slave FPGAs with Identical Configurations Vcc FPGA RESET RESET DIN CCLK D/P INIT VCC DATA CLK CE OE/RESET VPP DATA CLK Cascaded Serial CE Memory OE/RESET SCP CEO (Low Resets the Address Pointer) CCLK (OUTPUT) DIN DOUT (OUTPUT) X8256 Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active. 5-4 December 10, 1997 (Version 1.1) Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. Programming The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Table 1: Truth Table for XC1700 Control Inputs Control Inputs RESET Inactive Active Inactive Active CE Low Low High High Internal Address if address < TC: increment if address > TC: don’t change Held reset Not changing Held reset Outputs DATA active 3-state 3-state 3-state 3-state CEO High Low High High High Icc active reduced active standby standby Notes: 1. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC+1 = address 0. IMPORTANT: Always tie the VPP pin to VCC in your application. Never leave VPP floating. December 10, 1997 (Version 1.1) 5-5 XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs XC1701 Absolute Maximum Ratings Symbol VCC VPP VIN VTS TSTG TSOL Note: Description Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) -0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V °C °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Description Commercial Industrial Military Supply voltage relative to GND 0°C to +70°C junction Supply voltage relative to GND -40°C to +85°C junction Supply voltage relative to GND -55°C to +125°C case Min 4.75 4.50 4.50 Max 5.25 5.50 5.50 Units V V V DC Characteristics Over Operating Condition Symbol VIH VIL VOH VOL VOH VOL ICCA ICCS IL High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode Supply current, standby mode Input or output leakage current -10.0 Industrial 3.76 0.37 10.0 50.0 10.0 Commercial Description Min 2.0 0 3.86 0.32 Max VCC 0.8 Units V V V V V V mA µA µA Note: During normal read operation VPP must be connected to VCC 5-6 December 10, 1997 (Version 1.1) XC1701L/XC17512L Absolute Maximum Ratings Symbol VCC VPP VIN VTS TSTG TSOL Description Supply voltage relative to GND Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) -0.5 to +6.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V °C °C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Description Commercial Supply voltage relative to GND 0°C to +70°C junction Min 3.0 Max 3.6 Units V DC Characteristics Over Operating Condition Symbol VIH VIL VOH VOL ICCA ICCS IL High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode Supply current, standby mode Input or output leakage current -10.0 Description Min 2.0 0 2.4 0.4 5.0 50.0 10.0 Max VCC 0.8 Units V V V V mA µA µA Note: During normal read operation VPP must be connected to VCC December 10, 1997 (Version 1.1) 5-7 XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs AC Characteristics Over Operating Condition CE 9 RESET/OE 11 THOE TLC 7 CLK TOE 2 DATA 4 TOH X2634 TSCE 9 TSCE 10 THCE 8 THC 6 TCYC 1 3 TCAC 4 TOH 5 TDF TCE Symbol Description XC1701 Min Max 25 45 45 50 67 20 20 20 0 20 XC1701L XC17512L Min Max 30 60 60 50 100 25 25 25 0 25 Units ns ns ns ns ns ns ns ns ns ns ns OE to Data Delay 1 TOE 2 TCE CE to Data Delay CLK to Data Delay 3 TCAC 4 TOH Data Hold From CE, OE, or CLK CE or OE to Data Float Delay2 5 TDF 6 TCYC Clock Periods CLK Low Time3 7 TLC 8 THC CLK High Time3 CE Setup Time to CLK (to guarantee proper counting) 9 TSCE 10 THCE CE Hold Time to CLK (to guarantee proper counting) OE Hold Time (guarantees counters are reset) 11 THOE Notes: 1. AC test load = 50 pF 0 0 2. Float delays are measured with minimum tester ac load and maximum dc load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V. 5-8 December 10, 1997 (Version 1.1) AC Characteristics Over Operating Condition (continued) RESET/OE CE CLK 12 TCDF DATA Last Bit 13 TOCK CEO 14 TOCE 14 TOCE X3183 First Bit 15 TOOE Symbol 12 13 14 15 TCDF TOCK TOCE TOOE Description CLK to Data Float Delay2 CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay XC1701 Min Max 50 30 35 30 XC1701L XC17512L Min Max 50 30 35 30 Units ns ns ns ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with minimum tester ac load and maximum dc load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V. December 10, 1997 (Version 1.1) 5-9 XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs Ordering Information XC1701L PC20 C Device Number XC1701L XC1701 XC17512L Operating Range/Processing Package Type PD8 = 8-Pin Plastic DIP SO20 = 20-Pin Plastic Small-Outline Package PC20 = 20-Pin Plastic Leaded Chip Carrier C = Commercial (0° to +70°C) I = Industrial (–40° to +85°C) Marking Information Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows. 1701L Device Number XC1701L XC1701 XC17512L P C Operating Range/Processing C = Commercial (0° to +70°C) I = Industrial (–40° to +85°C) Package Type P S J = 8-Pin Plastic DIP = 20-Pin Plastic Small-Outline Package = 20-Pin Plastic Leaded Chip Carrier 5-10 December 10, 1997 (Version 1.1)