57
XA Spartan-3A Automotive
FPGA Family Data Sheet
DS681 (v2.1) February 5, 2021
Product Specification
Summary
The Xilinx Automotive (XA) Spartan®-3A family of FPGAs
solves the design challenges in most high-volume,
cost-sensitive, I/O-intensive automotive electronics
applications. The four-member family offers densities
ranging from 200,000 to 1.4 million system gates, as shown
in Table 1.
Introduction
•
•
•
•
•
•
XA devices are available in both extended-temperature
Q-Grade (–40°C to +125°C TJ) and I-Grade (–40°C to
+100°C TJ) and are qualified to the industry recognized
AEC-Q100 standard.
The XA Spartan-3A family builds on the success of the
earlier XA Spartan-3E and XA Spartan-3 FPGA families by
increasing the amount of I/O per logic, significantly reducing
the cost per I/O. New features improve system performance
and reduce the cost of configuration. These XA Spartan-3A
family enhancements, combined with proven 90 nm process
technology, deliver more functionality and bandwidth per
dollar than ever before, setting the new standard in the
programmable logic industry.
Because of their exceptionally low cost, XA Spartan-3A
FPGAs are ideally suited to a wide range of automotive
electronics applications, including infotainment, driver
information, and driver assistance modules.
The XA Spartan-3A family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial mask set
costs and lengthy development cycles, while also permitting
design upgrades in the field with no hardware replacement
necessary because of its inherent programmability, an
impossibility with conventional ASICs and ASSPs with their
inflexible architecture.
Abundant, flexible logic resources
• Densities up to 25,344 logic cells, including optional shift
•
•
•
•
•
640+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O
with integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 266 Mb/s
Fully compliant 32-/64-bit, 33 MHz PCI™ technology
support
register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
• Up to 576 Kbits of fast block RAM with byte write enables
•
for processor applications
Up to 176 Kbits of efficient distributed RAM
•
Up to eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 320 MHz)
•
Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
•
Configuration interface to industry-standard PROMs
• Low-cost, space-saving SPI serial Flash PROM
• x8 or x8/x16 parallel NOR Flash PROM
•
Unique Device DNA identifier for design authentication
•
Complete Xilinx ISE® and WebPACK™ software
support plus Spartan-3A Starter Kit
•
MicroBlaze™ and PicoBlaze embedded processor
cores
BGA packaging, Pb-free ONLY
• Common footprints support easy density migration
Features
•
Very low cost, high-performance logic solution for
high-volume, cost-conscious applications
•
•
Dual-range VCCAUX supply simplifies 3.3V-only design
•
Suspend, Hibernate modes reduce system power
•
Multi-voltage, multi-standard SelectIO™ interface pins
Refer to the Spartan-3A FPGA Family Data Sheet (DS529)
for a full product description, AC and DC specifications, and
package pinout descriptions. Any values shown specifically
in this XA Spartan-3A Automotive FPGA Family data sheet
override those shown in DS529.
•
•
•
•
•
•
Up to 375 I/O pins or 165 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V 10% compatibility and hot swap compliance
For information regarding reliability qualification, refer to
RPT103 (Xilinx Spartan-3A Family Automotive Qualification
Report) and RPT070 (Spartan-3A Commercial Qualification
Report).
© Copyright 2008–2021 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Key Feature Differences from Commercial XC Devices
•
AEC-Q100 device qualification and full production part approval process (PPAP) documentation support available in
both extended temperature I- and Q-Grades
•
Guaranteed to meet full electrical specification over the TJ = –40°C to +125°C temperature range (Q-Grade)
•
XA Spartan-3A devices are available in the -4 speed grade only
•
PCI-66 is not supported in the XA Spartan-3A FPGA product line
•
Platform Flash is not supported within the XA family
•
XA Spartan-3A devices are available in Pb-Free packaging only.
•
MultiBoot is not supported in XA versions of this product.
•
The XA Spartan-3A device must be power cycled prior to reconfiguration.
Table 1: Summary of XA Spartan-3A FPGA Attributes)
CLB Array
Maximum
Block
Equivalent
(One CLB = Four Slices)
Dedicated
Maximum
Distributed
Logic
(1) RAM Multipliers DCMs User I/O Differential
RAM
bits
Total Total
I/O Pairs
bits(1)
Cells
Rows Columns
CLBs Slices
Device
System
Gates
XA3S200A
200K
4,032
32
16
448
1,792
28K
288K
16
4
195
90
XA3S400A
400K
8,064
40
24
896
3,584
56K
360K
20
4
311
142
XA3S700A
700K
13,248
48
32
1,472 5,888
92K
360K
20
8
372
165
XA3S1400A 1400K
25,344
72
40
2,816 11,264
176K
576K
32
8
375
165
Notes:
1.
By convention, one Kb is equivalent to 1,024 bits.
Architectural Overview
The XA Spartan-3A family architecture consists of five fundamental programmable functional elements:
•
Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage
elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data.
•
Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs
support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several
high-performance differential standards. Double Data-Rate (DDR) registers are included.
•
Block RAM provides data storage in the form of 18-Kb dual-port blocks.
•
Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product.
•
Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying,
multiplying, dividing, and phase-shifting clock signals.These elements are organized as shown in Figure 1. A dual ring
of staggered IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM. Each RAM column
consists of several 18-Kb RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the bottom of the device. The XA3S700A and XA3S1400A add
two DCMs in the middle of the two columns of block RAM and multipliers. The XA Spartan-3A family features a rich
network of routing that interconnect all five functional elements, transmitting signals among them. Each functional
element has an associated switch matrix that permits multiple connections to the routing.
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XA Spartan-3A Automotive FPGA Family Data Sheet
X-Ref Target - Figure 1
IOBs
Multiplier
DCM
Block RAM
CLB
IOBs
OBs
IOBs
IOBs
CLBs
DCM
Block RAM / Multiplier
DCM
IOBs
DS681_01_041111
Notes:
1.
The XA3S700A and XA3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines.
Figure 1: XA Spartan-3A Family Architecture
Configuration
XA Spartan-3A FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS
configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a SPI serial Flash or some other non-volatile medium, either on or off the board.
After applying power, the configuration data is written to the FPGA using any of five different modes:
•
Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash
•
Byte Peripheral Interface (BPI) Up from an industry-standard x8 or x8/x16 parallel NOR Flash
•
Slave Serial, typically downloaded from a processor
•
Slave Parallel, typically downloaded from a processor
•
Boundary Scan (JTAG), typically downloaded from a processor or system tester
Additionally, each XA Spartan-3A FPGA contains a unique, factory-programmed Device DNA identifier useful for tracking
purposes, anti-cloning designs, or IP protection.
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XA Spartan-3A Automotive FPGA Family Data Sheet
I/O Capabilities
The XA Spartan-3A FPGA SelectIO interface supports many popular single-ended and differential standards. Table 2 shows
the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Some
of the user I/Os are unidirectional input-only pins as indicated in Table 2.
XA Spartan-3A FPGAs support the following single-ended standards:
•
3.3V low-voltage TTL (LVTTL)
•
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V
•
3.3V PCI at 33 MHz
•
HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications
•
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications
XA Spartan-3A FPGAs support the following differential standards:
•
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or 3.3V
•
Bus LVDS I/O at 2.5V
•
TMDS I/O at 3.3V
•
Differential HSTL and SSTL I/O
•
LVPECL inputs at 2.5V or 3.3V
Table 2: Available User I/Os and Differential I/O Pairs
Device
FTG256
FGG400
FGG484
User
Differential
User
Differential
User
Differential
XA3S200A
195
(35)
90
(50)
–
–
–
–
XA3S400A
195
(35)
90
(50)
311
(63)
142
(78)
–
–
–
–
311
(63)
142
(78)
372
(84)
165
(93)
–
–
–
–
375
(87)
165
(93)
XA3S700A
XA3S1400A
Notes:
1.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
Production Status
Table 3 indicates the production status of each XA Spartan-3A FPGA by temperature range and speed grade. The table also
lists the earliest speed file version required for creating a production configuration bitstream. Later versions are also
supported.
Part Number
Table 3: XA Spartan-3A FPGA Family Production Status (Production Speed File)
Temperature Range
I-Grade
Q-Grade
Speed Grade
Standard (-4)
Standard (-4)
XA3S200A
Production (v1.41)
Production (v1.41)
XA3S400A
Production (v1.41)
Production (v1.41)
XA3S700A
Production (v1.41)
Production (v1.41)
XA3S1400A
Production (v1.41)
Production (v1.41)
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XA Spartan-3A Automotive FPGA Family Data Sheet
Package Marking
Figure 2 shows the top marking for Spartan-3A FPGAs in BGA packages. The markings for the BGA packages are nearly
identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator.
X-Ref Target - Figure 2
Mask Revision Code
BGA Ball A1
R
SPARTAN
R
XA3S200ATM
FTG256AGQ0625
D1234567A
4I
Device Type
Package
Fabrication Code
Process Code
Date Code
Lot Code
Speed Grade
Temperature Range
DS681_02_041111
Figure 2: XA Spartan-3A FPGA BGA Package Marking Example
Ordering Information
XA Spartan-3A FPGAs are available in Pb-free packaging only for all device/package combinations.
Pb-Free Packaging
X-Ref Target - Figure 3
Example:
XA3S200A -4 FT G 256 I
Device Type
Temperature Range:
Q - Grade (TJ = –40°C to 125°C)
I - Grade (TJ = –40°C to 100°C)
Number of Pins
Pb-free
Speed Grade
-4: Standard Performance
Package Type
Figure 3: Ordering Information
Device
XA3S200A
Speed Grade
-4 Standard
Performance
Package Type / Number of Pins
Temperature Range (TJ )
FTG256
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
I I-Grade (–40°C to 100°C)
XA3S400A
FGG400
400-ball Fine-Pitch Ball Grid Array (FBGA)
Q Q-Grade (–40°C to 125°C)
XA3S700A
FGG484
484-ball Fine-Pitch Ball Grid Array (FBGA)
XA3S1400A
Notes:
1.
2.
The XA Spartan-3A FPGA product line is available in -4 Speed Grade only.
See XCN20010 for XA3S700A product discontinuation information.
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XA Spartan-3A Automotive FPGA Family Data Sheet
DC Electrical Characteristics
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise
noted, the published parameter values apply to all XA Spartan-3A devices, and AC and DC characteristics are specified
using the same numbers for both I-Grade and Q-Grade.
Absolute Maximum Ratings
Stresses beyond those listed under Table 4: Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under
the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of
time adversely affects device reliability.
Table 4: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Max
Units
VCCINT
Internal supply voltage
–0.5
1.32
V
VCCAUX
Auxiliary supply voltage
–0.5
3.75
V
VCCO
Output driver supply voltage
–0.5
3.75
V
VREF
Input reference voltage
–0.5
VCCO + 0.5
V
–0.95
4.6
V
–0.5
4.6
V
–
±100
mA
Human body model
–
±2000
V
Charged device model
–
±500
V
Machine model
–
±200
V
VIN
Voltage applied to all User I/O pins and
dual-purpose pins
Driver in a high-impedance state
Voltage applied to all Dedicated pins
IIK
VESD
Input clamp current per I/O pin
Electrostatic Discharge Voltage
–0.5V < VIN < (VCCO +
0.5V) (1)
TJ
Junction temperature
–
125
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1.
2.
Upper clamp applies only when using PCI IOSTANDARDs.
For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Power Supply Specifications
Table 5: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
0.8
2.0
V
VCCO2T
Threshold for the VCCO Bank 2 supply
0.8
2.0
V
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel
NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last
for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 6: Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
VCCINTR
Ramp rate from GND to valid VCCINT supply level
0.2
100
ms
VCCAUXR
Ramp rate from GND to valid VCCAUX supply level
0.2
100
ms
VCCO2R
Ramp rate from GND to valid VCCO Bank 2 supply level
0.2
100
ms
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel
NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last
for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data
Symbol
Description
Min
Units
VDRINT
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
1.0
V
VDRAUX
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
2.0
V
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XA Spartan-3A Automotive FPGA Family Data Sheet
General Recommended Operating Conditions
Table 8: General Recommended Operating Conditions
Symbol
VCCINT
(1)
VCCAUX
VIN
TIN
Min
Nominal
Max
Units
I-Grade
–40
–
100
C
Q-Grade
–40
–
125
C
Internal supply voltage
1.140
1.200
1.260
V
Output driver supply voltage
1.100
–
3.600
V
Auxiliary supply
voltage(2)
VCCAUX = 2.5
2.250
2.500
2.750
V
VCCAUX = 3.3
3.000
3.300
3.600
V
PCI IOSTANDARD
–0.5
–
VCCO+0.5
V
IP or IO_#
–0.5
–
4.10
V
IO_Lxxy_# (4)
–0.5
–
4.10
V
–
–
500
ns
Junction temperature
TJ
VCCO
Description
Input
voltage(3)
Input signal transition
All other
IOSTANDARDs
time(5)
Notes:
1.
2.
3.
4.
5.
This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards.
Define VCCAUX selection using CONFIG VCCAUX constraint.
See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
Measured between 10% and 90% VCCO.
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XA Spartan-3A Automotive FPGA Family Data Sheet
General DC Characteristics for I/O Pins
Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (1)
Symbol
Description
Test Conditions
Min
Typ
Max
Units
IL(2)
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10
–
+10
µA
IHS
Leakage current on pins during
hot socketing, FPGA unpowered
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
–10
–
+10
µA
Add IHS + IRPU
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
IRPU(3)
RPU
(3)
IRPD
(3)
RPD(3)
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
VCCAUX.
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPU per Note 3)
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPD per Note 3)
VIN = GND
VCCO or VCCAUX =
3.0V to 3.6V
–151
–315
–710
µA
VCCO or VCCAUX =
2.3V to 2.7V
–82
–182
–437
µA
VCCO = 1.7V to 1.9V
–36
–88
–226
µA
VCCO = 1.4V to 1.6V
–22
–56
–148
µA
VCCO = 1.14V to 1.26V
–11
–31
–83
µA
VCCO = 3.0V to 3.6V
5.1
11.4
23.9
k
VCCO = 2.3V to 2.7V
6.2
14.8
33.1
k
VCCO = 1.7V to 1.9V
8.4
21.6
52.6
k
VCCO = 1.4V to 1.6V
10.8
28.4
74.0
k
VCCO = 1.14V to 1.26V
15.3
41.1
119.4
k
VCCAUX = 3.0V to 3.6V
167
346
659
µA
VCCAUX = 2.25V to 2.75V
100
225
457
µA
VIN = 3.0V to 3.6V
5.5
10.4
20.8
k
VIN = 2.3V to 2.7V
4.1
7.8
15.7
k
VIN = 1.7V to 1.9V
3.0
5.7
11.1
k
VIN = 1.4V to 1.6V
2.7
5.1
9.6
k
VIN = 1.14V to 1.26V
2.4
4.5
8.1
k
VIN = 3.0V to 3.6V
7.9
16.0
35.0
k
VIN = 2.3V to 2.7V
5.9
12.0
26.3
k
VIN = 1.7V to 1.9V
4.2
8.5
18.6
k
VIN = 1.4V to 1.6V
3.6
7.2
15.7
k
VIN = GND
VIN = VCCO
VCCAUX = 3.0V to 3.6V
VCCAUX = 2.25V to 2.75V
VIN = 1.14V to 1.26V
IREF
VREF current per pin
CIN
Input capacitance
RDT
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
µA
All VCCO levels
–
3.0
6.0
12.5
k
–10
–
+10
µA
3
–
10
pF
VCCO = 3.3V ± 10%
LVDS_33,
MINI_LVDS_33,
RSDS_33
90
100
115
VCCO = 2.5V ± 10%
LVDS_25,
MINI_LVDS_25,
RSDS_25
90
110
–
Notes:
1.
2.
3.
The numbers in this table are based on the conditions set forth in Table 8.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See "Parasitic Leakage" in UG331, Spartan-3 Generation FPGA User Guide.
This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Quiescent Current Requirements
Table 10: Quiescent Supply Current Characteristics
Symbol
ICCINTQ
ICCOQ
ICCAUXQ
Description
Quiescent VCCINT supply current
Quiescent VCCO supply current
Quiescent VCCAUX supply current
Typical(2)
I-Grade
Maximum(2)
Q-Grade
Maximum(2)
Units
XA3S200A
7
70
110
mA
XA3S400A
10
125
230
mA
XA3S700A
13
185
330
mA
XA3S1400A
24
310
580
mA
XA3S200A
0.2
3
4
mA
XA3S400A
0.3
4
5
mA
XA3S700A
0.3
4
5
mA
XA3S1400A
0.3
4
5
mA
XA3S200A
5
15
20
mA
XA3S400A
5
24
40
mA
XA3S700A
6
34
60
mA
XA3S1400A
10
58
95
mA
Device
Notes:
1.
2.
3.
4.
5.
The numbers in this table are based on the conditions set forth in Table 8.
Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX
= 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage
limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design
with no functional elements instantiated). For conditions other than those described above (for example, a design including functional
elements), measured quiescent current levels will be different than the values in the table.
There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
Spartan-3A FPGA XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower
Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates.
The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Single-Ended I/O Standards
Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
VCCO for Drivers(2)
VREF
Min (V)
Nom (V)
Max (V)
VIL
VIH
Max (V)
Min (V)
Min (V)
Nom (V)
Max (V)
LVTTL
3.0
3.3
3.6
0.8
2.0
LVCMOS33(4)
3.0
3.3
3.6
0.8
2.0
LVCMOS25(4,5)
2.3
2.5
2.7
0.7
1.7
0.4
0.8
VREF is not used for
these I/O standards
LVCMOS18
1.65
1.8
1.95
LVCMOS15
1.4
1.5
1.6
0.4
0.8
LVCMOS12
1.1
1.2
1.3
0.4
0.7
PCI33_3(6)
3.0
3.3
3.6
0.3 VCCO
0.5 VCCO
HSTL_I
1.4
1.5
1.6
0.68
0.75
0.9
VREF – 0.1
VREF + 0.1
HSTL_III
1.4
1.5
1.6
–
0.9
–
VREF – 0.1
VREF + 0.1
HSTL_I_18
1.7
1.8
1.9
0.8
0.9
1.1
VREF – 0.1
VREF + 0.1
HSTL_II_18
1.7
1.8
1.9
–
0.9
–
VREF – 0.1
VREF + 0.1
HSTL_III_18
1.7
1.8
1.9
–
1.1
–
VREF – 0.1
VREF + 0.1
SSTL18_I
1.7
1.8
1.9
0.833
0.900
0.969
VREF – 0.125
VREF + 0.125
SSTL18_II
1.7
1.8
1.9
0.833
0.900
0.969
VREF – 0.125
VREF + 0.125
SSTL2_I
2.3
2.5
2.7
1.15
1.25
1.38
VREF – 0.150
VREF + 0.150
SSTL2_II
2.3
2.5
2.7
1.15
1.25
1.38
VREF – 0.150
VREF + 0.150
SSTL3_I
3.0
3.3
3.6
1.3
1.5
1.7
VREF – 0.2
VREF + 0.2
SSTL3_II
3.0
3.3
3.6
1.3
1.5
1.7
VREF – 0.2
VREF + 0.2
Notes:
1.
2.
3.
4.
5.
6.
Descriptions of the symbols used in this table are as follows:
VCCO – the supply voltage for output drivers
VREF – the reference voltage for setting the input switching threshold
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when VCCAUX = 3.3V range
and for PCI I/O standards.
For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 8.
There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS25 or
LVCMOS33 standard depending on VCCAUX. The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode.
When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as
well as throughout configuration.
For information on PCI IP solutions, see http://www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCI
IOSTANDARD is not supported on input-only pins. The PCIX IOSTANDARD is available and has equivalent characteristics, but no PCI-X IP
is supported.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 12: DC Characteristics of User I/Os Using Single-Ended Standards
IOSTANDARD Attribute
LVTTL(3)
LVCMOS33(3)
LVCMOS25(3)
LVCMOS18(3)
LVCMOS15(3)
LVCMOS12(3)
Test Conditions
Logic Level Characteristics
IOL (mA)
IOH (mA)
VOL Max (V)
VOH Min (V)
2
2
–2
0.4
2.4
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16
16
–16
24
24(6)
–24
0.4
VCCO – 0.4
0.4
VCCO – 0.4
0.4
VCCO – 0.4
0.4
VCCO – 0.4
0.4
VCCO – 0.4
10% VCCO
90% VCCO
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16
16
–16(6)
24(4)
24
–24(6)
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16(4)
16
–16(6)
24(4)
24(6)
–24(6)
2
2
–2
4
4
–4
6
6
–6(6)
8
8
–8
12(4)
12
–12(6)
16(4)
16
–16
2
2
–2
4
4
–4
6
6
–6
8(4)
8
–8
12(4)
12
–12
2
2
–2
4(4)
4
–4
6(4)
6
–6
1.5
–0.5
PCI33_3(5)
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 12: DC Characteristics of User I/Os Using Single-Ended Standards (Cont’d)
Test Conditions
IOSTANDARD Attribute
Logic Level Characteristics
IOL (mA)
IOH (mA)
VOL Max (V)
VOH Min (V)
8
–8
0.4
VCCO – 0.4
–8
0.4
VCCO – 0.4
–8
0.4
VCCO – 0.4
0.4
VCCO – 0.4
–8
0.4
VCCO – 0.4
HSTL_I(4)
HSTL_III(4)
24(7)
HSTL_I_18
8
HSTL_II_18(4)
16
HSTL_III_18
24(7)
SSTL18_I
6.7
–6.7
VTT – 0.475
VTT + 0.475
SSTL18_II(4)
13.4
–13.4
VTT – 0.475
VTT + 0.475
SSTL2_I
8.1
–8.1
VTT – 0.61
VTT + 0.61
SSTL2_II(4)
16.2
–16.2
VTT – 0.80
VTT + 0.80
SSTL3_I
8
–8
VTT – 0.6
VTT + 0.6
SSTL3_II
16
–16
VTT – 0.8
VTT + 0.8
–16(7)
Notes:
1.
2.
The numbers in this table are based on the conditions set forth in Table 8 and Table 11.
Descriptions of the symbols used in this table are as follows:
3.
4.
For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes.
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O
Resources" in UG331.
Tested according to the relevant PCI specifications. For information on PCI IP solutions, see
http://www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCI IOSTANDARD is not supported on
input-only pins. The PCIX IOSTANDARD is available and has equivalent characteristics, but no PCI-X IP is supported.
DE-RATE by 20% for TJ above 100°C
DE-RATE by 5% for TJ above 100°C
5.
6.
7.
IOL – the output current condition under which VOL is tested
IOH – the output current condition under which VOH is tested
VOL – the output voltage that indicates a Low logic level
VOH – the output voltage that indicates a High logic level
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
VCCO – the supply voltage for output drivers
VREF – the reference voltage for setting the input switching threshold
VTT – the voltage applied to a resistor termination
Differential I/O Standards
Differential Input Pairs
X-Ref Target - Figure 4
VINP
Internal
Logic
VINN
VINN
VINP
Differential
I/O Pair Pins
P
N
VID
50%
VICM
GND level
VICM = Input common mode voltage =
VINP + VINN
2
VID = Differential input voltage = VINP - VINN
DS681_03_041111
Figure 4: Differential Input Voltages
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VCCO for Drivers(1)
VICM(2)
VID
Min (V)
Nom (V)
Max (V)
LVDS_25(3)
Min (mV) Nom (mV) Max (mV)
Min (V)
Nom (V)
Max (V)
2.25
2.5
2.75
100
350
LVDS_33(3)
600
0.3
1.25
2.35
3.0
3.3
3.6
100
BLVDS_25(4)
350
600
0.3
1.25
2.35
2.25
2.5
2.75
MINI_LVDS_25(3)
100
300
–
0.3
1.3
2.35
2.25
2.5
MINI_LVDS_33(3)
2.75
200
–
600
0.3
1.2
1.95
3.0
3.3
3.6
200
–
600
0.3
1.2
1.95
LVPECL_25(5)
Inputs Only
100
800
1000
0.3
1.2
1.95
LVPECL_33(5)
Inputs Only
100
800
1000
0.3
1.2
2.8(6)
RSDS_25(3)
2.25
2.5
2.75
100
200
–
0.3
1.2
1.5
RSDS_33(3)
3.0
3.3
3.6
100
200
–
0.3
1.2
1.5
TMDS_33(3,4,7)
3.14
3.3
3.47
150
–
1200
2.7
–
3.23
PPDS_25(3)
2.25
2.5
2.75
100
–
400
0.2
–
2.3
PPDS_33(3)
3.0
3.3
3.6
100
–
400
0.2
–
2.3
DIFF_HSTL_I_18
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_II_18(8)
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_III_18
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_I
1.4
1.5
1.6
100
–
–
0.68
DIFF_HSTL_III
1.4
1.5
1.6
100
–
–
–
0.9
–
DIFF_SSTL18_I
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL18_II(8)
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL2_I
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL2_II(8)
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL3_I
3.0
3.3
3.6
100
–
–
1.1
–
1.9
DIFF_SSTL3_II
3.0
3.3
3.6
100
–
–
1.1
–
1.9
0.9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The VCCO rails supply only differential output drivers, not input circuits.
VICM must be less than VCCAUX.
These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O
Resources" in UG331.
See External Termination Requirements for Differential I/O, page 16.
LVPECL is supported on inputs only, not outputs. LVPECL_33 requires VCCAUX=3.3V ± 10%.
LVPECL_33 maximum VICM = the lower of 2.8V or VCCAUX – (VID / 2)
Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) VICM (VCCAUX – 37 mV)
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O
Resources" in UG331.
VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in
Table 11. Other differential standards do not use VREF.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Differential Output Pairs
X-Ref Target - Figure 5
VOUTP
Internal
Logic
P
N
VOUTN
Differential
I/O Pair Pins
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
VOCM = Output common mode voltage =
VOUTP + VOUTN
2
VOD = Output differential voltage = VOUTP - VOUTN
VOH = Output voltage indicating a High logic level
VOL = Output voltage indicating a Low logic levelDS681_04_041111
Figure 5: Differential Output Voltages
Table 14: DC Characteristics of User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VOCM
VOD
Min (mV)
Typ (mV) Max (mV)
VOH
VOL
Min (V)
Typ (V)
Max (V)
Min (V)
Max (V)
LVDS_25
247
350
454
1.125
–
–
–
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
247
240
300
300
100
100
400
100
350
350
1.125
–
–
–
–
1.30
–
–
–
1.0
1.0
1.0
1.0
VCCO – 0.405
0.5
–
–
–
–
–
–
–
–
–
–
0.8
1.4
1.4
1.4
1.4
VCCO – 0.190
1.4
–
–
454
460
600
600
400
400
800
400
1.375
1.375
–
–
PPDS_33
–
–
–
–
–
–
–
–
–
100
–
400
0.5
0.8
1.4
–
–
DIFF_HSTL_I_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_II_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_III_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_I
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_III
–
–
–
–
–
–
DIFF_SSTL18_I
–
–
–
–
–
–
DIFF_SSTL18_II
–
–
–
–
–
–
DIFF_SSTL2_I
–
–
–
–
–
–
DIFF_SSTL2_II
–
–
–
–
–
–
DIFF_SSTL3_I
–
–
–
–
–
–
DIFF_SSTL3_II
–
–
–
–
–
–
VCCO – 0.4
VTT + 0.475
VTT + 0.475
VTT + 0.61
VTT + 0.81
VTT + 0.6
VTT + 0.8
VTT – 0.475
VTT – 0.475
VTT – 0.61
VTT – 0.81
VTT – 0.6
VTT – 0.8
0.4
Notes:
1.
2.
3.
4.
The numbers in this table are based on the conditions set forth in Table 8 and Table 13.
See External Termination Requirements for Differential I/O, page 16.
Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100 across the N and P pins of the
differential signal pair.
At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V
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XA Spartan-3A Automotive FPGA Family Data Sheet
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
X-Ref Target - Figure 6
Bank 0 and 2
Any Bank
Bank 0
Bank 2
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
Bank 1
1/4 th of Bourns
Part Number
Z0 = 50Ω CAT16-PT4F4
Bank 3
Bank 0
No VCCO Restrictions
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
Bank 2
100Ω
Z0 = 50Ω
DIFF_TERM=No
a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
RDT
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
DIFF_TERM=Yes
b) Differential pairs using DIFF_TERM=Yes constraint
DS681_05_041111
Figure 6: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
X-Ref Target - Figure 7
Any Bank
Any Bank
Bank 0
Bank 3
1/4 th of Bourns
Part Number
CAT16-PT4F4
Z0 = 50Ω
165Ω
140Ω
BLVDS_25
Z0 = 50Ω
Bank 1
Bank 1
Bank 2
VCCO = 2.5V
1/4 th of Bourns
Part Number
CAT16-LV4F12
Bank 3
Bank 0
Bank 2
No VCCO Requirement
100Ω
BLVDS_25
165Ω
DS681_06_041111
Figure 7: External Termination Resistors for BLVDS_25 I/O Standard
TMDS_33 I/O Standard
X-Ref Target - Figure 8
Any Bank
Bank 0 and 2
Bank 0
3.3V
Bank 2
50Ω
Bank 1
Bank 3
Bank 0
50Ω
Bank 2
VCCAUX = 3.3V
VCCO = 3.3V
TMDS_33
TMDS_33
DVI/HDMI cable
DS681_07_041111
Figure 8: External Input Resistors Required for TMDS_33 I/O Standard
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XA Spartan-3A Automotive FPGA Family Data Sheet
Device DNA Data Retention, Read Endurance
Table 15: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
30,000,000
Read
cycles
Switching Characteristics
All XA Spartan-3A FPGAs ship in the -4 speed grade. Switching characteristics in this document are designated as
Production as shown in Table 16.
Production: These specifications are approved once enough production silicon of a particular device family member has
been characterized to provide full correlation between speed files and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes.
Software Version Requirements
Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status.
FPGA designs using a less mature speed file designation should only be used during system prototyping or pre-production
qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a
production-quality system.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE
software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software
updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise
noted, the published parameter values apply to all XA Spartan-3A devices, and AC and DC characteristics are specified
using the same numbers for both I-Grade and Q-Grade.
To create a Xilinx user account and sign up for automatic E-mail notification whenever this data sheet is updated:
Sign Up for Alerts: www.xilinx.com/support/answers/18683.htm
Timing parameters and their representative values are selected for inclusion below either because they are important as
general design requirements or they indicate fundamental device performance characteristics. The XA Spartan-3A FPGA
speed files (v1.41), part of the Xilinx Development Software, are the original source for many but not all of the values. The
speed grade designations for these files are shown in Table 16. For more complete, more precise, and worst-case data, use
the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to
the simulation netlist.
Table 16: XA Spartan-3A FPGA v1.41 Speed Grade Designations
Device
Production
XA3S200A
-4
XA3S400A
-4
XA3S700A
-4
XA3S1400A
-4
Table 17 provides the recent history of the XA Spartan-3A FPGA speed files.
Table 17: XA Spartan-3A FPGA Speed File Version History
Version
ISE Release
Description
1.39
10.1.01i
Initial release.
1.40
10.1.02i
Updated input timing adjustments.
1.41
10.1.03i
Updated output timing adjustments.
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XA Spartan-3A Automotive FPGA Family Data Sheet
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Symbol
Description
Conditions
When reading from the Output Flip-Flop
(OFF), the time from the active transition on
the Global Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25(2), 12mA
output drive, Fast slew
rate, with DCM(3)
Speed Grade: -4
Device
Max
Units
Clock-to-Output Times
TICKOFDCM
TICKOF
LVCMOS25(2),
When reading from OFF, the time from the
12mA
active transition on the Global Clock pin to
output drive, Fast slew
data appearing at the Output pin. The DCM is rate, without DCM
not in use.
XA3S200A
3.27
ns
XA3S400A
3.33
ns
XA3S700A
3.50
ns
XA3S1400A
3.99
ns
XA3S200A
5.24
ns
XA3S400A
5.12
ns
XA3S700A
5.34
ns
XA3S1400A
5.69
ns
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 22. If the latter is true, add the appropriate Output adjustment from Table 25.
DCM output jitter is included in all measurements.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Description
Conditions
Device
Speed Grade: -4
Min
Units
Setup Times
TPSDCM
TPSFD
When writing to the Input Flip-Flop (IFF), the LVCMOS25(2),
time from the setup of data at the Input pin IFD_DELAY_VALUE = 0,
to the active transition at a Global Clock pin. with DCM(4)
The DCM is in use. No Input Delay is
programmed.
XA3S200A
2.84
ns
XA3S400A
2.68
ns
XA3S700A
2.57
ns
XA3S1400A
2.17
ns
When writing to IFF, the time from the setup LVCMOS25(2),
of data at the Input pin to an active transition IFD_DELAY_VALUE = 5,
at the Global Clock pin. The DCM is not in without DCM
use. The Input Delay is progr ammed.
XA3S200A
2.76
ns
XA3S400A
2.60
ns
XA3S700A
2.63
ns
XA3S1400A
2.41
ns
When writing to IFF, the time from the active LVCMOS25(3),
transition at the Global Clock pin to the point IFD_DELAY_VALUE = 0,
when data must be held at the Input pin. The with DCM(4)
DCM is in use. No Input Delay is
programmed.
XA3S200A
–0.52
ns
XA3S400A
–0.29
ns
XA3S700A
–0.12
ns
XA3S1400A
0.00
ns
When writing to IFF, the time from the active LVCMOS25(3),
transition at the Global Clock pin to the point IFD_DELAY_VALUE = 5,
when data must be held at the Input pin. The without DCM
DCM is not in use. The Input Delay is
programmed.
XA3S200A
–0.56
ns
XA3S400A
–0.42
ns
XA3S700A
–0.75
ns
XA3S1400A
–0.69
ns
Hold Times
TPHDCM
TPHFD
Notes:
1.
2.
3.
4.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 22. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 22. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Speed Grade: -4
0
XA3S200A
1.81
ns
XA3S400A
1.51
ns
XA3S700A
1.51
ns
XA3S1400A
1.74
ns
Min
Units
Setup Times
TIOPICK
Time from the setup of data at the
Input pin to the active transition at
the ICLK input of the Input
Flip-Flop (IFF). No Input Delay is
programmed.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 20: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
TIOPICKD
Description
Time from the setup of data at the
Input pin to the active transition at
the ICLK input of the Input
Flip-Flop (IFF). The Input Delay is
programmed.
Conditions
LVCMOS25(2)
IFD_
DELAY_
VALUE
Device
Speed Grade: -4
1
XA3S200A
Min
Units
2.20
ns
2
2.93
ns
3
3.78
ns
4
4.37
ns
5
4.20
ns
6
5.23
ns
7
6.11
ns
6.71
ns
2.02
ns
2
2.67
ns
3
3.43
ns
4
3.96
ns
5
3.95
ns
6
4.81
ns
7
5.66
ns
8
1
XA3S400A
6.19
ns
1.95
ns
2
2.83
ns
3
3.72
ns
4
4.31
ns
5
4.14
ns
6
5.19
ns
7
6.10
ns
8
1
XA3S700A
6.73
ns
2.17
ns
2
2.92
ns
3
3.76
ns
4
4.32
ns
5
4.19
ns
6
5.09
ns
7
5.98
ns
8
6.57
ns
XA3S200A
–0.65
ns
XA3S400A
–0.42
ns
XA3S700A
–0.67
ns
XA3S1400A
–0.71
ns
8
1
XA3S1400A
Hold Times
TIOICKP
Time from the active transition at
the ICLK input of the Input
Flip-Flop (IFF) to the point where
data must be held at the Input pin.
No Input Delay is programmed.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 20: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
TIOICKPD
Description
Time from the active transition at
the ICLK input of the Input
Flip-Flop (IFF) to the point where
data must be held at the Input pin.
The Input Delay is programmed.
Conditions
LVCMOS25(3)
IFD_
DELAY_
VALUE
Device
Speed Grade: -4
1
XA3S200A
Min
Units
–1.51
ns
2
–2.09
ns
3
–2.40
ns
4
–2.68
ns
5
–2.56
ns
6
–2.99
ns
7
–3.29
ns
–3.61
ns
–1.12
ns
2
–1.70
ns
3
–2.08
ns
4
–2.38
ns
5
–2.23
ns
6
–2.69
ns
7
–3.08
ns
8
1
XA3S400A
–3.35
ns
–1.67
ns
2
–2.27
ns
3
–2.59
ns
4
–2.92
ns
5
–2.89
ns
6
–3.22
ns
7
–3.52
ns
8
1
XA3S700A
–3.81
ns
–1.60
ns
2
–2.06
ns
3
–2.46
ns
4
–2.86
ns
5
–2.88
ns
6
–3.24
ns
7
–3.55
ns
8
–3.89
ns
1.61
ns
8
1
XA3S1400A
Set/Reset Pulse Width
TRPW_IOB
Minimum pulse width to SR control
input on IOB
All
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 22.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 22. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Input Propagation Times
Table 21: Propagation Times for the IOB Input Path
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Speed Grade: -4
0
XA3S200A
2.04
ns
XA3S400A
1.74
ns
XA3S700A
1.74
ns
XA3S1400A
1.97
ns
XA3S200A
Max
Units
Propagation Times
TIOPLI
TIOPLID
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
LVCMOS25(2)
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2)
2.43
ns
2
1
3.16
ns
3
4.01
ns
4
4.60
ns
5
4.43
ns
6
5.46
ns
7
6.33
ns
8
6.94
ns
2.25
ns
2
2.90
ns
3
3.66
ns
4
4.19
ns
5
4.18
ns
6
5.03
ns
7
5.88
ns
8
6.42
ns
1
XA3S400A
2.18
ns
2
3.06
ns
3
3.95
ns
4
4.54
ns
5
4.37
ns
6
5.42
ns
7
6.33
ns
8
6.96
ns
1
XA3S700A
2.40
ns
2
3.15
ns
3
3.99
ns
4
4.55
ns
5
4.42
ns
6
5.32
ns
7
6.21
ns
8
6.80
ns
1
XA3S1400A
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 22.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Input Timing Adjustments
Table 22: Input Timing Adjustments by IOSTANDARD
Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD)
Single-Ended Standards
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
Differential Standards
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Add the Adjustment Below
Speed Grade: -4
Units
0.62
0.54
0
0.83
0.60
0.31
0.45
0.72
0.85
0.69
0.83
0.79
0.71
0.71
0.71
0.71
0.78
0.78
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.79
0.79
0.79
0.84
0.84
0.80
0.80
0.83
0.83
0.80
0.81
0.81
0.80
0.98
1.05
0.77
1.05
0.76
0.76
0.77
0.77
1.06
1.06
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8, Table 11, and Table 13.
These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other
signal standards.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Output Propagation Times
Table 23: Timing for the IOB Output Path
Symbol
Description
Conditions
Device
Speed Grade: -4
Max
Units
Clock-to-Output Times
TIOCKP
When reading from the Output Flip-Flop (OFF),
the time from the active transition at the OCLK
input to data appearing at the Output pin
LVCMOS25(2), 12 mA
output drive, Fast slew
rate
All
3.13
ns
LVCMOS25(2), 12 mA
output drive, Fast slew
rate
All
2.91
ns
LVCMOS25(2), 12 mA
output drive, Fast slew
rate
All
3.89
ns
9.65
ns
Propagation Times
TIOOP
The time it takes for data to travel from the IOB’s
O input to the Output pin
Set/Reset Times
TIOSRP
TIOGSRQ
Time from asserting the OFF’s SR input to
setting/resetting data at the Output pin
Time from asserting the Global Set Reset (GSR)
input on the STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 25.
Three-State Output Propagation Times
Table 24: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Device
Speed Grade: -4
Max
Units
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK input LVCMOS25, 12 mA
output drive, Fast slew
of the Three-state Flip-Flop (TFF) to when the
rate
Output pin enters the high-impedance state
TIOCKON(2)
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
All
0.76
ns
3.06
ns
All
10.36
ns
All
1.86
ns
3.82
ns
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State (GTS) LVCMOS25, 12 mA
input on the STARTUP_SPARTAN3A primitive to output drive, Fast slew
when the Output pin enters the high-impedance
rate
state
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
TIOSRON(2)
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
LVCMOS25, 12 mA
output drive, Fast slew
rate
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 25.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Output Timing Adjustments
Table 25: Output Timing Adjustments for IOB
Convert Output Time from LVCMOS25 with 12 mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
Add the Adjustment Below
Speed Grade: -4
Units
Single-Ended Standards
LVTTL
Slow
Fast
QuietIO
LVCMOS33
Slow
Fast
QuietIO
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2 mA
5.58
ns
4 mA
3.45
ns
6 mA
3.45
ns
8 mA
2.26
ns
12 mA
1.66
ns
16 mA
1.29
ns
24 mA
2.97
ns
2 mA
3.37
ns
4 mA
2.27
ns
6 mA
2.27
ns
8 mA
0.63
ns
12 mA
0.61
ns
16 mA
0.59
ns
24 mA
0.60
ns
2 mA
27.67
ns
4 mA
27.67
ns
6 mA
27.67
ns
8 mA
16.71
ns
12 mA
16.67
ns
16 mA
16.22
ns
24 mA
12.11
ns
2 mA
5.58
ns
4 mA
3.30
ns
6 mA
3.30
ns
8 mA
2.26
ns
12 mA
1.29
ns
16 mA
1.22
ns
24 mA
2.79
ns
2 mA
3.72
ns
4 mA
2.05
ns
6 mA
2.08
ns
8 mA
0.53
ns
12 mA
0.59
ns
16 mA
0.59
ns
24 mA
0.51
ns
2 mA
27.67
ns
4 mA
27.67
ns
6 mA
27.67
ns
8 mA
16.71
ns
12 mA
16.29
ns
16 mA
16.18
ns
24 mA
12.11
ns
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 25: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12 mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
LVCMOS25
Slow
Fast
QuietIO
LVCMOS18
Slow
Fast
QuietIO
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Add the Adjustment Below
Speed Grade: -4
Units
2 mA
5.33
ns
4 mA
2.91
ns
6 mA
2.92
ns
8 mA
1.23
ns
12 mA
1.23
ns
16 mA
0.91
ns
24 mA
2.31
ns
2 mA
4.71
ns
4 mA
2.20
ns
6 mA
1.49
ns
8 mA
0.39
ns
12 mA
0
ns
16 mA
0.01
ns
24 mA
0.01
ns
2 mA
25.92
ns
4 mA
25.92
ns
6 mA
25.92
ns
8 mA
15.57
ns
12 mA
15.59
ns
16 mA
14.27
ns
24 mA
11.37
ns
2 mA
5.00
ns
4 mA
3.69
ns
6 mA
2.91
ns
8 mA
2.03
ns
12 mA
1.57
ns
16 mA
1.19
ns
2 mA
4.12
ns
4 mA
2.63
ns
6 mA
1.91
ns
8 mA
1.06
ns
12 mA
0.83
ns
16 mA
0.63
ns
2 mA
24.97
ns
4 mA
24.97
ns
6 mA
24.08
ns
8 mA
16.43
ns
12 mA
14.52
ns
16 mA
13.41
ns
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 25: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12 mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
LVCMOS15
Slow
Fast
QuietIO
LVCMOS12
Slow
Fast
QuietIO
Add the Adjustment Below
Speed Grade: -4
Units
2 mA
6.42
ns
4 mA
3.97
ns
6 mA
3.21
ns
8 mA
2.53
ns
12 mA
2.06
ns
2 mA
5.83
ns
4 mA
3.05
ns
6 mA
1.95
ns
8 mA
1.60
ns
12 mA
1.30
ns
2 mA
34.11
ns
4 mA
25.66
ns
6 mA
24.64
ns
8 mA
22.06
ns
12 mA
20.64
ns
2 mA
7.14
ns
4 mA
4.87
ns
6 mA
5.67
ns
2 mA
6.77
ns
4 mA
5.02
ns
6 mA
4.09
ns
2 mA
50.76
ns
4 mA
43.17
ns
6 mA
37.31
ns
PCI33_3
0.34
ns
HSTL_I
0.86
ns
HSTL_III
1.16
ns
HSTL_I_18
0.35
ns
HSTL_II_18
0.30
ns
HSTL_III_18
0.47
ns
SSTL18_I
0.40
ns
SSTL18_II
0.30
ns
SSTL2_I
0
ns
SSTL2_II
–0.05
ns
SSTL3_I
0
ns
SSTL3_II
0.17
ns
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 25: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12 mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
Add the Adjustment Below
Speed Grade: -4
Units
Differential Standards
LVDS_25
1.50
ns
LVDS_33
0.47
ns
BLVDS_25
0.11
ns
MINI_LVDS_25
1.11
ns
MINI_LVDS_33
0.41
ns
LVPECL_25
Input Only
LVPECL_33
Input Only
RSDS_25
1.73
ns
RSDS_33
0.64
ns
TMDS_33
0.07
ns
PPDS_25
1.28
ns
PPDS_33
0.88
ns
DIFF_HSTL_I_18
0.43
ns
DIFF_HSTL_II_18
0.41
ns
DIFF_HSTL_III_18
0.36
ns
DIFF_HSTL_I
1.01
ns
DIFF_HSTL_III
1.16
ns
DIFF_SSTL18_I
0.49
ns
DIFF_SSTL18_II
0.41
ns
DIFF_SSTL2_I
0.91
ns
DIFF_SSTL2_II
0.11
ns
DIFF_SSTL3_I
1.18
ns
DIFF_SSTL3_II
0.28
ns
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8, Table 11, and Table 13.
These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with 12 mA drive
and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a
high-impedance state.
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Timing Measurement Methodology
When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions.
Table 26 lists the conditions to use for each standard.
The method for measuring Input timing is as follows: A signal that swings between a Low logic level of VL and a High logic
level of VH is applied to the Input under test. Some standards also require the application of a bias voltage to the VREF pins
of a given bank to properly set the input-switching threshold. The measurement point of the Input signal (VM) is commonly
located halfway between VL and VH.
The Output test setup is shown in Figure 9. A termination voltage VT is applied to the termination resistor RT, the other end
of which is connected to the Output. For each standard, RT and VT generally take on the standard values recommended for
minimizing signal reflections. If the standard does not ordinarily use terminations (for example, LVCMOS, LVTTL), then RT
is set to 1 M to indicate an open connection, and VT is set to zero. The same measurement point (VM) that was used at the
Input is also used at the Output.
X-Ref Target - Figure 9
VT (VREF)
FPGA Output
RT (RREF)
VM (VMEAS)
CL (CREF)
DS681_08_041111
Notes:
1.
The names shown in parentheses are
used in the IBIS file.
Figure 9: Output Test Setup
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Table 26: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Inputs
Inputs and
Outputs
Outputs
VREF (V)
VL (V)
VH (V)
RT ()
VT (V)
VM (V)
LVTTL
–
0
3.3
1M
0
1.4
LVCMOS33
–
0
3.3
1M
0
1.65
LVCMOS25
–
0
2.5
1M
0
1.25
LVCMOS18
–
0
1.8
1M
0
0.9
LVCMOS15
–
0
1.5
1M
0
0.75
LVCMOS12
–
0
1.2
1M
0
0.6
–
Note 3
Note 3
25
0
0.94
25
3.3
2.03
Single-Ended
PCI33_3
Rising
Falling
HSTL_I
0.75
VREF – 0.5
VREF + 0.5
50
0.75
VREF
HSTL_III
0.9
VREF – 0.5
VREF + 0.5
50
1.5
VREF
HSTL_I_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
HSTL_II_18
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
SSTL18_I
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
SSTL2_I
1.25
VREF – 0.75
VREF + 0.75
50
1.25
VREF
SSTL2_II
1.25
VREF – 0.75
VREF + 0.75
25
1.25
VREF
SSTL3_I
1.5
VREF – 0.75
VREF + 0.75
50
1.5
VREF
SSTL3_II
1.5
VREF – 0.75
VREF + 0.75
25
1.5
VREF
LVDS_25
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVDS_33
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
BLVDS_25
–
VICM – 0.125
VICM + 0.125
1M
0
VICM
MINI_LVDS_25
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
MINI_LVDS_33
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVPECL_25
–
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
LVPECL_33
–
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
RSDS_25
–
VICM – 0.1
VICM + 0.1
50
1.2
VICM
RSDS_33
–
VICM – 0.1
VICM + 0.1
50
1.2
VICM
TMDS_33
–
VICM – 0.1
VICM + 0.1
50
3.3
VICM
PPDS_25
–
VICM – 0.1
VICM + 0.1
50
0.8
VICM
PPDS_33
–
VICM – 0.1
VICM + 0.1
50
0.8
VICM
DIFF_HSTL_I
0.75
VREF – 0.5
VREF + 0.5
50
0.75
VREF
DIFF_HSTL_III
0.9
VREF – 0.5
VREF + 0.5
50
1.5
VREF
DIFF_HSTL_I_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
DIFF_HSTL_II_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
DIFF_HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
DIFF_SSTL18_I
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
Differential
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 26: Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard
(IOSTANDARD)
Inputs
Inputs and
Outputs
Outputs
VREF (V)
VL (V)
VH (V)
RT ()
VT (V)
VM (V)
DIFF_SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
DIFF_SSTL2_I
1.25
VREF – 0.5
VREF + 0.5
50
1.25
VREF
DIFF_SSTL2_II
1.25
VREF – 0.5
VREF + 0.5
50
1.25
VREF
DIFF_SSTL3_I
1.5
VREF – 0.5
VREF + 0.5
50
1.5
VREF
DIFF_SSTL3_II
1.5
VREF – 0.5
VREF + 0.5
50
1.5
VREF
Notes:
1.
2.
3.
Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 M when no parallel termination is required
VT – Termination voltage
The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
According to the PCI specification.
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load Conditions in Application
IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS
model (VREF, RREF, and VMEAS) correspond directly with the parameters used in Table 26 (VT, RT, and VM). Do not confuse
VREF (the termination voltage) from the IBIS model with VREF (the input-switching threshold) from the table. A fourth
parameter, CREF, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in
the Xilinx development software as well as at the following link:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
Delays for a given application are simulated according to its specific load conditions as follows:
1. Simulate the desired signal standard with the output driver connected to the test setup shown in Figure 9. Use
parameter values VT, RT, and VM from Table 26. CREF is zero.
2. Record the time to VM.
3. Simulate the same signal standard with the output driver connected to the PCB trace with load. Use the appropriate IBIS
model (including VREF, RREF, CREF, and VMEAS values) or capacitive value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of steps 2 and 4. Add (or subtract) the increase (or decrease) in delay to (or from) the appropriate
Output standard adjustment (Table 25) to yield the worst-case delay of the PCB trace.
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Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended maximum allowable number of Simultaneous Switching Outputs
(SSOs). These guidelines describe the maximum number of user I/O pins of a given output signal standard that should
simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for
the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.
Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output
drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the VCCO rail; High-to-Low
transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the
inductance that exists between the die pad and the power supply or ground return. The inductance is associated with
bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO
noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage
consequently affects internal switching noise margins and ultimately signal quality.
Table 27 and Table 28 provide the essential SSO guidelines. For each device/package combination, Table 27 provides the
number of equivalent VCCO/GND pairs. For each output signal standard and drive strength, Table 28 recommends the
maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The guidelines
in Table 28 are categorized by package style, slew rate, and output drive current. Furthermore, the number of SSOs is
specified by I/O bank. Generally, the left and right I/O banks (Banks 1 and 3) support higher output drive current.
Multiply the appropriate numbers from Table 27 and Table 28 to calculate the maximum number of SSOs allowed within an
I/O bank. Exceeding these SSO guidelines might result in increased power or ground bounce, degraded signal integrity, or
increased system jitter.
SSOMAX/IO Bank = Table 27 x Table 28
The recommended maximum SSO values assumes that the FPGA is soldered on the printed circuit board and that the board
uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance
introduced by the socket.
Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs.
Table 27: Equivalent VCCO/GND Pairs per Bank
Device
Package Style (Pb-free)
FTG256
FGG400
FGG484
XA3S200A
4
–
–
XA3S400A
4
5
–
XA3S700A
–
5
5
XA3S1400A
–
–
6
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO/GND Pair (VCCAUX=3.3V)
Package Type: FTG256, FGG400, FGG484
Signal Standard (IOSTANDARD)
Top, Bottom (Banks 0,2)
Left, Right (Banks 1,3)
2
60
60
4
41
41
6
29
29
8
22
22
12
13
13
16
11
11
Single-Ended Standards
LVTTL
Slow
Fast
QuietIO
LVCMOS33
Slow
Fast
QuietIO
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9
9
2
10
10
4
6
6
6
5
5
8
3
3
12
3
3
16
3
3
24
2
2
2
80
80
4
48
48
6
36
36
8
27
27
12
16
16
16
13
13
24
12
12
2
76
76
4
46
46
6
27
27
8
20
20
12
13
13
16
10
10
24
–
9
2
10
10
4
8
8
6
5
5
8
4
4
12
4
4
16
2
2
24
–
2
2
76
76
4
46
46
6
32
32
8
26
26
12
18
18
16
14
14
24
–
10
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Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO/GND Pair (VCCAUX=3.3V) (Cont’d)
Package Type: FTG256, FGG400, FGG484
Signal Standard (IOSTANDARD)
LVCMOS25
Slow
Fast
QuietIO
LVCMOS18
Slow
Fast
QuietIO
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Top, Bottom (Banks 0,2)
Left, Right (Banks 1,3)
2
76
76
4
46
46
6
33
33
8
24
24
12
18
18
16
–
11
24
–
7
2
18
18
4
14
14
6
6
6
8
6
6
12
3
3
16
–
3
24
–
2
2
76
76
4
60
60
6
48
48
8
36
36
12
36
36
16
–
36
24
–
8
2
64
64
4
34
34
6
22
22
8
18
18
12
–
13
16
–
10
2
18
18
4
9
9
6
7
7
8
4
4
12
–
4
16
–
3
2
64
64
4
64
64
6
48
48
8
36
36
12
–
36
16
–
24
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Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO/GND Pair (VCCAUX=3.3V) (Cont’d)
Package Type: FTG256, FGG400, FGG484
Signal Standard (IOSTANDARD)
LVCMOS15
Slow
Fast
QuietIO
Top, Bottom (Banks 0,2)
Left, Right (Banks 1,3)
2
55
55
4
31
31
6
18
18
8
–
15
12
–
10
2
25
25
4
10
10
6
6
6
8
–
4
12
–
3
2
70
70
4
40
40
6
31
31
8
–
31
12
–
20
2
40
40
4
–
25
6
–
18
2
31
31
4
–
13
6
–
9
2
55
55
4
–
36
6
–
36
PCI33_3
16
16
HSTL_I
–
20
HSTL_III
–
8
HSTL_I_18
17
17
HSTL_II_18
–
5
HSTL_III_18
10
8
SSTL18_I
7
15
SSTL18_II
–
9
SSTL2_I
18
18
SSTL2_II
–
9
SSTL3_I
8
10
SSTL3_II
6
7
LVCMOS12
Slow
Fast
QuietIO
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO/GND Pair (VCCAUX=3.3V) (Cont’d)
Package Type: FTG256, FGG400, FGG484
Signal Standard (IOSTANDARD)
Top, Bottom (Banks 0,2)
Left, Right (Banks 1,3)
LVDS_25
22
–
LVDS_33
27
–
BLVDS_25
4
4
MINI_LVDS_25
22
–
MINI_LVDS_33
27
–
RSDS_25
22
–
RSDS_33
27
–
TMDS_33
27
–
PPDS_25
22
–
PPDS_33
27
–
DIFF_HSTL_I
–
10
Differential Standards (Number of I/O Pairs or Channels)
LVPECL_25
LVPECL_33
DIFF_HSTL_III
–
4
DIFF_HSTL_I_18
8
8
DIFF_HSTL_II_18
–
2
DIFF_HSTL_III_18
5
4
DIFF_SSTL18_I
3
7
DIFF_SSTL18_II
–
4
DIFF_SSTL2_I
9
9
DIFF_SSTL2_II
–
4
DIFF_SSTL3_I
4
5
DIFF_SSTL3_II
3
3
Notes:
1.
2.
3.
Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than
the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and
TMDS, are only supported in top or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3 Generation FPGA User Guide for
additional information.
The numbers in this table are recommendations that assume sound board layout practice. Test limits are the VIL/VIH voltage limits for the
respective I/O standard.
If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689: Managing Ground Bounce in Large FPGAs for
information on how to perform weighted average SSO calculations.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Configurable Logic Block (CLB) Timing
Table 29: CLB (SLICEM) Timing
Symbol
Description
Speed Grade: -4
Units
Min
Max
When reading from the FFX (FFY) Flip-Flop, the time from the active transition
at the CLK input to data appearing at the XQ (YQ) output
–
0.68
ns
TAS
Time from the setup of data at the F or G input to the active transition at the
CLK input of the CLB
0.36
–
ns
TDICK
Time from the setup of data at the BX or BY input to the active transition at the
CLK input of the CLB
1.88
–
ns
TAH
Time from the active transition at the CLK input to the point where data is last
held at the F or G input
0
–
ns
TCKDI
Time from the active transition at the CLK input to the point where data is last
held at the BX or BY input
0
–
ns
Clock-to-Output Times
TCKO
Setup Times
Hold Times
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
0.75
–
ns
TCL
The Low pulse width of the CLK signal
0.75
–
ns
FTOG
Toggle frequency (for export control)
0
667
MHz
The time it takes for data to travel from the CLB’s F (G) input to the X (Y) output
–
0.71
ns
1.61
–
ns
Propagation Times
TILO
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to the CLB’s SR input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
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Table 30: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade: -4
Units
Min
Max
–
2.01
ns
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
Setup Times
TDS
Setup time of data at the BX or BY input before the active transition at the CLK
input of the distributed RAM
–0.02
–
ns
TAS
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
0.36
–
ns
TWS
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
0.59
–
ns
TDH
Hold time of the BX and BY data inputs after the active transition at the CLK
input of the distributed RAM
0.13
–
ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
0.01
–
ns
Minimum High or Low pulse width at CLK input
1.01
–
ns
Hold Times
Clock Pulse Width
TWPH, TWPL
Table 31: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade: -4
Units
Min
Max
–
4.82
ns
Setup time of data at the BX or BY input before the active transition at the CLK
input of the shift register
0.18
–
ns
Hold time of the BX or BY data input after the active transition at the CLK input
of the shift register
0.16
–
ns
Minimum High or Low pulse width at CLK input
1.01
–
ns
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on the shift
register output
Setup Times
TSRLDS
Hold Times
TSRLDH
Clock Pulse Width
TWPH, TWPL
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Clock Buffer/Multiplexer Switching Characteristics
Table 32: Clock Distribution Switching Characteristics
Symbol
Description
Speed Grade: -4
Min
Max
Units
TGIO
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
–
0.23
ns
TGSI
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs.
Same as BUFGCE enable CE-input
–
0.63
ns
FBUFG
Frequency of signals distributed on global buffers (all sides)
0
333
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
18 x 18 Embedded Multiplier Timing
Table 33: 18 x 18 Embedded Multiplier Timing
Symbol
Description
Speed Grade: -4
Units
Min
Max
–
4.88
ns
Combinatorial Delay
TMULT
Combinational multiplier propagation delay from the A and B inputs to the P
outputs, assuming 18-bit inputs and a 36-bit product (AREG, BREG, and
PREG registers unused)
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to valid data
appearing on the P outputs when using the PREG register(2,3)
–
1.30
ns
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to valid data
appearing on the P outputs when using either the AREG or BREG register(2,4)
–
4.97
ns
Setup Times
TMSDCK_P
Data setup time at the A or B input before the active transition at the CLK
when using only the PREG output register (AREG, BREG registers
unused)(3)
3.98
–
ns
TMSDCK_A
Data setup time at the A input before the active transition at the CLK when
using the AREG input register(4)
0.00
–
ns
TMSDCK_B
Data setup time at the B input before the active transition at the CLK when
using the BREG input register(4)
0.00
–
ns
TMSCKD_P
Data hold time at the A or B input after the active transition at the CLK when
using only the PREG output register (AREG, BREG registers unused)(3)
0.00
–
ns
TMSCKD_A
Data hold time at the A input after the active transition at the CLK when using
the AREG input register(4)
0.45
–
ns
TMSCKD_B
Data hold time at the B input after the active transition at the CLK when using
the BREG input register(4)
0.45
–
ns
Internal operating frequency for a two-stage 18x18 multiplier using the AREG
and BREG input registers and the PREG output register(1)
0
250
MHz
Hold Times
Clock Frequency
FMULT
Notes:
1.
2.
3.
4.
5.
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
The PREG register is typically used when inferring a single-stage multiplier.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
The numbers in this table are based on the operating conditions set forth in Table 8.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Block RAM Timing
Table 34: Block RAM Timing
Symbol
Description
Speed Grade: -4
Units
Min
Max
When reading from block RAM, the delay from the active transition at the CLK
input to data appearing at the DOUT output
–
2.49
ns
TRCCK_ADDR
Setup time for the ADDR inputs before the active transition at the CLK input
of the block RAM
0.36
–
ns
TRDCK_DIB
Setup time for data at the DIN inputs before the active transition at the CLK
input of the block RAM
0.31
–
ns
TRCCK_ENB
Setup time for the EN input before the active transition at the CLK input of the
block RAM
0.77
–
ns
TRCCK_WEB
Setup time for the WE input before the active transition at the CLK input of the
block RAM
1.26
–
ns
Clock-to-Output Times
TRCKO
Setup Times
Hold Times
TRCKC_ADDR
Hold time on the ADDR inputs after the active transition at the CLK input
0
–
ns
TRCKD_DIB
Hold time on the DIN inputs after the active transition at the CLK input
0
–
ns
TRCKC_ENB
Hold time on the EN input after the active transition at the CLK input
0
–
ns
TRCKC_WEB
Hold time on the WE input after the active transition at the CLK input
0
–
ns
Clock Timing
TBPWH
High pulse width of the CLK signal
1.79
–
ns
TBPWL
Low pulse width of the CLK signal
1.79
–
ns
0
280
MHz
Clock Frequency
FBRAM
Block RAM clock frequency
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Digital Clock Manager Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency
Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB
inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 35
and Table 36) apply to any application that only employs the DLL component. When the DFS and/or the PS components are
used together with the DLL, then the specifications listed in the DFS and PS tables (Table 37 through Table 40) supersede
any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions
are presented in Table 35 and Table 36.
Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. In a histogram of
period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods
sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop
Table 35: Recommended Operating Conditions for the DLL
Symbol
Speed Grade: -4
Description
Min
Max
Units
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
5(2)
Frequency of the CLKIN clock input
250(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a percentage of
the CLKIN period
Input Clock Jitter Tolerance and Delay Path
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
FCLKIN 150 MHz
40%
60%
–
FCLKIN 150 MHz
45%
55%
–
FCLKIN 150 MHz
–
±300
ps
FCLKIN 150 MHz
–
±150
ps
Variation(4)
Cycle-to-cycle jitter at the CLKIN
input
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input
–
±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay from the DCM
output to the CLKFB input
–
±1
ns
Notes:
1.
2.
3.
4.
5.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 37.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock period by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 36: Switching Characteristics for the DLL
Symbol
Description
Device
Speed Grade: -4
Units
Min
Max
5
250
MHz
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and CLK180 outputs
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and CLK270 outputs
5
200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
10
334
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output
0.3125
166
MHz
–
±100
ps
Output Clock
All
Jitter(2,3,4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output
All
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output
–
±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output
–
±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output
–
±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
–
±[0.5% of CLKIN
period + 100]
ps
CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing integer
division
–
±150
ps
CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing non-integer
division
–
±[0.5% of CLKIN
period + 100]
ps
All
–
±[1% of CLKIN
period + 350]
ps
All
–
±150
ps
CLK0 to CLK2X
(not CLK2X180)
–
±[1% of CLKIN
period + 100]
ps
All others
–
±[1% of CLKIN
period + 150]
ps
–
5
ms
–
600
s
15
35
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_ Duty cycle variation for the CLK0, CLK90, CLK180, CLK270,
DLL
CLK2X, CLK2X180, and CLKDV outputs, including the
BUFGMUX and clock tree duty-cycle distortion
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN and CLKFB inputs
CLKOUT_PHASE_DLL
Phase offset between DLL outputs
Lock Time
LOCK_DLL(3)
When using the DLL alone: The
time from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase
5 MHz FCLKIN
15 MHz
All
FCLKIN 15 MHz
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, averaged over all steps
All
Notes:
1.
2.
3.
4.
5.
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 35.
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
The typical delay step size is 23 ps.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Digital Frequency Synthesizer
Table 37: Recommended Operating Conditions for the DFS
Symbol
Speed Grade: -4
Description
Units
Min
Max
0.200
333
MHz
FCLKFX 150 MHz
–
±300
ps
FCLKFX 150 MHz
–
±150
ps
–
±1
ns
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency
Period jitter at the CLKIN input
Notes:
1.
2.
3.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 35.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
Table 38: Switching Characteristics for the DFS
Symbol
Description
Device
Speed Grade: -4
Units
Min
Max
All
5
320
MHz
All
Typ
Max
ps
Output Frequency Ranges
CLKOUT_FREQ_FX(2)
Output Clock
Frequency for the CLKFX and CLKFX180 outputs
Jitter(3,4)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and
CLKFX180 outputs.
CLKIN 20 MHz
Use the Spartan-3A
Jitter Calculator:
www.xilinx.com/supp
ort/documentation/dat
a_sheets/s3a_jitter_c
alc.zip
CLKIN 20 MHz
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
ps
Duty Cycle(5,6)
CLKOUT_DUTY_CYCLE_FX
Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
All
–
±[1% of
CLKFX
period
+ 350]
ps
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL
CLK0 output when both the DFS and DLL are used
All
–
±200
ps
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
All
–
±[1% of
CLKFX
period
+ 200]
ps
Phase Alignment(6)
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XA Spartan-3A Automotive FPGA Family Data Sheet
Table 38: Switching Characteristics for the DFS (Cont’d)
Symbol
Description
Device
Speed Grade: -4
Units
Min
Max
–
5
ms
–
450
s
Lock Time
LOCK_FX(2,3)
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output.
The DFS asserts LOCKED when
the CLKFX and CLKFX180
signals are valid. If using both the
DLL and the DFS, use the longer
locking time.
5 MHz FCLKIN 15 MHz
All
FCLKIN 15 MHz
Notes:
1.
2.
3.
4.
5.
6.
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 37.
DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an FPGA. Output jitter
strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities,
switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
Phase Shifter
Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
Speed Grade: -4
Units
Min
Max
1
167
MHz
40%
60%
–
Operating Frequency Ranges
PSCLK_FREQ (FPSCLK)
Frequency for the PSCLK input
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
Table 40: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shift Amount
Units
CLKIN 60 MHz
[INTEGER(10 (TCLKIN – 3 ns))]
steps
CLKIN 60 MHz
[INTEGER(15 (TCLKIN – 3 ns))]
Phase Shifting Range
MAX_STEPS(2)
Maximum allowed number of
DCM_DELAY_STEP(3) steps for a
given CLKIN clock period, where
T = CLKIN clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting
[MAX_STEPS
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
[MAX_STEPS
DCM_DELAY_STEP_MAX]
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 39.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 36.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Miscellaneous DCM Timing
Table 41: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–
CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
N/A
seconds
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
N/A
N/A
minutes
Notes:
1.
2.
3.
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex®-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.
DNA Port Timing
Table 42: DNA_PORT Interface Timing
Symbol
Description
Min
Max
Units
TDNASSU
Setup time on SHIFT before the rising edge of CLK
1.0
–
ns
TDNASH
Hold time on SHIFT after the rising edge of CLK
0.5
–
ns
TDNADSU
Setup time on DIN before the rising edge of CLK
1.0
–
ns
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
–
ns
TDNARSU
Setup time on READ before the rising edge of CLK
5.0
10,000
ns
TDNARH
Hold time on READ after the rising edge of CLK
0
–
ns
0.5
1.5
ns
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
TDNACLKF
CLK frequency
0
100
MHz
TDNACLKH
CLK High time
1.0
ns
TDNACLKL
CLK Low time
1.0
ns
Notes:
1.
The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs.
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XA Spartan-3A Automotive FPGA Family Data Sheet
Suspend Mode Timing
X-Ref Target - Figure 10
Entering Suspend Mode
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
SUSPEND Input
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
AWAKE Output
tAWAKE_GWE
tSUSPEND_GWE
Flip-Flops, Block RAM,
Distributed RAM
Write Protected
tAWAKE_GTS
tSUSPEND_GTS
FPGA Outputs
Defined by SUSPEND constraint
tSUSPEND_DISABLE
FPGA Inputs,
Interconnect
tSUSPEND_ENABLE
Blocked
DS681_09_041111
Figure 10: Suspend Mode Timing
Table 43: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max Units
–
7
–
ns
+160
+300
+600
ns
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–
10
–
ns
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–
