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XC2C128 CoolRunner-II CPLD
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DS093 (v3.2) March 8, 2007
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Product Specification
Features
Description
•
The CoolRunner-II 128-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reliability is improved
•
•
•
Optimized for 1.8V systems
- As fast as 5.7 ns pin-to-pin delays
- As low as 13 μA quiescent current
Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 100 user I/O
- 132-ball CP (0.5mm) BGA with 100 user I/O
- Pb-free available for all packages
Advanced system features
- Fastest in system programming
·
1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
·
DataGATE enable (DGE) signal control
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
·
Optional DualEDGE triggered registers
·
Clock divider (divide by 2,4,6,8,10,12,14,16)
·
CoolCLOCK
- Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
Multiple global output enables
·
Global set/reset
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- PLA architecture
·
Superior pinout retention
·
100% product term routability across function
block
- Optional bus-hold, 3-state or weak pull-up on
selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
·
SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot pluggable
Refer to the CoolRunner™-II family data sheet for architecture description.
This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be
configured as direct input registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
© 2002-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS093 (v3.2) March 8, 2007
Product Specification
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1
XC2C128 CoolRunner-II CPLD
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By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 128
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 128 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see Table 1). This
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital technology, a design technique that makes use
of CMOS technology in both the fabrication and design
methodology. RealDigital technology employs a cascade of
CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high-performance and low power operation.
Supported I/O Standards
for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL make use of a VREF pin for JEDEC
compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C128(1)
IOSTANDARD
Attribute
Board
Input Termination
VREF Voltage VTT
Output
VCCIO
Input
VCCIO
LVTTL
3.3
3.3
N/A
N/A
LVCMOS33
3.3
3.3
N/A
N/A
LVCMOS25
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
LVCMOS15(2)
1.5
1.5
N/A
N/A
HSTL_1
1.5
1.5
0.75
0.75
SSTL2_1
2.5
2.5
1.25
1.25
SSTL3_1
3.3
3.3
1.5
1.5
(1) For information on assigning Vref pins, see XAPP399
(2) LVCMOS15 requires use of Schmitt-trigger inputs.
The CoolRunner-II 128 macrocell features LVCMOS,
LVTTL, SSTL and HSTL I/O implementations. See Table 1
ICC (mA)
40
20
0
50
0
100
150
200
250
Frequency (MHz)
DS093_041905
Figure 1: ICC vs Frequency
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
Typical ICC (mA)
0
25
50
75
100
150
175
200
225
250
0.019
3.97
7.95
11.92
15.89
23.83
27.80
31.93
35.73
39.70
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
2
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DS093 (v3.2) March 8, 2007
Product Specification
XC2C128 CoolRunner-II CPLD
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Absolute Maximum Ratings
Symbol
Description
Value
Units
VCC
Supply voltage relative to ground
–0.5 to 2.0
V
VCCIO
Supply voltage for output drivers
–0.5 to 4.0
V
VJTAG(2)
JTAG input voltage limits
–0.5 to 4.0
V
VCCAUX
JTAG input supply voltage
–0.5 to 4.0
V
VIN(1)
Input voltage relative to ground
–0.5 to 4.0
V
VTS(1)
Voltage applied to 3-state output
–0.5 to 4.0
V
TSTG(3)
Storage Temperature (ambient)
–65 to +150
°C
+ 150
°C
TJ
Junction Temperature
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0V or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Recommended Operating Conditions
Symbol
VCC
VCCIO
VCCAUX
Parameter
Min
Max
Units
Commercial TA = 0°C to +70°C
1.7
1.9
V
Industrial TA = –40°C to +85°C
1.7
1.9
V
Supply voltage for output drivers @ 3.3V operation
3.0
3.6
V
Supply voltage for output drivers @ 2.5V operation
2.3
2.7
V
Supply voltage for output drivers @ 1.8V operation
1.7
1.9
V
Supply voltage for output drivers @ 1.5V operation
1.4
1.6
V
Supply voltage for JTAG programming
1.7
3.6
V
Supply voltage for internal logic
and input buffers
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol
Parameter
Test Conditions
Typical
Max.
Units
ICCSB
Standby current Commercial
VCC = 1.9V, VCCIO = 3.6V
30
120
μA
ICCSB
Standby current Industrial
VCC = 1.9V, VCCIO = 3.6V
60
200
μA
f = 1 MHz
-
500
μA
f = 50 MHz
-
10
mA
ICC
(1)
Dynamic current
CJTAG
JTAG input capacitance
f = 1 MHz
-
10
pF
CCLK
Global clock input capacitance
f = 1 MHz
-
12
pF
CIO
I/O capacitance
f = 1 MHz
-
10
pF
IIL
(2)
Input leakage current
VIN = 0V or VCCIO to 3.9V
-
+/–1
μA
(2)
I/O High-Z leakage
VIN = 0V or VCCIO to 3.9V
-
+/–1
μA
IIH
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
2. See Quality and Reliability section in CoolRunner-II family data sheet for details.
DS093 (v3.2) March 8, 2007
Product Specification
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XC2C128 CoolRunner-II CPLD
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LVCMOS and LVTTL 3.3V DC Voltage Specifications
Min.
Max.
Units
VCCIO
Symbol
Input source voltage
3.0
3.6
V
VIH
High level input voltage
2.0
3.9
V
VIL
Low level input voltage
–0.3
0.8
V
VOH
High level output voltage
IOH = –8 mA, VCCIO = 3V
VCCIO – 0.4V
-
V
IOH = –0.1 mA, VCCIO = 3V
VCCIO – 0.2V
-
V
IOL = 8 mA, VCCIO = 3V
-
0.4
V
IOL = 0.1 mA, VCCIO = 3V
-
0.2
V
VOL
Parameter
Low level output voltage
Test Conditions
LVCMOS 2.5V DC Voltage Specifications
Symbol
VCCIO
Parameter
Test Conditions
Input source voltage
Min.
Max.
Units
2.3
2.7
V
0.3(1)
VIH
High level input voltage
1.7
VIL
Low level input voltage
–0.3
0.7
V
VOH
High level output voltage
IOH = –8 mA, VCCIO = 2.3V
VCCIO –0.4V
-
V
IOH = –0.1 mA, VCCIO = 2.3V
VCCIO – 0.2V
-
V
IOL = 8 mA, VCCIO = 2.3V
-
0.4
V
IOL = 0.1 mA, VCCIO = 2.3V
-
0.2
V
VOL
Low level output voltage
VCCIO +
V
(1) The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without
physical damage.
LVCMOS 1.8V DC Voltage Specifications
Symbol
VCCIO
Parameter
Test Conditions
Input source voltage
Min.
Max.
Units
1.7
1.9
V
+ 0.3(1)
V
VIH
High level input voltage
0.65 x VCCIO
VIL
Low level input voltage
–0.3
0.35 x VCCIO
V
VOH
High level output voltage
IOH = –8 mA, VCCIO = 1.7V
VCCIO – 0.45
-
V
IOH = –0.1 mA, VCCIO = 1.7V
VCCIO – 0.2
-
V
IOL = 8 mA, VCCIO = 1.7V
-
0.45
V
IOL = 0.1 mA, VCCIO = 1.7V
-
0.2
V
VOL
Low level output voltage
VCCIO
(1) The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without
physical damage.
LVCMOS 1.5V DC Voltage Specifications(1)
Symbol
Parameter
VCCIO
Input source voltage
VT+
Input hysteresis threshold voltage
Test Conditions
VTVOH
4
High level output voltage
Min.
Max.
Units
1.4
1.6
V
0.5 x VCCIO
0.8 x VCCIO
V
0.2 x VCCIO
0.5 x VCCIO
V
IOH = –8 mA, VCCIO = 1.4V
VCCIO – 0.45
V
IOH = –0.1 mA, VCCIO = 1.4V
VCCIO – 0.2
V
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DS093 (v3.2) March 8, 2007
Product Specification
XC2C128 CoolRunner-II CPLD
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Symbol
VOL
Parameter
Test Conditions
Low level output voltage
Min.
Max.
Units
IOL = 8 mA, VCCIO = 1.4V
0.4
V
IOL = 0.1 mA, VCCIO = 1.4V
0.2
V
Min.
Max.
Units
1.4
3.9
V
0.5 x VCCIO
0.8 x VCCIO
V
0.2 x VCCIO
0.5 x VCCIO
V
Notes:
1. Hysteresis used on 1.5V inputs.
Schmitt Trigger Input DC Voltage Specifications
Symbol
Parameter
Test Conditions
VCCIO
Input source voltage
VT+
Input hysteresis threshold voltage
VT-
SSTL2-1 DC Voltage Specifications
Min.
Typ.
Max.
Units
VCCIO
Symbol
Input source voltage
Parameter
Test Conditions
2.3
2.5
2.7
V
VREF(1)
VTT(2)
Input reference voltage
1.15
1.25
1.35
V
Termination voltage
VREF – 0.04
1.25
VREF + 0.04
V
VIH
High level input voltage
VREF + 0.18
-
3.9
V
VIL
Low level input voltage
–0.3
-
VREF – 0.18
V
VOH
High level output voltage
IOH = –8 mA, VCCIO = 2.3V
VCCIO – 0.62
-
-
V
VOL
Low level output voltage
IOL = 8 mA, VCCIO = 2.3V
-
-
0.54
V
Notes:
1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed ±2% VREF.
2. VTT of transmitting device must track VREF of receiving devices.
SSTL3-1 DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
VCCIO
Input source voltage
3.0
3.3
3.6
V
VREF(1)
VTT(2)
Input reference voltage
1.3
1.5
1.7
V
Termination voltage
VREF – 0.05
1.5
VREF + 0.05
V
VIH
High level input voltage
VREF + 0.2
-
VCCIO + 0.3
V
VIL
Low level input voltage
–0.3
-
VREF – 0.2
V
VOH
High level output voltage
IOH = –8 mA, VCCIO = 3V
VCCIO – 1.1
-
-
V
VOL
Low level output voltage
IOL = 8 mA, VCCIO = 3V
-
-
0.7
V
Notes:
1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed ±2% VREF.
2. VTT of transmitting device must track VREF of receiving devices.
HSTL1 DC Voltage Specifications
Min.
Typ.
Max.
Units
VCCIO
Symbol
Input source voltage
Parameter
Test Conditions
1.4
1.5
1.6
V
VREF(1)
VTT(2)
Input reference voltage
0.68
0.75
0.90
V
VIH
High level input voltage
VREF + 0.1
-
1.9
V
VIL
Low level input voltage
–0.3
-
VREF – 0.1
V
Termination voltage
DS093 (v3.2) March 8, 2007
Product Specification
VCCIO x 0.5
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5
XC2C128 CoolRunner-II CPLD
Symbol
Parameter
R
Test Conditions
Min.
Typ.
Max.
Units
VOH
High level output voltage
IOH = –8 mA, VCCIO = 1.7V
VCCIO -0.4
-
-
V
VOL
Low level output voltage
IOL = 8 mA, VCCIO = 1.7V
-
-
0.4
V
Notes:
1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed ±2% VREF.
2. VTT of transmitting device must track VREF of receiving devices.
6
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DS093 (v3.2) March 8, 2007
Product Specification
XC2C128 CoolRunner-II CPLD
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AC Electrical Characteristics Over Recommended Operating Conditions
-6
Symbol
Parameter
-7
Min.
Max.
Min.
Max.
Units
TPD1
Propagation delay single p-term
-
5.7
-
7.0
ns
TPD2
Propagation delay OR array
-
6.0
-
7.5
ns
TSUD
Direct input register set-up time
3.6
-
4.6
-
ns
TSU1
Setup time fast (single p-term)
2.4
-
3.0
-
ns
TSU2
Setup time (OR array)
2.7
-
3.5
-
ns
THD
Direct input register hold time
0.0
-
0.0
-
ns
TH
Hold time (Or array or p-term)
0.0
-
0.0
-
ns
TCO
Clock to output
-
4.2
-
5.4
ns
FTOGGLE(1)
Internal toggle rate
-
450
-
300
MHz
FSYSTEM1
(2)
Maximum system frequency
-
244
-
152
MHz
FSYSTEM2
(2)
Maximum system frequency
-
227
-
141
MHz
FEXT1(3)
Maximum external frequency
-
152
-
119
MHz
(3)
Maximum external frequency
-
145
-
112
MHz
FEXT2
TPSUD
Direct input register p-term clock setup time
2.5
-
3.1
-
ns
TPSU1
P-term clock setup time (single p-term)
1.3
-
1.5
-
ns
TPSU2
P-term clock setup time (OR array)
1.6
-
2.0
-
ns
TPHD
Direct input register p-term clock hold time
0.2
-
0.2
-
ns
TPH
P-term clock hold
0.7
-
1.0
-
ns
TPCO
P-term clock to output
-
5.9
-
7.3
ns
TOE/TOD
Global OE to output enable/disable
-
5.9
-
7.5
ns
TPOE/TPOD
P-term OE to output enable/disable
-
7.0
-
8.5
ns
TMOE/TMOD
Macrocell driven OE to output enable/disable
-
7.7
-
9.9
ns
TPAO
P-term set/reset to output valid
-
6.6
-
8.1
ns
TAO
Global set/reset to output valid
-
5.0
-
7.6
ns
TSUEC
Register clock enable setup time
3.1
-
3.5
-
ns
THEC
Register clock enable hold time
0.0
-
0.0
-
ns
TCW
Global clock pulse width High or Low
1.1
-
1.6
-
ns
TAPRPW
Asynchronous preset/reset pulse width (High or Low)
6.0
-
7.5
-
ns
TPCW
P-term pulse width High or Low
6.0
-
7.5
-
ns
TDGSU
Set-up before DataGATE latch assertion
0.0
-
0.0
-
ns
TDGH
Hold to DataGATE latch assertion
4.0
-
6.0
-
ns
TDGR
DataGATE recovery to new data
-
8.2
-
9.0
ns
TDGW
DataGATE low pulse width
3.0
-
4.0
-
ns
TCDRSU
CDRST setup time before falling edge GCLK2
1.3
-
2.0
-
ns
TCDRH
Hold time CDRST after falling edge GCLK2
0.0
-
0.0
-
ns
TCONFIG(4)
Configuration time
-
350
-
350
us
Notes:
1. FTOGGLE is the maximum clock frequency to which a T flip-flop can reliably toggle (see the CoolRunner-II family data sheet).
2. FSYSTEM1 is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell while
FSYSTEM2 is through the OR array (one counter per function block).
3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array.
4. Typical configuration current during TCONFIG is 10 mA.
DS093 (v3.2) March 8, 2007
Product Specification
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XC2C128 CoolRunner-II CPLD
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Internal Timing Parameters
-6
Parameter(1)
Min.
Max.
Min.
Max.
Units
Input buffer delay
-
2.0
-
2.6
ns
Direct data register input delay
-
3.7
-
5.3
ns
TGCK
Global Clock buffer delay
-
1.5
-
2.1
ns
TGSR
Global set/reset buffer delay
-
1.6
-
3.5
ns
TGTS
Global 3-state buffer delay
-
2.1
-
3.0
ns
TOUT
Output buffer delay
-
2.3
-
2.6
ns
TEN
P-term Delays
TCT
Output buffer enable/disable delay
-
3.8
-
4.5
ns
Control term delay
-
1.2
-
1.4
ns
TLOGI1
Single P-term delay adder
-
0.5
-
1.1
ns
Symbol
Buffer Delays
TIN
TDIN
TLOGI2
Multiple P-term delay adder
Macrocell Delay
TPDI
Input to output valid
-
0.3
-
0.5
ns
-
0.9
-
0.7
ns
TLDI
Setup before clock (transparent latch)
-
2.1
-
2.5
ns
TSUI
Setup before clock
1.4
-
1.4
-
ns
THI
Hold after clock
0.0
-
0.0
-
ns
TECSU
Enable clock setup time
1.4
-
1.6
-
ns
TECHO
Enable clock hold time
0.0
-
0.0
-
ns
TCOI
Clock to output valid
-
0.4
-
0.7
ns
TAOI
Set/reset to output valid
-
1.1
-
1.5
ns
-
0.0
-
0.0
ns
-
1.8
-
3.4
ns
-
2.0
-
2.6
ns
-
3.0
-
4.0
ns
TCDBL
Clock doubler delay
Feedback Delays
TF
Feedback delay
TOEM
Macrocell to global OE delay
I/O Standard Time Adder Delays 1.5V CMOS
THYS15
Hysteresis input adder
TOUT15
8
-7
-
0.8
-
1.0
ns
TSLEW15
Output slew rate adder
I/O Standard Time Adder Delays 1.8V CMOS
THYS18
Hysteresis input adder
Output adder
-
4.0
-
4.0
ns
-
2.0
-
4.0
ns
TIN18
Input adder
-
0
-
0
ns
TOUT18
Output adder
-
0.0
-
0.0
ns
TSLEW18
Output slew rate adder
-
2.5
-
4.0
ns
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DS093 (v3.2) March 8, 2007
Product Specification
XC2C128 CoolRunner-II CPLD
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Internal Timing Parameters (Continued)
-6
Parameter(1)
Symbol
-7
Min.
Max.
Min.
Max.
Units
I/O Standard Time Adder Delays 2.5V CMOS
TIN25
Standard input adder
-
0.6
-
0.7
ns
THYS25
Hysteresis input adder
-
1.5
-
3.0
ns
TOUT25
Output adder
-
0.8
-
0.9
ns
TSLEW25
Output slew rate adder
I/O Standard Time Adder Delays 3.3V CMOS/TTL
TIN33
Standard input adder
-
3.0
-
4.0
ns
-
0.5
-
0.6
ns
THYS33
Hysteresis input adder
-
1.2
-
3.0
ns
TOUT33
Output adder
-
1.2
-
1.4
ns
-
3.0
-
4.0
ns
-
0.8
-
2.5
ns
Output adder to TOUT
-
0.5
-
0.5
ns
SSTL3-1
Input adder to TIN, TDIN, TGCK, TGSR,
TGTS
-
0.8
-
2.5
ns
Output adder to TOUT
-
0.5
-
0.5
ns
HSTL-1
Input adder to TIN, TDIN, TGCK, TGSR,
TGTS
-
2.0
-
2.5
ns
Output adder to TOUT
-
0.0
-
0.0
ns
TSLEW33
Output slew rate adder
I/O Standard Time Adder Delays HSTL, SSTL
SSTL2-1
Input adder to TIN, TDIN, TGCK, TGSR,
TGTS
Notes:
1. 1.5 ns input pin signal rise/fall.
Switching Characteristics
Switching Test Conditions
VCC
VCC = VCCIO = 1.8V, 25oC
5.0
R1
4.8
Device
Under Test
Test Point
TPD2 (ns)
4.6
R2
CL
4.4
Output Type
4.2
4.0
1
2
4
8
16
Number of Outputs Switching
DS093_02_050103
Figure 2: Derating Curve for TPD
LVTTL33
R1
268Ω
R2
235Ω
CL
35 pF
LVCMOS33
275Ω
275Ω
35 pF
LVCMOS25
188Ω
188Ω
35 pF
LVCMOS18
112.5Ω
112.5Ω
35 pF
LVCMOS15
150Ω
150Ω
35 pF
Notes:
1. CL includes test fixtures and probe capacitance.
2. 1.5 nsec maximum rise/fall times on inputs.
Figure 3: AC Load Circuits
DS093 (v3.2) March 8, 2007
Product Specification
www.xilinx.com
DS092_03_092302
9
XC2C128 CoolRunner-II CPLD
R
Typical I/V Output Curves
The I/V curve illustrates the nominal amount of current that an I/O can source/sink at different voltage levels.
3.3V
60
IO (Output Current mA)
50
2.5V
40
1.8V
Iol
30
20
1.5V
10
0
.5
0
1.0
1.5
2.0
2.5
VO (Output Volts)
3.0
3.5
XC128_IV_all_050703
Figure 4: Typical I/V Curves for XC2C128
Pin Descriptions (Continued)
Pin Descriptions
11
I/O
Bank
Function
Block
Macrocell
17
2
2
1
-
G2
19
1
F1
16
2
2
2
14
G3
21
1
12
F2
15
2
2
3
15
H1
22
1
4
11
F3
14
2
2
4
16
H2
23
1
1
5
10
E1
13
2
2
5
17
H3
24
1
1
6
9
E2
12
2
2
6
18
J1
25
1
1
7
-
-
-
-
2
7
-
-
-
-
1
8
-
-
-
-
2
8
-
-
-
-
1
9
-
-
-
-
2
9
-
-
-
-
1
10
-
-
-
-
2
10
-
-
-
-
1
11
8
E3
11
2
2
11
19
J2
26
1
1
12
7
D1
10
2
2
12
-
K1
28
1
1
13
6
D2
9
2
2(GCK0)
13
22
K3
30
1
1
14
-
C1
7
2
2(GCK1)
14
23
L2
32
1
1(GTS1)
15
4
C2
6
2
2(CDRST)
15
24
M2
35
1
1(GTS0)
16
3
C3
5
2
2(GCK2)
16
27
N2
38
1
Function
Block
Macrocell
1
1
13
G1
1
2
-
1
3
1
10
VQ100 CP132 TQ144
www.xilinx.com
VQ100 CP132 TQ144
I/O
Bank
DS093 (v3.2) March 8, 2007
Product Specification
XC2C128 CoolRunner-II CPLD
R
Pin Descriptions (Continued)
Function
Block
Macrocell
3
1
-
B1
3(GTS3)
2
2
3(GTS2)
3
3(GSR)
Pin Descriptions (Continued)
I/O
Bank
Function
Block
Macrocell
4
2
5
1
65
G13
94
2
B2
3
2
5
2
66
G12
95
2
1
A1
2
2
5
3
67
F14
96
2
4
99
A3
143
2
5
4
-
F13
97
2
3
5
97
B4
140
2
5
5
68
F12
98
2
3
6
96
A4
138
2
5
6
-
E13
100
2
3
7
95
C5
136
2
5
7
70
E12
101
2
3
8
-
-
-
-
5
8
-
-
-
-
3
9
-
-
-
-
5
9
-
-
-
-
3
10
-
-
-
-
5
10
-
-
-
-
3
11
94
B5
134
2
5
11
71
D14
102
2
3
12
A5
133
2
5
12
72
D13
103
2
3
13
93
C6
132
2
5
13
73
D12
104
2
3
14
92
B6
131
2
5
14
74
C14
105
2
3
15
91
A6
130
2
5
15
76
B13
110
2
3
16
90
C7
129
2
5
16
-
A13
111
2
4(DGE)
1
28
P2
39
1
6
1
64
H12
92
1
4
2
-
M3
40
1
6
2
63
H13
91
1
4
3
-
N3
41
1
6
3
61
J13
88
1
4
4
29
P3
43
1
6
4
60
J12
87
1
4
5
30
M4
45
1
6
5
59
K14
86
1
4
6
32
M5
49
1
6
6
58
K13
85
1
4
7
33
N5
50
1
6
7
-
-
-
-
4
8
-
-
-
-
6
8
-
-
-
-
4
9
-
-
-
-
6
9
-
-
-
-
4
10
-
-
-
-
6
10
-
-
-
-
4
11
34
P5
51
1
6
11
-
L14
83
1
4
12
35
M6
52
1
6
12
56
L13
82
1
4
13
36
N6
53
1
6
13
-
L12
81
1
4
14
37
P6
54
1
6
14
55
M14
80
1
4
15
39
N7
56
1
6
15
-
M13
79
1
4
16
40
M7
57
1
6
16
54
M12
78
1
VQ100 CP132 TQ144
DS093 (v3.2) March 8, 2007
Product Specification
www.xilinx.com
VQ100 CP132 TQ144
I/O
Bank
11
XC2C128 CoolRunner-II CPLD
R
Pin Descriptions (Continued)
Function
Block
Macrocell
7
1
77
C12
7
2
78
7
3
7
Pin Descriptions (Continued)
I/O
Bank
Function
Block
Macrocell
112
2
8
1
-
N14
77
1
B12
113
2
8
2
53
N13
76
1
-
A12
115
2
8
3
52
P14
74
1
4
79
C11
116
2
8
4
50
P12
71
1
7
5
80
B11
117
2
8
5
-
M11
70
1
7
6
81
A11
118
2
8
6
49
N11
69
1
7
7
-
C10
119
2
8
7
-
-
-
-
7
8
-
-
-
-
8
8
-
-
-
-
7
9
-
-
-
-
8
9
-
-
-
-
7
10
-
-
-
-
8
10
-
-
-
-
7
11
82
A10
120
2
8
11
-
P11
68
1
7
12
-
C9
121
2
8
12
46
P10
64
1
7
13
85
A8
124
2
8
13
44
P9
61
1
7
14
86
B8
125
2
8
14
43
M8
60
1
7
15
87
C8
126
2
8
15
42
N8
59
1
7
16
89
B7
128
2
8
16
41
P8
58
1
VQ100 CP132 TQ144
VQ100 CP132 TQ144
I/O
Bank
Notes:
1. GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
2. GCK, GSR, and GTS pins can also be used for general
purpose I/O.
12
www.xilinx.com
DS093 (v3.2) March 8, 2007
Product Specification
XC2C128 CoolRunner-II CPLD
R
XC2C128 JTAG, Power/Ground, No Connect Pins and Total User I/O
VQ100(1)
CP132(1)
TQ144(1)
TCK
48
M10
67
TDI
45
M9
63
TDO
83
B9
122
TMS
47
N10
65
VCCAUX (JTAG supply voltage)
5
D3
8
26, 57
P1, K12, A2
1, 37, 84
Power Bank 1 I/O (VCCIO1)
20, 38, 51
J3, P7, G14, P13
27, 55, 73, 93
Power Bank 2 I/O (VCCIO2)
88, 98
A14, C4, A7
109, 127, 141
21, 25, 31, 62, 69, 75,
84, 100
K2, N1, P4, N9, N12, J14,
H14, E14, B14, A9, B3
29, 36, 47, 62, 72, 89, 90,
99, 108, 123, 144
-
L1, L3, M1, N4, C13, B10
18, 20, 31, 33, 34, 42, 44,
46, 48, 66, 75, 106, 107,
114, 135, 137, 139, 142
80
100
100
Pin Type
Power internal (VCC)
Ground
No connects
Total user I/O (including dual function
pins)
Notes:
1. Pin compatible with all larger and smaller densities except where I/O banking is used.
Ordering Information
Pin/Ball
Spacing
θJA
(C/Watt)
θJC
(C/Watt)
XC2C128-6VQ100C
0.5mm
47.5
12.5
XC2C128-7VQ100C
0.5mm
47.5
XC2C128-6CP132C
0.5mm
XC2C128-7CP132C
Comm.
(C)
Package Body
Dimensions
I/O
Ind. (I)(1)
Very Thin Quad Flat
Pack
14mm x 14mm
80
C
12.5
Very Thin Quad Flat
Pack
14mm x 14mm
80
C
72.4
15.7
Chip Scale Package
8mm x 8mm
100
C
0.5mm
72.4
15.7
Chip Scale Package
8mm x 8mm
100
C
XC2C128-6TQ144C
0.5mm
46.1
7.9
Thin Quad Flat Pack
20mm x 20mm
100
C
XC2C128-7TQ144C
0.5mm
46.1
7.9
Thin Quad Flat Pack
20mm x 20mm
100
C
XC2C128-6VQG100C
0.5mm
47.5
12.5
Very Thin Quad Flat
Pack; Pb-free
14mm x 14mm
80
C
XC2C128-7VQG100C
0.5mm
47.5
12.5
Very Thin Quad Flat
Pack; Pb-free
14mm x 14mm
80
C
XC2C128-6CPG132C
0.5mm
72.4
15.7
Chip Scale
Package; Pb-free
8mm x 8mm
100
C
XC2C128-7CPG132C
0.5mm
72.4
15.7
Chip Scale
Package; Pb-free
8mm x 8mm
100
C
XC2C128-6TQG144C
0.5mm
46.1
7.9
Thin Quad Flat
Pack; Pb-free
20mm x 20mm
100
C
XC2C128-7TQG144C
0.5mm
46.1
7.9
Thin Quad Flat
Pack; Pb-free
20mm x 20mm
100
C
XC2C128-7VQ100I
0.5mm
47.5
12.5
Very Thin Quad Flat
Pack
14mm x 14mm
80
I
Part Number
DS093 (v3.2) March 8, 2007
Product Specification
Package Type
www.xilinx.com
13
XC2C128 CoolRunner-II CPLD
R
Pin/Ball
Spacing
θJA
(C/Watt)
θJC
(C/Watt)
XC2C128-7CP132I
0.5mm
72.4
15.7
XC2C128-7TQ144I
0.5mm
46.1
7.9
XC2C128-7VQG100I
0.5mm
47.5
12.5
XC2C128-7CPG132I
0.5mm
72.4
XC2C128-7TQG144I
0.5mm
46.1
Part Number
Comm.
(C)
Package Body
Dimensions
I/O
Ind. (I)(1)
Chip Scale Package
8mm x 8mm
100
I
Thin Quad Flat Pack
20mm x 20mm
100
I
Very Thin Quad Flat
Pack; Pb-free
14mm x 14mm
80
I
15.7
Chip Scale
Package; Pb-free
8mm x 8mm
100
I
7.9
Thin Quad Flat
Pack; Pb-free
20mm x 20mm
100
I
Package Type
Notes: C = Commercial (T A = 0° C to +70° C); I = Industrial (T A = –40° C to +85° C).
Standard Example: XC2C128
-6 TQ
144
Pb-Free Example: XC2C128
C
-6 TQ
G
144
C
Device
Speed Grade
Package Type
Pb-Free
Number of Pins
Temperature Range
Device
Speed Grade
Package Type
Number of Pins
Temperature Range
Device Part Marking
R
Device Type
Package
Speed
Operating Range
XC2Cxxx
TQ144
This line not
related to device
part number
7C
Part Marking for all non chip scale packages
Figure 5: Sample Package with Part Marking
Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package
marking. Part marking on chip scale packages by line are:
•
•
•
14
Line 1 = X (Xilinx logo) then truncated part number
Line 2 = Not related to device part number
Line 3 = Not related to device part number
•
Line 4 = Package code, speed, operating temperature,
three digits not related to device part number. Package
codes: C5 = CP132, C6 = CPG132.
www.xilinx.com
DS093 (v3.2) March 8, 2007
Product Specification
XC2C128 CoolRunner-II CPLD
VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO2
I/O
I/O
I/O
GND
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VQ100
Top View
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
VCCIO1
VCC
I/O(2)
I/O(5)
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
TMS
TCK
I/O
I/O
I/O(1)
I/O(1)
I/O(1)
I/O(1)
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO1
GND
I/O(2)
I/O(2)
I/O(4)
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GND
I/O(3)
R
(1)
(2)
(3)
(4)
(5)
-
Global Output Enable
Global Clock
Global Set/Reset
Clock Divide Reset
Data Gate
Figure 6: VQ100 Very Thin Quad Flat Pack
DS093 (v3.2) March 8, 2007
Product Specification
www.xilinx.com
15
XC2C128 CoolRunner-II CPLD
3
4
5
6
7
8
9
10
11
12
14
2
P
VCC
I/O(5)
I/O
GND
I/O
I/O
VCCIO1
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
N
GND
I/O(2)
I/O
NC
I/O
I/O
I/O
I/O
GND
TMS
I/O
GND
I/O
I/O
M
NC
I/O(4)
I/O
I/O
I/O
I/O
I/O
I/O
TDI
TCK
I/O
I/O
I/O
I/O
L
NC
I/O(2)
NC
I/O
I/O
I/O
K
I/O
GND
I/O(2)
VCC
I/O
I/O
J
I/O
I/O
VCCIO1
I/O
I/O
GND
H
I/O
I/O
I/O
I/O
I/O
GND
G
I/O
I/O
I/O
I/O
I/O
VCCIO1
F
I/O
I/O
I/O
I/O
I/O
I/O
E
I/O
I/O
I/O
I/O
I/O
GND
D
I/O
I/O
VAUX
I/O
I/O
I/O
C
I/O
I/O(1)
I/O(1)
VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
B
I/O
I/O(1)
GND
I/O
I/O
I/O
I/O
I/O
TDO
NC
I/O
I/O
I/O
GND
A
I/O(1)
VCC
I/O(3)
I/O
I/O
I/O
VCCIO2
I/O
GND
I/O
I/O
I/O
I/O
VCCIO2
CP132
Bottom View
13
1
R
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
Figure 7: CP132 Chip Scale Package
16
www.xilinx.com
DS093 (v3.2) March 8, 2007
Product Specification
XC2C128 CoolRunner-II CPLD
VCC
I/O(1)
I/O(1)
I/O
I/O(1)
I/O(1)
I/O
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TQ144
Top View
GND
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
VCCIO1
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
GND
TDI
I/O
TMS
NC
TCK
I/O
I/O
I/O
I/O
GND
VCC
I/O(2)
I/O(5)
I/O
I/O
NC
I/O
NC
I/O
NC
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VCCIO1
I/O
GND
I/O(2)
NC
I/O(2)
NC
NC
I/O(4)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
GND
I/O(3)
NC
VCCIO2
I/O
NC
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO2
I/O
I/O
I/O
GND
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
VCCIO2
R
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
Figure 8: TQ144 Thin Quad Flat Pack
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS093 (v3.2) March 8, 2007
Product Specification
www.xilinx.com
17
XC2C128 CoolRunner-II CPLD
R
Additional Information
Additional information is available for the following CoolRunner-II topics:
•
•
•
•
•
•
XAPP784: Bulletproof CPLD Design Practices
XAPP375: Timing Model
XAPP376: Logic Engine
XAPP378: Advanced Features
XAPP382: I/O Characteristics
XAPP389: Powering CoolRunner-II
•
XAPP399: Assigning VREF Pins
To access these and all application notes with their associated reference designs, click the following link and scroll
down the page until you find the document you want:
CoolRunner-II Data Sheets and Application Notes
Device Packages
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
10/01/02
1.0
Initial Xilinx release.
5/19/03
2.0
Added bin 6, 7 characterization data.
8/25/03
2.1
Edit Package diagram, other minor formatting edits.
01/26/04
2.2
Update links.
03/01/04
2.3
Fixed cropping on Figure 6.
7/30/04
2.4
Added Pb-free documentation.
10/01/04
2.5
Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
01/30/05
2.6
Change to ICCSB MAX for Commercial and Industrial.
03/07/05
2.7
Delete -4 speed grade. Modifications to Table 1, IOSTANDARDs.
04/21/05
2.8
Recharacterization of AC Specifications
06/28/05
2.9
Move to Product Specification.
03/20/06
3.0
Add Warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can also
be used for general purpose I/O. Replaced Figure 3 with a higher resolution graphic.
18
02/15/07
3.1
Corrections to timing parameters tF, tCT, tDIN, tGTS, tOEM and fTOGGLE for -6 speed grade.
Corrections to tDIN, tGCK, tEN, tSUI, tECSU, tF, tOEM, FEXT1, and FEXT2 for the -7 speed grade.
Values now match the software. There were no changes to silicon or characterization.
Change to VIH specification for 2.5V and 1.8V LVCMOS.
03/08/07
3.2
Fixed typo in note for VIL for LVCMOS18; removed note for VIL for LVCMOS33.
www.xilinx.com
DS093 (v3.2) March 8, 2007
Product Specification
