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DS311 (v2.3) November 19, 2008
XC2C64A CoolRunner-II CPLD
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Product Specification
Features
Description
•
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reliability is improved.
•
•
•
Optimized for 1.8V systems
- As fast as 4.6 ns pin-to-pin logic delays
- As low as 15 μA quiescent current
Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
Available in multiple package options
- 44-pin VQFP with 33 user I/Os
- 48-land QFN with 37 user I/Os
- 56-ball CP BGA with 45 user I/Os
- 100-pin VQFP with 64 user I/Os
- Pb-free available for all packages
Advanced system features
- Fastest in system programming
·
1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
·
Optional DualEDGE triggered registers
- Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
Multiple global output enables
·
Global set/reset
- Efficient control term clocks, output enables, and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Optional bus-hold, 3-state, or weak pullup on
selected I/O pins
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
·
Superior pinout retention
·
100% product term routability across function
block
- Hot pluggable
Refer to the CoolRunner™-II family data sheet for architecture description.
This device consists of four Function Blocks inter-connected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain, and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers can be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset, and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 64A
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
1
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XC2C64A CoolRunner-II CPLD
RealDigital Design Technology
Xilinx® CoolRunner-II CPLDs are fabricated on a
0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II
CPLDs employ RealDigital, a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead
of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation.
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible
with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C64A
IOSTANDARD Output
Attribute
VCCIO
Input
VCCIO
Input
VREF
Board
Termination
Voltage VT
LVTTL
3.3
3.3
N/A
N/A
LVCMOS33
3.3
3.3
N/A
N/A
Supported I/O Standards
LVCMOS25
2.5
2.5
N/A
N/A
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
LVCMOS18
1.8
1.8
N/A
N/A
LVCMOS15(1)
1.5
1.5
N/A
N/A
1.
LVCMOS15 requires Schmitt-trigger inputs.
20
ICC (mA)
15
10
5
0
50
0
100
150
200
250
Frequency (MHz)
DS092_01_092302
Figure 1: ICC vs Frequency
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
Typical ICC (mA)
0
25
50
75
100
150
175
200
225
240
0.017
1.8
3.7
5.5
7.48
11.0
12.7
14.6
15.3
17.77
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
2
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DS311 (v2.3) November 19, 2008
Product Specification
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XC2C64A CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol
Description
Value
Units
VCC
Supply voltage relative to ground
–0.5 to 2.0
V
VCCIO
Supply voltage for output drivers
–0.5 to 4.0
V
VJTAG(2)
JTAG input voltage limits
–0.5 to 4.0
V
VCCAUX
JTAG input supply voltage
–0.5 to 4.0
V
VIN(1)
Input voltage relative to ground(1)
–0.5 to 4.0
V
VTS(1)
Voltage applied to 3-state output(1)
–0.5 to 4.0
V
Storage Temperature (ambient)
–65 to +150
°C
+150
°C
VSTG(3)
TJ
Junction Temperature
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins might undershoot to –2.0V or overshoot to +4.5V, provided this overshoot or undershoot lasts less than 10 ns and
with the forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free
packages, see XAPP427.
Recommended Operating Conditions
Symbol
VCC
VCCIO
VCCAUX
Parameter
Min
Max
Units
Commercial TA = 0°C to +70°C
1.7
1.9
V
Industrial TA = –40°C to +85°C
1.7
1.9
V
Supply voltage for output drivers @ 3.3V operation
3.0
3.6
V
Supply voltage for output drivers @ 2.5V operation
2.3
2.7
V
Supply voltage for output drivers @ 1.8V operation
1.7
1.9
V
Supply voltage for output drivers @ 1.5V operation
1.4
1.6
V
JTAG programming pins
1.7
3.6
V
Supply voltage for internal logic
and input buffers
DC Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Typical
Max.
Units
ICCSB
Standby current Commercial
VCC = 1.9V, VCCIO = 3.6V
31
100
μA
ICCSB
Standby current Industrial
VCC = 1.9V, VCCIO = 3.6V
43
165
μA
ICC(1)
Dynamic current
f = 1 MHz
-
500
μA
f = 50 MHz
-
5
mA
CJTAG
JTAG input capacitance
f = 1 MHz
-
10
pF
CCLK
Global clock input capacitance
f = 1 MHz
-
12
pF
CIO
I/O capacitance
f = 1 MHz
-
10
pF
IIL(2)
Input leakage current
VIN = 0V or VCCIO to 3.9V
-
+/–1
μA
IIH(2)
I/O High-Z leakage
VIN = 0V or VCCIO to 3.9V
-
+/–1
μA
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at VCC=VCCIO= 1.9V.
2. See Quality and Reliability section of the CoolRunner-II family data sheet.
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
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XC2C64A CoolRunner-II CPLD
LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min.
Max.
Units
3.0
3.6
V
VCCIO
Input source voltage
VIH
High level input voltage
2
3.9
V
VIL
Low level input voltage
–0.3
0.8
V
VOH
High level output voltage
IOH = –8 mA, VCCIO = 3V
VCCIO – 0.4V
-
V
IOH = –0.1 mA, VCCIO = 3V
VCCIO – 0.2V
-
V
IOL = 8 mA, VCCIO = 3V
-
0.4
V
IOL = 0.1 mA, VCCIO = 3V
-
0.2
V
Min.
Max.
Units
2.3
2.7
V
VOL
Low level output voltage
LVCMOS 2.5V DC Voltage Specifications
Symbol
VCCIO
Parameter
Test Conditions
Input source voltage
0.3(1)
VIH
High level input voltage
1.7
VIL
Low level input voltage
–0.3
0.7
V
VOH
High level output voltage
IOH = –8 mA, VCCIO = 2.3V
VCCIO – 0.4V
-
V
IOH = –0.1 mA, VCCIO = 2.3V
VCCIO – 0.2V
-
V
IOL = 8 mA, VCCIO = 2.3V
-
0.4
V
IOL = 0.1 mA, VCCIO = 2.3V
-
0.2
V
VOL
1.
Low level output voltage
VCCIO +
V
The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V
without physical damage.
LVCMOS 1.8V DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min.
Max.
Units
VCCIO
Input source voltage
-
1.7
1.9
V
VIH
High level input voltage
-
0.65 x VCCIO
VCCIO + 0.3(1)
V
VIL
Low level input voltage
-
–0.3
0.35 x VCCIO
V
VOH
High level output voltage
IOH = –8 mA, VCCIO = 1.7V
VCCIO – 0.45
-
V
IOH = –0.1 mA, VCCIO = 1.7V
VCCIO – 0.2
-
V
IOL = 8 mA, VCCIO = 1.7V
-
0.45
V
IOL = 0.1 mA, VCCIO = 1.7V
-
0.2
V
VOL
1.
4
Low level output voltage
The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V
without physical damage.
www.xilinx.com
DS311 (v2.3) November 19, 2008
Product Specification
R
XC2C64A CoolRunner-II CPLD
LVCMOS 1.5V DC Voltage Specifications
Symbol
Parameter(1)
Test Conditions
Min.
Max.
Units
VCCIO
Input source voltage
-
1.4
1.6
V
VT+
Input hysteresis threshold voltage
-
0.5 x VCCIO
0.8 x VCCIO
V
-
0.2 x VCCIO
0.5 x VCCIO
V
IOH = –8 mA, VCCIO = 1.4V
VCCIO – 0.45
-
V
IOH = –0.1 mA, VCCIO = 1.4V
VCCIO – 0.2
-
V
IOL = 8 mA, VCCIO = 1.4V
-
0.4
V
IOL = 0.1 mA, VCCIO = 1.4V
-
0.2
V
VTVOH
VOL
High level output voltage
Low level output voltage
Notes:
1. Hysteresis used on 1.5V inputs.
Schmitt Trigger Input DC Voltage Specifications
Test Conditions
Min.
Max.
Units
VCCIO
Symbol
Input source voltage
Parameter
-
1.4
3.9
V
VT+
Input hysteresis threshold voltage
-
0.5 x VCCIO
0.8 x VCCIO
V
-
0.2 x VCCIO
0.5 x VCCIO
V
VT-
DS311 (v2.3) November 19, 2008
Product Specification
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5
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XC2C64A CoolRunner-II CPLD
AC Electrical Characteristics Over Recommended Operating Conditions
-5
Symbol
Parameter
-7
Min.
Max.
Min.
Max.
Units
TPD1
Propagation delay single p-term
-
4.6
-
6.7
ns
TPD2
Propagation delay OR array
-
5.0
-
7.5
ns
TSUD
Direct input register clock setup time
2.4
-
3.3
-
ns
TSU1
Setup time (single p-term)
2.0
-
2.5
-
ns
TSU2
Setup time (OR array)
2.4
-
3.3
-
ns
THD
Direct input register hold time
0
-
0
-
ns
TH
P-term hold time
0
-
0
-
ns
TCO
Clock to output
-
3.9
-
6.0
ns
FTOGGLE(1)
Internal toggle rate(1)
-
500
-
300
MHz
FSYSTEM1(2)
Maximum system frequency(2)
-
263
-
159
MHz
FSYSTEM2(2)
Maximum system frequency(2)
-
238
-
141
MHz
FEXT1(3)
Maximum external frequency(3)
-
169
-
118
MHz
FEXT2(3)
Maximum external frequency(3)
-
159
-
108
MHz
TPSUD
Direct input register p-term clock setup time
0.9
-
1.7
-
ns
TPSU1
P-term clock setup time (single p-term)
0.6
-
0.9
-
ns
TPSU2
P-term clock setup time (OR array)
1.0
-
1.7
-
ns
TPHD
Direct input register p-term clock hold time
1.3
-
1.4
-
ns
TPH
P-term clock hold
1.5
-
1.7
-
ns
TPCO
P-term clock to output
-
6.0
-
8.4
ns
TOE/TOD
Global OE to output enable/disable
-
8.0
-
10.0
ns
TPOE/TPOD
P-term OE to output enable/disable
-
9.0
-
11.0
ns
TMOE/TMOD
Macrocell driven OE to output enable/disable
-
9.0
-
11.0
ns
TPAO
P-term set/reset to output valid
-
7.3
-
9.7
ns
TAO
Global set/reset to output valid
-
6.0
-
8.3
ns
TSUEC
Register clock enable setup time
3.0
-
3.7
-
ns
THEC
Register clock enable hold time
0
-
0
-
ns
TCW
Global clock pulse width High or Low
1.4
-
2.2
-
ns
TPCW
P-term pulse width High or Low
5.0
-
7.5
-
ns
TAPRPW
Asynchronous preset/reset pulse width (High or Low)
5.0
-
7.5
-
ns
TCONFIG(4)
Configuration time
-
50.0
-
50.0
μs
Notes:
1. FTOGGLE is the maximum frequency of a dual edge triggered T flip-flop with output enabled.
2. FSYSTEM (1/TCYCLE) is the internal operating frequency for a device fully populated with 16-bit up/down, Resetable binary counter
(one counter per function block).
3. FEXT (1/TSU1+TCO) is the maximum external frequency.
4. Typical configuration current during TCONFIG is 2.3 mA.
6
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DS311 (v2.3) November 19, 2008
Product Specification
R
XC2C64A CoolRunner-II CPLD
Internal Timing Parameters
-5
Parameter(1)
Symbol
-7
Min.
Max.
Min.
Max.
Units
Buffer Delays
TIN
Input buffer delay
-
1.7
-
2.4
ns
TDIN
Direct data register input delay
-
2.6
-
4.0
ns
TGCK
Global clock buffer delay
-
1.6
-
2.5
ns
TGSR
Global set/reset buffer delay
-
2.4
-
3.5
ns
TGTS
Global 3-state buffer delay
-
2.7
-
3.9
ns
TOUT
Output buffer delay
-
1.9
-
2.8
ns
TEN
Output buffer enable/disable delay
-
5.3
-
6.1
ns
TCT
Control term delay
-
2.0
-
2.5
ns
TLOGI1
Single P-term delay adder
-
0.5
-
0.8
ns
TLOGI2
Multiple P-term delay adder
-
0.4
-
0.8
ns
TPDI
Input to output valid
-
0.5
-
0.7
ns
TSUI
Setup before clock
1.4
-
1.8
-
ns
THI
Hold after clock
0.0
-
0.0
-
ns
TECSU
Enable clock setup time
0.9
-
1.3
-
ns
TECHO
Enable clock hold time
0
-
0
-
ns
TCOI
Clock to output valid
-
0.4
-
0.7
ns
TAOI
Set/reset to output valid
-
1.7
-
2.0
ns
TCDBL
Clock doubler delay
-
0
-
0
ns
TF
Feedback delay
-
1.5
-
3.0
ns
TOEM
Macrocell to global OE delay
-
1.7
-
1.7
ns
P-term Delays
Macrocell Delay
Feedback Delays
I/O Standard Time Adder Delays 1.5V CMOS
THYS15
Hysteresis input adder
-
4.0
-
6.0
ns
TOUT15
Output adder
-
0.9
-
1.5
ns
TSLEW15
Output slew rate adder
-
4.0
-
6.0
ns
I/O Standard Time Adder Delays 1.8V CMOS
THYS18
Hysteresis input adder
-
3.0
-
4.0
ns
TOUT18
Output adder
-
0
-
0
ns
TSLEW
Output slew rate adder
-
3.5
-
5.0
ns
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
7
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XC2C64A CoolRunner-II CPLD
Internal Timing Parameters (Continued)
-5
Parameter(1)
Symbol
-7
Min.
Max.
Min.
Max.
Units
I/O Standard Time Adder Delays 2.5V CMOS
TIN25
Standard input adder
-
0.5
-
0.6
ns
THYS25
Hysteresis input adder
-
2.5
-
3.0
ns
TOUT25
Output adder
-
0.8
-
0.9
ns
TSLEW25
Output slew rate adder
-
4.0
-
5.0
ns
I/O Standard Time Adder Delays 3.3V CMOS/TTL
TIN33
Standard input adder
-
0.5
-
0.6
ns
THYS33
Hysteresis input adder
-
2.0
-
3.0
ns
TOUT33
Output adder
-
1.2
-
1.4
ns
TSLEW33
Output slew rate adder
-
4.0
-
5.0
ns
1.
8
1.5 ns input pin signal rise/fall.
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DS311 (v2.3) November 19, 2008
Product Specification
R
XC2C64A CoolRunner-II CPLD
Switching Characteristics
Typical I/O Output Curves
VCC = VCCIO = 1.8V, T = 25oC
Vdde1
I/O Output Current (mA)
5.5
5.0
TPD2 (ns)
4.5
4.0
1.5V
1.8V
2.5V
3.3V
3.5
Vo Output Volts
3.0
1
2
4
8
16
Figure 4: Typical I/O Output Curves
Number of Outputs Switching
DS092_02_092302
Figure 2: Derating Curve for TPD
AC Test Circuit
VCC
R1
Device
Under Test
Test Point
R2
Output Type
LVTTL33
CL
R1
268Ω
R2
235Ω
CL
35 pF
LVCMOS33
275Ω
275Ω
35 pF
LVCMOS25
188Ω
188Ω
35 pF
LVCMOS18
112.5Ω
112.5Ω
35 pF
LVCMOS15
150Ω
150Ω
35 pF
Notes:
1. CL includes test fixtures and probe capacitance.
2. 1.5 ns maximum rise/fall times on inputs.
DS311_03_102108
Figure 3: AC Load Circuit
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
9
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XC2C64A CoolRunner-II CPLD
Pin Descriptions
10
Function Block
Macrocell
PC44(1)
VQ44
1
1
44
38
1
2
43
37
1
3
42
36
1
4
-
1
5
1
QFG48
CP56
VQ100
I/O Banking
F1
13
Bank 2
5
E3
12
Bank 2
4
E1
11
Bank 2
-
-
10
Bank 2
-
-
-
9
Bank 2
6
-
-
-
8
Bank 2
1
7
-
-
-
7
Bank 2
1
8
-
-
-
6
Bank 2
1(GTS1)
9
40
34
2
D1
4
Bank 2
1(GTS0)
10
39
33
1
C1
3
Bank 2
1(GTS3)
11
38
32
48
A3
2
Bank 2
1(GTS2)
12
37
31
47
A2
1
Bank 2
1(GSR)
13
36
30
46
B1
99
Bank 2
1
14
-
-
A1
97
Bank 2
1
15
-
-
C3
94
Bank 2
1
16
-
-
-
92
Bank 2
2
1
1
39
6
G1
14
Bank 1
2
2
2
40
7
F3
15
Bank 1
2
3
-
-
8
-
16
Bank 1
2
4
-
-
9
-
17
Bank 1
2
5
3
41
10
H1
18
Bank 1
2
6
4
42
G3
19
Bank 1
2(GCK0)
7
5
43
11
J1
22
Bank 1
2(GCK1)
8
6
44
12
K1
23
Bank 1
2
9
-
-
K4
24
Bank 1
2(GCK2)
10
7
1
K2
27
Bank 1
2
11
-
-
-
28
Bank 1
2
12
8
2
14
K3
29
Bank 1
2
13
9
3
15
H3
30
Bank 1
2
14
-
-
K5
32
Bank 1
2
15
-
-
-
33
Bank 1
2
16
-
-
-
34
Bank 1
www.xilinx.com
13
DS311 (v2.3) November 19, 2008
Product Specification
R
XC2C64A CoolRunner-II CPLD
Pin Descriptions (Continued)
1.
2.
3.
Function Block
Macrocell
PC44(1)
VQ44
QFG48
CP56
VQ100
I/O Banking
3
1
35
29
45
C4
91
Bank 2
3
2
34
28
44
A4
90
Bank 2
3
3
33
27
43
C5
89
Bank 2
3
4
-
-
A7
81
Bank 2
3
5
-
-
39
C8
79
Bank 2
3
6
29
23
38
A8
78
Bank 2
3
7
-
-
A9
77
Bank 2
3
8
-
-
-
76
Bank 2
3
9
-
-
37
A5
74
Bank 2
3
10
28
22
36
A10
72
Bank 2
3
11
27
21
35
B10
71
Bank 2
3
12
26
20
34
C10
70
Bank 2
3
13
-
-
D8
68
Bank 2
3
14
25
19
33
E8
67
Bank 2
3
15
24
18
32
D10
64
Bank 2
3
16
-
-
-
61
Bank 2
4
1
11
5
17
K6
35
Bank 1
4
2
12
6
18
H5
36
Bank 1
4
3
-
-
K7
37
Bank 1
4
4
-
-
-
39
Bank 1
4
5
-
-
H7
40
Bank 1
4
6
-
-
-
41
Bank 1
4
7
14
8
H8
42
Bank 1
4
8
-
-
-
43
Bank 1
4
9
-
-
-
49
Bank 1
4
10
-
-
24
K8
50
Bank 1
4
11
18
12
25
H10
52
Bank 1
4
12
-
-
26
-
53
Bank 1
4
13
19
13
27
G10
55
Bank 1
4
14
20
14
28
-
56
Bank 1
4
15
22
16
F10
58
Bank 1
4
16
-
-
E10
60
Bank 1
20
30
This is an obsolete package type. It remains here for legacy support only.
GTS = global output enable, GSR = global set reset, GCK = global clock.
GCK, GSR, and GTS pins can also be used for general purpose I/Os.
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
11
R
XC2C64A CoolRunner-II CPLD
XC2C64A Global, JTAG, Power/Ground, and No Connect Pins
PC44(1)
VQ44
QFG48
CP56
VQ100
TCK
17
11
23
K10
48
TDI
15
9
21
J10
45
TDO
30
24
40
A6
83
TMS
16
10
22
K9
47
VCCAUX (JTAG supply voltage)
41
35
3
D3
5
Power internal (VCC)
21
15
29
G8
26,57
Power bank 1 I/O (VCCIO1)
13
7
19
H6
38, 51
Power bank 2 I/O (VCCIO2)
32
26
42
C6
88, 98
10, 23, 31
4,17,25
16, 31, 41
H4, F8, C7
21, 31, 62, 69, 84,100
Pin Type
Ground
No connects
20, 25, 44, 46, 54, 59, 63, 65, 66,
73, 75, 80, 82, 85, 86, 87, 93, 95,
96
Total user I/O
1.
33
33
37
45
64
This is an obsolete package type. It remains here for legacy support only.
Ordering Information
Device Ordering No. Pin/Ball
θJA
θJC
and Part Marking No. Spacing (°C/Watt) ({C/Watt)
Package Type
Package Body
Dimensions
Comm(C)
I/O Ind. (I)(1)
XC2C64A-5QFG48C
0.5mm
31.2
21.2
Quad Flat No Lead
7mm x 7mm
37
C
XC2C64A-7QFG48C
0.5mm
31.2
21.2
Quad Flat No Lead
7mm x 7mm
37
C
XC2C64A-5VQ44C
0.8mm
46.6
8.2
Very Thin Quad Flat Pack
10mm x 10mm
33
C
XC2C64A-7VQ44C
0.8mm
46.6
8.2
Very Thin Quad Flat Pack
10mm x 10mm
33
C
XC2C64A-5CP56C
0.5mm
65.0
15.0
Chip Scale Package
6mm x 6mm
45
C
XC2C64A-7CP56C
0.5mm
65.0
15.0
Chip Scale Package
6mm x 6mm
45
C
XC2C64A-5VQ100C
0.5mm
53.2
14.6
Very Thin Quad Flat Pack
14mm x 14mm
64
C
XC2C64A-7VQ100C
0.5mm
53.2
14.6
Very Thin Quad Flat Pack
14mm x 14mm
64
C
XC2C64A-5VQG44C
0.8mm
46.6
8.2
Very Thin Quad Flat
Pack; Pb-free
10mm x 10mm
33
C
XC2C64A-7VQG44C
0.8mm
46.6
8.2
Very Thin Quad Flat
Pack; Pb-free
10mm x 10mm
33
C
XC2C64A-5CPG56C
0.5mm
65.0
15.0
Chip Scale Package;
Pb-free
6mm x 6mm
45
C
XC2C64A-7CPG56C
0.5mm
65.0
15.0
Chip Scale Package;
Pb-free
6mm x 6mm
45
C
XC2C64A-5VQG100C
0.5mm
53.2
14.6
Very Thin Quad Flat
Pack; Pb-free
14mm x 14mm
64
C
XC2C64A-7VQG100C
0.5mm
53.2
14.6
Very Thin Quad Flat
Pack; Pb-free
14mm x 14mm
64
C
XC2C64A-7VQ44I
0.8mm
46.6
8.2
Very Thin Quad Flat Pack
10mm x 10mm
33
I
XC2C64A-7QFG48I
0.5mm
31.2
21.2
Quad Flat No Lead;
Pb-free
7mm x 7mm
37
I
XC2C64A-7CP56I
0.5mm
65.0
15.0
Chip Scale Package
6mm x 6mm
45
I
XC2C64A-7VQ100I
0.5mm
53.2
14.6
Very Thin Quad Flat Pack
14mm x 14mm
64
I
12
www.xilinx.com
DS311 (v2.3) November 19, 2008
Product Specification
R
XC2C64A CoolRunner-II CPLD
Device Ordering No. Pin/Ball
θJA
θJC
and Part Marking No. Spacing (°C/Watt) ({C/Watt)
Package Type
Package Body
Dimensions
Comm(C)
I/O Ind. (I)(1)
XC2C64A-7VQG44I
0.8mm
46.6
8.2
Very Thin Quad Flat
Pack; Pb-free
10mm x 10mm
33
I
XC2C64A-7CPG56I
0.5mm
65.0
15.0
Chip Scale Package;
Pb-free
6mm x 6mm
45
I
XC2C64A-7VQG100I
0.5mm
53.2
14.6
Very Thin Quad Flat
Pack; Pb-free
14mm x 14mm
64
I
-4 TQ
C
Notes:
1. C = Commercial (TA = 0°C to +70°C); I = Industrial (TA = –40°C to +85°C).
Standard Example: XC2C128
-4 TQ
144
C
Pb-Free Example: XC2C128
G
144
Device
Speed Grade
Package Type
Pb-Free
Number of Pins
Temperature Range
Device
Speed Grade
Package Type
Number of Pins
Temperature Range
Device Part Marking
R
XC2Cxxx
TQ144
Device Type
Package
7C
Speed
Operating Range
This line not
related to device
part number
Part marking for non-chip scale package
DS311_05_102108
Figure 5: Sample Package with Part Marking
Note: Due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be
included on the package marking. Part marking on chip scale and quad flat no lead packages by line are:
1. X (Xilinx logo) then truncated part number
2. Not related to device part number
3. Not related to device part number
DS311 (v2.3) November 19, 2008
Product Specification
4. Device code, speed, operating temperature, three digits
not related to device part number. Device codes: C3 =
CP56, C4 = CPG56, Q2 = QFG48.
www.xilinx.com
13
R
XC2C64A CoolRunner-II CPLD
I/O(1)
I/O(1)
I/O(1)
I/O(3)
I/O
I/O
I/O
VCCIO2
GND
TDO
I/O
48
47
46
45
44
43
42
41
40
39
38
37
QFG48
Top View
I/O(2)
I/O
I/O
Gnd
I/O
I/O
Vccio1
I/O
TDI
TMS
TCK
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
I/O(2)
I/O(2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VAUX
I/O(1)
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
I/O(1)
I/O(1)
I/O(1)
I/O(3)
I/O
I/O
I/O
VCCIO2
Gnd
TDO
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
TDI
TMS
TCK
PC44
Top View
39
38
37
36
35
34
33
32
31
30
29
K
I/O(2)
I/O(2)
I/O
I/O
I/O
I/O
I/O
I/O
J
I/O(2)
H
I/O
I/O
G
I/O
I/O
F
I/O
I/O
E
I/O
D
TCK
TDI
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O(1)
VAUX
I/O
I/O
C
I/O(1)
I/O
I/O
I/O
B
I/O(3)
A
I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 7: PC44 Package (Obsolete package shown for
legacy support only)
14
TMS
10
Figure 8: QFG48 Package
Figure 6: VQ44 Package
7
8
9
10
11
12
13
14
15
16
17
I/O
I/O
I/O
I/O
I/O
Gnd
I/O
Vcc
I/O
I/O
I/O
I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
I/O(2)
I/O
I/O
GND
I/O
I/O
36
35
34
33
32
31
30
29
28
27
26
25
9
VQ44
Top View
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
12
13
14
15
16
17
18
19
20
21
22
VCCIO1
I/O
TDI
TMS
TCK
1
2
3
4
5
6
7
8
9
10
11
I/O(1)
I/O(1)
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O(2)
13
14
15
16
17
18
19
20
21
22
23
24
I/O(2)
I/O
I/O
GND
I/O
I/O
44
43
42
41
40
39
38
37
36
35
34
I/O(2)
I/O(2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VAUX
I/O(1)
I/O(1)
I/O(1)
I/O(3)
I/O
I/O
I/O
Vccio2
Gnd
TDO
I/O
I/O
I/O
Package Pinout Diagrams
www.xilinx.com
GND
I/O
VCCIO1
I/O
CP56
Bottom View
I/O
I/O
VCCIO2
GND
I/O
I/O(1)
I/O(1)
I/O
I/O
TDO
I/O
I/O
I/O
I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 9: CP56 Package
DS311 (v2.3) November 19, 2008
Product Specification
R
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GND
I/O(3)
VCCIO2
I/O
NC
NC
I/O
NC
I/O
I/O
I/O
I/O
VCCIO2
NC
NC
NC
GND
TDO
NC
I/O
NC
I/O
I/O
I/O
I/O
XC2C64A CoolRunner-II CPLD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VQ100
Top View
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O
NC
I/O
I/O
I/O
GND
I/O
I/O
NC
NC
I/O
NC
GND
I/O
I/O
NC
I/O
Vcc
I/O
I/O
NC
I/O
I/O
VCCIO1
VCCIO1
I/O
I/O
I/O
I/O
I/O
NC
TDI
NC
TMS
TCK
I/O
I/O
VCC
I/O(2)
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O(1)
I/O(1)
I/O(1)
I/O(1)
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
GND
I/O(2)
I/O(2)
I/O
NC
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
Figure 12: VQ100 Package
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
15
R
XC2C64A CoolRunner-II CPLD
Additional Information
Additional information is available for the following
CoolRunner-II CPLD topics at
www.xilinx.com/support/documentation/coolrunner-ii.htm:
•
•
•
•
Package drawings and dimensions are available at:
Device pinouts in the density specific data sheets
Termination, power sequencing, voltage thresholds,
and slew rate data in the CPLD IO User Guide
Reliability data in the Device Reliability Report
Packaging thermal and electrical data in the Device
Package User Guide
www.xilinx.com/support/documentation/package_specifications.htm
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
5/15/04
1.0
Initial Xilinx release.
8/30/04
1.1
Pb-free documentation
10/01/04
1.2
Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
11/08/04
1.3
Product Release. No change to documentation.
11/29/04
1.4
Change to QFG package drawing (Figure 8). Pin 29 relabelled.
12/14/04
1.5
Changes to Figure 4, Typical I/O Output Curves; Changes to tOUT25 and tOUT33, Internal
Timing Parameters, page 8.
01/18/05
1.6
Changes to ICCSB, fTOGGLE, tPSU1, tPSU2, tPHD, tCW, tSLEW25, and tSLEW33
03/07/05
1.7
Format change to specifications IIL and IIH, page 3. Improvement to pin-to-pin logic delay,
page 1. Modifications to Table 1, IOSTANDARDs.
06/28/05
1.8
Move to Product Specification. Change to TIN25, TOUT25, TIN33, and TOUT33.
01/30/06
1.9
Modified footnote 1 from AC Specifications Table to remove incorrect equation.
03/20/06
2.0
Add Warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can also
be used for general purpose I/O.
16
02/15/07
2.1
Change to VIH specification for 2.5V and 1.8V LVCMOS. Change TF specification on -7
speed grade from 2.0 to 3.0 ns.
03/08/07
2.2
Fixed typo in note for VIL for LVCMOS18; removed note for VIL for LVCMOS33.
11/19/08
2.3
Added note to Pin Description tables to indicate the PC44 packages are obsolete. Removed
part numbers for devices in PC44 packages the Features section and from the ordering
information. See Product Discontinuation Notice xcn07022.pdf.
www.xilinx.com
DS311 (v2.3) November 19, 2008
Product Specification
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