XC3030-100PC44C

IMPORTANT NOTICE  All new designs should use XC3000A. Information on XC3000 is presented here as a reference for existing designs. XC3000 bitstreams are upward compatible to XC3000A without modification. XC3000 Logic Cell Array Family Product Specification Features Description • Industry-leading FPGA family with five device types XC3000 is the original family of devices in the XC3000 class of Field Programmable Gate Array (FPGA) architectures. The XC3000 family has a proven track record in addressing a wide range of design applications, including general logic replacement and sub-systems integration. For a thorough description of the XC3000 architecture see the preceding pages of this data book. – Logic densities from 1,000 to 6,000 gates – Up to 144 user-definable I/Os • Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns logic delays • Advanced CMOS static memory technology – Low quiescent and active power consumption • XC3000-specific features – Ultra-low current option in Power-Down mode – 4-mA output sink and source current – Broad range of package options includes plastic and ceramic quad flat packs, plastic leaded chip carriers and pin grid arrays The XC3000 Family covers a range of nominal device densities from 2,000 to 9,000 gates, practically achievable densities from 1,000 to 6,000 gates. Device speeds, described in terms of maximum guaranteed toggle frequencies, range from 70 to 125 MHz. The performance of a completed design depends upon placement and routing implementation, so, like with any gate array, the final verification of device utilization and performance can only be known after the design has been placed and routed. – 100% bitstream compatible with the XC3100 family – Commercial, industrial, military, “high rel”, and MILSTD-883 Class B grade devices – Easy migration to XC3300 series of HardWire maskprogrammed devices for high-volume production Device CLBs XC3020 XC3030 XC3042 XC3064 XC3090 64 100 144 224 320 Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 User I/Os Max 64 80 96 120 144 2-153 Flip-Flops Horizontal Longlines Configuration Data Bits 256 360 480 688 928 16 20 24 32 40 14,779 22,176 30,784 46,064 64,160 XC3000 Logic Cell Array Family Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. Absolute Maximum Ratings Symbol Description Units VCC Supply voltage relative to GND –0.5 to +7.0 V VIN Input voltage with respect to GND –0.5 to VCC +0.5 V VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V TSTG Storage temperature (ambient) –65 to +150 °C TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C Junction temperature plastic +125 °C Junction temperature ceramic +150 °C TJ Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Description Min Max Units Supply voltage relative to GND Commercial 0°C to +85°C junction 4.75 5.25 V Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5 V VIHT High-level input voltage — TTL configuration 2.0 VCC V VILT Low-level input voltage — TTL configuration 0 0.8 V VIHC High-level input voltage — CMOS configuration 70% 100% VCC VILC Low-level input voltage — CMOS configuration 0 20% VCC TIN Input signal transition time 250 ns At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C. 2-154 DC Characteristics Over Operating Conditions Symbol VOH Description Min High-level output voltage (@ IOH = –4.0 mA, VCC min) Max 3.86 Units V Commercial VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) 0.40 3.76 V V Industrial VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) VCCPD Power-down supply voltage (PWRDWN must be Low) ICCPD Power-down supply current (VCC(MAX) @ TMAX)1 ICCO 0.40 2.30 V V XC3020 50 µA XC3030 80 µA XC3042 120 µA XC3064 170 µA XC3090 250 µA 500 µA 10 mA +10 µA Quiescent LCA supply current in addition to ICCPD2 Chip thresholds programmed as CMOS levels Chip thresholds programmed as TTL levels IIL Input Leakage Current –10 CIN Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 10 15 pF pF Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 15 20 pF pF 0.17 mA 3.4 mA IRIN Pad pull-up (when selected) @ VIN = 0 V (sample tested) IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.02 Note: 1. Devices with much lower ICCPD tested and guaranteed at VCC = 3.2 V, T = 25°C can be ordered with a Special Product Code. XC3020 SPC0107: ICCPD = 1 µA XC3030 SPC0107: ICCPD = 2 µA XC3042 SPC0107: ICCPD = 3 µA XC3064 SPC0107: ICCPD= 4 µA XC3090 SPC0107: ICCPD= 5 µA 2. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the LCA configured with a MakeBits tie option. 2-155 XC3000 Logic Cell Array Family CLB Switching Characteristic Guidelines CLB Output (X, Y) (Combinatorial) 1 TILO CLB Input (A,B,C,D,E) 2 TICK 3 TCKI CLB Clock 12 TCL 11 TCH 4 TDICK 5 TCKDI CLB Input (Direct In) 6 TECCK 7 TCKEC CLB Input (Enable Clock) 8 TCKO CLB Output (Flip-Flop) CLB Input (Reset Direct) 13 TRPW 9 TRIO CLB Output (Flip-Flop) X5388 Buffer (Internal) Switching Characteristic Guidelines Description Speed Grade -70 -100 -125 Symbol Max Max Max Units Global and Alternate Clock Distribution* Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TPID 8.0 7.5 7.0 ns TPIDC 6.5 6.0 5.7 ns TBUF driving a Horizontal Longline (L.L.)* I to L.L. while T is Low (buffer active) T↓ to L.L. active and valid with single pull-up resistor T↓ to L.L. active and valid with pair of pull-up resistors T↑ to L.L. High with single pull-up resistor T↑ to L.L. High with pair of pull-up resistors TIO TON TON TPUS TPUF 5.0 11.0 12.0 24.0 17.0 4.7 10.0 11.0 22.0 15.0 4.5 9.0 10.0 17.0 12.0 ns ns ns ns ns BIDI Bidirectional buffer delay TBIDI 2.0 1.8 1.7 ns * Timing is based on the XC3042, for other devices see XACT timing calculator. 2-156 CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade -70 Symbol Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y 1 TILO 9.0 7.0 5.5 ns 8 TCKO 6.0 5.0 4.5 ns TQLO 13.0 10.0 8.0 ns Set-up time before clock K Logic Variables A, B, C, D, E Data In DI Enable Clock EC Reset Direct inactive RD Hold Time after clock K Logic Variables Data In Enable Clock A, B, C, D, E DI EC Max Min Max Units 2 TICK 4 TDICK 6 TECCK 8.0 5.0 7.0 1.0 7.0 4.0 5.0 1.0 5.5 3.0 4.5 1.0 ns ns ns ns 3 TCKI 5 TCKDI 7 TCKEC 0 4.0 0 0 2.0 0 0 1.5 0 ns ns ns 4.0 4.0 100 3.0 3.0 125 Clock Clock High time Clock Low time Max flip-flop toggle rate 11 TCH 12 TCL FCLK 5.0 5.0 70 Reset Direct (RD) RD width delay from rd to outputs X or Y 13 TRPW 9 TRIO 8.0 TMRW TMRQ 25.0 Global Reset (RESET Pad)* RESET width (Low) delay from RESET pad to outputs X or Y Min -125 Description Sequential delay Clock k to outputs X or Y Clock k to outputs X or Y when Q is returned through function generators F or G to drive X or Y Min Max -100 7.0 8.0 6.0 7.0 21.0 23.0 ns ns MHz 6.0 ns ns 17.0 ns ns 20.0 19.0 *Timing is based on the XC3042, for other devices see XACT timing calculator. Note: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. 2-157 XC3000 Logic Cell Array Family IOB Switching Characteristic Guidelines I/O Block (I) 3 T PID I/O Pad Input T PICK 1 I/O Clock (IK/OK) 12 TIOL 11 TIOH I/O Block (RI) 4 13 TRRI TIKRI RESET 5 TOOK 6 TOKO 15 TRPO I/O Block (O) 10 TOP I/O Pad Output (Direct) TOKPO 7 I/O Pad Output (Registered) I/O Pad TS 8 T TSHZ 9 TTSON I/O Pad Output X5425 Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3- STATE (OUTPUT ENABLE) OUT OUTPUT SELECT 3-STATE INVERT SLEW RATE PASSIVE PULL UP T O D Q FLIP FLOP OUTPUT BUFFER I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH TTL or CMOS INPUT THRESHOLD R OK (GLOBAL RESET) IK CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP 2-158 X3029 IOB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent Clock (IK) to Registered In (Q) Symbol Min Max -100 -125 Min Max Min Max 4 Set-up Time (Input) Pad to Clock (IK) set-up time 1 TPICK Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) same (slew-rate limited) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) same (slew -rate limited) 7 7 10 10 9 9 8 8 TOKPO TOKPO TOPF TOPS TTSHZ TTSHZ TTSON TTSON Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time Output (O) to clock (OK) hold time 5 6 TOOK TOKO 10 0 9 0 8 0 ns ns 11 12 TIOH TIOL FCLK 5 5 70 4 4 100 3 3 125 ns ns MHz 13 15 15 TRRI TRPO TRPO Global Reset Delays (based on XC3042) RESET Pad to Registered In (Q) RESET Pad to output pad (fast) (slew-rate limited) 6 21 5.5 20 4 17 4 Units TPID TPTG TIKRI Clock Clock High time Clock Low time Max. flip-flop toggle rate 3 -70 17 13 33 9 29 8 28 14 34 25 35 53 3 16 3 ns ns ns 16 10 27 6 23 8 25 12 29 24 33 45 ns 9 24 5 20 7 24 11 27 ns ns ns ns ns ns ns ns 23 29 42 ns ns ns Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad setup time and hold times are specified with respect to the internal clock (IK). To calculate system setup time, subtract clock delay (clock pad to IK) from the specified input pad setup time value, but the subtracted value cannot be less than zero (i.e., negative hold time). Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero, provided the input clock uses the Global signal distribution from pad to IK . 2-159 XC3000 Logic Cell Array Family For a detailed description of the device architecture, see pages 2-105 through 2-123. For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132. For detailed lists of package pin-outs, see pages 2-140 through 2-150. For package physical dimensions and thermal data, see Section 4. Ordering Information XC3030-70PC44C Example: Device Type Temperature Range Toggle Rate Number of Pins Package Type Component Availability 44 PINS TYPE CODE XC3020 XC3030 XC3042 XC3064 XC3090 -50 -70 -100 -125 -50 -70 -100 -125 -50 -70 -100 -125 -50 -70 -100 -125 -50 -70 -100 -125 64 68 84 100 PLAST. PQFP PLAST. TQFP 132 144 TOPPLAST. BRAZED PLAST. CERAM. PLAST. VQFP CQFP PGA PGA TQFP 160 164 175 176 TOPPLAST. BRAZED PLAST. CERAM. PLAST. PQFP CQFP PGA PGA TQFP PLAST. PLCC PLAST. VQFP PLAST. PLCC PLAST. CERAM. PLCC PGA PC44 VQ64 PC68 PC84 CI CI CIMB CI CMB CI CI CIMB CI CMB C C C C CI CI CI CIM CI CI CI CI CIM CI C C C C C C C CI CIMB CI C CMB C CIMB CI CIMB CI C CMB C CIMB C C C C C C CI CI CIM CI CI CI CIM CI C C C C 208 223 PLAST. CERAM. PQFP PGA PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223 M B M B M C M B M B M B M M B M B CI CI CMB CI CIMB CI CI CI CMB CI CIMB CI C C C C C C = Commercial = 0° to +70° C I = Industrial = -40° to +85° C Parentheses indicate future product plans 2-160 M = Mil Temp = -55° to +125° C B = MIL-STD-883C Class B