1
Spartan-3AN FPGA Family Data Sheet
DS557 January 9, 2019
Product Specification
Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS557(v4.3) January 9, 2019
DS557 (v4.3) January 9, 2019
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•
•
•
•
•
•
•
•
Introduction
Features
Architectural Overview
Configuration Overview
In-system Flash Memory Overview
General I/O Capabilities
Supported Packages and Package Marking
Ordering Information
•
Module 2:
Functional Description
DS557 (v4.3) January 9, 2019
The functionality of the Spartan®-3AN FPGA family is
described in the following documents:
•
•
DS557 (v4.3) January 9, 2019
•
Pin Descriptions
•
Package Overview
•
Pinout Tables
•
Footprint Diagrams
Table 1: Production Status of Spartan-3AN FPGAs
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
•
I/O Resources
•
Embedded Multiplier Blocks
•
Programmable Interconnect
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ISE® Design Tools and IP Cores
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Embedded Processing and Control Solutions
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Pin Types and Package Overview
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Package Drawings
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Powering FPGAs
•
Power Management
UG332: Spartan-3 Generation Configuration User Guide
•
Configuration Overview
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Configuration Pins and Behavior
•
Bitstream Sizes
•
Detailed Descriptions by Mode
-
•
•
Module 4:
Pinout Descriptions
UG331: Spartan-3 Generation FPGA User Guide
•
Clocking Resources
•
Digital Clock Managers (DCMs)
•
Block RAM
•
Configurable Logic Blocks (CLBs)
-
DC Electrical Characteristics
•
Absolute Maximum Ratings
•
Supply Voltage Specifications
•
Recommended Operating Conditions
Switching Characteristics
•
I/O Timing
•
Configurable Logic Block (CLB) Timing
•
Multiplier Timing
•
Block RAM Timing
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Digital Clock Manager (DCM) Timing
•
Suspend Mode Timing
•
Device DNA Timing
•
Configuration and JTAG Timing
Spartan-3AN FPGA
Status
XC3S50AN
Production
XC3S200AN
Production
XC3S400AN
Production
XC3S700AN
Production
XC3S1400AN
Production
Additional information on the Spartan-3AN family can be
found at:
http://www.xilinx.com/support/index.html/content/xilinx/en/s
upportNav/silicon_devices/fpga/spartan-3an.html.
Self-contained In-System Flash mode
Master Serial Mode using Platform Flash PROM
Master SPI Mode using Commodity Serial Flash
Master BPI Mode using Commodity Parallel Flash
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
•
ISE iMPACT Programming Examples
•
MultiBoot Reconfiguration
•
Design Authentication using Device DNA
UG333: Spartan-3AN In-System Flash User Guide
UG334: Spartan-3AN Starter Kit User Guide
© Copyright 2007–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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9
Spartan-3AN FPGA Family:
Introduction and Ordering Information
DS557(v4.3) January 9, 2019
Product Specification
Introduction
The Spartan®-3AN FPGA family combines the best attributes of a
leading edge, low cost FPGA with nonvolatile technology across a
broad range of densities. The family combines all the features of
the Spartan-3A FPGA family plus leading technology in-system
Flash memory for configuration and nonvolatile data storage.
The Spartan-3AN FPGAs are part of the Extended Spartan-3A
family, which also includes the Spartan-3A FPGAs and the higher
density Spartan-3A DSP FPGAs. The Spartan-3AN FPGA family
is excellent for space-constrained applications such as blade
servers, medical devices, automotive infotainment, telematics,
GPS, and other small consumer products. Combining FPGA and
Flash technology minimizes chip count, PCB traces and overall
size while increasing system reliability.
The Spartan-3AN FPGA internal configuration interface is
completely self-contained, increasing design security. The family
maintains full support for external configuration. The Spartan-3AN
FPGA is the world’s first nonvolatile FPGA with MultiBoot,
supporting two or more configuration files in one device, allowing
alternative configurations for field upgrades, test modes, or
multiple system configurations.
•
•
•
•
•
•
Features
•
•
•
•
•
•
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The new standard for low cost nonvolatile FPGA solutions
Eliminates traditional nonvolatile FPGA limitations with the
advanced 90 nm Spartan-3A device feature set
•
Memory, multipliers, DCMs, SelectIO, hot swap, power
management, etc.
Integrated robust configuration memory
•
Saves board space
•
Improves ease-of-use
•
Simplifies design
•
Reduces support issues
Plentiful amounts of nonvolatile memory available to the user
•
Up to 11+ Mb available
•
MultiBoot support
•
Embedded processing and code shadowing
•
Scratchpad memory
Robust 100K Flash memory program/erase cycles
20 years Flash memory data retention
Security features provide bitstream anti-cloning protection
•
•
•
•
•
•
•
•
Buried configuration interface
Unique Device DNA serial number in each device for
design Authentication to prevent unauthorized copying
•
Flash memory sector protection and lockdown
Configuration watchdog timer automatically recovers from
configuration errors
Suspend mode reduces system power consumption
•
Retains all design state and FPGA configuration data
•
Fast response time, typically less than 100 μs
Full hot-swap compliance
Multi-voltage, multi-standard SelectIO™ interface pins
•
Up to 502 I/O pins or 227 differential signal pairs
•
LVCMOS, LVTTL, HSTL, and SSTL single-ended signal
standards
•
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
•
Up to 24 mA output drive
•
3.3V ±10% compatibility and hot swap compliance
•
622+ Mb/s data transfer rate per I/O
•
DDR/DDR2 SDRAM support up to 400 Mb/s
•
LVDS, RSDS, mini-LVDS, PPDS, and HSTL/SSTL
differential I/O
Abundant, flexible logic resources
•
Densities up to 25,344 logic cells
•
Optional shift register or distributed RAM support
•
Enhanced 18 x 18 multipliers with optional pipeline
Hierarchical SelectRAM™ memory architecture
•
Up to 576 Kbits of dedicated block RAM
•
Up to 176 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
Eight global clocks and eight additional clocks per each half
of device, plus abundant low-skew routing
Complete Xilinx® ISE® and WebPACK™ software
development system support
MicroBlaze™ and PicoBlaze embedded processor cores
Fully compliant 32-/64-bit 33 MHz PCI™ technology support
Low-cost QFP and BGA Pb-free (RoHS) packaging options
•
Pin-compatible with the same packages in the
Spartan-3A FPGA family
Table 2: Summary of Spartan-3AN FPGA Attributes
System Equivalent
Distributed Block RAM Dedicated
Maximum Max Differential Bitstream In-System
Device
Gates Logic Cells CLBs Slices RAM Bits (1)
Bits (1)
Multipliers DCMs User I/O
I/O Pairs
Size (1) Flash Bits
XC3S50AN
50K
1,584
176
704
11K
54K
3
2
108
50
427K
1M(2)
XC3S200AN
200K
4,032
448
1,792
28K
288K
16
4
195
90
1,168K
4M
XC3S400AN
400K
8,064
896
3,584
56K
360K
20
4
311
142
1,842K
4M
XC3S700AN
700K
13,248
1,472 5,888
92K
360K
20
8
372
165
2,669K
8M
XC3S1400AN 1400K
25,344
2,816 11,264
176K
576K
32
8
502
227
4,644K
16M
Notes:
1. By convention, one Kb is equivalent to 1,024 bits and one Mb is equivalent to 1,024 Kb.
2. Maximum supported by Xilinx tools. See the customer notice XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition
for Spartan-3AN FPGA Devices.
© Copyright 2007–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Spartan-3AN FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3AN FPGA architecture is compatible with that
of the Spartan-3A FPGA. The architecture consists of five
fundamental programmable functional elements:
•
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches.
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. They support a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
•
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
•
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
•
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in Figure 1. A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50AN, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50AN has DCMs only at the
top, while the XC3S700AN and XC3S1400AN add two
DCMs in the middle of the two columns of block RAM and
multipliers.
The Spartan-3AN FPGA features a rich network of traces
that interconnect all five functional elements, transmitting
signals among them. Each functional element has an
associated switch matrix that permits multiple connections
to the routing.
X-Ref Target - Figure 1
IOBs
Multiplier
DCM
Block RAM
CLB
IOBs
OBs
IOBs
IOBs
CLBs
DCM
Block RAM / Multiplier
DCM
IOBs
DS557-1_01_122006
Notes:
1.
The XC3S700AN and XC3S1400AN have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50AN has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1: Spartan-3AN Family Architecture
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Spartan-3AN FPGA Family: Introduction and Ordering Information
X-Ref Target - Figure 2
Spartan-3AN FPGA
Configure
from internal
flash memory
‘0’
M2
VCCAUX
‘1’
M1
INIT_B
‘1’
M0
DONE
3.3V
Indicates when
configuration is
finished
DS557-1_06_082810
Figure 2: Spartan-3AN FPGA Configuration Interface from Internal SPI Flash Memory
Configuration
In-System Flash Memory
Spartan-3AN FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored on-chip in nonvolatile Flash
memory, or externally in a PROM or some other nonvolatile
medium, either on or off the board. After applying power, the
configuration data is written to the FPGA using any of seven
different modes:
Each Spartan-3AN FPGA contains abundant integrated SPI
serial Flash memory, shown in Table 3, used primarily to
store the FPGA’s configuration bitstream. However, the
Flash memory array is large enough to store at least two
MultiBoot FPGA configuration bitstreams or nonvolatile
data required by the FPGA application, such as
code-shadowed MicroBlaze processor applications.
•
Table 3: Spartan-3AN Device In-System Flash Memory
Part Number
Total Flash
Memory
(Bits)
FPGA
Bitstream
(Bits)
Additional
Flash
Memory
(Bits)(1)
XC3S50AN
1,081,344(2)
437,312
642,048
Configure from internal SPI Flash memory (Figure 2)
•
•
•
Completely self-contained
Reduced board space
Easy-to-use configuration interface
•
Master Serial from a Xilinx Platform Flash PROM
XC3S200AN
4,325,376
1,196,128
3,127,872
•
Serial Peripheral Interface (SPI) from an external
industry-standard SPI serial Flash
XC3S400AN
4,325,376
1,886,560
2,437,248
XC3S700AN
8,650,752
2,732,640
5,917,824
•
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
XC3S1400AN
17,301,504
4,755,296
12,545,280
•
Slave Serial, typically downloaded from a processor
•
Slave Parallel, typically downloaded from a processor
•
Boundary-Scan (JTAG), typically downloaded from a
processor or system tester
The MultiBoot feature stores multiple configuration files in
the on-chip Flash, providing extended life with field
upgrades. MultiBoot also supports multiple system
solutions with a single board to minimize inventory and
simplify the addition of new features, even in the field.
Flexibility is maintained to do additional MultiBoot
configurations via the external configuration method.
The Spartan-3AN device authentication protocol prevents
cloning. Design cloning, unauthorized overbuilding, and
complete reverse engineering have driven device security
requirements to higher and higher levels. Authentication
moves the security from bitstream protection to the next
generation of design-level security protecting both the
design and embedded microcode. The authentication
algorithm is entirely user defined, implemented using FPGA
logic. Every product, generation, or design can have a
different algorithm and functionality to enhance security.
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Notes:
1.
2.
Aligned to next available page location.
Maximum supported by Xilinx tools.
After configuration, the FPGA design has full access to the
in-system Flash memory via an internal SPI interface; the
control logic is implemented with FPGA logic. Additionally,
the FPGA application itself can store nonvolatile data or
provide live, in-system Flash updates.
The Spartan-3AN device in-system Flash memory supports
leading-edge serial Flash features.
•
Small page size (264 or 528 bytes) simplifies
nonvolatile data storage
•
Randomly accessible, byte addressable
•
Up to 66 MHz serial data transfers
•
SRAM page buffers
•
•
•
•
Read Flash data while programming another Flash
page
EEPROM-like byte write functionality
Two buffers in most devices, one in XC3S50AN
Page, Block, and Sector Erase
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Spartan-3AN FPGA Family: Introduction and Ordering Information
•
•
Sector Protect: Write- and erase-protect a sector
(changeable)
Sector Lockdown: Sector data is unchangeable
(permanent)
•
•
I/O Capabilities
Sector-based data protection and security features
The Spartan-3AN FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 4
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional,
input-only pins as indicated in Table 4.
128-byte Security Register
•
Separate from FPGA’s unique Device DNA
identifier
64-byte factory-programmed identifier unique to
the in-system Flash memory
64-byte one-time programmable,
user-programmable field
•
•
Spartan-3AN FPGAs support the following single-ended
standards:
•
3.3V low-voltage TTL (LVTTL)
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Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
•
100,000 Program/Erase cycles
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20-year data retention
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3.3V PCI at 33 MHz or 66 MHz
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Comprehensive programming support
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HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
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SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
•
In-system prototype programming via JTAG using
Xilinx Platform Cable USB and iMPACT software
Product programming support using BPM
Microsystems programmers with appropriate
programming adapter
Design examples demonstrating in-system
programming from a Spartan-3AN FPGA
application
•
•
Spartan-3AN FPGAs support the following differential
standards:
•
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
•
Bus LVDS I/O at 2.5V
•
TMDS I/O at 3.3V
•
Differential HSTL and SSTL I/O
•
LVPECL inputs at 2.5V or 3.3V
Table 4: Available User I/Os and Differential (Diff) I/O Pairs
Package (1)
TQ144
TQG144
FT256
FTG256
FG400
FGG400
FG484
FGG484
FG676
FGG676
Body Size (mm)
20 x 20 (2)
17 x 17
21 x 21
23 x 23
27 x 27
Device (3)
Diff
User
Diff
64(5)
(7)
50
(24)
144(5)
(32)
(32)
XC3S200AN
–
–
195
(35)
XC3S400AN
–
–
XC3S700AN
–
XC3S1400AN
–
XC3S50AN
User
108 (4)
User
Diff
User
Diff
User
Diff
–
–
–
–
–
–
90
(50)
–
–
–
–
–
–
195
(35)
90
(50)
311
(63)
142
(78)
–
–
–
–
–
–
–
–
–
372
(84)
165
(93)
–
–
–
–
–
–
–
375(5)
(87)
165(5)
(93)
502
(94)
227
(131)
Notes:
1.
2.
3.
4.
5.
See Pb and Pb-Free Packaging, page 7 for details on Pb and Pb-free packaging options.
The footprint for the TQ(G)144 (22 mm x 22 mm) package is larger than the package body.
Each Spartan-3AN FPGA has a pin-compatible Spartan-3A FPGA equivalent, although Spartan-3A FPGAs do not have internal SPI flash
and offer more part/package combinations.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
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Spartan-3AN FPGA Family: Introduction and Ordering Information
Package Marking
The “5C” and “4I” Speed Grade/Temperature Range part
combinations may be dual marked as “5C/4I”. Devices
with the dual mark can be used as either -5C or -4I devices.
Devices with a single mark are only guaranteed for the
marked speed grade and temperature range.
Figure 3 provides a top marking example for Spartan-3AN
FPGAs in the quad-flat packages. Figure 4 shows the top
marking for Spartan-3AN FPGAs in BGA packages. The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator.
X-Ref Target - Figure 3
Mask Revision Code
Fabrication Code
R
SPARTAN
Device Type
Package
Speed Grade
R
Process Technology
XC3S50ANTM
TQG144 AGQ0725
D1234567A
Date Code
4C
Lot Code
Temperature Range
Pin P1
DS557-1_02_080107
Figure 3: Spartan-3AN FPGA QFP Package Marking Example
X-Ref Target - Figure 4
Mask Revision Code
BGA Ball A1
R
SPARTAN
Device Type
Package
R
XC3S200ANTM
FTG256 AGQ0725
D1234567A
4C
Fabrication Code
Process Code
Date Code
Lot Code
Speed Grade
Temperature Range
DS557-1_03_080107
Figure 4: Spartan-3AN FPGA BGA Package Marking Example
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Spartan-3AN FPGA Family: Introduction and Ordering Information
Pb and Pb-Free Packaging
Spartan-3AN FPGAs are available in both leaded (Pb) and Pb-free packaging options (see Table 5). The Pb-free packages
are available for all devices and include a ‘G’ character in the ordering code. Leaded (non-Pb-free) packages are available
for selected devices. The ordering code for the leaded devices does not have an extra ‘G’. Leaded and Pb-free devices have
the same pin-out.
Table 5: Pb and Pb-Free Package Options
Pins
144
256
400
484
676
Type
TQFP
FTBGA
FBGA
FBGA
FBGA
Material
Device
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Pb-Free
Speed Range TQG144
Pb
TQ144
Pb-Free
Pb
Pb-Free
Pb
Pb-Free
Pb
Pb-Free
Pb
FTG256 FT256 FGG400 FG400 FGG484 FG484 FGG676 FG676
-4
C, I
✔
SCD4100 (1)
-5
C
✔
Note 2
-4
C, I
✔
✔
-5
C
✔
✔
-4
C, I
✔
✔
✔
✔
-5
C
✔
✔
✔
Note 2
-4
C, I
✔
✔
-5
C
✔
Note 2
-4
C, I
Note 3
Note 3
✔
✔
-5
C
Note 3
Note 3
✔
Note 2
Note 3
Note 3
Note 3
Note 3
Notes:
1.
2.
3.
To order a Pb package for the XC3S50AN -4 option, append SCD4100 to the part number (XC3S50AN-4TQ144C4100).
For Pb packaging for these options, contact your Xilinx sales representative.
Xilinx has issued a discontinuation notice for these highlighted devices/packages. For more information see XCN13016: Product
Discontinuation Notice For Selected Spartan-3AN FPGA Products.
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Spartan-3AN FPGA Family: Introduction and Ordering Information
Ordering Information
X-Ref Target - Figure 5
Example:
XC3S50AN -4 TQG144
C
Device Type
Temperature Range:
C = Commercial (TJ = 0oC to 85oC)
I = Industrial (TJ = -40oC to 100oC)
Speed Grade
Package Type/Number of Pins
DS557-1_05_101109
Figure 5: Device Numbering Format
Device
XC3S50AN
Speed Grade
Package Type / Number of Pins
Temperature Range (TJ )
-4 Standard Performance TQ144/ 144-pin Thin Quad Flat Pack (TQFP)
TQG144
C Commercial (0°C to 85°C)
XC3S200AN -5 High Performance(1)
FT256/ 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) I
FTG256
XC3S400AN
FG400/ 400-ball Fine-Pitch Ball Grid Array (FBGA)
FGG400
XC3S700AN
FG484/ 484-ball Fine-Pitch Ball Grid Array (FBGA)
FGG484
XC3S1400AN
FG676/ 676-ball Fine-Pitch Ball Grid Array (FBGA)
FGG676
Industrial (–40°C to 100°C)
Notes:
1.
2.
The -5 speed grade is exclusively available in the Commercial temperature range.
See Table 4 and Table 5 for available package combinations.
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Spartan-3AN FPGA Family: Introduction and Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
02/26/2007
1.0
Initial release.
08/16/2007
2.0
Updated for Production release of initial device.
09/12/2007
2.0.1
12/12/2007
3.0
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
non-Pb-free packages may be available for selected devices.
06/02/2008
3.1
Minor updates.
11/19/2009
3.2
Updated document throughout to reflect availability of Pb package options. Added references to the
Extended Spartan-3A family. Removed table note 2 from Table 2. In Table 4, added Pb packages,
added table note 4, and updated table note 2. Added Table 5.
12/02/2010
4.0
Updated Notice of Disclaimer.
04/01/2011
4.1
In Table 2, revised the Maximum Differential I/O Pairs and Maximum User I/O values for the
XC3S50AN. In Table 4, added packages to the XC3S50AN, XC3S400AN, and XC3S1400AN. Updated
Pb and Pb-Free Packaging section and Table 5 to include the new device/package combinations for
the XC3S50AN, XC3S400AN, and XC3S1400AN.
06/11/2014
4.2
In Table 2, revised the XC3S50AN values in Maximum User I/O and Max Differential I/O Pairs columns,
and added Note 2 to the In-System Flash Bits column. In Table 3, added the same Note 2. Descriptions
of these changes and further links to the product changes are outlined in the customer notice
XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN
FPGA Devices.
Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the
XC3S1400AN in the FG(G)484 package. See XCN13016: Product Discontinuation Notice For
Selected Spartan-3AN FPGA Products. This customer notice is highlighted in Table 4 and Table 5.
Updated Notice of Disclaimer.
01/09/2019
4.3
Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
Noted that only dual-mark devices are guaranteed for both -4I and -5C.
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain
products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx
products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and
liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF
AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY
CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY DESIGN”).
CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH
SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK
OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
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Spartan-3AN FPGA Family:
Functional Description
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Spartan-3AN FPGA Design Documentation
The functionality of the Spartan®-3AN FPGA family is
described in the following documents. The topics covered in
each guide are listed below:
UG333: Spartan-3AN FPGA In-System Flash User
Guide
•
For FPGA applications that write to or read from
the In-System Flash memory after configuration
UG331: Spartan-3 Generation FPGA User Guide
•
SPI_ACCESS interface
•
•
•
•
•
In-System Flash memory architecture
•
Read, program, and erase commands
•
Status registers
•
Sector Protection and Sector Lockdown features
•
Security Register with Unique Identifier
•
DS706: Extended Spartan-3A Family Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
•
Sign Up for Alerts on Xilinx.com
https://secure.xilinx.com/webreg/register.do?group=my
profile&languageID=1
Spartan-3AN FPGA Starter Kit
For specific hardware examples, please see the
Spartan-3AN FPGA Starter Kit board web page, which has
links to various design examples and the user guide.
UG332: Spartan-3 Generation Configuration
User Guide
•
Spartan-3AN FPGA Starter Kit Board Page
http://www.xilinx.com/s3anstarter
•
•
UG334: Spartan-3AN FPGA Starter Kit User Guide
•
Configuration Overview
- Configuration Pins and Behavior
- Bitstream Sizes
Detailed Descriptions by Mode
- Master Serial Mode using Xilinx® Platform
Flash
- Master SPI Mode using SPI Serial Flash
PROM
- Internal Master SPI Mode
- Master BPI Mode using Parallel NOR Flash
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
ISE iMPACT Programming Examples
•
MultiBoot Reconfiguration
•
Design Authentication using Device DNA
•
Related Product Families
The Spartan-3AN FPGA family is generally compatible with
the Spartan-3A FPGA family.
•
DS529: Spartan-3A FPGA Family Data Sheet
© Copyright 2007–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Spartan-3AN FPGA Family: Functional Description
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
02/26/2007
1.0
Initial release.
08/16/2007
2.0
Updated for Production release of initial device.
09/12/2007
2.0.1
09/24/2007
2.1
Added note that In-System Flash commands were not supported by simulation until ISE 10.1 software.
12/12/2007
3.0
Updated to Production status with Production release of final family member, XC3S50AN. Noted that
SPI_ACCESS simulation is supported in ISE 10.1 software. Updated links.
06/02/2008
3.1
Minor updates.
11/19/2009
3.2
In the Spartan-3AN FPGA Design Documentation section, added link to DS706, Extended Spartan-3A
Family Overview and removed references to older software versions.
12/02/2010
4.0
Updated link to sign up for Alerts and updated Notice of Disclaimer.
04/01/2011
4.1
Added the FT(G)256 package selection for the XC3S50AN and XC3S400AN devices and the
FG(G)484 package selection for the XC3S1400AN device throughout this data sheet.
06/11/2014
4.2
Xilinx has issued a discontinuation notice for the XC3S50AN in the FT(G)256 package and the
XC3S1400AN in the FG(G)484 package. See XCN13016: Product Discontinuation Notice For
Selected Spartan-3AN FPGA Products. Updated Notice of Disclaimer.
01/09/2019
4.3
Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
Minor updates to text.
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain
products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx
products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and
liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at
www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF
AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY
CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY DESIGN”).
CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH
SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK
OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
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70
Spartan-3AN FPGA Family:
DC and Switching Characteristics
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Product Specification
DC Electrical Characteristics
In this section, specifications can be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan®-3AN devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Absolute Maximum Ratings
Stresses beyond those listed under Table 6: Absolute
Maximum Ratings might cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
Table 6: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Max
Units
VCCINT
Internal supply voltage
–0.5
1.32
V
VCCAUX
Auxiliary supply voltage
–0.5
3.75
V
VCCO
Output driver supply voltage
–0.5
3.75
V
VREF
Input reference voltage
–0.5
VCCO + 0.5
V
–0.95
4.6
V
–0.5
4.6
V
–
±100
mA
VIN
Voltage applied to all User I/O pins and
dual-purpose pins
Driver in a high-impedance state
Voltage applied to all Dedicated pins
IIK
0.5V)(1)
Input clamp current per I/O pin
–0.5V < VIN < (VCCO +
Electrostatic Discharge Voltage
Human body model
–
±2000
V
Charged device model
–
±500
V
Machine model
–
±200
V
VESD
TJ
Junction temperature
–
125
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1.
1.
Upper clamp applies only when using PCI IOSTANDARDs.
For soldering guidelines, see UG112: Device Package User Guide and XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free
Packages.
© Copyright 2007–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Power Supply Specifications
Table 7: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
1.0
2.0
V
VCCO2T
Threshold for the VCCO Bank 2 supply
1.0
2.0
V
Notes:
1.
2.
When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT, VCCAUX, and VCCO supplies to the FPGA can
be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the
data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see the chapter called “Powering
Spartan-3 Generation FPGAs” in UG331 for more information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 8: Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
VCCINTR
Ramp rate from GND to valid VCCINT supply level
0.2
100
ms
VCCAUXR
Ramp rate from GND to valid VCCAUX supply level
0.2
100
ms
VCCO2R
Ramp rate from GND to valid VCCO Bank 2 supply level
0.2
100
ms
Notes:
1.
2.
When configuring from the In-System Flash, VCCAUX must be in the recommended operating range; on power-up make sure VCCAUX
reaches at least 3.0V before INIT_B goes High to indicate the start of configuration. VCCINT , VCCAUX , and VCCO supplies to the FPGA can
be applied in any order if this requirement is met. However, an external configuration source might have specific requirements. Check the
data sheet for the attached configuration source. Apply VCCINT last for lowest overall power consumption (see the chapter called “Powering
Spartan-3 Generation FPGAs” in UG331 for more information).
To ensure successful power-on, VCCINT , VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 9: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data
Symbol
Description
Min
Units
VDRINT
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
1.0
V
VDRAUX
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
2.0
V
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Spartan-3AN FPGA Family: DC and Switching Characteristics
General Recommended Operating Conditions
Table 10: General Recommended Operating Conditions
Symbol
TJ
Description
Min
Nominal
Max
Units
0
–
85
°C
–40
–
100
°C
Internal supply voltage
1.14
1.20
1.26
V
Output driver supply voltage
1.10
–
3.60
V
Junction temperature
Commercial
Industrial
VCCINT
VCCO
(1)
VCCAUX
VIN
(2)
Auxiliary supply voltage
VCCAUX = 3.3V
3.00
3.30
3.60
V
Input voltage
PCI IOSTANDARD
–0.5
–
VCCO + 0.5
V
IP or IO_#
–0.5
–
4.10
V
IO_Lxxy_#(3)
–0.5
–
4.10
V
–
–
500
ns
All other
IOSTANDARDs
TIN
Input signal transition
time (4)
Notes:
1.
2.
3.
4.
This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 13 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 15 lists that specific to the differential standards.
See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
General DC Characteristics for I/O Pins
Table 11: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
IL
(2)
IHS
Description
Test Conditions
Min
Typ
Max
Units
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10
–
+10
µA
Leakage current on pins during
hot socketing, FPGA unpowered
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
–10
–
+10
µA
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
IRPU(3)
RPU(3)
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
VCCAUX.(4)
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPU per Note 3)
IRPD(3)
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
RPD(3)
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPD per Note 3)
IREF
VREF current per pin
CIN
Input capacitance
RDT
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
VIN = GND
Add IHS + IRPU
µA
VCCO or VCCAUX =
3.0V to 3.6V
–151
–315
–710
µA
VCCO = 2.3V to 2.7V
–82
–182
–437
µA
VCCO = 1.7V to 1.9V
–36
–88
–226
µA
VCCO = 1.4V to 1.6V
–22
–56
–148
µA
VCCO = 1.14V to 1.26V
–11
–31
–83
µA
VCCO = 3.0V to 3.6V
5.1
11.4
23.9
kΩ
VCCO = 2.3V to 2.7V
6.2
14.8
33.1
kΩ
VCCO = 1.7V to 1.9V
8.4
21.6
52.6
kΩ
VCCO = 1.4V to 1.6V
10.8
28.4
74.0
kΩ
VCCO = 1.14V to 1.26V
15.3
41.1
119.4
kΩ
VIN = VCCO
VCCAUX = 3.0V to 3.6V
167
346
659
µA
VCCAUX = 3.0V to 3.6V
VIN = 3.0V to 3.6V
5.5
10.4
20.8
kΩ
VIN = 2.3V to 2.7V
4.1
7.8
15.7
kΩ
VIN = 1.7V to 1.9V
3.0
5.7
11.1
kΩ
VIN = 1.4V to 1.6V
2.7
5.1
9.6
kΩ
VIN = 1.14V to 1.26V
2.4
4.5
8.1
kΩ
All VCCO levels
–10
–
+10
µA
–
–
–
10
pF
VIN = GND
VCCO = 3.3V ± 10%
LVDS_33,
MINI_LVDS_33,
RSDS_33
90
100
115
Ω
VCCO = 2.5V ± 10%
LVDS_25,
MINI_LVDS_25,
RSDS_25
90
110
–
Ω
Notes:
1.
2.
3.
4.
The numbers in this table are based on the conditions set forth in Table 10.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
VCCAUX must be 3.3V on Spartan-3AN FPGAs. VCCAUX for Spartan-3A FPGAs can be either 3.3V or 2.5V.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Quiescent Current Requirements
Table 12: Spartan-3AN FPGA Quiescent Supply Current Characteristics
Symbol
Description
ICCINTQ
Quiescent VCCINT supply current
ICCOQ
ICCAUXQ
Quiescent VCCO supply current
Quiescent VCCAUX supply current
Typical(2)
Commercial
Maximum(2)
XC3S50AN
2
20
30
mA
XC3S200AN
7
50
70
mA
XC3S400AN
10
85
125
mA
XC3S700AN
13
120
185
mA
XC3S1400AN
24
220
310
mA
XC3S50AN
0.2
2
3
mA
XC3S200AN
0.2
2
3
mA
XC3S400AN
0.3
3
4
mA
XC3S700AN
0.3
3
4
mA
XC3S1400AN
0.3
3
4
mA
XC3S50AN
3.1
8.1
10.1
mA
XC3S200AN
5.1
12.1
15.1
mA
XC3S400AN
5.1
18.1
24.1
mA
XC3S700AN
6.1
28.1
34.1
mA
XC3S1400AN
10.1
50.1
58.1
mA
Device
Industrial
Maximum(2)
Units
Notes:
1.
2.
The numbers in this table are based on the conditions set forth in Table 10.
Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. The internal SPI Flash is deselected (CSB = High); the internal SPI Flash current is consumed on the VCCAUX supply rail. Typical
values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX = 3.3V). The
maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with
VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design with no
functional elements instantiated). For conditions other than those described above (for example, a design including functional elements),
measured quiescent current levels will be different than the values in the table.
3. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design:
• The Spartan-3AN FPGA Xilinx Power Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design.
• Xilinx Power Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. For more
information on power for the In-System Flash memory, see the Power Management chapter of UG333.
4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
5. For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Single-Ended I/O Standards
Table 13: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
VCCO for Drivers(2)
VREF
Min (V)
Nom (V)
Max (V)
VIL
VIH(3)
Max (V)
Min (V)
Min (V)
Nom (V)
Max (V)
LVTTL
3.0
3.3
3.6
0.8
2.0
LVCMOS33(4)
3.0
3.3
3.6
0.8
2.0
LVCMOS25(4)(5)
2.3
2.5
2.7
0.7
1.7
LVCMOS18
1.65
1.8
1.95
0.4
0.8
LVCMOS15
1.4
1.5
1.6
0.4
0.8
LVCMOS12
1.1
1.2
1.3
0.4
0.7
PCI33_3(6)
3.0
3.3
3.6
0.3 • VCCO
0.5 • VCCO
PCI66_3(6)
3.0
3.3
3.6
0.3 • VCCO
0.5 • VCCO
HSTL_I
1.4
1.5
1.6
0.68
0.75
0.9
VREF – 0.1
VREF + 0.1
HSTL_III
1.4
1.5
1.6
–
0.9
–
VREF – 0.1
VREF + 0.1
HSTL_I_18
1.7
1.8
1.9
0.8
0.9
1.1
VREF – 0.1
VREF + 0.1
HSTL_II_18
1.7
1.8
1.9
–
0.9
–
VREF – 0.1
VREF + 0.1
HSTL_III_18
1.7
1.8
1.9
–
1.1
–
VREF – 0.1
VREF + 0.1
SSTL18_I
1.7
1.8
1.9
0.833
0.900
0.969
VREF – 0.125
VREF + 0.125
SSTL18_II
1.7
1.8
1.9
0.833
0.900
0.969
VREF – 0.125
VREF + 0.125
SSTL2_I
2.3
2.5
2.7
1.13
1.25
1.38
VREF – 0.150
VREF + 0.150
SSTL2_II
2.3
2.5
2.7
1.13
1.25
1.38
VREF – 0.150
VREF + 0.150
SSTL3_I
3.0
3.3
3.6
1.3
1.5
1.7
VREF – 0.2
VREF + 0.2
SSTL3_II
3.0
3.3
3.6
1.3
1.5
1.7
VREF – 0.2
VREF + 0.2
VREF is not used for
these I/O standards
Notes:
1.
2.
3.
4.
5.
6.
Descriptions of the symbols used in this table are as follows:
VCCO – the supply voltage for output drivers
VREF – the reference voltage for setting the input switching threshold
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs and for PCI™ I/O standards.
For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 6.
There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS33
standard. The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a
standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.
For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 14: DC Characteristics of User I/Os Using
Single-Ended Standards (Cont’d)
Table 14: DC Characteristics of User I/Os Using
Single-Ended Standards
IOSTANDARD
Attribute
LVTTL(3)
LVCMOS33(3)
LVCMOS25(3)
LVCMOS18(3)
LVCMOS15(3)
LVCMOS12(3)
Test
Conditions
IOL
IOH
(mA) (mA)
Logic Level
Characteristics
VOL
Max (V)
VOH
Min (V)
0.4
2.4
IOSTANDARD
Attribute
Test
Conditions
IOL
IOH
(mA) (mA)
Logic Level
Characteristics
VOL
Max (V)
VOH
Min (V)
HSTL_I(5)
8
–8
0.4
VCCO - 0.4
–4
HSTL_III(5)
24
–8
0.4
VCCO - 0.4
6
–6
HSTL_I_18
8
–8
0.4
VCCO - 0.4
8
8
–8
HSTL_II_18(5)
16
–16
0.4
VCCO - 0.4
12
12
–12
HSTL_III_18
24
–8
0.4
VCCO - 0.4
16
16
–16
SSTL18_I
6.7
–6.7
VTT – 0.475
VTT + 0.475
24
24
–24
SSTL18_II(5)
13.4
–13.4 VTT – 0.603
VTT + 0.603
2
2
–2
SSTL2_I
8.1
–8.1
VTT – 0.61
VTT + 0.61
4
4
–4
SSTL2_II(5)
16.2
–16.2
VTT – 0.81
VTT + 0.81
6
6
–6
SSTL3_I
8
–8
VTT – 0.6
VTT + 0.6
8
8
–8
SSTL3_II
16
–16
VTT – 0.8
VTT + 0.8
12
12
–12
Notes:
16
16
–16
1.
24(5)
24
–24
2.
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16(5)
16
–16
24(5)
24
–24
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12(5)
12
–12
16(5)
16
–16
2
2
–2
4
4
–4
6
6
–6
8(5)
8
–8
12(5)
12
–12
2
2
–2
4(5)
4
–4
6(5)
2
2
–2
4
4
6
0.4
0.4
VCCO – 0.4
VCCO – 0.4
3.
4.
0.4
VCCO – 0.4
0.4
VCCO – 0.4
0.4
VCCO – 0.4
6
–6
PCI33_3(4)
1.5
–0.5
10% VCCO
90% VCCO
PCI66_3(4)
1.5
–0.5
10% VCCO
90% VCCO
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5.
The numbers in this table are based on the conditions set forth in
Table 10 and Table 13.
Descriptions of the symbols used in this table are as follows:
IOL – the output current condition under which VOL is tested
IOH – the output current condition under which VOH is tested
VOL – the output voltage that indicates a Low logic level
VOH – the output voltage that indicates a High logic level
VCCO – the supply voltage for output drivers
VTT – the voltage applied to a resistor termination
For the LVCMOS and LVTTL standards: the same VOL and VOH
limits apply for the Fast, Slow and QUIETIO slew attributes.
Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/products/
design_resources/conn_central/protocols/pci_pcix.htm. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
“Using I/O Resources” in UG331.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Differential I/O Standards
Differential Input Pairs
X-Ref Target - Figure 6
VINP
Internal
Logic
VINN
VINN
VINP
Differential
I/O Pair Pins
P
N
VID
50%
VICM
GND level
VICM = Input common mode voltage =
VINP + VINN
2
VID = Differential input voltage = VINP - VINN
DS529-3_10_012907
Figure 6: Differential Input Voltages
Table 15: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VCCO for Drivers(1)
VICM(2)
VID
Min (V)
Nom (V)
Max (V)
LVDS_25(3)
Min (mV) Nom (mV) Max (mV)
Min (V)
Nom (V)
Max (V)
2.25
2.5
2.75
100
350
LVDS_33(3)
600
0.3
1.25
2.35
3.0
3.3
3.6
100
BLVDS_25(4)
350
600
0.3
1.25
2.35
2.25
2.5
2.75
MINI_LVDS_25(3)
100
300
–
0.3
1.3
2.35
2.25
2.5
MINI_LVDS_33(3)
2.75
200
–
600
0.3
1.2
1.95
3.0
3.3
3.6
200
–
600
0.3
1.2
1.95
LVPECL_25(5)
Inputs Only
100
800
1000
0.3
1.2
1.95
LVPECL_33(5)
Inputs Only
100
800
1000
0.3
1.2
2.8(6)
RSDS_25(3)
2.25
2.5
2.75
100
200
–
0.3
1.2
1.5
RSDS_33(3)
3.0
3.3
3.6
100
200
–
0.3
1.2
1.5
TMDS_33(3), (4), (7)
3.14
3.3
3.47
150
–
1200
2.7
–
3.23
PPDS_25(3)
2.25
2.5
2.75
100
–
400
0.2
–
2.3
PPDS_33(3)
3.0
3.3
3.6
100
–
400
0.2
–
2.3
DIFF_HSTL_I_18(8)
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_II_18 (8)(9)
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_III_18(8)
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_I(8)
1.4
1.5
1.6
100
–
–
0.68
DIFF_HSTL_III(8)
1.4
1.5
1.6
100
–
–
–
0.9
–
DIFF_SSTL18_I(8)
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL18_II (8)(9)
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL2_I(8)
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL2_II(8)(9)
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL3_I(8)
3.0
3.3
3.6
100
–
–
1.1
–
1.9
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 15: Recommended Operating Conditions for User I/Os Using Differential Signal Standards (Cont’d)
VCCO for Drivers(1)
IOSTANDARD Attribute
Min (V)
Nom (V)
Max (V)
3.0
3.3
3.6
DIFF_SSTL3_II(8)
VICM(2)
VID
Min (mV) Nom (mV) Max (mV)
100
–
Min (V)
Nom (V)
Max (V)
1.1
–
1.9
–
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The VCCO rails supply only differential output drivers, not input circuits.
VICM must be less than VCCAUX.
These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the “Using I/O Resources”
chapter in UG331.
See External Termination Requirements for Differential I/O, page 22.
LVPECL is supported on inputs only, not outputs. Requires VCCAUX = 3.3V ± 10%.
LVPECL_33 maximum VICM = VCCAUX – (VID / 2)
Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) ≤ VICM ≤ (VCCAUX – 37 mV)
VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in
Table 13. Other differential standards do not use VREF.
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the “Using I/O Resources”
chapter in UG331.
Differential Output Pairs
X-Ref Target - Figure 7
VOUTP
Internal
Logic
VOUTN
Differential
I/O Pair Pins
VOH
VOUTN
VOUTP
P
N
VOD
50%
VOL
VOCM
GND level
VOCM = Output common mode voltage =
VOUTP + VOUTN
2
VOD = Output differential voltage = VOUTP - VOUTN
VOH = Output voltage indicating a High logic level
VOL = Output voltage indicating a Low logic levelDS529-3_11_082810
Figure 7: Differential Output Voltages
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 16: DC Characteristics of User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VOD
VOCM
VOH
VOL
Min (mV)
Typ (mV)
Max (mV)
Min (V)
Typ (V)
Max (V)
Min (V)
Max (V)
LVDS_25
247
350
454
1.125
–
1.375
–
–
LVDS_33
247
350
454
1.125
–
1.375
–
–
BLVDS_25
240
350
460
–
1.30
–
–
–
MINI_LVDS_25
300
–
600
1.0
–
1.4
–
–
MINI_LVDS_33
300
–
600
1.0
–
1.4
–
–
RSDS_25
100
–
400
1.0
–
1.4
–
–
RSDS_33
100
–
400
1.0
–
1.4
–
–
TMDS_33
400
–
800
VCCO – 0.405
–
VCCO – 0.190
–
–
PPDS_25
100
–
400
0.5
0.8
1.4
–
–
PPDS_33
100
–
400
0.5
0.8
1.4
–
–
DIFF_HSTL_I_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_II_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_III_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_I
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_III
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_SSTL18_I
–
–
–
–
–
–
VTT + 0.475
VTT – 0.475
DIFF_SSTL18_II
–
–
–
–
–
–
VTT + 0.475
VTT – 0.475
DIFF_SSTL2_I
–
–
–
–
–
–
VTT + 0.61
VTT – 0.61
DIFF_SSTL2_II
–
–
–
–
–
–
VTT + 0.81
VTT – 0.81
DIFF_SSTL3_I
–
–
–
–
–
–
VTT + 0.6
VTT – 0.6
DIFF_SSTL3_II
–
–
–
–
–
–
VTT + 0.8
VTT – 0.8
Notes:
1.
2.
3.
4.
The numbers in this table are based on the conditions set forth in Table 10 and Table 15.
See External Termination Requirements for Differential I/O, page 22.
Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the
differential signal pair.
At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V
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Spartan-3AN FPGA Family: DC and Switching Characteristics
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
X-Ref Target - Figure 8
Bank 0 and 2
Any Bank
Bank 0
Bank 0
Bank 2
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
Bank 3
Bank 1
1/4th of Bourns
Part Number
Z0 = 50Ω CAT16-PT4F4
No VCCO Restrictions
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
Bank 2
100Ω
Z0 = 50Ω
DIFF_TERM=No
a) Input-only Differential Pairs or Pairs not Using DIFF_TERM=Yes Constraint
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
RDT
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
DIFF_TERM=Yes
b) Differential Pairs Using DIFF_TERM=Yes Constraint
DS529-3_09_080307
Figure 8: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
X-Ref Target - Figure 9
Any Bank
Any Bank
Bank 0
Z0 = 50Ω
165Ω
140Ω
Bank 3
BLVDS_25
1/4th of Bourns
Part Number
CAT16-PT4F4
Z0 = 50Ω
Bank 1
Bank 1
Bank 2
VCCO = 2.5V
1/4th of Bourns
Part Number
CAT16-LV4F12
Bank 3
Bank 0
Bank 2
No VCCO Requirement
100Ω
BLVDS_25
165Ω
DS529-3_07_080307
Figure 9: External Output and Input Termination Resistors for BLVDS_25 I/O Standard
TMDS_33 I/O Standard
X-Ref Target - Figure 10
Any Bank
Bank 0 and 2
Bank 0
3.3V
Bank 2
50Ω
Bank 1
Bank 3
Bank 0
50Ω
Bank 2
VCCAUX = 3.3V
VCCO = 3.3V
TMDS_33
TMDS_33
DVI/HDMI cable
DS529-3_08_020107
Figure 10: External Input Resistors Required for TMDS_33 I/O Standard
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Device DNA Read Endurance
Table 17: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations
30,000,000
Read
cycles
Minimum(1)
Units
Data retention
20
Years
Time that the ISF memory is selected and active. SPI_ACCESS design primitive
pins CSB = Low, CLK toggling
2
Years
Number of program/erase cycles, per ISF memory page
100,000
Cycles
Number of cumulative random (non-sequential) page erase/program operations
within a sector before pages must be rewritten
10,000
Cycles
ISF_SPR_CYCLES
Number of program/erase cycles for Sector Protection Register
10,000
Cycles
ISF_SEC_CYCLES
Number of program cycles for Sector Lockdown Register per sector,
user-programmable field in Security Register, and Power-of-2 Page Size
1
Cycle
In-System Flash Memory Data Retention, Program/Write Endurance
Table 18: In-System Flash (ISF) Memory Characteristics
Symbol
ISF_RETENTION
ISF_ACTIVE
ISF_PAGE_CYCLES
ISF_PAGE_REWRITE
Description
Notes:
1.
Minimum value at which functionality is still guaranteed. Do not exceed these values.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Switching Characteristics
All Spartan-3AN FPGAs ship in two speed grades: -4 and
the higher performance -5. Switching characteristics in this
document are designated as Preview, Advance,
Preliminary, or Production, as shown in Table 19. Each
category is defined as follows:
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
Preview: These specifications are based on estimates only
and should not be used for timing analysis.
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le&languageID=1
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Timing parameters and their representative values are
selected for inclusion either because they are important as
general design requirements or they indicate fundamental
device performance characteristics. The Spartan-3AN
speed files (v1.41), part of the Xilinx Development Software,
are the original source for many but not all of the values.
The speed grade designations for these files are shown in
Table 19. For more complete, more precise, and worst-case
data, use the values reported by the Xilinx static timing
analyzer (TRACE in the Xilinx development software) and
back-annotated to the simulation netlist.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Preview, Advance, or Preliminary should
not be used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the
FPGA design incorporates the latest timing information and
software updates.
In some cases, a particular family member (and speed
grade) is released to Production at a different time than
when the speed file is released with the Production label.
Any labeling discrepancies are corrected in subsequent
speed file releases. See Table 19 for devices that can be
considered to have the Production label.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3AN devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
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Table 19: Spartan-3AN Family v1.41 Speed Grade
Designations
Device
Preview
Advance
Preliminary
Production
XC3S50AN
-4, -5
XC3S200AN
-4, -5
XC3S400AN
-4, -5
XC3S700AN
-4, -5
XC3S1400AN
-4, -5
Table 20 provides the recent history of the Spartan-3AN
speed files.
Table 20: Spartan-3AN Speed File Version History
Version
ISE
Release
Description
1.41
ISE 10.1.03
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
1.40
ISE 10.1.02
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
1.39
ISE 10.1
Updated for Spartan-3A family. No
change to data for Spartan-3AN family.
1.38
ISE 9.2.03i
1.37
Updated pin-to-pin setup and hold
times, TMDS output adjustment,
ISE 9.2.01i
multiplier setup/hold times, and block
RAM clock width.
1.36
ISE 9.2i
Updated to Production. No change to
data.
Added -5 speed grade, updated to
Advance.
1.34
ISE 9.1.03i Updated pin-to-pin timing.
1.32
ISE 9.1.01i Preview speed files for -4 speed grade.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 21: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Max
Max
XC3S50AN
3.18
3.42
ns
XC3S200AN
3.21
3.27
ns
XC3S400AN
2.97
3.33
ns
XC3S700AN
3.39
3.50
ns
XC3S1400AN
3.51
3.99
ns
XC3S50AN
4.59
5.02
ns
XC3S200AN
4.88
5.24
ns
XC3S400AN
4.68
5.12
ns
XC3S700AN
4.97
5.34
ns
XC3S1400AN
5.06
5.69
ns
Clock-to-Output Times
TICKOFDCM
TICKOF
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25(2), 12 mA
output drive, Fast slew
rate, with DCM(3)
When reading from OFF, the time LVCMOS25(2), 12 mA
from the active transition on the
output drive, Fast slew
Global Clock pin to data appearing rate, without DCM
at the Output pin. The DCM is not
in use.
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 26. If the latter is true, add the appropriate Output adjustment from Table 29.
DCM output jitter is included in all measurements.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Pin-to-Pin Setup and Hold Times
Table 22: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Units
Min
Min
XC3S50AN
2.45
2.68
ns
XC3S200AN
2.59
2.84
ns
XC3S400AN
2.38
2.68
ns
XC3S700AN
2.38
2.57
ns
XC3S1400AN
1.91
2.17
ns
XC3S50AN
2.55
2.76
ns
XC3S200AN
2.32
2.76
ns
XC3S400AN
2.21
2.60
ns
XC3S700AN
2.28
2.63
ns
XC3S1400AN
2.33
2.41
ns
XC3S50AN
–0.36
–0.36
ns
XC3S200AN
–0.52
–0.52
ns
XC3S400AN
–0.33
–0.29
ns
XC3S700AN
–0.17
–0.12
ns
XC3S1400AN
–0.07
0.00
ns
XC3S50AN
–0.63
–0.58
ns
XC3S200AN
–0.56
–0.56
ns
XC3S400AN
–0.42
–0.42
ns
XC3S700AN
–0.80
–0.75
ns
XC3S1400AN
–0.69
–0.69
ns
Setup Times
TPSDCM
TPSFD
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
When writing to IFF, the time from LVCMOS25(2),
the setup of data at the Input pin IFD_DELAY_VALUE = 5,
to an active transition at the
without DCM
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
Hold Times
TPHDCM
TPHFD
When writing to IFF, the time from LVCMOS25(3),
the active transition at the Global IFD_DELAY_VALUE = 0,
Clock pin to the point when data with DCM(4)
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
When writing to IFF, the time from LVCMOS25(3),
the active transition at the Global IFD_DELAY_VALUE = 5,
Clock pin to the point when data without DCM
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
Notes:
1.
2.
3.
4.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 26. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 26. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Input Setup and Hold Times
Table 23: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Speed Grade
Device
-5
-4
Units
Min
Min
XC3S50AN
1.56
1.58
ns
XC3S200AN
1.71
1.81
ns
XC3S400AN
1.30
1.51
ns
XC3S700AN
1.34
1.51
ns
XC3S1400AN
1.36
1.74
ns
XC3S50AN
2.16
2.18
ns
2
3.10
3.12
ns
3
3.51
3.76
ns
4
4.04
4.32
ns
5
3.88
4.24
ns
6
4.72
5.09
ns
7
5.47
5.94
ns
8
5.97
6.52
ns
2.05
2.20
ns
2
2.72
2.93
ns
3
3.38
3.78
ns
4
3.88
4.37
ns
5
3.69
4.20
ns
6
4.56
5.23
ns
7
5.34
6.11
ns
8
5.85
6.71
ns
1.79
2.02
ns
2
2.43
2.67
ns
3
3.02
3.43
ns
4
3.49
3.96
ns
5
3.41
3.95
ns
6
4.20
4.81
ns
7
4.96
5.66
ns
8
5.44
6.19
ns
Setup Times
TIOPICK
TIOPICKD
Time from the setup of data at the
LVCMOS25(2)
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
No Input Delay is programmed.
Time from the setup of data at the
LVCMOS25(2)
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
0
1
1
1
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XC3S200AN
XC3S400AN
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27
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 23: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
TIOPICKD
Description
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
Conditions
LVCMOS25(2)
IFD_
DELAY_
VALUE
Speed Grade
-5
-4
Min
Min
1.82
1.95
ns
2
2.62
2.83
ns
3
3.32
3.72
ns
4
3.83
4.31
ns
5
3.69
4.14
ns
6
4.60
5.19
ns
7
5.39
6.10
ns
8
5.92
6.73
ns
1.79
2.17
ns
2
2.55
2.92
ns
3
3.38
3.76
ns
4
3.75
4.32
ns
5
3.81
4.19
ns
6
4.39
5.09
ns
7
5.16
5.98
ns
8
5.69
6.57
ns
XC3S50AN
–0.66
–0.64
ns
XC3S200AN
–0.85
–0.65
ns
XC3S400AN
–0.42
–0.42
ns
XC3S700AN
–0.81
–0.67
ns
XC3S1400AN
–0.71
–0.71
ns
XC3S50AN
–0.88
–0.88
ns
2
–1.33
–1.33
ns
3
–2.05
–2.05
ns
4
–2.43
–2.43
ns
5
–2.34
–2.34
ns
6
–2.81
–2.81
ns
7
–3.03
–3.03
ns
8
–3.83
–3.57
ns
–1.51
–1.51
ns
2
–2.09
–2.09
ns
3
–2.40
–2.40
ns
4
–2.68
–2.68
ns
5
–2.56
–2.56
ns
6
–2.99
–2.99
ns
7
–3.29
–3.29
ns
8
–3.61
–3.61
ns
1
1
Device
XC3S700AN
XC3S1400AN
Units
Hold Times
TIOICKP
TIOICKPD
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. No Input Delay is
programmed.
LVCMOS25(3)
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
LVCMOS25(3)
0
1
1
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28
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 23: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
TIOICKPD
Description
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
Conditions
LVCMOS25(3)
Speed Grade
IFD_
DELAY_
VALUE
-5
-4
Min
Min
–1.12
–1.12
ns
2
–1.70
–1.70
ns
3
–2.08
–2.08
ns
4
–2.38
–2.38
ns
5
–2.23
–2.23
ns
6
–2.69
–2.69
ns
7
–3.08
–3.08
ns
8
–3.35
–3.35
ns
–1.67
–1.67
ns
2
–2.27
–2.27
ns
3
–2.59
–2.59
ns
4
–2.92
–2.92
ns
5
–2.89
–2.89
ns
6
–3.22
–3.22
ns
7
–3.52
–3.52
ns
8
–3.81
–3.81
ns
–1.60
–1.60
ns
2
–2.06
–2.06
ns
3
–2.46
–2.46
ns
4
–2.86
–2.86
ns
5
–2.88
–2.88
ns
6
–3.24
–3.24
ns
7
–3.55
–3.55
ns
8
–3.89
–3.89
ns
1.33
1.61
ns
1
1
1
Device
XC3S400AN
XC3S700AN
XC3S1400AN
Units
Set/Reset Pulse Width
TRPW_IOB
Minimum pulse width to SR control
input on IOB
–
–
All
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 26.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 26. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 24: Sample Window (Source Synchronous)
Symbol
TSAMP
Description
Maximum
Units
Setup and hold capture
The input capture sample window value is highly specific to a particular application, device,
window of an IOB flip-flop. package, I/O standard, I/O placement, DCM usage, and clock buffer.
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29
Spartan-3AN FPGA Family: DC and Switching Characteristics
Input Propagation Times
Table 25: Propagation Times for the IOB Input Path
Speed
Grade
Symbol
Description
Conditions
DELAY_VALUE
Device
Units
-5
-4
Max
Max
1.04
1.12
ns
XC3S200AN
0.87
0.87
ns
XC3S400AN
0.65
0.72
ns
XC3S700AN
0.92
0.92
ns
XC3S1400AN
0.96
1.21
ns
XC3S50AN
1.79
2.07
ns
2
2.13
2.46
ns
3
2.36
2.71
ns
4
2.88
3.21
ns
5
3.11
3.46
ns
6
3.45
3.84
ns
7
3.75
4.19
ns
8
4.00
4.47
ns
9
3.61
4.11
ns
10
3.95
4.50
ns
11
4.18
4.67
ns
12
4.75
5.20
ns
13
4.98
5.44
ns
14
5.31
5.95
ns
15
5.62
6.28
ns
16
5.86
6.57
ns
1.57
1.65
ns
2
1.87
1.97
ns
3
2.16
2.33
ns
4
2.68
2.96
ns
5
2.87
3.19
ns
6
3.20
3.60
ns
7
3.57
4.02
ns
8
3.79
4.26
ns
9
3.42
3.86
ns
10
3.79
4.25
ns
11
4.02
4.55
ns
12
4.62
5.24
ns
13
4.86
5.53
ns
14
5.18
5.94
ns
Propagation Times
TIOPI
TIOPID
The time it takes for data to travel
from the Input pin to the I output
with no input delay programmed
The time it takes for data to travel
from the Input pin to the I output
with the input delay programmed
LVCMOS25(2)
IBUF_DELAY_VALUE=0 XC3S50AN
LVCMOS25(2)
1
1
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 25: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
TIOPID
Description
Conditions
The time it takes for data to travel
from the Input pin to the I output
with the input delay programmed
LVCMOS25(2)
DELAY_VALUE
-4
Max
Max
5.43
6.24
ns
5.75
6.59
ns
1.32
1.43
ns
2
1.67
1.83
ns
3
1.90
2.07
ns
4
2.33
2.52
ns
5
2.60
2.91
ns
6
2.94
3.20
ns
7
3.23
3.51
ns
8
3.50
3.85
ns
9
3.18
3.55
ns
10
3.53
3.95
ns
11
3.76
4.20
ns
12
4.26
4.67
ns
13
4.51
4.97
ns
14
4.85
5.32
ns
15
5.14
5.64
ns
16
5.40
5.95
ns
1.84
1.87
ns
2
2.20
2.27
ns
3
2.46
2.60
ns
4
2.93
3.15
ns
5
3.21
3.45
ns
6
3.54
3.80
ns
7
3.86
4.16
ns
8
4.13
4.48
ns
9
3.82
4.19
ns
10
4.17
4.58
ns
11
4.43
4.89
ns
12
4.95
5.49
ns
13
5.22
5.83
ns
14
5.57
6.21
ns
15
5.89
6.55
ns
16
6.16
6.89
ns
1.95
2.18
ns
2
2.29
2.59
ns
3
2.54
2.84
ns
4
2.96
3.30
ns
15
XC3S200AN
16
1
1
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XC3S400AN
XC3S700AN
XC3S1400AN
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 25: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
TIOPID
TIOPLI
Description
Conditions
The time it takes for data to travel
from the Input pin to the I output
with the input delay programmed
LVCMOS25(2)
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
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LVCMOS25(2)
DELAY_VALUE
Units
-5
-4
Max
Max
3.17
3.52
ns
6
3.52
3.92
ns
7
3.82
4.18
ns
8
4.10
4.57
ns
9
3.84
4.31
ns
10
4.20
4.79
ns
11
4.46
5.06
ns
12
4.87
5.51
ns
13
5.07
5.73
ns
14
5.43
6.08
ns
15
5.73
6.33
ns
16
6.01
6.77
ns
XC3S50AN
1.70
1.81
ns
XC3S200AN
1.85
2.04
ns
XC3S400AN
1.44
1.74
ns
XC3S700AN
1.48
1.74
ns
XC3S1400AN
1.50
1.97
ns
5
IFD_DELAY_VALUE=0
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 25: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
TIOPLID
Description
Conditions
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2)
DELAY_VALUE
-4
Max
Max
2.30
2.41
ns
2
3.24
3.35
ns
3
3.65
3.98
ns
4
4.18
4.55
ns
5
4.02
4.47
ns
6
4.86
5.32
ns
7
5.61
6.17
ns
8
6.11
6.75
ns
2.19
2.43
ns
2
2.86
3.16
ns
3
3.52
4.01
ns
4
4.02
4.60
ns
5
3.83
4.43
ns
6
4.70
5.46
ns
7
5.48
6.33
ns
8
5.99
6.94
ns
1.93
2.25
ns
2
2.57
2.90
ns
3
3.16
3.66
ns
4
3.63
4.19
ns
5
3.55
4.18
ns
6
4.34
5.03
ns
7
5.09
5.88
ns
8
5.58
6.42
ns
1.96
2.18
ns
2
2.76
3.06
ns
3
3.45
3.95
ns
4
3.97
4.54
ns
5
3.83
4.37
ns
6
4.74
5.42
ns
7
5.53
6.33
ns
8
6.06
6.96
ns
1
1
1
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XC3S200AN
XC3S400AN
XC3S700AN
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 25: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
TIOPLID
Description
Conditions
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2)
DELAY_VALUE
Device
Units
-5
-4
Max
Max
1.93
2.40
ns
2
2.69
3.15
ns
3
3.52
3.99
ns
4
3.89
4.55
ns
5
3.95
4.42
ns
6
4.53
5.32
ns
7
5.30
6.21
ns
8
5.83
6.80
ns
1
XC3S1400AN
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 26.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Input Timing Adjustments
Table 26: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
Units
-4
Table 26: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
-4
Units
Differential Standards
Single-Ended Standards
LVTTL
0.62
0.62
ns
LVDS_25
0.76
0.76
ns
LVCMOS33
0.54
0.54
ns
LVDS_33
0.79
0.79
ns
LVCMOS25
0
0
ns
BLVDS_25
0.79
0.79
ns
LVCMOS18
0.83
0.83
ns
MINI_LVDS_25
0.78
0.78
ns
LVCMOS15
0.60
0.60
ns
MINI_LVDS_33
0.79
0.79
ns
LVCMOS12
0.31
0.31
ns
LVPECL_25
0.78
0.78
ns
PCI33_3
0.41
0.41
ns
LVPECL_33
0.79
0.79
ns
PCI66_3
0.41
0.41
ns
RSDS_25
0.79
0.79
ns
HSTL_I
0.72
0.72
ns
RSDS_33
0.77
0.77
ns
HSTL_III
0.77
0.77
ns
TMDS_33
0.79
0.79
ns
HSTL_I_18
0.69
0.69
ns
PPDS_25
0.79
0.79
ns
HSTL_II_18
0.69
0.69
ns
PPDS_33
0.79
0.79
ns
HSTL_III_18
0.79
0.79
ns
DIFF_HSTL_I_18
0.74
0.74
ns
SSTL18_I
0.71
0.71
ns
DIFF_HSTL_II_18
0.72
0.72
ns
SSTL18_II
0.71
0.71
ns
DIFF_HSTL_III_18
1.05
1.05
ns
SSTL2_I
0.68
0.68
ns
DIFF_HSTL_I
0.72
0.72
ns
SSTL2_II
0.68
0.68
ns
DIFF_HSTL_III
1.05
1.05
ns
SSTL3_I
0.78
0.78
ns
DIFF_SSTL18_I
0.71
0.71
ns
SSTL3_II
0.78
0.78
ns
DIFF_SSTL18_II
0.71
0.71
ns
DIFF_SSTL2_I
0.74
0.74
ns
DIFF_SSTL2_II
0.75
0.75
ns
DIFF_SSTL3_I
1.06
1.06
ns
DIFF_SSTL3_II
1.06
1.06
ns
Notes:
1.
2.
DS557 (v4.3) January 9, 2019
Product Specification
The numbers in this table are tested using the methodology
presented in Table 30 and are based on the operating conditions
set forth in Table 10, Table 13, and Table 15.
These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Output Propagation Times
Table 27: Timing for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Max
Max
Units
Clock-to-Output Times
TIOCKP
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.87
3.13
ns
The time it takes for data to travel from LVCMOS25(2), 12 mA output
the IOB’s O input to the Output pin
drive, Fast slew rate
All
2.78
2.91
ns
All
3.63
3.89
ns
8.62
9.65
ns
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin
Propagation Times
TIOOP
Set/Reset Times
TIOSRP
TIOGSRQ
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 29.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Three-State Output Propagation Times
Table 28: Timing for the IOB Three-State Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Max
Max
Units
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK
LVCMOS25, 12 mA
input of the Three-state Flip-Flop (TFF) to when output drive, Fast slew
the Output pin enters the high-impedance state rate
All
0.63
0.76
ns
TIOCKON(2)
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
All
2.80
3.06
ns
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
9.47
10.36
ns
Time from asserting TFF’s SR input to when the LVCMOS25, 12 mA
Output pin enters a high-impedance state
output drive, Fast slew
rate
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
All
1.61
1.86
ns
All
3.57
3.82
ns
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
Set/Reset Times
TIOSRHZ
TIOSRON(2)
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
Table 10 and Table 13.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 29.
DS557 (v4.3) January 9, 2019
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Output Timing Adjustments
Table 29: Output Timing Adjustments for IOB (Cont’d)
Table 29: Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
Units
-4
LVCMOS33
Single-Ended Standards
LVTTL
Slow
Fast
QuietIO
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Slow
Add the
Adjustment Below
Speed Grade
Units
-5
-4
2 mA
5.58
5.58
ns
2 mA
5.58
5.58
ns
4 mA
3.17
3.17
ns
4 mA
3.16
3.16
ns
6 mA
3.17
3.17
ns
6 mA
3.17
3.17
ns
8 mA
2.09
2.09
ns
8 mA
2.09
2.09
ns
12 mA
1.24
1.24
ns
12 mA
1.62
1.62
ns
16 mA
1.15
1.15
ns
16 mA
1.24
1.24
ns
24 mA
2.55(3)
2.55(3)
ns
24 mA
2.74(3)
2.74(3)
ns
2 mA
3.02
3.02
ns
2 mA
3.03
3.03
ns
4 mA
1.71
1.71
ns
4 mA
1.71
1.71
ns
6 mA
1.72
1.72
ns
6 mA
1.71
1.71
ns
8 mA
0.53
0.53
ns
8 mA
0.53
0.53
ns
12 mA
0.59
0.59
ns
12 mA
0.53
0.53
ns
16 mA
0.59
0.59
ns
16 mA
0.59
0.59
ns
24 mA
0.51
0.51
ns
24 mA
0.60
0.60
ns
2 mA
27.67
27.67
ns
2 mA
27.67
27.67
ns
4 mA
27.67
27.67
ns
4 mA
27.67
27.67
ns
6 mA
27.67
27.67
ns
6 mA
27.67
27.67
ns
8 mA
16.71
16.71
ns
8 mA
16.71
16.71
ns
12 mA
16.29
16.29
ns
12 mA
16.67
16.67
ns
16 mA
16.18
16.18
ns
16 mA
16.22
16.22
ns
24 mA
12.11
12.11
ns
24 mA
12.11
12.11
ns
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QuietIO
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 29: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
LVCMOS25
Slow
Fast
QuietIO
Add the
Adjustment Below
Speed Grade
Units
-5
-4
2 mA
5.33
5.33
ns
4 mA
2.81
2.81
6 mA
2.82
8 mA
Table 29: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
Units
-5
-4
2 mA
4.48
4.48
ns
ns
4 mA
3.69
3.69
ns
2.82
ns
6 mA
2.91
2.91
ns
1.14
1.14
ns
8 mA
1.99
1.99
ns
12 mA
1.10
1.10
ns
12 mA
1.57
1.57
ns
16 mA
0.83
0.83
ns
16 mA
1.19
1.19
ns
24 mA
2.26(3)
2.26(3)
ns
2 mA
3.96
3.96
ns
2 mA
4.36
4.36
ns
4 mA
2.57
2.57
ns
4 mA
1.76
1.76
ns
6 mA
1.90
1.90
ns
6 mA
1.25
1.25
ns
8 mA
1.06
1.06
ns
8 mA
0.38
0.38
ns
12 mA
0.83
0.83
ns
12 mA
0
0
ns
16 mA
0.63
0.63
ns
16 mA
0.01
0.01
ns
2 mA
24.97
24.97
ns
24 mA
0.01
0.01
ns
4 mA
24.97
24.97
ns
2 mA
25.92
25.92
ns
6 mA
24.08
24.08
ns
4 mA
25.92
25.92
ns
8 mA
16.43
16.43
ns
6 mA
25.92
25.92
ns
12 mA
14.52
14.52
ns
8 mA
15.57
15.57
ns
16 mA
13.41
13.41
ns
12 mA
15.59
15.59
ns
2 mA
5.82
5.82
ns
16 mA
14.27
14.27
ns
4 mA
3.97
3.97
ns
24 mA
11.37
11.37
ns
6 mA
3.21
3.21
ns
8 mA
2.53
2.53
ns
12 mA
2.06
2.06
ns
2 mA
5.23
5.23
ns
4 mA
3.05
3.05
ns
6 mA
1.95
1.95
ns
8 mA
1.60
1.60
ns
12 mA
1.30
1.30
ns
2 mA
34.11
34.11
ns
4 mA
25.66
25.66
ns
6 mA
24.64
24.64
ns
8 mA
22.06
22.06
ns
12 mA
20.64
20.64
ns
LVCMOS18
Slow
Fast
QuietIO
LVCMOS15
Slow
Fast
QuietIO
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 29: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Table 29: Output Timing Adjustments for IOB (Cont’d)
Add the
Adjustment Below
Speed Grade
Convert Output Time from
LVCMOS25 with 12 mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Units
LVDS_25
1.16
1.16
ns
ns
LVDS_33
0.46
0.46
ns
6.77
ns
BLVDS_25
0.11
0.11
ns
5.02
5.02
ns
MINI_LVDS_25
0.75
0.75
ns
6 mA
4.09
4.09
ns
MINI_LVDS_33
0.40
0.40
ns
2 mA
50.76
50.76
ns
LVPECL_25
4 mA
43.17
43.17
ns
LVPECL_33
6 mA
37.31
37.31
ns
RSDS_25
1.42
1.42
ns
PCI33_3
0.34
0.34
ns
RSDS_33
0.58
0.58
ns
PCI66_3
0.34
0.34
ns
TMDS_33
0.46
0.46
ns
HSTL_I
0.78
0.78
ns
PPDS_25
1.07
1.07
ns
HSTL_III
1.16
1.16
ns
PPDS_33
0.63
0.63
ns
HSTL_I_18
0.35
0.35
ns
DIFF_HSTL_I_18
0.43
0.43
ns
HSTL_II_18
0.30
0.30
ns
DIFF_HSTL_II_18
0.41
0.41
ns
HSTL_III_18
0.47
0.47
ns
DIFF_HSTL_III_18
0.36
0.36
ns
SSTL18_I
0.40
0.40
ns
DIFF_HSTL_I
1.01
1.01
ns
SSTL18_II
0.30
0.30
ns
DIFF_HSTL_III
0.54
0.54
ns
SSTL2_I
0
0
ns
DIFF_SSTL18_I
0.49
0.49
ns
SSTL2_II
–0.05
–0.05
ns
DIFF_SSTL18_II
0.41
0.41
ns
SSTL3_I
0
0
ns
DIFF_SSTL2_I
0.82
0.82
ns
SSTL3_II
0.17
0.17
ns
DIFF_SSTL2_II
0.09
0.09
ns
DIFF_SSTL3_I
1.16
1.16
ns
DIFF_SSTL3_II
0.28
0.28
ns
Fast
QuietIO
2 mA
7.14
7.14
ns
Differential Standards
4 mA
4.87
4.87
ns
6 mA
5.67
5.67
2 mA
6.77
4 mA
Units
-4
Slow
-4
Speed Grade
-5
LVCMOS12
-5
Add the
Adjustment Below
Input Only
Notes:
1.
2.
3.
DS557 (v4.3) January 9, 2019
Product Specification
The numbers in this table are tested using the methodology
presented in Table 30 and are based on the operating conditions
set forth in Table 10, Table 13, and Table 15.
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Note that 16 mA drive is faster than 24 mA drive for the Slow slew
rate.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Timing Measurement Methodology
LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an
open connection, and VT is set to zero. The same
measurement point (VM) that was used at the Input is also
used at the Output.
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 30 lists the conditions to use for each
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (VM) is commonly located halfway between VL
and VH.
X-Ref Target - Figure 11
VT (VREF)
FPGA Output
RT (RREF)
VM (VMEAS)
CL (CREF)
The Output test setup is shown in Figure 11. A termination
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard,
RT and VT generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
DS312-3_04_102406
Notes:
1.
The names shown in parentheses are
used in the IBIS file.
Figure 11: Output Test Setup
Table 30: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Inputs and
Outputs
Outputs(2)
Inputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
LVTTL
–
0
3.3
1M
0
1.4
LVCMOS33
–
0
3.3
1M
0
1.65
LVCMOS25
–
0
2.5
1M
0
1.25
LVCMOS18
–
0
1.8
1M
0
0.9
LVCMOS15
–
0
1.5
1M
0
0.75
LVCMOS12
–
0
1.2
1M
0
0.6
–
Note 3
Note 3
25
0
0.94
25
3.3
2.03
–
Note 3
Note 3
25
0
0.94
25
3.3
2.03
HSTL_I
0.75
VREF – 0.5
VREF + 0.5
50
0.75
VREF
HSTL_III
0.9
VREF – 0.5
VREF + 0.5
50
1.5
VREF
HSTL_I_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
HSTL_II_18
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
SSTL18_I
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
SSTL2_I
1.25
VREF – 0.75
VREF + 0.75
50
1.25
VREF
SSTL2_II
1.25
VREF – 0.75
VREF + 0.75
25
1.25
VREF
SSTL3_I
1.5
VREF – 0.75
VREF + 0.75
50
1.5
VREF
SSTL3_II
1.5
VREF – 0.75
VREF + 0.75
25
1.5
VREF
Single-Ended
PCI33_3
Rising
Falling
PCI66_3
Rising
Falling
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 30: Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard
(IOSTANDARD)
Inputs and
Outputs
Outputs(2)
Inputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
LVDS_25
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVDS_33
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
BLVDS_25
–
VICM – 0.125
VICM + 0.125
1M
0
VICM
MINI_LVDS_25
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
MINI_LVDS_33
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVPECL_25
–
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
LVPECL_33
–
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
RSDS_25
–
VICM – 0.1
VICM + 0.1
50
1.2
VICM
RSDS_33
–
VICM – 0.1
VICM + 0.1
50
1.2
VICM
TMDS_33
–
VICM – 0.1
VICM + 0.1
50
3.3
VICM
PPDS_25
–
VICM – 0.1
VICM + 0.1
50
0.8
VICM
PPDS_33
–
VICM – 0.1
VICM + 0.1
50
0.8
VICM
DIFF_HSTL_I
–
VICM – 0.5
VICM + 0.5
50
0.75
VICM
DIFF_HSTL_III
–
VICM – 0.5
VICM + 0.5
50
1.5
VICM
DIFF_HSTL_I_18
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_II_18
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_III_18
–
VICM – 0.5
VICM + 0.5
50
1.8
VICM
DIFF_SSTL18_I
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL18_II
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL2_I
–
VICM – 0.5
VICM + 0.5
50
1.25
VICM
DIFF_SSTL2_II
–
VICM – 0.5
VICM + 0.5
50
1.25
VICM
DIFF_SSTL3_I
–
VICM – 0.5
VICM + 0.5
50
1.5
VICM
DIFF_SSTL3_II
–
VICM – 0.5
VICM + 0.5
50
1.5
VICM
Differential
Notes:
1.
2.
3.
Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
VT – Termination voltage
The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
According to the PCI specification. For information on PCI IP solutions, see
www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
The capacitive load (CL) is connected between the output
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
CL value of zero. High-impedance probes (less than 1 pF)
are used for all measurements. Any delay that the test
fixture might contribute to test measurements is subtracted
from those measurements to produce the final timing
numbers as published in the speed files and data sheet.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (VREF, RREF, and VMEAS) correspond directly
with the parameters used in Table 30 (VT, RT, and VM). Do
not confuse VREF (the termination voltage) from the IBIS
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
www.xilinx.com/support/download/index.htm
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 11.
Use parameter values VT, RT, and VM from Table 30.
CREF is zero.
2. Record the time to VM.
3. Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including VREF, RREF, CREF,
and VMEAS values) or capacitive value to represent the
load.
4. Record the time to VMEAS.
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 29) to
yield the worst-case delay of the PCB trace.
Simultaneously Switching Output
Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
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and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 31and Table 32 provide the essential SSO guidelines.
For each device/package combination, Table 31provides
the number of equivalent VCCO/GND pairs. The equivalent
number of pairs is based on characterization and may not
match the physical number of pairs. For each output signal
standard and drive strength, Table 32 recommends the
maximum number of SSOs, switching in the same direction,
allowed per VCCO/GND pair within an I/O bank. The
guidelines in Table 32 are categorized by package style,
slew rate, and output drive current. Furthermore, the
number of SSOs is specified by I/O bank. Generally, the left
and right I/O banks (Banks 1 and 3) support higher output
drive current.
Multiply the appropriate numbers from Table 31and
Table 32 to calculate the maximum number of SSOs
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table 31 x Table 32
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The number of SSOs allowed for quad-flat packages (TQ) is
lower than for ball grid array packages (FG) due to the
larger lead inductance of the quad-flat packages. Ball grid
array packages are recommended for applications with a
large number of simultaneously switching outputs.
Table 31: Equivalent VCCO/GND Pairs per Bank
Device
Package Style
TQG144 FTG256 FGG400 FGG484 FGG676
XC3S50AN
2
3
–
–
–
XC3S200AN
–
4
–
–
–
XC3S400AN
–
4
5
–
–
XC3S700AN
–
–
–
5
–
XC3S1400AN
–
–
–
6
9
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Package Type
Package Type
TQG144
Signal Standard
(IOSTANDARD)
Top,
Bottom
Left,
Right
FTG256,
FGG400,
FGG484,
FGG676
Top,
Bottom
TQG144
Signal Standard
(IOSTANDARD)
Top,
Bottom
Left,
Right
LVTTL
Slow
Fast
QuietIO
Left,
Right
Top,
Bottom
Left,
Right
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
LVCMOS33
Single-Ended Standards
FTG256,
FGG400,
FGG484,
FGG676
Slow
2
24
24
76
76
2
20
20
60
60
4
14
14
46
46
4
10
10
41
41
6
11
11
27
27
6
10
10
29
29
8
10
10
20
20
8
6
6
22
22
12
9
9
13
13
12
6
6
13
13
16
8
8
10
10
16
5
5
11
11
24
–
8
–
9
24
4
4
9
9
2
10
10
10
10
2
10
10
10
10
4
8
8
8
8
4
6
6
6
6
6
5
5
5
5
6
5
5
5
5
8
4
4
4
4
8
3
3
3
3
12
4
4
4
4
12
3
3
3
3
16
2
2
2
2
16
3
3
3
3
24
–
2
–
2
24
2
2
2
2
2
36
36
76
76
2
40
40
80
80
4
32
32
46
46
4
24
24
48
48
6
24
24
32
32
6
20
20
36
36
8
16
16
26
26
8
16
16
27
27
12
16
16
18
18
12
12
12
16
16
16
12
12
14
14
16
9
9
13
13
24
–
10
–
10
24
9
9
12
12
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Package Type
TQG144
Signal Standard
(IOSTANDARD)
Top,
Bottom
Left,
Right
Package Type
FTG256,
FGG400,
FGG484,
FGG676
Top,
Bottom
TQG144
Signal Standard
(IOSTANDARD)
Left,
Right
Top,
Bottom
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
LVCMOS25
Slow
Fast
QuietIO
2
16
16
76
76
4
10
10
46
6
8
8
8
7
12
FTG256,
FGG400,
FGG484,
FGG676
Left,
Right
Top,
Bottom
Left,
Right
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
LVCMOS18
Slow
2
13
13
64
64
46
4
8
8
34
34
33
33
6
8
8
22
22
7
24
24
8
7
7
18
18
6
6
18
18
12
–
5
–
13
16
–
6
–
11
16
–
5
–
10
24
–
5
–
7
2
13
13
18
18
2
12
12
18
18
4
8
8
9
9
4
10
10
14
14
6
7
7
7
7
6
8
8
6
6
8
4
4
4
4
8
6
6
6
6
12
–
4
–
4
12
3
3
3
3
16
–
3
–
3
16
–
3
–
3
2
30
30
64
64
24
–
2
–
2
4
24
24
64
64
2
36
36
76
76
6
20
20
48
48
4
30
30
60
60
8
16
16
36
36
6
24
24
48
48
12
–
12
–
36
8
20
20
36
36
16
–
12
–
24
12
12
12
36
36
2
12
12
55
55
16
–
12
–
36
4
7
7
31
31
24
–
8
–
8
6
7
7
18
18
8
–
6
–
15
12
–
5
–
10
2
10
10
25
25
4
7
7
10
10
6
6
6
6
6
8
–
4
–
4
12
–
3
–
3
2
30
30
70
70
4
21
21
40
40
6
18
18
31
31
8
–
12
–
31
12
–
12
–
20
Fast
QuietIO
LVCMOS15
Slow
Fast
QuietIO
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Package Type
FTG256,
FGG400,
FGG484,
FGG676
TQG144
Signal Standard
(IOSTANDARD)
Top,
Bottom
Package Type
Left,
Right
Top,
Bottom
Signal Standard
(IOSTANDARD)
Left,
Right
LVCMOS12
Slow
TQG144
Top,
Bottom
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
FTG256,
FGG400,
FGG484,
FGG676
Left,
Right
Top,
Bottom
Left,
Right
Banks 0,2 Banks 1,3 Banks 0,2 Banks 1,3
2
17
17
40
40
PPDS_33
8
–
27
–
4
–
13
–
25
DIFF_HSTL_I
–
5
–
10
6
–
10
–
18
DIFF_HSTL_III
–
3
–
4
2
12
9
31
31
DIFF_HSTL_I_18
6
6
8
8
4
–
9
–
13
DIFF_HSTL_II_18
–
2
–
2
6
–
9
–
9
DIFF_HSTL_III_18
4
4
5
4
2
36
36
55
55
DIFF_SSTL18_I
3
6
3
7
4
–
33
–
36
DIFF_SSTL18_II
–
4
–
4
6
–
27
–
36
DIFF_SSTL2_I
5
5
9
9
PCI33_3
9
9
16
16
DIFF_SSTL2_II
–
3
–
4
PCI66_3
–
9
–
13
DIFF_SSTL3_I
3
4
4
5
HSTL_I
–
11
–
20
DIFF_SSTL3_II
2
3
3
3
HSTL_III
–
7
–
8
Notes:
HSTL_I_18
13
13
17
17
HSTL_II_18
–
5
–
5
HSTL_III_18
8
8
10
8
SSTL18_I
7
13
7
15
SSTL18_II
–
9
–
9
SSTL2_I
10
10
18
18
SSTL2_II
–
6
–
9
SSTL3_I
7
8
8
10
SSTL3_II
5
6
6
7
Fast
QuietIO
1.
2.
3.
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS, RSDS,
PPDS, miniLVDS, and TMDS, are only supported in top or bottom
banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the VIL/VIH voltage
limits for the respective I/O standard.
If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
8
–
22
–
LVDS_33
8
–
27
–
BLVDS_25
1
1
4
4
MINI_LVDS_25
8
–
22
–
MINI_LVDS_33
8
–
27
–
LVPECL_25
Input Only
LVPECL_33
Input Only
RSDS_25
8
–
22
–
RSDS_33
8
–
27
–
TMDS_33
8
–
27
–
PPDS_25
8
–
22
–
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 33: CLB (SLICEM) Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
–
0.60
–
0.68
ns
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.18
–
0.36
–
ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
1.58
–
1.88
–
ns
TAH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
0
–
0
–
ns
TCKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
0
–
0
–
ns
Clock-to-Output Times
TCKO
Setup Times
Hold Times
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
0.63
–
0.75
–
ns
TCL
The Low pulse width of the CLK signal
0.63
–
0.75
–
ns
FTOG
Toggle frequency (for export control)
0
770
0
667
MHz
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
–
0.62
–
0.71
ns
1.33
–
1.61
–
ns
Propagation Times
TILO
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 34: CLB Distributed RAM Switching Characteristics
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
–
1.69
–
2.01
ns
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
Setup Times
TDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
–0.07
–
–0.02
–
ns
TAS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
0.18
–
0.36
–
ns
TWS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
0.30
–
0.59
–
ns
TDH
Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM
0.13
–
0.13
–
ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
0.01
–
0.01
–
ns
0.88
–
1.01
–
ns
Hold Times
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
Table 35: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
–
4.11
–
4.82
ns
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.13
–
0.18
–
ns
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
0.16
–
0.16
–
ns
0.90
–
1.01
–
ns
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on
the shift register output
Setup Times
TSRLDS
Hold Times
TSRLDH
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 36: Clock Distribution Switching Characteristics
Maximum
Description
Symbol
Minimum
Speed Grade
-5
-4
Units
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
TGIO
–
0.22
0.23
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
TGSI
–
0.56
0.63
ns
FBUFG
0
350
334
MHz
Frequency of signals distributed on global buffers (all sides)
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 37: 18 x 18 Embedded Multiplier Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
–
4.36
–
4.88
ns
Combinatorial Delay
TMULT
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
register(2)(3)
–
0.84
–
1.30
ns
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register(2)(4)
–
4.44
–
4.97
ns
TMSDCK_P
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
3.56
–
3.98
–
ns
TMSDCK_A
Data setup time at the A input before the active transition at the CLK
when using the AREG input register(4)
0.00
–
0.00
–
ns
TMSDCK_B
Data setup time at the B input before the active transition at the CLK
when using the BREG input register(4)
0.00
–
0.00
–
ns
TMSCKD_P
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
0.00
–
0.00
–
ns
TMSCKD_A
Data hold time at the A input after the active transition at the CLK
when using the AREG input register(4)
0.35
–
0.45
–
ns
TMSCKD_B
Data hold time at the B input after the active transition at the CLK
when using the BREG input register(4)
0.35
–
0.45
–
ns
0
280
0
250
MHz
Setup Times
Hold Times
Clock Frequency
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
register(5)
Notes:
1.
2.
3.
4.
5.
The numbers in this table are based on the operating conditions set forth in Table 10.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
The PREG register is typically used when inferring a single-stage multiplier.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Block RAM Timing
Table 38: Block RAM Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
–
2.06
–
2.49
ns
TRCCK_ADDR Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
0.32
–
0.36
–
ns
TRDCK_DIB
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
0.28
–
0.31
–
ns
TRCCK_ENB
Setup time for the EN input before the active transition at the
CLK input of the block RAM
0.69
–
0.77
–
ns
TRCCK_WEB
Setup time for the WE input before the active transition at the
CLK input of the block RAM
1.12
–
1.26
–
ns
TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the
CLK input
0
–
0
–
ns
TRCKD_DIB
Hold time on the DIN inputs after the active transition at the
CLK input
0
–
0
–
ns
TRCKC_ENB
Hold time on the EN input after the active transition at the CLK
input
0
–
0
–
ns
TRCKC_WEB
Hold time on the WE input after the active transition at the CLK
input
0
–
0
–
ns
Clock-to-Output Times
TRCKO
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
Setup Times
Hold Times
Clock Timing
TBPWH
High pulse width of the CLK signal
1.56
–
1.79
–
ns
TBPWL
Low pulse width of the CLK signal
1.56
–
1.79
–
ns
0
320
0
280
MHz
Clock Frequency
FBRAM
Block RAM clock frequency
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Aspects of DLL operation play a role in all DCM
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
DLL tables (Table 39 and Table 40) apply to any application
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
(Table 41 through Table 44) supersede any corresponding
ones in the DLL tables. DLL specifications that do not
change with the addition of DFS or PS functions are
presented in Table 39 and Table 40.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469:
Spread-Spectrum Clocking Reception for Displays for
details.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Delay-Locked Loop (DLL)
Table 39: Recommended Operating Conditions for the DLL
Speed Grade
Symbol
Description
-5
Min
-4
Max
Units
Min
Max
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency of the CLKIN clock input
5(2)
280(3)
5(2)
250(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN < 150 MHz
40%
60%
40%
60%
%
FCLKIN > 150 MHz
45%
55%
45%
55%
%
FCLKIN < 150 MHz
–
±300
–
±300
ps
FCLKIN > 150 MHz
–
±150
–
±150
ps
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
Cycle-to-cycle jitter at the
CLKIN input
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input
–
±1
–
±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay
from the DCM output to the CLKFB input
–
±1
–
±1
ns
Notes:
1.
2.
3.
4.
5.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 41.
The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to FBUFG. When set to TRUE,
CLKIN_DIVIDE_BY_2 divides the incoming clock frequency by two as it enters the DCM.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 40: Switching Characteristics for the DLL
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
5
280
5
250
MHz
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and CLK180 outputs
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and CLK270 outputs
5
200
5
200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
10
334
10
334
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output
0.3125
186
0.3125
166
MHz
–
±100
–
±100
ps
Output Clock
All
Jitter(2)(3)(4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output
All
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
–
±[0.5%
of
CLKIN
period
+ 100]
–
±[0.5%
of
CLKIN
period
+ 100]
ps
CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing
integer division
–
±150
–
±150
ps
CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing
non-integer division
–
±[0.5%
of
CLKIN
period
+ 100]
–
±[0.5%
of
CLKIN
period
+ 100]
ps
All
–
±[1% of
CLKIN
period
+ 350]
–
±[1% of
CLKIN
period
+ 350]
ps
All
–
±150
–
±150
ps
CLK0 to CLK2X
(not CLK2X180)
–
±[1% of
CLKIN
period
+ 100]
–
±[1% of
CLKIN
period
+ 100]
ps
All others
–
±[1% of
CLKIN
period
+ 150]
–
±[1% of
CLKIN
period
+ 150]
ps
–
5
–
5
ms
–
600
–
600
µs
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN and CLKFB inputs
CLKOUT_PHASE_DLL
Phase offset between DLL
outputs
Lock Time
LOCK_DLL(3)
When using the DLL alone:
The time from deassertion at
the DCM’s Reset input to the
rising transition at its LOCKED
output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 40: Switching Characteristics for the DLL (Cont’d)
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
15
35
15
35
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, average over all taps
All
ps
Notes:
1.
2.
3.
4.
5.
The numbers in this table are based on the operating conditions set forth in Table 10 and Table 39.
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps.
The typical delay step size is 23 ps.
Digital Frequency Synthesizer (DFS)
Table 41: Recommended Operating Conditions for the DFS
Speed Grade
Symbol
Input Frequency
FCLKIN
Description
-5
-4
Units
Min
Max
Min
Max
0.200
333(3)
0.200
333(3)
MHz
FCLKFX < 150 MHz
–
±300
–
±300
ps
FCLKFX > 150 MHz
–
±150
–
±150
ps
–
±1
–
±1
ns
Ranges(2)
CLKIN_FREQ_FX
Input Clock Jitter
Frequency for the CLKIN input
Tolerance(4)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
Notes:
1.
2.
3.
4.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 39.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 42: Switching Characteristics for the DFS
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX
Output Clock
Frequency for the CLKFX and CLKFX180 outputs
All
5
350
5
320
Period jitter at the CLKFX and
CLKFX180 outputs.
All
Typ
Max
Typ
Max
MHz
Jitter(2)(3)
CLKOUT_PER_JITT_FX
≤
CLKIN
20 MHz
CLKIN
> 20 MHz
Use the Spartan-3A Jitter
Calculator:
www.xilinx.com/support/documenta
tion/data_sheets/s3a_jitter_calc.zip
ps
±[1% of ±[1% of ±[1% of ±[1% of
CLKFX CLKFX CLKFX CLKFX
period period period period
+ 100] + 200] + 100] + 200]
ps
Duty Cycle(4)(5)
Duty cycle precision for the CLKFX and CLKFX180
outputs, including the BUFGMUX and clock tree
duty-cycle distortion
All
–
±[1% of
CLKFX
period
+ 350]
–
±[1% of
CLKFX
period
+ 350]
ps
Phase offset between the DFS CLKFX
output and the DLL CLK0 output when
both the DFS and DLL are used
All
–
±200
–
±200
ps
CLKOUT_PHASE_FX180 Phase offset between the DFS
CLKFX180 output and the DLL CLK0
output when both the DFS and DLL
are used
All
–
±[1% of
CLKFX
period
+ 200]
–
±[1% of
CLKFX
period
+ 200]
ps
All
–
5
–
5
ms
–
450
–
450
µs
CLKOUT_DUTY_CYCLE_FX
Phase Alignment(5)
CLKOUT_PHASE_FX
Lock Time
LOCK_FX(2)
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
valid. If using both the DLL and the
DFS, use the longer locking time.
5 MHz < FCLKIN
< 15 MHz
FCLKIN >
15 MHz
Notes:
1.
2.
3.
4.
5.
The numbers in this table are based on the operating conditions set forth in Table 10 and Table 41.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA.
Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching
activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Table 43: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
1
167
1
167
MHz
40%
60%
40%
60%
%
Operating Frequency Ranges
PSCLK_FREQ (FPSCLK) Frequency for the PSCLK input
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
Table 44: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shift Amount
Units
Phase Shifting Range
MAX_STEPS (2)(3)
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double
the clock effective clock period.
CLKIN < 60 MHz ±[INTEGER(10 • (TCLKIN – 3 ns))]
steps
CLKIN ≥ 60 MHz ±[INTEGER(15 • (TCLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
±[MAX_STEPS •
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase shifting
±[MAX_STEPS •
DCM_DELAY_STEP_MAX]
ns
Notes:
1.
2.
3.
The numbers in this table are based on the operating conditions set forth in Table 10 and Table 43.
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of Table 40.
Miscellaneous DCM Timing
Table 45: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–
CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
N/A
seconds
N/A
N/A
seconds
N/A
N/A
minutes
N/A
N/A
minutes
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
Notes:
1.
2.
3.
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex™-4 FPGA DCM_RESET specification. This specification does not apply for Spartan-3AN
FPGAs.
This specification is equivalent to the Virtex-4 FPGA TCONFIG specification. This specification does not apply for Spartan-3AN FPGAs.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
DNA Port Timing
Table 46: DNA_PORT Interface Timing
Symbol
Description
Min
Max
Units
TDNASSU
Setup time on SHIFT before the rising edge of CLK
1.0
–
ns
TDNASH
Hold time on SHIFT after the rising edge of CLK
0.5
–
ns
TDNADSU
Setup time on DIN before the rising edge of CLK
1.0
–
ns
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
–
ns
TDNARSU
Setup time on READ before the rising edge of CLK
5.0
10,000
ns
TDNARH
Hold time on READ after the rising edge of CLK
0
–
ns
0.5
1.5
ns
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
TDNACLKF
CLK frequency
0
100
MHz
TDNACLKH
CLK High time
1.0
∞
ns
TDNACLKL
CLK Low time
1.0
∞
ns
Notes:
1.
The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs.
Internal SPI Access Port Timing
Table 47: SPI_ACCESS Interface Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
TSPICCK_MOSI
Setup time on MOSI before the active edge of CLK
4.47
–
5.0
–
ns
TSPICKC_MOSI
Hold time on MOSI after the active edge of CLK
4.03
–
4.5
–
ns
50
–
50
–
ns
TCSB
CSB High time
TSPICCK_CSB
Setup time on CSB before the active edge of CLK
7.15
–
8.0
–
ns
TSPICCK_CSB
Hold time on CSB after the active edge of CLK
7.15
–
8.0
–
ns
TSPICKO_MISO
Clock-to-output delay on MISO after active edge of CLK
–
14.3
–
16.0
ns
FSPICLK
CLK frequency
–
50
–
50
MHz
FSPICAR1
CLK frequency for Continuous Array Read command
–
50
–
50
MHz
FSPICAR1
CLK frequency for Continuous Array Read command,
reduced initial latency
–
33
–
33
MHz
TSPICLKL
CLK High time
–
∞
–
∞
ns
TSPICLKH
CLK Low time
6.8
∞
6.8
∞
ns
Notes:
1.
For details on using SPI_ACCESS and the In-System Flash memory, see UG333 Spartan-3AN FPGA In-System Flash User Guide.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
In-System Flash (ISF) Memory Timing
Table 48: In-System Flash (ISF) Memory Operations
Symbol
Description
Device
Typical(1)
Max
Units
TXFER
Page to Buffer transfer time
All
–
400
µs
TCOMP
Page to Buffer compare time
All
–
400
µs
XC3S50AN
XC3S200AN
XC3S400AN
2
4
ms
XC3S700AN
XC3S1400AN
3
6
ms
XC3S50AN
XC3S200AN
XC3S400AN
13
32
ms
XC3S700AN(2)
XC3S1400AN
15
35
ms
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN(3)
14
35
ms
XC3S1400AN
17
40
ms
XC3S50AN
15
35
ms
XC3S200AN
XC3S400AN
30
75
ms
XC3S700AN
XC3S1400AN
45
100
ms
XC3S50AN
0.8
2.5
s
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
1.6
5
s
TPP
TPE
TPEP
TBE
TSE
Page Programming time
Page Erase time
Page Erase and Programming time
Block Erase time
Sector Erase time
Notes:
1.
2.
3.
Typical values can vary with process and other conditions.
XC3S700AN TPE maximum is 50 ms for Flash devices manufactured using the UMC process. For more information, see the Xilinx customer
notice XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN FPGA Devices.
XC3S700AN TPEP maximum is 55 ms for Flash devices manufactured using the UMC process. For more information, see the Xilinx
customer notice XCN14003: Flash Wafer Fabrication Change and Gold (Au) To Copper (Cu) Transition for Spartan-3AN FPGA
Devices.
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Suspend Mode Timing
X-Ref Target - Figure 12
Entering Suspend Mode
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
SUSPEND Input
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
AWAKE Output
tAWAKE_GWE
tSUSPEND_GWE
Flip-Flops, Block RAM,
Distributed RAM
Write Protected
tAWAKE_GTS
tSUSPEND_GTS
Defined by SUSPEND constraint
FPGA Outputs
tSUSPEND_DISABLE
FPGA Inputs,
Interconnect
tSUSPEND_ENABLE
Blocked
DS610-3_08_061207
Figure 12: Suspend Mode Timing
Table 49: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max Units
–
7
–
ns
+160
+300
+600
ns
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled
(suspend_filter:Yes)
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–
10
–
ns
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–
