0
Spartan-3A FPGA Family:
Data Sheet
DS529 December 18, 2018
0
0
Product Specification
Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018
DS529 (v2.1) December 18, 2018
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Introduction
Features
Architectural and Configuration Overview
General I/O Capabilities
Production Status
Supported Packages and Package Marking
Ordering Information
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Module 2:
Spartan-3A FPGA Family: Functional
Description
DS529 (v2.1) December 18, 2018
DC Electrical Characteristics
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Absolute Maximum Ratings
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Supply Voltage Specifications
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Recommended Operating Conditions
Switching Characteristics
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I/O Timing
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Configurable Logic Block (CLB) Timing
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Multiplier Timing
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Block RAM Timing
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Digital Clock Manager (DCM) Timing
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Suspend Mode Timing
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Device DNA Timing
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Configuration and JTAG Timing
The functionality of the Spartan®-3A FPGA family is
described in the following documents.
Module 4:
Pinout Descriptions
•
DS529 (v2.1) December 18, 2018
•
•
UG331: Spartan-3 Generation FPGA User Guide
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Clocking Resources
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Digital Clock Managers (DCMs)
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Block RAM
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Configurable Logic Blocks (CLBs)
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
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I/O Resources
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Embedded Multiplier Blocks
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Programmable Interconnect
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ISE® Design Tools and IP Cores
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Embedded Processing and Control Solutions
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Pin Types and Package Overview
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Package Drawings
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Powering FPGAs
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Power Management
UG332: Spartan-3 Generation Configuration User Guide
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Configuration Overview
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Configuration Pins and Behavior
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Bitstream Sizes
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Detailed Descriptions by Mode
Master Serial Mode using Platform Flash PROM
Master SPI Mode using Commodity Serial Flash
Master BPI Mode using Commodity Parallel Flash
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
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ISE iMPACT Programming Examples
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MultiBoot Reconfiguration
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Design Authentication using Device DNA
UG334: Spartan-3A/3AN FPGA Starter Kit User Guide
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•
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Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
For more information on the Spartan-3A FPGA family, go to
www.xilinx.com/spartan3a
Spartan-3A FPGA
Status
XC3S50A
Production
XC3S200A
Production
XC3S400A
Production
XC3S700A
Production
XC3S1400A
Production
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529 December 18, 2018
Product Specification
www.xilinx.com
1
Spartan-3A FPGA Family: Data Sheet
2
www.xilinx.com
DS529 December 18, 2018
Product Specification
8
Spartan-3A FPGA Family:
Introduction and Ordering Information
DS529 (v2.1) December 18, 2018
Product Specification
Introduction
The Spartan®-3A family of Field-Programmable Gate
Arrays (FPGAs) solves the design challenges in most
high-volume, cost-sensitive, I/O-intensive electronic
applications. The five-member family offers densities ranging
from 50,000 to 1.4 million system gates, as shown in Table 1.
The Spartan-3A FPGAs are part of the Extended
Spartan-3A family, which also include the non-volatile
Spartan-3AN and the higher density Spartan-3A DSP
FPGAs. The Spartan-3A family builds on the success of the
earlier Spartan-3E and Spartan-3 FPGA families. New
features improve system performance and reduce the cost
of configuration. These Spartan-3A family enhancements,
combined with proven 90 nm process technology, deliver
more functionality and bandwidth per dollar than ever before,
setting the new standard in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3A FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home networking,
display/projection, and digital television equipment.
The Spartan-3A family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost,
lengthy development cycles, and the inherent inflexibility of
conventional ASICs, and permit field design upgrades.
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Very low cost, high-performance logic solution for
high-volume, cost-conscious applications
Dual-range VCCAUX supply simplifies 3.3V-only design
Suspend, Hibernate modes reduce system power
Multi-voltage, multi-standard SelectIO™ interface pins
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Up to 502 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot swap compliance
•
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Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 BPI parallel NOR Flash PROM
Low-cost Xilinx® Platform Flash with JTAG
Unique Device DNA identifier for design authentication
Load multiple bitstreams under FPGA control
Post-configuration CRC checking
Complete Xilinx ISE® and WebPACK™ development
system software support plus Spartan-3A Starter Kit
MicroBlaze™ and PicoBlaze embedded processors
Low-cost QFP and BGA packaging, Pb-free options
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Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
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Up to 576 Kbits of fast block RAM with byte write enables
for processor applications
Up to 176 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
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Densities up to 25,344 logic cells, including optional shift
register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
•
Features
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Abundant, flexible logic resources
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640+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O
with integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 400 Mb/s
Fully compliant 32-/64-bit, 33/66 MHz PCI® technology
support
Common footprints support easy density migration
Compatible with select Spartan-3AN nonvolatile FPGAs
Compatible with higher density Spartan-3A DSP FPGAs
XA Automotive version available
Table 1: Summary of Spartan-3A FPGA Attributes
CLB Array
(One CLB = Four Slices)
Device
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
System Equivalent
Gates Logic Cells Rows Columns
CLBs
Slices
50K
200K
400K
700K
1400K
176
448
896
1,472
2,816
704
1,792
3,584
5,888
11,264
1,584
4,032
8,064
13,248
25,344
16
32
40
48
72
12
16
24
32
40
Distributed
RAM bits(1)
Block
RAM
bits(1)
11K
28K
56K
92K
176K
54K
288K
360K
360K
576K
Maximum
Dedicated
Maximum Differential
Multipliers DCMs User I/O
I/O Pairs
3
16
20
20
32
2
4
4
8
8
144
248
311
372
502
64
112
142
165
227
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529 (v2.1) December 18, 2018
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3
Introduction and Ordering Information
Architectural Overview
•
The Spartan-3A family architecture consists of five
fundamental programmable functional elements:
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Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus 3-state
operation. Supports a variety of signal standards,
including several high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in Figure 1. A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50A, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50A has DCMs only at the
top, while the XC3S700A and XC3S1400A add two DCMs in
the middle of the two columns of block RAM and multipliers.
The Spartan-3A family features a rich network of routing that
interconnect all five functional elements, transmitting signals
among them. Each functional element has an associated
switch matrix that permits multiple connections to the
routing.
IOBs
Multiplier
DCM
Block RAM
CLB
IOBs
OBs
IOBs
IOBs
CLBs
DCM
Block RAM / Multiplier
DCM
IOBs
DS312-1_01_032606
Notes:
1.
The XC3S700A and XC3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50A has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1: Spartan-3A FPGA Architecture
4
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DS529 (v2.1) December 18, 2018
Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3A FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
The Spartan-3A FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional
input-only pins as indicated in Table 2.
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Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
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•
•
Furthermore, Spartan-3A FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Spartan-3A FPGAs support the following single-ended
standards:
•
•
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
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Spartan-3A FPGAs support the following differential
standards:
•
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
•
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•
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Additionally, each Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Package
VQ100
VQG100
Body Size
(mm)
TQ144
TQG144
14 x 14(2)
20 x 20(2)
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
FG676
FGG676
17 x 17
19 x 19
21 x 21
23 x 23
27 x 27
Device
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
XC3S50A
68
(13)
60
(24)
108
(7)
50
(24)
144
(32)
64
(32)
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-
-
-
-
-
-
XC3S200A
68
(13)
60
(24)
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-
195
(35)
90
(50)
248
(56)
112
(64)
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-
-
-
-
-
XC3S400A
-
-
-
-
195
(35)
90
(50)
251
(59)
112
(64)
311
(63)
142
(78)
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-
-
-
XC3S700A
-
-
-
-
161
(13)
74
(36)
-
-
311
(63)
142
(78)
372
(84)
165
(93)
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-
XC3S1400A
-
-
-
-
161
(13)
74
(36)
-
-
-
-
375
(87)
165
(93)
502
(94)
227
(131)
Notes:
1.
2.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
The footprints for the VQ/TQ packages are larger than the package body. See the Package Drawings for details.
DS529 (v2.1) December 18, 2018
www.xilinx.com
5
Introduction and Ordering Information
Production Status
Table 3 indicates the production status of each Spartan-3A
FPGA by temperature range and speed grade. The table
also lists the earliest speed file version required for creating
a production configuration bitstream. Later versions are also
supported.
Table 3: Spartan-3A FPGA Production Status (Production Speed File)
Temperature Range
Commercial (C)
Part Number
Speed Grade
Industrial
Standard (–4)
High-Performance (–5)
Standard (–4)
XC3S50A
Production
(v1.35)
Production
(v1.35)
Production
(v1.35)
XC3S200A
Production
(v1.35)
Production
(v1.35)
Production
(v1.35)
XC3S400A
Production
(v1.36)
Production
(v1.36)
Production
(v1.36)
XC3S700A
Production
(v1.34)
Production
(v1.35)
Production
(v1.34)
XC3S1400A
Production
(v1.34)
Production
(v1.35)
Production
(v1.34)
Package Marking
The “5C” and “4I” Speed Grade/Temperature Range part
combinations may be dual marked as “5C/4I”. Devices with
a single mark are only guaranteed for the marked speed
grade and temperature range.
Figure 2 provides a top marking example for Spartan-3A
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3A FPGAs in BGA packages. The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator.
Mask Revision Code
Fabrication Code
R
SPARTAN
R
Process Technology
TM
Device Type
Package
XC3S50A
TQ144AGQ0625
D1234567A
Date Code
Speed Grade
4C
Lot Code
Temperature Range
Pin P1
DS529-1_03_080406
Figure 2: Spartan-3A QFP Package Marking Example
Mask Revision Code
BGA Ball A1
R
SPARTAN
Device Type
Package
R
XC3S50ATM
FT256 AGQ0625
D1234567A
4C
Fabrication Code
Process Code
Date Code
Lot Code
Speed Grade
Temperature Range
DS529-1_02_021206
Figure 3: Spartan-3A BGA Package Marking Example
6
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DS529 (v2.1) December 18, 2018
Introduction and Ordering Information
Ordering Information
Spartan-3A FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a ‘G’ character in the ordering code.
Example:
XC3S50A -4 FT 256 C
Device Type
Temperature Range
Speed Grade
Package Type/Number of Pins
DS529-1_05_011309
Device
Package Type / Number of Pins(1)
Speed Grade
Temperature Range ( TJ )
XC3S50A
–4 Standard Performance VQ100/
VQG100
100-pin Very Thin Quad Flat Pack (VQFP)
C Commercial (0°C to 85°C)
XC3S200A
–5 High Performance
(Commercial only)
TQ144/
TQG144
144-pin Thin Quad Flat Pack (TQFP)
I Industrial (–40°C to 100°C)
XC3S400A
FT256/
FTG256
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
XC3S700A
FG320/
FGG320
320-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S1400A
FG400/
FGG400
400-ball Fine-Pitch Ball Grid Array (FBGA)
FG484/
FGG484
484-ball Fine-Pitch Ball Grid Array (FBGA)
FG676
FGG676
676-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1.
2.
See Table 2 for specific device/package combinations.
See DS681 for the XA Automotive Spartan-3A FPGAs.
Revision History
The following table shows the revision history for this document.
Date
Version
12/05/06
1.0
Initial release.
02/02/07
1.1
Promoted to Preliminary status. Updated maximum differential I/O count for XC3S50A in Table 1.
Updated differential input-only pin counts in Table 2.
03/16/07
1.2
Minor formatting updates.
04/23/07
1.3
Added "Production Status" section.
05/08/07
1.4
Updated XC3S400A to Production.
07/10/07
1.4.1
04/15/08
1.6
Added VQ100 for XC3S50A and XC3S200A and extended FT256 to XC3S700A and XC3S1400A
Added reference to SCD 4103 for 750 Mbps performance.
05/28/08
1.7
Added reference to XA Automotive version.
03/06/09
1.8
Simplified Ordering Information. Added references to Extended Spartan-3A Family.
Removed reference to SCD 4103.
08/19/10
2.0
Updated Table 2 to clarify TQ/VQ size.
12/18/2018
2.1
Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
DS529 (v2.1) December 18, 2018
Revision
Minor updates.
www.xilinx.com
7
Introduction and Ordering Information
8
www.xilinx.com
DS529 (v2.1) December 18, 2018
10
Spartan-3A FPGA Family:
Functional Description
DS529 (v2.1) December 18, 2018
Product Specification
0
Spartan-3A FPGA Design Documentation
•
The functionality of the Spartan®-3A FPGA Family is
described in the following documents. The topics covered in
each guide is listed below.
•
DS706: Extended Spartan-3A Family Overview
www.xilinx.com/support/documentation/
data_sheets/ds706.pdf
•
UG331: Spartan-3 Generation FPGA User Guide
www.xilinx.com/support/documentation/
user_guides/ug331.pdf
•
•
Clocking Resources
•
Digital Clock Managers (DCMs)
•
Block RAM
•
Configurable Logic Blocks (CLBs)
-
Distributed RAM
-
SRL16 Shift Registers
-
Carry and Arithmetic Logic
Detailed Descriptions by Mode
-
Master Serial Mode using Xilinx® Platform
Flash PROM
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Master SPI Mode using Commodity SPI Serial
Flash PROM
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Master BPI Mode using Commodity Parallel
NOR Flash PROM
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Slave Parallel (SelectMAP) using a Processor
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Slave Serial using a Processor
-
JTAG Mode
•
ISE iMPACT Programming Examples
•
MultiBoot Reconfiguration
•
Design Authentication using Device DNA
For application examples, see the Spartan-3A FPGA
application notes.
•
Spartan-3A FPGA Application Notes
www.xilinx.com/support/documentation/
spartan-3a_application_notes.htm
•
I/O Resources
•
Embedded Multiplier Blocks
•
Programmable Interconnect
•
ISE® Software Design Tools
•
IP Cores
For specific hardware examples, please see the Spartan-3A
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
•
Embedded Processing and Control Solutions
•
•
Pin Types and Package Overview
Spartan-3A/3AN FPGA Starter Kit Board Page
www.xilinx.com/s3astarter
•
Package Drawings
•
•
Powering FPGAs
•
Power Management
UG334: Spartan-3A/3AN FPGA Starter Kit User
Guide
www.xilinx.com/support/documentation/
boards_and_kits/ug334.pdf
UG332: Spartan-3 Generation Configuration User
Guide
www.xilinx.com/support/documentation/
user_guides/ug332.pdf
•
For information on the XA Automotive version of the
Spartan-3A family, see the following data sheet.
•
Configuration Overview
-
Configuration Pins and Behavior
-
Bitstream Sizes
XA Spartan-3A Automotive FPGA Family Data Sheet
www.xilinx.com/support/documentation/data_sheets/
ds681.pdf
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
•
Sign Up for Alerts
www.xilinx.com/support/answers/18683.htm
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529 (v2.1) December 18, 2018
www.xilinx.com
9
Spartan-3A FPGA Family: Functional Description
Related Product Families
The Spartan-3AN nonvolatile FPGA family is architecturally
identical to the Spartan-3A FPGA family, except that it has
in-system flash memory and is offered in select
pin-compatible package options.
•
DS557: Spartan-3AN Family Data Sheet
www.xilinx.com/support/documentation/
data_sheets/ds557.pdf
The compatible Spartan-3A DSP FPGA family replaces the
18-bit multiplier with the DSP48A block, while also
increasing the block RAM capability and quantity. The two
members of the Spartan-3A DSP FPGA family extend the
Spartan-3A density range up to 37,440 and 53,712 logic
cells.
•
DS610: Spartan-3A DSP FPGA Family Data Sheet
www.xilinx.com/support/documentation/
data_sheets/ds610.pdf
•
UG431: XtremeDSP DSP48A for Spartan-3A DSP
FPGAs
www.xilinx.com/support/documentation/
user_guides/ug431.pdf
Revision History
The following table shows the revision history for this document.
Date
Version
12/05/06
1.0
Initial release.
02/02/07
1.1
Promoted to Preliminary status.
03/16/07
1.2
Added cross-reference to nonvolatile Spartan-3AN FPGA family.
04/23/07
1.3
Added cross-reference to compatible Spartan-3A DSP family.
07/10/07
1.4
Updated Starter Kit reference to new UG334.
04/15/08
1.6
Updated trademarks.
05/28/08
1.7
Added reference to XA Automotive version.
03/06/09
1.8
Added link to DS706 on Extended Spartan-3A family.
08/19/10
2.0
Updated link to sign up for Alerts.
12/18/18
10
Revision
Updated for Lead-Frame Plating Composition Change For Legacy Eutectic Products (XCN18024).
www.xilinx.com
DS529 (v2.1) December 18, 2018
64
Spartan-3A FPGA Family:
DC and Switching Characteristics
DS529 (v2.1) December 18, 2018
Product Specification
0
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan®-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Absolute Maximum Ratings
Stresses beyond those listed under Table 4: Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
Table 4: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Max
Units
VCCINT
Internal supply voltage
–0.5
1.32
V
VCCAUX
Auxiliary supply voltage
–0.5
3.75
V
VCCO
Output driver supply voltage
–0.5
3.75
V
VREF
Input reference voltage
–0.5
VCCO + 0.5
V
–0.95
4.6
V
–0.5
4.6
V
–
±100
mA
Human body model
–
±2000
V
Charged device model
–
±500
V
Machine model
–
±200
V
VIN
Voltage applied to all User I/O pins and
dual-purpose pins
Driver in a high-impedance state
Voltage applied to all Dedicated pins
IIK
VESD
Input clamp current per I/O pin
Electrostatic Discharge Voltage
–0.5V < VIN < (VCCO +
0.5V) (1)
TJ
Junction temperature
–
125
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1.
2.
Upper clamp applies only when using PCI IOSTANDARDs.
For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
© Copyright 2006–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529 (v2.1) December 18, 2018
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11
DC and Switching Characteristics
Power Supply Specifications
Table 5: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
1.0
2.0
V
VCCO2T
Threshold for the VCCO Bank 2 supply
1.0
2.0
V
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply VCCINT last for lowest overall power consumption (see UG331 chapter “Powering Spartan-3 Generation FPGAs” for more
information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 6: Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
VCCINTR
Ramp rate from GND to valid VCCINT supply level
0.2
100
ms
VCCAUXR
Ramp rate from GND to valid VCCAUX supply level
0.2
100
ms
VCCO2R
Ramp rate from GND to valid VCCO Bank 2 supply level
0.2
100
ms
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply VCCINT last for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more
information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM
Data
Symbol
12
Description
Min
Units
VDRINT
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
1.0
V
VDRAUX
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
2.0
V
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
General Recommended Operating Conditions
Table 8: General Recommended Operating Conditions
Symbol
TJ
Description
Junction temperature
Commercial
Industrial
Min
Nominal
Max
Units
0
–40
–
85
°C
–
100
°C
VCCINT
Internal supply voltage
1.14
1.20
1.26
V
VCCO (1)
Output driver supply voltage
1.10
–
3.60
V
VCCAUX
Auxiliary supply voltage(2)
VCCAUX = 2.5
2.25
2.50
2.75
V
VCCAUX = 3.3
3.00
3.30
3.60
V
PCI IOSTANDARD
–0.5
–
VCCO+0.5
V
IP or IO_#
All other
IOSTANDARDs IO_Lxxy_# (4)
–0.5
–
4.10
V
–0.5
–
4.10
V
–
–
500
ns
VIN
TIN
Input
voltage(3)
Input signal transition time(5)
Notes:
1.
2.
3.
4.
5.
This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards.
Define VCCAUX selection using CONFIG VCCAUX constraint.
See XAPP459, “Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.”
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide .
Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.
DS529 (v2.1) December 18, 2018
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13
DC and Switching Characteristics
General DC Characteristics for I/O Pins
Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (1)
Symbol
IL
(2)
IHS
Description
Test Conditions
Min
Typ
Max
Units
Leakage current at User I/O,
input-only, dual-purpose, and
dedicated pins, FPGA powered
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10
–
+10
µA
Leakage current on pins during
hot socketing, FPGA unpowered
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
–10
–
+10
µA
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
IRPU(3)
RPU(3)
IRPD
(3)
RPD(3)
Current through pull-up resistor
at User I/O, dual-purpose,
input-only, and dedicated pins.
Dedicated pins are powered by
VCCAUX.
Equivalent pull-up resistor value
at User I/O, dual-purpose,
input-only, and dedicated pins
(based on IRPU per Note 3)
VIN = GND
VCCO or VCCAUX =
3.0V to 3.6V
–151
–315
–710
µA
VCCO or VCCAUX =
2.3V to 2.7V
–82
–182
–437
µA
VCCO = 1.7V to 1.9V
–36
–88
–226
µA
VCCO = 1.4V to 1.6V
–22
–56
–148
µA
VCCO = 1.14V to 1.26V
–11
–31
–83
µA
VCCO = 3.0V to 3.6V
5.1
11.4
23.9
kΩ
VCCO = 2.3V to 2.7V
6.2
14.8
33.1
kΩ
VCCO = 1.7V to 1.9V
8.4
21.6
52.6
kΩ
VCCO = 1.4V to 1.6V
10.8
28.4
74.0
kΩ
VCCO = 1.14V to 1.26V
15.3
41.1
119.4
kΩ
VCCAUX = 3.0V to 3.6V
167
346
659
µA
100
225
457
µA
VIN = 3.0V to 3.6V
5.5
10.4
20.8
kΩ
VIN = 2.3V to 2.7V
4.1
7.8
15.7
kΩ
VIN = 1.7V to 1.9V
3.0
5.7
11.1
kΩ
VIN = 1.4V to 1.6V
2.7
5.1
9.6
kΩ
VIN = 1.14V to 1.26V
2.4
4.5
8.1
kΩ
VIN = 3.0V to 3.6V
7.9
16.0
35.0
kΩ
VIN = 2.3V to 2.7V
5.9
12.0
26.3
kΩ
VIN = 1.7V to 1.9V
4.2
8.5
18.6
kΩ
VIN = 1.4V to 1.6V
3.6
7.2
15.7
kΩ
VIN = GND
Current through pull-down
resistor at User I/O,
dual-purpose, input-only, and
dedicated pins. Dedicated pins
are powered by VCCAUX.
VIN = VCCO
Equivalent pull-down resistor
value at User I/O, dual-purpose,
input-only, and dedicated pins
(based on IRPD per Note 3)
VCCAUX = 3.0V to 3.6V
VCCAUX = 2.25V to 2.75V
VCCAUX = 2.25V to 2.75V
VIN = 1.14V to 1.26V
IREF
VREF current per pin
CIN
Input capacitance
RDT
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
µA
Add IHS + IRPU
3.0
6.0
12.5
kΩ
All VCCO levels
–10
–
+10
µA
–
–
–
10
pF
VCCO = 3.3V ± 10%
LVDS_33,
MINI_LVDS_33,
RSDS_33
90
100
115
Ω
VCCO = 2.5V ± 10%
LVDS_25,
MINI_LVDS_25,
RSDS_25
90
110
–
Ω
Notes:
1.
2.
3.
14
The numbers in this table are based on the conditions set forth in Table 8.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See "Parasitic Leakage" in UG331, Spartan-3 Generation FPGA User Guide .
This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Quiescent Current Requirements
Table 10: Quiescent Supply Current Characteristics
Symbol
ICCINTQ
ICCOQ
ICCAUXQ
Description
Quiescent VCCINT supply current
Quiescent VCCO supply current
Quiescent VCCAUX supply current
Typical(2)
Commercial
Maximum(2)
Industrial
Maximum(2)
Units
XC3S50A
2
20
30
mA
XC3S200A
7
50
70
mA
XC3S400A
10
85
125
mA
XC3S700A
13
120
185
mA
XC3S1400A
24
220
310
mA
XC3S50A
0.2
2
3
mA
XC3S200A
0.2
2
3
mA
XC3S400A
0.3
3
4
mA
XC3S700A
0.3
3
4
mA
XC3S1400A
0.3
3
4
mA
XC3S50A
3
8
10
mA
XC3S200A
5
12
15
mA
XC3S400A
5
18
24
mA
XC3S700A
6
28
34
mA
XC3S1400A
10
50
58
mA
Device
Notes:
1.
2.
3.
4.
5.
The numbers in this table are based on the conditions set forth in Table 8.
Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX
= 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage
limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design
with no functional elements instantiated). For conditions other than those described above (for example, a design including functional
elements), measured quiescent current levels will be different than the values in the table.
For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power
consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3A FPGA XPower Estimator provides quick, approximate,
typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as
well as more accurate typical estimates.
The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
DS529 (v2.1) December 18, 2018
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15
DC and Switching Characteristics
Single-Ended I/O Standards
Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
VCCO for Drivers(2)
VREF
Min (V)
Nom (V)
Max (V)
VIL
VIH
Max (V)
Min (V)
Min (V)
Nom (V)
Max (V)
LVTTL
3.0
3.3
3.6
0.8
2.0
LVCMOS33(4)
3.0
3.3
3.6
0.8
2.0
LVCMOS25(4,5)
2.3
2.5
2.7
0.7
1.7
LVCMOS18
1.65
1.8
1.95
0.4
0.8
LVCMOS15
1.4
1.5
1.6
0.4
0.8
LVCMOS12
1.1
1.2
1.3
0.4
0.7
PCI33_3(6)
3.0
3.3
3.6
0.3 • VCCO
0.5 • VCCO
PCI66_3(6)
3.0
3.3
3.6
0.3 • VCCO
0.5 • VCCO
HSTL_I
1.4
1.5
1.6
0.68
0.75
0.9
VREF – 0.1
VREF + 0.1
HSTL_III
1.4
1.5
1.6
–
0.9
-
VREF – 0.1
VREF + 0.1
HSTL_I_18
1.7
1.8
1.9
0.8
0.9
1.1
VREF – 0.1
VREF + 0.1
HSTL_II_18
1.7
1.8
1.9
–
0.9
–
VREF – 0.1
VREF + 0.1
HSTL_III_18
1.7
1.8
1.9
–
1.1
–
VREF – 0.1
VREF + 0.1
SSTL18_I
1.7
1.8
1.9
0.833
0.900
0.969
VREF – 0.125
VREF + 0.125
SSTL18_II
1.7
1.8
1.9
0.833
0.900
0.969
VREF – 0.125
VREF + 0.125
SSTL2_I
2.3
2.5
2.7
1.13
1.25
1.38
VREF – 0.150
VREF + 0.150
SSTL2_II
2.3
2.5
2.7
1.13
1.25
1.38
VREF – 0.150
VREF + 0.150
SSTL3_I
3.0
3.3
3.6
1.3
1.5
1.7
VREF – 0.2
VREF + 0.2
SSTL3_II
3.0
3.3
3.6
1.3
1.5
1.7
VREF – 0.2
VREF + 0.2
VREF is not used for
these I/O standards
Notes:
1.
2.
3.
4.
5.
6.
16
Descriptions of the symbols used in this table are as follows:
VCCO – the supply voltage for output drivers
VREF – the reference voltage for setting the input switching threshold
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when VCCAUX = 3.3V range
and for PCI I/O standards.
For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 8.
There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS25 or
LVCMOS33 standard depending on VCCAUX. The dual-purpose configuration pins use the LVCMOS standard before the User mode. When
using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as
throughout configuration.
For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards(Continued)
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards
Test
Conditions
IOL
IOH
(mA) (mA)
IOSTANDARD
Attribute
LVTTL(3)
2
4
LVCMOS33(3)
LVCMOS25(3)
LVCMOS18(3)
LVCMOS15(3)
LVCMOS12(3)
2
4
Test
Conditions
Logic Level
Characteristics
VOL
Max (V)
VOH
Min (V)
0.4
2.4
IOSTANDARD
Attribute
IOL
IOH
(mA) (mA)
Logic Level
Characteristics
VOL
Max (V)
VOH
Min (V)
PCI33_3(5)
1.5
–0.5
10% VCCO
90% VCCO
–4
PCI66_3(5)
1.5
–0.5
10% VCCO
90% VCCO
8
–8
0.4
VCCO - 0.4
–2
6
6
–6
HSTL_I(4)
8
8
–8
HSTL_III(4)
24
–8
0.4
VCCO - 0.4
12
12
–12
HSTL_I_18
8
–8
0.4
VCCO - 0.4
16
16
–16
HSTL_II_18(4)
16
–16
0.4
VCCO - 0.4
24
24
–24
HSTL_III_18
24
–8
0.4
VCCO - 0.4
2
2
–2
SSTL18_I
6.7
–6.7
13.4
–13.4 VTT – 0.603 VTT + 0.603
0.4
VCCO – 0.4
VTT – 0.475 VTT + 0.475
4
4
–4
SSTL18_II(4)
6
6
–6
SSTL2_I
8.1
–8.1
VTT – 0.61
VTT + 0.61
16.2
–16.2
VTT – 0.81
VTT + 0.81
8
8
–8
SSTL2_II(4)
12
12
–12
SSTL3_I
8
–8
VTT – 0.6
VTT + 0.6
16
16
–16
SSTL3_II
16
–16
VTT – 0.8
VTT + 0.8
24(4)
24
–24
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16(4)
16
–16
24(4)
24
–24
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12(4)
12
–12
16(4)
16
–16
2
2
–2
4
4
–4
6
6
–6
8(4)
8
–8
12(4)
12
–12
2
2
–2
4(4)
4
–4
6(4)
6
–6
Notes:
0.4
VCCO – 0.4
1.
2.
IOL – the output current condition under which VOL is tested
IOH – the output current condition under which VOH is tested
VOL – the output voltage that indicates a Low logic level
VOH – the output voltage that indicates a High logic level
VCCO – the supply voltage for output drivers
VTT – the voltage applied to a resistor termination
3.
4.
DS529 (v2.1) December 18, 2018
The numbers in this table are based on the conditions set forth in
Table 8 and Table 11.
Descriptions of the symbols used in this table are as follows:
0.4
VCCO – 0.4
5.
0.4
VCCO – 0.4
0.4
VCCO – 0.4
For the LVCMOS and LVTTL standards: the same VOL and VOH
limits apply for the Fast, Slow, and QUIETIO slew attributes.
These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
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17
DC and Switching Characteristics
Differential I/O Standards
Differential Input Pairs
VINP
Internal
Logic
VINN
VINN
VID
50%
VINP
Differential
I/O Pair Pins
P
N
VICM
GND level
VICM = Input common mode voltage =
VINP + VINN
2
VID = Differential input voltage = VINP - VINN
DS529-3_10_012907
Figure 4: Differential Input Voltages
Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
Min (V)
VICM(2)
Nom (V)
LVDS_25(3)
2.25
2.5
2.75
100
350
600
0.3
1.25
2.35
LVDS_33(3)
3.0
3.3
3.6
100
350
600
0.3
1.25
2.35
BLVDS_25(4)
2.25
2.5
2.75
100
300
–
0.3
1.3
2.35
MINI_LVDS_25(3)
2.25
2.5
2.75
200
–
600
0.3
1.2
1.95
MINI_LVDS_33(3)
3.0
3.3
3.6
200
–
600
0.3
1.2
1.95
IOSTANDARD Attribute
VCCO for Drivers(1)
Min (V)
Nom (V)
Max (V)
VID
Min (mV) Nom (mV) Max (mV)
Max (V)
LVPECL_25(5)
Inputs Only
100
800
1000
0.3
1.2
1.95
LVPECL_33(5)
Inputs Only
100
800
1000
0.3
1.2
2.8(6)
1.5
RSDS_25(3)
2.25
2.5
2.75
100
200
–
0.3
1.2
RSDS_33(3)
3.0
3.3
3.6
100
200
–
0.3
1.2
1.5
TMDS_33(3, 4, 7)
3.14
3.3
3.47
150
–
1200
2.7
–
3.23
PPDS_25(3)
2.25
2.5
2.75
100
–
400
0.2
–
2.3
PPDS_33(3)
3.0
3.3
3.6
100
–
400
0.2
–
2.3
DIFF_HSTL_I_18
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_II_18(8)
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_III_18
1.7
1.8
1.9
100
–
–
0.8
–
DIFF_HSTL_I
1.4
1.5
1.6
100
–
–
0.68
1.1
0.9
DIFF_HSTL_III
1.4
1.5
1.6
100
–
–
–
0.9
–
DIFF_SSTL18_I
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL18_II(8)
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL2_I
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL2_II(8)
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL3_I
3.0
3.3
3.6
100
–
–
1.1
–
1.9
DIFF_SSTL3_II
3.0
3.3
3.6
100
–
–
1.1
–
1.9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
18
The VCCO rails supply only differential output drivers, not input circuits.
VICM must be less than VCCAUX.
These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
See "External Termination Requirements for Differential I/O," page 20.
LVPECL is supported on inputs only, not outputs. LVPECL_33 requires VCCAUX=3.3V ± 10%.
LVPECL_33 maximum VICM = the lower of 2.8V or VCCAUX – (VID / 2)
Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) ≤ VICM ≤ (VCCAUX – 37 mV)
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint.
www.xilinx.com
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Differential Output Pairs
VOUTP
Internal
Logic
P
N
VOUTN
Differential
I/O Pair Pins
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
VOCM = Output common mode voltage =
VOUTP + VOUTN
2
VOD = Output differential voltage = VOUTP - VOUTN
VOH = Output voltage indicating a High logic level
VOL = Output voltage indicating a Low logic levelDS529-3_11_012907
Figure 5: Differential Output Voltages
Table 14: DC Characteristics of User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Min (mV)
247
247
240
300
300
100
100
400
100
100
–
–
–
VOD
Typ
(mV)
350
350
350
–
–
–
–
–
–
–
–
–
–
VOCM
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max (mV)
Min (V)
454
1.125
454
1.125
460
–
600
1.0
600
1.0
400
1.0
400
1.0
800
VCCO – 0.405
400
0.5
400
0.5
–
–
–
–
–
–
Typ (V)
–
–
1.30
–
–
–
–
–
0.8
0.8
–
–
–
Max (V)
1.375
1.375
–
1.4
1.4
1.4
1.4
VCCO – 0.190
1.4
1.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VOH
VOL
Min (V)
–
–
–
–
–
–
–
–
–
–
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VTT + 0.475
VTT + 0.603
VTT + 0.61
VTT + 0.81
VTT + 0.6
VTT + 0.8
Max (V)
–
–
–
–
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
VTT – 0.475
VTT – 0.603
VTT – 0.61
VTT – 0.81
VTT – 0.6
VTT – 0.8
Notes:
1.
2.
3.
4.
The numbers in this table are based on the conditions set forth in Table 8 and Table 13.
See "External Termination Requirements for Differential I/O," page 20.
Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the
differential signal pair.
At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V
DS529 (v2.1) December 18, 2018
www.xilinx.com
19
DC and Switching Characteristics
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
Bank 0 and 2
Any Bank
Bank 0
Bank 2
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
Bank 1
1/4 th of Bourns
Part Number
Z0 = 50Ω CAT16-PT4F4
Bank 3
Bank 0
No VCCO Restrictions
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
Bank 2
100Ω
Z0 = 50Ω
DIFF_TERM=No
a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
RDT
Z0 = 50Ω
DIFF_TERM=Yes
b) Differential pairs using DIFF_TERM=Yes constraint
DS529-3_09_020107
Figure 6: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
Any Bank
Any Bank
Bank 0
Bank 3
1/4 th of Bourns
Part Number
CAT16-PT4F4
Z0 = 50Ω
165Ω
140Ω
BLVDS_25
Bank 1
Bank 1
Bank 2
VCCO = 2.5V
1/4 th of Bourns
Part Number
CAT16-LV4F12
Bank 3
Bank 0
Bank 2
No VCCO Requirement
100Ω
Z0 = 50Ω
BLVDS_25
165Ω
DS529-3_07_020107
Figure 7: External Output and Input Termination Resistors for BLVDS_25 I/O Standard
TMDS_33 I/O Standard
Any Bank
Bank 0 and 2
Bank 0
3.3V
Bank 2
50Ω
Bank 1
Bank 3
Bank 0
50Ω
Bank 2
VCCAUX = 3.3V
VCCO = 3.3V
TMDS_33
TMDS_33
DVI/HDMI cable
DS529-3_08_020107
Figure 8: External Input Resistors Required for TMDS_33 I/O Standard
Device DNA Read Endurance
Table 15: Device DNA Identifier Memory Characteristics
20
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
30,000,000
Read
cycles
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Switching Characteristics
All Spartan-3A FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document are designated as Advance, Preliminary, or
Production, as shown in Table 16. Each category is defined
as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device has been
characterized to provide full correlation between speed files
and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal
notification of any subsequent changes. Typically, the
slowest speed grades transition to Production before faster
speed grades.
To create a Xilinx user account and sign up for automatic
E-mail notification whenever this data sheet is updated:
•
Sign Up for Alerts
www.xilinx.com/support/answers/18683.htm
Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3A FPGA speed files (v1.41), part of the Xilinx
Development Software, are the original source for many but
not all of the values. The speed grade designations for these
files are shown in Table 16. For more complete, more
precise, and worst-case data, use the values reported by the
Xilinx static timing analyzer (TRACE in the Xilinx
development software) and back-annotated to the
simulation netlist.
Table 16: Spartan-3A v1.41 Speed Grade Designation
Device
Advance
Preliminary
Production
XC3S50A
-4, -5
XC3S200A
-4, -5
XC3S400A
-4, -5
XC3S700A
-4, -5
XC3S1400A
-4, -5
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Advance or Preliminary should not be
used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the FPGA
design incorporates the latest timing information and
software updates.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
DS529 (v2.1) December 18, 2018
Table 17 provides the recent history of the Spartan-3A
FPGA speed files.
Table 17: Spartan-3A Speed File Version History
Version
ISE
Release
Description
1.41
ISE 10.1.03 Updated Automotive output delays
1.40
ISE 10.1.02 Updated Automotive input delays.
1.39
ISE 10.1.01 Added Automotive parts.
1.38
ISE 9.2.03i
Added Absolute Minimum values.
ISE 9.2.01i
Updated pin-to-pin setup and hold
times (Table 19), TMDS output
adjustment (Table 26) multiplier
setup/hold times (Table 34), and block
RAM clock width (Table 35).
1.37
1.36
ISE 9.2i;
XC3S400A, all speed grades and all
previously temperature grades, upgraded to
available via Production
Answer
Record
AR24992
1.35
Answer
Record
AR24992
XC3S50A, XC3S200A, XC3S700A,
XC3S1400A, all speed grades and all
temperature grades, upgraded to
Production.
1.34
ISE 9.1.03i
XC3S700A and XC3S1400A -4 speed
grade upgraded to Production. Updated
pin-to-pin timing numbers.
www.xilinx.com
21
DC and Switching Characteristics
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
-5
-4
Max
Max
Units
XC3S50A
3.18
3.42
ns
XC3S200A
3.21
3.27
ns
XC3S400A
2.97
3.33
ns
XC3S700A
3.39
3.50
ns
XC3S1400A
3.51
3.99
ns
XC3S50A
4.59
5.02
ns
XC3S200A
4.88
5.24
ns
XC3S400A
4.68
5.12
ns
XC3S700A
4.97
5.34
ns
XC3S1400A
5.06
5.69
ns
Device
Clock-to-Output Times
TICKOFDCM
TICKOF
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25(2), 12mA
output drive, Fast slew
rate, with DCM(3)
When reading from OFF, the time LVCMOS25(2), 12mA
from the active transition on the
output drive, Fast slew
Global Clock pin to data appearing rate, without DCM
at the Output pin. The DCM is not
in use.
Notes:
1.
2.
3.
22
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 23. If the latter is true, add the appropriate Output adjustment from Table 26.
DCM output jitter is included in all measurements.
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
Symbol
Description
Conditions
-5
-4
Device
Min
Min
Units
XC3S50A
2.45
2.68
ns
XC3S200A
2.59
2.84
ns
XC3S400A
2.38
2.68
ns
XC3S700A
2.38
2.57
ns
XC3S1400A
1.91
2.17
ns
XC3S50A
2.55
2.76
ns
XC3S200A
2.32
2.76
ns
XC3S400A
2.21
2.60
ns
XC3S700A
2.28
2.63
ns
XC3S1400A
2.33
2.41
ns
XC3S50A
-0.36
-0.36
ns
XC3S200A
-0.52
-0.52
ns
XC3S400A
-0.33
-0.29
ns
XC3S700A
-0.17
-0.12
ns
XC3S1400A
-0.07
0.00
ns
XC3S50A
-0.63
-0.58
ns
XC3S200A
-0.56
-0.56
ns
XC3S400A
-0.42
-0.42
ns
XC3S700A
-0.80
-0.75
ns
XC3S1400A
-0.69
-0.69
ns
Setup Times
TPSDCM
TPSFD
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
LVCMOS25(2),
When writing to IFF, the time from
the setup of data at the Input pin IFD_DELAY_VALUE = 5,
to an active transition at the
without DCM
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
Hold Times
TPHDCM
TPHFD
When writing to IFF, the time from LVCMOS25(3),
the active transition at the Global IFD_DELAY_VALUE = 0,
Clock pin to the point when data with DCM(4)
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
LVCMOS25(3),
When writing to IFF, the time from
the active transition at the Global IFD_DELAY_VALUE = 5,
Clock pin to the point when data without DCM
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
Notes:
1.
2.
3.
4.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 23. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 23. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
DS529 (v2.1) December 18, 2018
www.xilinx.com
23
DC and Switching Characteristics
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
Speed Grade
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
-5
-4
Min
Min
Units
XC3S50A
1.56
1.58
ns
XC3S200A
1.71
1.81
ns
XC3S400A
1.30
1.51
ns
XC3S700A
1.34
1.51
ns
XC3S1400A
1.36
1.74
ns
XC3S50A
2.16
2.18
ns
2
3.10
3.12
ns
3
3.51
3.76
ns
4
4.04
4.32
ns
5
3.88
4.24
ns
6
4.72
5.09
ns
7
5.47
5.94
ns
8
5.97
6.52
ns
2.05
2.20
ns
2
2.72
2.93
ns
3
3.38
3.78
ns
4
3.88
4.37
ns
5
3.69
4.20
ns
6
4.56
5.23
ns
7
5.34
6.11
ns
8
5.85
6.71
ns
1.79
2.02
ns
2
2.43
2.67
ns
3
3.02
3.43
ns
4
3.49
3.96
ns
5
3.41
3.95
ns
6
4.20
4.81
ns
7
4.96
5.66
ns
8
5.44
6.19
ns
Device
Setup Times
TIOPICK
TIOPICKD
Time from the setup of data at the
LVCMOS25(2)
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
No Input Delay is programmed.
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
LVCMOS25(2)
0
1
1
1
24
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XC3S200A
XC3S400A
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Speed Grade
Symbol
TIOPICKD
Description
Conditions
Time from the setup of data at the
LVCMOS25(2)
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
IFD_
DELAY_
VALUE
-5
-4
Device
Min
Min
Units
XC3S700A
1.82
1.95
ns
2
2.62
2.83
ns
3
3.32
3.72
ns
4
3.83
4.31
ns
5
3.69
4.14
ns
6
4.60
5.19
ns
7
5.39
6.10
ns
8
5.92
6.73
ns
1.79
2.17
ns
2
2.55
2.92
ns
3
3.38
3.76
ns
4
3.75
4.32
ns
5
3.81
4.19
ns
6
4.39
5.09
ns
7
5.16
5.98
ns
8
5.69
6.57
ns
XC3S50A
–0.66
–0.64
ns
XC3S200A
–0.85
–0.65
ns
XC3S400A
–0.42
–0.42
ns
XC3S700A
–0.81
–0.67
ns
XC3S1400A
–0.71
–0.71
ns
XC3S50A
–0.88
–0.88
ns
2
–1.33
–1.33
ns
3
–2.05
–2.05
ns
4
–2.43
–2.43
ns
5
–2.34
–2.34
ns
6
–2.81
–2.81
ns
7
–3.03
–3.03
ns
8
–3.83
–3.57
ns
–1.51
–1.51
ns
2
–2.09
–2.09
ns
3
–2.40
–2.40
ns
4
–2.68
–2.68
ns
5
–2.56
–2.56
ns
6
–2.99
–2.99
ns
7
–3.29
–3.29
ns
8
–3.61
–3.61
ns
1
1
XC3S1400A
Hold Times
TIOICKP
TIOICKPD
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. No Input Delay is
programmed.
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
LVCMOS25(3)
LVCMOS25(3)
0
1
1
DS529 (v2.1) December 18, 2018
www.xilinx.com
XC3S200A
25
DC and Switching Characteristics
Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Speed Grade
Symbol
TIOICKPD
Description
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
Conditions
LVCMOS25(3)
IFD_
DELAY_
VALUE
-5
-4
Min
Min
Units
–1.12
–1.12
ns
2
–1.70
–1.70
ns
3
–2.08
–2.08
ns
4
–2.38
–2.38
ns
5
–2.23
–2.23
ns
6
–2.69
–2.69
ns
7
–3.08
–3.08
ns
8
–3.35
–3.35
ns
–1.67
–1.67
ns
2
–2.27
–2.27
ns
3
–2.59
–2.59
ns
4
–2.92
–2.92
ns
5
–2.89
–2.89
ns
6
–3.22
–3.22
ns
7
–3.52
–3.52
ns
8
–3.81
–3.81
ns
–1.60
–1.60
ns
2
–2.06
–2.06
ns
3
–2.46
–2.46
ns
4
–2.86
–2.86
ns
5
–2.88
–2.88
ns
6
–3.24
–3.24
ns
7
–3.55
–3.55
ns
8
–3.89
–3.89
ns
1.33
1.61
ns
1
1
1
Device
XC3S400A
XC3S700A
XC3S1400A
Set/Reset Pulse Width
TRPW_IOB
Minimum pulse width to SR control
input on IOB
-
-
All
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 23.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 23. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 21: Sample Window (Source Synchronous)
Symbol
TSAMP
26
Max
Description
Setup and hold
capture window of
an IOB flip-flop.
Units
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
• Answer Record 30879
www.xilinx.com
ps
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Input Propagation Times
Table 22: Propagation Times for the IOB Input Path
Speed Grade
Symbol
Description
Conditions
The time it takes for data to travel
from the Input pin to the I output with
no input delay programmed
LVCMOS25(2)
-5
-4
Device
Max
Max
Units
IBUF_DELAY_VALUE=0 XC3S50A
1.04
1.12
ns
XC3S200A
0.87
0.87
ns
XC3S400A
0.65
0.72
ns
XC3S700A
0.92
0.92
ns
XC3S1400A
0.96
1.21
ns
XC3S50A
1.79
2.07
ns
2
2.13
2.46
ns
3
2.36
2.71
ns
4
2.88
3.21
ns
5
3.11
3.46
ns
6
3.45
3.84
ns
7
3.75
4.19
ns
8
4.00
4.47
ns
9
3.61
4.11
ns
10
3.95
4.50
ns
11
4.18
4.67
ns
12
4.75
5.20
ns
13
4.98
5.44
ns
14
5.31
5.95
ns
15
5.62
6.28
ns
16
5.86
6.57
ns
1.57
1.65
ns
2
1.87
1.97
ns
3
2.16
2.33
ns
4
2.68
2.96
ns
5
2.87
3.19
ns
6
3.20
3.60
ns
7
3.57
4.02
ns
8
3.79
4.26
ns
9
3.42
3.86
ns
10
3.79
4.25
ns
11
4.02
4.55
ns
12
4.62
5.24
ns
13
4.86
5.53
ns
14
5.18
5.94
ns
DELAY_VALUE
Propagation Times
TIOPI
TIOPID
The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2)
1
1
DS529 (v2.1) December 18, 2018
www.xilinx.com
XC3S200A
27
DC and Switching Characteristics
Table 22: Propagation Times for the IOB Input Path(Continued)
Speed Grade
Symbol
TIOPID
-5
-4
Max
Max
Units
5.43
6.24
ns
5.75
6.59
ns
1.32
1.43
ns
2
1.67
1.83
ns
3
1.90
2.07
ns
4
2.33
2.52
ns
5
2.60
2.91
ns
6
2.94
3.20
ns
7
3.23
3.51
ns
8
3.50
3.85
ns
9
3.18
3.55
ns
10
3.53
3.95
ns
11
3.76
4.20
ns
12
4.26
4.67
ns
13
4.51
4.97
ns
14
4.85
5.32
ns
15
5.14
5.64
ns
16
5.40
5.95
ns
1.84
1.87
ns
2
2.20
2.27
ns
3
2.46
2.60
ns
4
2.93
3.15
ns
5
3.21
3.45
ns
6
3.54
3.80
ns
7
3.86
4.16
ns
8
4.13
4.48
ns
9
3.82
4.19
ns
10
4.17
4.58
ns
11
4.43
4.89
ns
12
4.95
5.49
ns
13
5.22
5.83
ns
14
5.57
6.21
ns
15
5.89
6.55
ns
16
6.16
6.89
ns
1.95
2.18
ns
2
2.29
2.59
ns
3
2.54
2.84
ns
4
2.96
3.30
ns
Description
Conditions
DELAY_VALUE
The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2)
15
XC3S200A
16
1
1
1
28
Device
www.xilinx.com
XC3S400A
XC3S700A
XC3S1400A
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Table 22: Propagation Times for the IOB Input Path(Continued)
Speed Grade
Symbol
TIOPID
TIOPLI
TIOPLID
-5
-4
Description
Conditions
DELAY_VALUE
Device
Max
Max
Units
The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2)
5
XC3S1400A
3.17
3.52
ns
6
3.52
3.92
ns
7
3.82
4.18
ns
8
4.10
4.57
ns
9
3.84
4.31
ns
10
4.20
4.79
ns
11
4.46
5.06
ns
12
4.87
5.51
ns
13
5.07
5.73
ns
14
5.43
6.08
ns
15
5.73
6.33
ns
16
6.01
6.77
ns
XC3S50A
1.70
1.81
ns
XC3S200A
1.85
2.04
ns
XC3S400A
1.44
1.74
ns
XC3S700A
1.48
1.74
ns
XC3S1400A
1.50
1.97
ns
XC3S50A
2.30
2.41
ns
2
3.24
3.35
ns
3
3.65
3.98
ns
4
4.18
4.55
ns
5
4.02
4.47
ns
6
4.86
5.32
ns
7
5.61
6.17
ns
8
6.11
6.75
ns
2.19
2.43
ns
2
2.86
3.16
ns
3
3.52
4.01
ns
4
4.02
4.60
ns
5
3.83
4.43
ns
6
4.70
5.46
ns
7
5.48
6.33
ns
8
5.99
6.94
ns
1.93
2.25
ns
2
2.57
2.90
ns
3
3.16
3.66
ns
4
3.63
4.19
ns
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2)
IFD_DELAY_VALUE=0
LVCMOS25(2)
1
1
1
DS529 (v2.1) December 18, 2018
www.xilinx.com
XC3S200A
XC3S400A
29
DC and Switching Characteristics
Table 22: Propagation Times for the IOB Input Path(Continued)
Speed Grade
Symbol
TIOPLID
Description
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
-5
-4
Max
Max
Units
3.55
4.18
ns
6
4.34
5.03
ns
7
5.09
5.88
ns
8
5.58
6.42
ns
1.96
2.18
ns
2
2.76
3.06
ns
3
3.45
3.95
ns
4
3.97
4.54
ns
5
3.83
4.37
ns
6
4.74
5.42
ns
7
5.53
6.33
ns
8
6.06
6.96
ns
1.93
2.40
ns
2
2.69
3.15
ns
3
3.52
3.99
ns
4
3.89
4.55
ns
5
3.95
4.42
ns
6
4.53
5.32
ns
7
5.30
6.21
ns
8
5.83
6.80
ns
Conditions
DELAY_VALUE
LVCMOS25(2)
5
1
1
Device
XC3S400A
XC3S700A
XC3S1400A
Notes:
1.
2.
30
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 23.
www.xilinx.com
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Input Timing Adjustments
Table 23: Input Timing Adjustments by IOSTANDARD(Continued)
Table 23: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
-4
Units
Add the
Adjustment Below
Speed Grade
-5
-4
Units
Differential Standards
Single-Ended Standards
LVTTL
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
0.62
0.62
ns
LVDS_25
0.76
0.76
ns
0.79
0.79
ns
LVCMOS33
0.54
0.54
ns
LVDS_33
LVCMOS25
0
0
ns
BLVDS_25
0.79
0.79
ns
0.78
0.78
ns
LVCMOS18
0.83
0.83
ns
MINI_LVDS_25
LVCMOS15
0.60
0.60
ns
MINI_LVDS_33
0.79
0.79
ns
LVCMOS12
0.31
0.31
ns
LVPECL_25
0.78
0.78
ns
0.79
0.79
ns
PCI33_3
0.41
0.41
ns
LVPECL_33
PCI66_3
0.41
0.41
ns
RSDS_25
0.79
0.79
ns
0.77
0.77
ns
HSTL_I
0.72
0.72
ns
RSDS_33
HSTL_III
0.77
0.77
ns
TMDS_33
0.79
0.79
ns
HSTL_I_18
0.69
0.69
ns
PPDS_25
0.79
0.79
ns
0.79
0.79
ns
0.74
0.74
ns
HSTL_II_18
0.69
0.69
ns
PPDS_33
HSTL_III_18
0.79
0.79
ns
DIFF_HSTL_I_18
SSTL18_I
0.71
0.71
ns
DIFF_HSTL_II_18
0.72
0.72
ns
1.05
1.05
ns
SSTL18_II
0.71
0.71
ns
DIFF_HSTL_III_18
SSTL2_I
0.68
0.68
ns
DIFF_HSTL_I
0.72
0.72
ns
1.05
1.05
ns
0.71
0.71
ns
SSTL2_II
0.68
0.68
ns
DIFF_HSTL_III
SSTL3_I
0.78
0.78
ns
DIFF_SSTL18_I
SSTL3_II
0.78
0.78
ns
DIFF_SSTL18_II
0.71
0.71
ns
DIFF_SSTL2_I
0.74
0.74
ns
DIFF_SSTL2_II
0.75
0.75
ns
DIFF_SSTL3_I
1.06
1.06
ns
DIFF_SSTL3_II
1.06
1.06
ns
Notes:
1.
2.
DS529 (v2.1) December 18, 2018
The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
www.xilinx.com
31
DC and Switching Characteristics
Output Propagation Times
Table 24: Timing for the IOB Output Path
Speed Grade
Symbol
-5
-4
Description
Conditions
Device
Max
Max
Units
When reading from the Output Flip-Flop (OFF),
the time from the active transition at the OCLK
input to data appearing at the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.87
3.13
ns
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.78
2.91
ns
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
3.63
3.89
ns
8.62
9.65
ns
Clock-to-Output Times
TIOCKP
Propagation Times
TIOOP
The time it takes for data to travel from the IOB’s
O input to the Output pin
Set/Reset Times
TIOSRP
TIOGSRQ
Time from asserting the OFF’s SR input to
setting/resetting data at the Output pin
Time from asserting the Global Set Reset (GSR)
input on the STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
Three-State Output Propagation Times
Table 25: Timing for the IOB Three-State Path
Speed Grade
Symbol
Description
Conditions
-5
-4
Device
Max
Max
Units
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK input of LVCMOS25, 12 mA
the Three-state Flip-Flop (TFF) to when the Output output drive, Fast slew
pin enters the high-impedance state
rate
All
0.63
0.76
ns
TIOCKON(2)
Time from the active transition at TFF’s OTCLK input
to when the Output pin drives valid data
All
2.80
3.06
ns
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
9.47
10.36
ns
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
1.61
1.86
ns
All
3.57
3.82
ns
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State (GTS)
input on the STARTUP_SPARTAN3A primitive to
when the Output pin enters the high-impedance
state
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
TIOSRON(2)
Time from asserting TFF’s SR input at TFF to when
the Output pin drives valid data
Notes:
1.
2.
32
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
www.xilinx.com
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Output Timing Adjustments
Table 26: Output Timing Adjustments for IOB(Continued)
Table 26: Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-5
-4
Units
Single-Ended Standards
LVTTL
Slow
Fast
QuietIO
Add the
Adjustment
Below
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Speed Grade
-5
-4
Units
LVCMOS33
2 mA
5.58
5.58
ns
3.17
3.17
ns
Slow
2 mA
5.58
5.58
ns
4 mA
4 mA
3.16
3.16
ns
6 mA
3.17
3.17
ns
2.09
2.09
ns
1.24
1.24
ns
6 mA
3.17
3.17
ns
8 mA
8 mA
2.09
2.09
ns
12 mA
12 mA
1.62
1.62
ns
16 mA
1.15
1.15
ns
24 mA
2.55(3)
2.55(3)
ns
2 mA
3.02
3.02
ns
16 mA
1.24
1.24
ns
24 mA
2.74(3)
2.74(3)
ns
2 mA
3.03
3.03
ns
4 mA
1.71
1.71
ns
1.72
1.72
ns
Fast
4 mA
1.71
1.71
ns
6 mA
6 mA
1.71
1.71
ns
8 mA
0.53
0.53
ns
8 mA
0.53
0.53
ns
12 mA
0.59
0.59
ns
16 mA
0.59
0.59
ns
12 mA
0.53
0.53
ns
16 mA
0.59
0.59
ns
QuietIO
24 mA
0.51
0.51
ns
2 mA
27.67
27.67
ns
24 mA
0.60
0.60
ns
2 mA
27.67
27.67
ns
4 mA
27.67
27.67
ns
4 mA
27.67
27.67
ns
6 mA
27.67
27.67
ns
16.71
16.71
ns
6 mA
27.67
27.67
ns
8 mA
8 mA
16.71
16.71
ns
12 mA
16.29
16.29
ns
16.18
16.18
ns
12.11
12.11
ns
12 mA
16.67
16.67
ns
16 mA
16 mA
16.22
16.22
ns
24 mA
24 mA
12.11
12.11
ns
DS529 (v2.1) December 18, 2018
www.xilinx.com
33
DC and Switching Characteristics
Table 26: Output Timing Adjustments for IOB(Continued)
Add the
Adjustment
Below
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Speed Grade
-5
-4
Units
LVCMOS25
2 mA
5.33
5.33
ns
4 mA
2.81
2.81
6 mA
2.82
8 mA
1.14
12 mA
16 mA
Slow
Fast
QuietIO
LVCMOS18
Slow
Fast
QuietIO
34
Table 26: Output Timing Adjustments for IOB(Continued)
Add the
Adjustment
Below
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Speed Grade
-5
-4
Units
LVCMOS15
2 mA
5.82
5.82
ns
ns
4 mA
3.97
3.97
ns
2.82
ns
6 mA
3.21
3.21
ns
1.14
ns
8 mA
2.53
2.53
ns
1.10
1.10
ns
0.83
0.83
ns
24 mA
2.26(3)
2.26(3)
2 mA
4.36
4 mA
1.76
6 mA
Slow
12 mA
2.06
2.06
ns
2 mA
5.23
5.23
ns
ns
4 mA
3.05
3.05
ns
4.36
ns
6 mA
1.95
1.95
ns
1.76
ns
8 mA
1.60
1.60
ns
1.25
1.25
ns
12 mA
1.30
1.30
ns
Fast
8 mA
0.38
0.38
ns
2 mA
34.11
34.11
ns
12 mA
0
0
ns
QuietIO
4 mA
25.66
25.66
ns
16 mA
0.01
0.01
ns
6 mA
24.64
24.64
ns
24 mA
0.01
0.01
ns
8 mA
22.06
22.06
ns
2 mA
25.92
25.92
ns
12 mA
20.64
20.64
ns
4 mA
25.92
25.92
ns
2 mA
7.14
7.14
ns
6 mA
25.92
25.92
ns
4 mA
4.87
4.87
ns
8 mA
15.57
15.57
ns
6 mA
5.67
5.67
ns
12 mA
15.59
15.59
ns
2 mA
6.77
6.77
ns
16 mA
14.27
14.27
ns
4 mA
5.02
5.02
ns
24 mA
11.37
11.37
ns
2 mA
4.48
4.48
ns
4 mA
3.69
3.69
ns
6 mA
2.91
2.91
ns
8 mA
1.99
1.99
ns
PCI33_3
12 mA
1.57
1.57
ns
PCI66_3
16 mA
1.19
1.19
ns
2 mA
3.96
3.96
ns
4 mA
2.57
2.57
ns
HSTL_I_18
0.35
0.35
ns
6 mA
1.90
1.90
ns
HSTL_II_18
0.30
0.30
ns
8 mA
1.06
1.06
ns
HSTL_III_18
0.47
0.47
ns
12 mA
0.83
0.83
ns
SSTL18_I
0.40
0.40
ns
16 mA
0.63
0.63
ns
SSTL18_II
0.30
0.30
ns
2 mA
24.97
24.97
ns
SSTL2_I
0
0
ns
4 mA
24.97
24.97
ns
SSTL2_II
–0.05
–0.05
ns
6 mA
24.08
24.08
ns
SSTL3_I
0
0
ns
8 mA
16.43
16.43
ns
SSTL3_II
0.17
0.17
ns
12 mA
14.52
14.52
ns
16 mA
13.41
13.41
ns
LVCMOS12
Slow
Fast
6 mA
4.09
4.09
ns
2 mA
50.76
50.76
ns
4 mA
43.17
43.17
ns
6 mA
37.31
37.31
ns
0.34
0.34
ns
0.34
0.34
ns
HSTL_I
0.78
0.78
ns
HSTL_III
1.16
1.16
ns
QuietIO
www.xilinx.com
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Table 26: Output Timing Adjustments for IOB(Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-5
-4
Units
1.16
1.16
ns
LVDS_33
0.46
0.46
ns
BLVDS_25
0.11
0.11
ns
MINI_LVDS_25
0.75
0.75
ns
MINI_LVDS_33
0.40
0.40
ns
Differential Standards
LVDS_25
LVPECL_25
Input Only
LVPECL_33
RSDS_25
1.42
1.42
ns
RSDS_33
0.58
0.58
ns
TMDS_33
0.46
0.46
ns
PPDS_25
1.07
1.07
ns
PPDS_33
0.63
0.63
ns
DIFF_HSTL_I_18
0.43
0.43
ns
DIFF_HSTL_II_18
0.41
0.41
ns
DIFF_HSTL_III_18
0.36
0.36
ns
DIFF_HSTL_I
1.01
1.01
ns
DIFF_HSTL_III
0.54
0.54
ns
DIFF_SSTL18_I
0.49
0.49
ns
DIFF_SSTL18_II
0.41
0.41
ns
DIFF_SSTL2_I
0.82
0.82
ns
DIFF_SSTL2_II
0.09
0.09
ns
DIFF_SSTL3_I
1.16
1.16
ns
DIFF_SSTL3_II
0.28
0.28
ns
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Note that 16 mA drive is faster than 24 mA drive for the Slow
slew rate.
DS529 (v2.1) December 18, 2018
www.xilinx.com
35
DC and Switching Characteristics
Timing Measurement Methodology
LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an open
connection, and VT is set to zero. The same measurement
point (VM) that was used at the Input is also used at the
Output.
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 27 lists the conditions to use for each
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (VM) is commonly located halfway between VL
and VH.
VT (VREF)
FPGA Output
RT (RREF)
VM (VMEAS)
CL (CREF)
The Output test setup is shown in Figure 9. A termination
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard,
RT and VT generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
DS312-3_04_102406
Notes:
1.
The names shown in parentheses are
used in the IBIS file.
Figure 9: Output Test Setup
Table 27: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Inputs
Inputs and
Outputs
Outputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
LVTTL
-
0
3.3
1M
0
1.4
LVCMOS33
-
0
3.3
1M
0
1.65
LVCMOS25
-
0
2.5
1M
0
1.25
LVCMOS18
-
0
1.8
1M
0
0.9
LVCMOS15
-
0
1.5
1M
0
0.75
LVCMOS12
-
0
1.2
1M
0
0.6
-
Note 3
Note 3
25
0
0.94
25
3.3
2.03
25
0
0.94
25
3.3
2.03
Single-Ended
PCI33_3
Rising
Falling
PCI66_3
Rising
-
Note 3
Note 3
Falling
HSTL_I
0.75
VREF – 0.5
VREF + 0.5
50
0.75
VREF
HSTL_III
0.9
VREF – 0.5
VREF + 0.5
50
1.5
VREF
HSTL_I_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
HSTL_II_18
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
SSTL18_I
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
SSTL2_I
1.25
VREF – 0.75
VREF + 0.75
50
1.25
VREF
SSTL2_II
1.25
VREF – 0.75
VREF + 0.75
25
1.25
VREF
SSTL3_I
1.5
VREF – 0.75
VREF + 0.75
50
1.5
VREF
SSTL3_II
1.5
VREF – 0.75
VREF + 0.75
25
1.5
VREF
36
www.xilinx.com
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Table 27: Test Methods for Timing Measurement at I/Os(Continued)
Signal Standard
(IOSTANDARD)
Inputs
Inputs and
Outputs
Outputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
LVDS_25
-
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVDS_33
-
VICM – 0.125
VICM + 0.125
50
1.2
VICM
BLVDS_25
-
VICM – 0.125
VICM + 0.125
1M
0
VICM
MINI_LVDS_25
-
VICM – 0.125
VICM + 0.125
50
1.2
VICM
MINI_LVDS_33
-
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVPECL_25
-
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
LVPECL_33
-
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
RSDS_25
-
VICM – 0.1
VICM + 0.1
50
1.2
VICM
RSDS_33
-
VICM – 0.1
VICM + 0.1
50
1.2
VICM
TMDS_33
-
VICM – 0.1
VICM + 0.1
50
3.3
VICM
PPDS_25
-
VICM – 0.1
VICM + 0.1
50
0.8
VICM
PPDS_33
-
VICM – 0.1
VICM + 0.1
50
0.8
VICM
DIFF_HSTL_I
-
VICM – 0.5
VICM + 0.5
50
0.75
VICM
DIFF_HSTL_III
-
VICM – 0.5
VICM + 0.5
50
1.5
VICM
DIFF_HSTL_I_18
-
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_II_18
-
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_III_18
-
VICM – 0.5
VICM + 0.5
50
1.8
VICM
DIFF_SSTL18_I
-
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL18_II
-
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL2_I
-
VICM – 0.5
VICM + 0.5
50
1.25
VICM
DIFF_SSTL2_II
-
VICM – 0.5
VICM + 0.5
50
1.25
VICM
DIFF_SSTL3_I
-
VICM – 0.5
VICM + 0.5
50
1.5
VICM
DIFF_SSTL3_II
-
VICM – 0.5
VICM + 0.5
50
1.5
VICM
Differential
Notes:
1.
2.
3.
Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
VT – Termination voltage
The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
According to the PCI specification.
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
DS529 (v2.1) December 18, 2018
www.xilinx.com
37
DC and Switching Characteristics
Using IBIS Models to Simulate Load Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (VREF, RREF, and VMEAS) correspond directly
with the parameters used in Table 27 (VT, RT, and VM). Do
not confuse VREF (the termination voltage) from the IBIS
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
www.xilinx.com/support/download/index.htm
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 9.
Use parameter values VT, RT, and VM from Table 27.
CREF is zero.
2. Record the time to VM.
3. Simulate the same signal standard with the output driver
connected to the PCB trace with load. Use the
appropriate IBIS model (including VREF, RREF, CREF,
and VMEAS values) or capacitive value to represent the
load.
4. Record the time to VMEAS.
Delays for a given application are simulated according to its
specific load conditions as follows:
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 26) to
yield the worst-case delay of the PCB trace.
Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 28 and Table 29 provide the essential SSO guidelines.
For each device/package combination, Table 28 provides
the number of equivalent VCCO/GND pairs. The equivalent
number of pairs is based on characterization and may not
match the physical number of pairs. For each output signal
standard and drive strength, Table 29 recommends the
maximum number of SSOs, switching in the same direction,
allowed per VCCO/GND pair within an I/O bank. The
guidelines in Table 29 are categorized by package style,
slew rate, and output drive current. Furthermore, the
number of SSOs is specified by I/O bank. Generally, the left
and right I/O banks (Banks 1 and 3) support higher output
drive current.
Multiply the appropriate numbers from Table 28 and
Table 29 to calculate the maximum number of SSOs allowed
within an I/O bank. Exceeding these SSO guidelines might
result in increased power or ground bounce, degraded
signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table 28 x Table 29
The recommended maximum SSO values assume that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The SSO values assume that the VCCAUX is powered at
3.3V. Setting VCCAUX to 2.5V provides better SSO
characteristics.
The number of SSOs allowed for quad-flat packages
(VQ/TQ) is lower than for ball grid array packages (FG) due
to the larger lead inductance of the quad-flat packages. Ball
grid array packages are recommended for applications with
a large number of simultaneously switching outputs.
38
www.xilinx.com
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Table 28: Equivalent VCCO/GND Pairs per Bank
Package Style (including Pb-free)
Device
VQ100
TQ144
FT256
FG320
FG400
FG484
FG676
XC3S50A
1
2
3
–
–
–
–
XC3S200A
1
–
4
4
–
–
–
XC3S400A
–
–
4
4
5
–
–
XC3S700A
–
–
4
–
5
5
–
XC3S1400A
–
–
4
–
–
6
9
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Package Type
Package Type
Signal Standard
(IOSTANDARD)
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
Top,
Bottom
Left,
Right
Top,
Bottom
Left,
Right
Top,
Bottom
Left,
Right
Top,
Bottom
Left,
Right
(Banks
0,2)
(Banks
1,3)
(Banks
0,2)
(Banks
1,3)
(Banks
0,2)
(Banks
1,3)
(Banks
0,2)
(Banks
1,3)
2
24
24
76
76
60
4
14
14
46
46
11
11
27
27
LVCMOS33
Single-Ended Standards
LVTTL
Slow
Fast
QuietIO
2
Signal Standard
(IOSTANDARD)
20
20
60
Slow
4
10
10
41
41
6
6
10
10
29
29
8
10
10
20
20
8
6
6
22
22
12
9
9
13
13
16
8
8
10
10
12
6
6
13
13
16
5
5
11
11
Fast
24
–
8
–
9
2
10
10
10
10
24
4
4
9
9
2
10
10
10
10
4
8
8
8
8
6
5
5
5
5
4
6
6
6
6
6
5
5
5
5
8
4
4
4
4
4
4
4
4
2
2
2
2
8
3
3
3
3
12
12
3
3
3
3
16
16
3
3
3
3
QuietIO
24
–
2
–
2
2
36
36
76
76
24
2
2
2
2
2
40
40
80
80
4
32
32
46
46
6
24
24
32
32
4
24
24
48
48
6
20
20
36
36
8
16
16
26
26
16
16
18
18
8
16
16
27
27
12
12
12
12
16
16
16
12
12
14
14
24
–
10
–
10
16
9
9
13
13
24
9
9
12
12
DS529 (v2.1) December 18, 2018
www.xilinx.com
39
DC and Switching Characteristics
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Package Type
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
Top,
Bottom
Left,
Right
Top,
Bottom
Left,
Right
Top,
Bottom
Left,
Right
Top,
Bottom
Left,
Right
(Banks
0,2)
(Banks
1,3)
(Banks
0,2)
(Banks
1,3)
(Banks
0,2)
(Banks
1,3)
(Banks
0,2)
(Banks
1,3)
2
16
16
76
76
2
12
12
55
55
4
10
10
46
46
4
7
7
31
31
6
8
8
33
33
6
7
7
18
18
Signal Standard
(IOSTANDARD)
LVCMOS25
Slow
Fast
QuietIO
LVCMOS18
Slow
Fast
QuietIO
40
Package Type
Signal Standard
(IOSTANDARD)
LVCMOS15
Slow
8
7
7
24
24
8
–
6
–
15
12
6
6
18
18
12
–
5
–
10
16
–
6
–
11
2
10
10
25
25
24
–
5
–
7
4
7
7
10
10
2
12
12
18
18
6
6
6
6
6
4
10
10
14
14
8
–
4
–
4
6
8
8
6
6
12
–
3
–
3
Fast
8
6
6
6
6
2
30
30
70
70
12
3
3
3
3
4
21
21
40
40
16
–
3
–
3
6
18
18
31
31
24
–
2
–
2
8
–
12
–
31
2
36
36
76
76
4
30
30
60
60
6
24
24
48
48
8
20
20
36
36
12
12
12
36
36
16
–
12
–
24
–
8
–
QuietIO
LVCMOS12
Slow
12
–
12
–
20
2
17
17
40
40
4
–
13
–
25
6
–
10
–
18
2
12
9
31
31
36
4
–
9
–
13
8
6
–
9
–
9
2
36
36
55
55
4
–
33
–
36
Fast
2
13
13
64
64
4
8
8
34
34
QuietIO
6
8
8
22
22
–
27
–
36
8
7
7
18
18
PCI33_3
9
9
16
16
12
–
5
–
13
PCI66_3
–
9
–
13
16
–
5
–
10
HSTL_I
–
11
–
20
2
13
13
18
18
HSTL_III
–
7
–
8
4
8
8
9
9
HSTL_I_18
13
13
17
17
6
7
7
7
7
HSTL_II_18
–
5
–
5
8
4
4
4
4
HSTL_III_18
8
8
10
8
12
–
4
–
4
SSTL18_I
7
13
7
15
6
16
–
3
–
3
SSTL18_II
–
9
–
9
2
30
30
64
64
SSTL2_I
10
10
18
18
4
24
24
64
64
SSTL2_II
–
6
–
9
6
20
20
48
48
SSTL3_I
7
8
8
10
8
16
16
36
36
SSTL3_II
5
6
6
7
12
–
12
–
36
16
–
12
–
24
www.xilinx.com
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (VCCAUX=3.3V)(Continued)
Package Type
Signal Standard
(IOSTANDARD)
VQ100, TQ144
FT256, FG320,
FG400, FG484,
FG676
Top,
Bottom
Left,
Right
Top,
Bottom
Left,
Right
(Banks
0,2)
(Banks
1,3)
(Banks
0,2)
(Banks
1,3)
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
8
–
22
–
LVDS_33
8
–
27
–
BLVDS_25
1
1
4
4
MINI_LVDS_25
8
–
22
–
MINI_LVDS_33
8
–
27
–
LVPECL_25
Input Only
LVPECL_33
Input Only
RSDS_25
8
–
22
–
RSDS_33
8
–
27
–
TMDS_33
8
–
27
–
PPDS_25
8
–
22
–
PPDS_33
8
–
27
–
DIFF_HSTL_I
–
5
–
10
DIFF_HSTL_III
–
3
–
4
DIFF_HSTL_I_18
6
6
8
8
DIFF_HSTL_II_18
–
2
–
2
DIFF_HSTL_III_18
4
4
5
4
DIFF_SSTL18_I
3
6
3
7
DIFF_SSTL18_II
–
4
–
4
DIFF_SSTL2_I
5
5
9
9
DIFF_SSTL2_II
–
3
–
4
DIFF_SSTL3_I
3
4
4
5
DIFF_SSTL3_II
2
3
3
3
Notes:
1.
2.
3.
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the VIL/VIH voltage
limits for the respective I/O standard.
If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
DS529 (v2.1) December 18, 2018
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41
DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 30: CLB (SLICEM) Timing
Speed Grade
-5
Symbol
-4
Description
Min
Max
Min
Max
Units
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
–
0.60
–
0.68
ns
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.18
–
0.36
–
ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
1.58
–
1.88
–
ns
TAH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
0
–
0
–
ns
TCKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
0
–
0
–
ns
Clock-to-Output Times
TCKO
Setup Times
Hold Times
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
0.63
–
0.75
–
ns
TCL
The Low pulse width of the CLK signal
0.63
–
0.75
–
ns
FTOG
Toggle frequency (for export control)
0
770
0
667
MHz
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
–
0.62
–
0.71
ns
1.33
–
1.61
–
ns
Propagation Times
TILO
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
Notes:
1.
42
The numbers in this table are based on the operating conditions set forth in Table 8.
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Table 31: CLB Distributed RAM Switching Characteristics
-5
Symbol
-4
Description
Min
Max
Min
Max
Units
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
–
1.69
–
2.01
ns
Clock-to-Output Times
TSHCKO
Setup Times
TDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
–0.07
–
–0.02
–
ns
TAS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
0.18
–
0.36
–
ns
TWS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
0.30
–
0.59
–
ns
TDH
Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM
0.13
–
0.13
–
ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
0.01
–
0.01
–
ns
0.88
–
1.01
–
ns
Hold Times
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
Table 32: CLB Shift Register Switching Characteristics
-5
Symbol
-4
Description
Min
Max
Min
Max
Units
Time from the active edge at the CLK input to data appearing on
the shift register output
–
4.11
–
4.82
ns
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.13
–
0.18
–
ns
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
0.16
–
0.16
–
ns
0.90
–
1.01
–
ns
Clock-to-Output Times
TREG
Setup Times
TSRLDS
Hold Times
TSRLDH
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
DS529 (v2.1) December 18, 2018
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43
DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 33: Clock Distribution Switching Characteristics
Maximum
Speed Grade
Description
Symbol
Minimum
-5
-4
Units
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
TGIO
–
0.22
0.23
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
TGSI
–
0.56
0.63
ns
FBUFG
0
350
334
MHz
Frequency of signals distributed on global buffers (all sides)
Notes:
1.
44
The numbers in this table are based on the operating conditions set forth in Table 8.
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 34: 18 x 18 Embedded Multiplier Timing
Speed Grade
-5
Symbol
-4
Description
Min
Max
Min
Max
Units
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
–
4.36
–
4.88
ns
Combinatorial Delay
TMULT
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
register(2,3)
–
0.84
–
1.30
ns
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register(2,4)
–
4.44
–
4.97
ns
TMSDCK_P
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
3.56
–
3.98
–
ns
TMSDCK_A
Data setup time at the A input before the active transition at the CLK
when using the AREG input register(4)
0.00
–
0.00
–
ns
TMSDCK_B
Data setup time at the B input before the active transition at the CLK
when using the BREG input register(4)
0.00
–
0.00
–
ns
TMSCKD_P
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
0.00
–
0.00
–
ns
TMSCKD_A
Data hold time at the A input after the active transition at the CLK
when using the AREG input register(4)
0.35
–
0.45
–
ns
TMSCKD_B
Data hold time at the B input after the active transition at the CLK
when using the BREG input register(4)
0.35
–
0.45
–
ns
0
280
0
250
MHz
Setup Times
Hold Times
Clock Frequency
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
register(1)
Notes:
1.
2.
3.
4.
5.
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
The PREG register is typically used when inferring a single-stage multiplier.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
The numbers in this table are based on the operating conditions set forth in Table 8.
DS529 (v2.1) December 18, 2018
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45
DC and Switching Characteristics
Block RAM Timing
Table 35: Block RAM Timing
Speed Grade
-5
Symbol
Description
-4
Min
Max
Min
Max
Units
–
2.06
–
2.49
ns
TRCCK_ADDR Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
0.32
–
0.36
–
ns
TRDCK_DIB
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
0.28
–
0.31
–
ns
TRCCK_ENB
Setup time for the EN input before the active transition at the
CLK input of the block RAM
0.69
–
0.77
–
ns
TRCCK_WEB
Setup time for the WE input before the active transition at the
CLK input of the block RAM
1.12
–
1.26
–
ns
TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the
CLK input
0
–
0
–
ns
TRCKD_DIB
Hold time on the DIN inputs after the active transition at the
CLK input
0
–
0
–
ns
TRCKC_ENB
Hold time on the EN input after the active transition at the CLK
input
0
–
0
–
ns
TRCKC_WEB
Hold time on the WE input after the active transition at the CLK
input
0
–
0
–
ns
Clock-to-Output Times
TRCKO
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
Setup Times
Hold Times
Clock Timing
TBPWH
High pulse width of the CLK signal
1.56
–
1.79
–
ns
TBPWL
Low pulse width of the CLK signal
1.56
–
1.79
–
ns
0
320
0
280
MHz
Clock Frequency
FBRAM
Block RAM clock frequency
Notes:
1.
46
The numbers in this table are based on the operating conditions set forth in Table 8.
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Aspects of DLL operation play a role in all DCM applications.
All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables (Table 36 and Table 37) apply to any application that
only employs the DLL component. When the DFS and/or the
PS components are used together with the DLL, then the
specifications listed in the DFS and PS tables (Table 38
through Table 41) supersede any corresponding ones in the
DLL tables. DLL specifications that do not change with the
addition of DFS or PS functions are presented in Table 36
and Table 37.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays for
details.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Delay-Locked Loop (DLL)
Table 36: Recommended Operating Conditions for the DLL
Speed Grade
-5
Symbol
Description
-4
Min
Max
Min
Max
Units
Frequency of the CLKIN clock input
5(2)
280(3)
5(2)
250(3)
MHz
CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN < 150 MHz
40%
60%
40%
60%
–
FCLKIN > 150 MHz
45%
55%
45%
55%
–
FCLKIN < 150 MHz
–
±300
–
±300
ps
FCLKIN > 150 MHz
–
±150
–
±150
ps
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Input Pulse Requirements
CLKIN_PULSE
Input Clock Jitter Tolerance and Delay Path
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
Variation(4)
Cycle-to-cycle jitter at the
CLKIN input
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input
–
±1
–
±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay
from the DCM output to the CLKFB input
–
±1
–
±1
ns
Notes:
1.
2.
3.
4.
5.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 38.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
DS529 (v2.1) December 18, 2018
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47
DC and Switching Characteristics
Table 37: Switching Characteristics for the DLL
Speed Grade
-5
Symbol
Description
-4
Device
Min
Max
Min
Max
Units
All
5
280
5
250
MHz
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and CLK180 outputs
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and CLK270 outputs
5
200
5
200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
10
334
10
334
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output
0.3125
186
0.3125
166
MHz
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output
–
±100
–
±100
ps
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
±[0.5%
of CLKIN
period
+ 100]
–
±[0.5%
of CLKIN
period
+ 100]
ps
–
–
±150
–
±150
ps
±[0.5%
of CLKIN
period
+ 100]
–
±[0.5%
of CLKIN
period
+ 100]
ps
–
±[1% of
CLKIN
period
+ 350]
–
±[1% of
CLKIN
period
+ 350]
ps
–
–
±150
–
±150
ps
–
±[1% of
CLKIN
period
+ 100]
ps
–
±[1% of
CLKIN
period
+ 100]
±[1% of
CLKIN
period
+ 150]
–
±[1% of
CLKIN
period
+ 150]
ps
–
–
5
–
5
ms
–
600
–
600
µs
15
35
15
35
ps
All
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output when performing integer
division
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing non-integer
division
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, and CLKDV outputs, including the
BUFGMUX and clock tree duty-cycle distortion
All
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN and CLKFB inputs
CLKOUT_PHASE_DLL
Phase offset between DLL outputs
All
CLK0 to CLK2X
(not CLK2X180)
All others
Lock Time
LOCK_DLL(3)
When using the DLL alone: The
5 MHz < FCLKIN < 15 MHz
time from deassertion at the DCM’s
FCLKIN > 15 MHz
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase
All
Finest delay resolution, averaged over all steps
All
Delay Lines
DCM_DELAY_STEP(5)
Notes:
1.
2.
3.
4.
5.
48
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 36.
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of
“±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps.
According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
The typical delay step size is 23 ps.
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Digital Frequency Synthesizer (DFS)
Table 38: Recommended Operating Conditions for the DFS
Speed Grade
-5
Symbol
Input Frequency
FCLKIN
Description
-4
Min
Max
Min
Max
Units
0.200
333(4)
0.200
333(4)
MHz
FCLKFX < 150 MHz
–
±300
–
±300
ps
FCLKFX > 150 MHz
–
±150
–
±150
ps
–
±1
–
±1
ns
Ranges(2)
CLKIN_FREQ_FX
Input Clock Jitter
Frequency for the CLKIN input
Tolerance(3)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the CLKIN
input, based on CLKFX output
frequency
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
Notes:
1.
2.
3.
4.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 36.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
Table 39: Switching Characteristics for the DFS
Speed Grade
-5
Symbol
Description
-4
Device
Min
Max
Min
Max
Units
Frequency for the CLKFX and CLKFX180 outputs
All
5
350
5
320
MHz
Period jitter at the CLKFX and CLKFX180
outputs.
All
Typ
Max
Typ
Max
Output Frequency Ranges
CLKOUT_FREQ_FX(2)
Output Clock
Jitter(3,4)
CLKOUT_PER_JITT_FX
CLKIN
≤ 20 MHz
CLKIN
> 20 MHz
Use the Spartan-3A Jitter Calculator:
www.xilinx.com/support/documentatio
n/data_sheets/s3a_jitter_calc.zip
ps
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
ps
±[1% of
CLKFX
period
+ 350]
–
±[1% of
CLKFX
period
+ 350]
ps
–
–
±200
–
±200
ps
±[1% of
CLKFX
period
+ 200]
–
±[1% of
CLKFX
period
+ 200]
ps
–
Duty Cycle(5,6)
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
All
Phase Alignment(6)
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL
CLK0 output when both the DFS and DLL are used
All
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
All
DS529 (v2.1) December 18, 2018
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49
DC and Switching Characteristics
Table 39: Switching Characteristics for the DFS(Continued)
Speed Grade
-5
Symbol
Description
-4
Device
Min
Max
Min
Max
Units
All
–
5
–
5
ms
450
µs
Lock Time
LOCK_FX(2, 3)
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts
LOCKED when the CLKFX and CLKFX180
signals are valid. If using both the DLL and
the DFS, use the longer locking time.
5 MHz < FCLKIN
< 15 MHz
FCLKIN >
15 MHz
450
–
–
Notes:
1.
2.
3.
4.
5.
6.
50
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 38.
DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching)
on an XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB
utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the
system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
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DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Phase Shifter (PS)
Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
-5
Symbol
Description
-4
Min
Max
Min
Max
Units
1
167
1
167
MHz
40%
60%
40%
60%
-
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK)
Frequency for the PSCLK input
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
Table 41: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shift Amount
Units
CLKIN < 60
MHz
±[INTEGER(10 • (TCLKIN – 3 ns))]
steps
CLKIN ≥ 60
MHz
±[INTEGER(15 • (TCLKIN – 3 ns))]
Phase Shifting Range
MAX_STEPS(2)
Maximum allowed number of
DCM_DELAY_STEP steps for a
given CLKIN clock period, where
T = CLKIN clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
±[MAX_STEPS •
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase shifting
±[MAX_STEPS •
DCM_DELAY_STEP_MAX]
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 40.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 37.
DS529 (v2.1) December 18, 2018
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51
DC and Switching Characteristics
Miscellaneous DCM Timing
Table 42: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–
CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
N/A
seconds
N/A
N/A
seconds
N/A
N/A
minutes
N/A
N/A
minutes
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
Notes:
1.
2.
3.
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex®-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.
DNA Port Timing
Table 43: DNA_PORT Interface Timing
Symbol
Description
Min
Max
Units
TDNASSU
Setup time on SHIFT before the rising edge of CLK
1.0
–
ns
TDNASH
Hold time on SHIFT after the rising edge of CLK
0.5
–
ns
TDNADSU
Setup time on DIN before the rising edge of CLK
1.0
–
ns
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
–
ns
TDNARSU
Setup time on READ before the rising edge of CLK
5.0
10,000
ns
TDNARH
Hold time on READ after the rising edge of CLK
0
–
ns
0.5
1.5
ns
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
TDNACLKF
CLK frequency
0
100
MHz
TDNACLKH
CLK High time
1.0
∞
ns
TDNACLKL
CLK Low time
1.0
∞
ns
Notes:
1.
2.
52
The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs.
The numbers in this table are based on the operating conditions set forth in Table 8.
www.xilinx.com
DS529 (v2.1) December 18, 2018
DC and Switching Characteristics
Suspend Mode Timing
Entering Suspend Mode
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
SUSPEND Input
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
AWAKE Output
tAWAKE_GWE
tSUSPEND_GWE
Flip-Flops, Block RAM,
Distributed RAM
Write Protected
tAWAKE_GTS
tSUSPEND_GTS
Defined by SUSPEND constraint
FPGA Outputs
tSUSPEND_DISABLE
FPGA Inputs,
Interconnect
tSUSPEND_ENABLE
Blocked
DS610-3_08_061207
Figure 10: Suspend Mode Timing
Table 44: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max
Units
–
7
–
ns
+160
+300
+600
ns
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–
10
–
ns
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–
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