1
Spartan-3A DSP FPGA Family Data Sheet
DS610 October 4, 2010
Product Specification
Module 1:
Introduction and Ordering Information
DS610 (v3.0) October 4, 2010
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Introduction
Features
Architectural Overview
Configuration Overview
General I/O Capabilities
Supported Packages and Package Marking
Ordering Information
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Module 2:
Functional Description
The functionality of the Spartan®-3A DSP FPGA family is
described in the following documents.
UG331: Spartan-3 Generation FPGA User Guide
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Clocking Resources
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Digital Clock Managers (DCMs)
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Block RAM
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Configurable Logic Blocks (CLBs)
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DSP48A Application Examples
DS610 (v3.0) October 4, 2010
•
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Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
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I/O Resources
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Programmable Interconnect
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ISE® Software Design Tools and IP Cores
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Embedded Processing and Control Solutions
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Pin Types and Package Overview
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Package Drawings
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Powering FPGAs
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Power Management
UG332: Spartan-3 Generation Configuration User Guide
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Configuration Overview
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Configuration Pins and Behavior
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Bitstream Sizes
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Detailed Descriptions by Mode
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18 x 18-Bit Multipliers
48-Bit Accumulator
18-bit Pre-Adder
Module 3:
DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
•
UG431: XtremeDSP™ DSP48A for Spartan-3A DSP
FPGAs User Guide
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DSP48A Slice Design Considerations
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DSP48A Architecture Highlights
DC Electrical Characteristics
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Absolute Maximum Ratings
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Supply Voltage Specifications
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Recommended Operating Conditions
Switching Characteristics
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I/O Timing
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Configurable Logic Block (CLB) Timing
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Digital Clock Manager (DCM) Timing
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Block RAM Timing
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XtremeDSP Slice Timing
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Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS610 (v3.0) October 4, 2010
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Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
Master Serial Mode using Platform Flash PROM
Master SPI Mode using Commodity Serial Flash
Master BPI Mode using Commodity Parallel Flash
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS610 October 4, 2010
Product Specification
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1
6
Spartan-3A DSP FPGA Family:
Introduction and Ordering Information
DS610 (v3.0) October 4, 2010
Product Specification
Introduction
The Spartan®-3A DSP family of Field-Programmable Gate Arrays
(FPGAs) solves the design challenges in most high- volume,
cost-sensitive, high-performance DSP applications. The
two-member family offers densities ranging from 1.8 to 3.4 million
system gates, as shown in Table 1.
The Spartan-3A DSP family builds on the success of the
Spartan-3A FPGA family by increasing the amount of memory per
logic and adding XtremeDSP™ DSP48A slices. New features
improve system performance and reduce the cost of configuration.
These Spartan-3A DSP FPGA enhancements, combined with
proven 90 nm process technology, deliver more functionality and
bandwidth per dollar than ever before, setting the new standard in
the programmable logic and DSP processing industry.
The Spartan-3A DSP FPGAs extend and enhance the Spartan-3A
FPGA family. The XC3SD1800A and the XC3SD3400A devices
are tailored for DSP applications and have additional block RAM
and XtremeDSP DSP48A slices. The XtremeDSP DSP48A slices
replace the 18x18 multipliers found in the Spartan-3A devices and
are based on the DSP48 blocks found in the Virtex®-4 devices.
The block RAMs are also enhanced to run faster by adding an
output register. Both the block RAM and DSP48A slices in the
Spartan-3A DSP devices run at 250 MHz in the lowest cost,
standard -4 speed grade.
Because of their exceptional DSP price/performance ratio,
Spartan-3A DSP FPGAs are ideally suited to a wide range of
consumer electronics applications, such as broadband access,
home networking, display/projection, and digital television.
The Spartan-3A DSP family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost, lengthy
development cycles, and the inherent inflexibility of conventional
ASICs. Also, FPGA programmability permits design upgrades in
the field with no hardware replacement necessary, an impossibility
with ASICs.
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Dedicated 18-bit by 18-bit multiplier
Available pipeline stages for enhanced performance of at
least 250 MHz in the standard -4 speed grade
48-bit accumulator for multiply-accumulate (MAC) operation
Integrated adder for complex multiply or multiply-add
operation
Integrated 18-bit pre-adder
Optional cascaded Multiply or MAC
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
Eight low-skew global clock networks, eight additional clocks
per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
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Very low cost, high-performance DSP solution for
high-volume, cost-conscious applications
250 MHz XtremeDSP DSP48A Slices
Densities up to 53712 logic cells, including optional shift
register
Efficient wide multiplexers, wide logic, fast carry logic
IEEE 1149.1/1532 JTAG programming/debug port
Eight Digital Clock Managers (DCMs)
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Up to 519 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot swap compliance
622+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with
integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 333 Mb/s
Fully compliant 32-/64-bit, 33/66 MHz PCI support
Abundant, flexible logic resources
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Up to 2268 Kbits of fast block RAM with byte write enables
for processor applications
Up to 373 Kbits of efficient distributed RAM
Registered outputs on the block RAM with operation of at
least 280 MHz in the standard -4 speed grade
Dual-range VCCAUX supply simplifies 3.3V-only design
Suspend, Hibernate modes reduce system power
Low-power option reduces quiescent current
Multi-voltage, multi-standard SelectIO™ interface pins
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Features
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Hierarchical SelectRAM™ memory architecture
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 BPI parallel NOR Flash PROM
Low-cost Xilinx® Platform Flash with JTAG
Unique Device DNA identifier for design authentication
Load multiple bitstreams under FPGA control
Post-configuration CRC checking
MicroBlaze™ and PicoBlaze™ embedded processor cores
BGA and CSP packaging with Pb-free options
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Common footprints support easy density migration
XA Automotive version available
Table 1: Summary of Spartan-3A DSP FPGA Attributes
CLB Array (One CLB = Four Slices) Distributed
System Equivalent
Total
Total
RAM
Gates Logic Cells Rows Columns CLBs
Slices
Bits(1)
1800K
37,440
88
48
4,160
16,640
260K
3400K
53,712
104
58
5,968
23,872
373K
Device
XC3SD1800A
XC3SD3400A
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
Block
RAM
Bits(1)
1512K
2268K
DSP48As
84
126
Maximum
Maximum Differential
DCMs User I/O
I/O Pairs
8
519
227
8
469
213
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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2
Spartan-3A DSP FPGA Family: Introduction and Ordering Information
Architectural Overview
The Spartan-3A DSP family architecture consists of five fundamental programmable functional elements:
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XtremeDSP™ DSP48A Slice provides an 18-bit x
18-bit multiplier, 18-bit pre-adder, 48-bit
post-adder/accumulator, and cascade capabilities for
various DSP applications.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
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Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in Figure 1. A dual
ring of staggered IOBs surrounds a regular array of CLBs.
The XC3SD1800A has four columns of DSP48As, and the
XC3SD3400A has five columns of DSP48As. Each
DSP48A has an associated block RAM. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device and in the two outer columns of the 4 or
5 columns of block RAM and DSP48As.
The Spartan-3A DSP family features a rich network of
routing that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple
connections to the routing.
X-Ref Target - Figure 1
IOBs
DSP48A Slice
DCM
Block RAM
CLB
IOBs
CLBs
DCM
IOBs
DCM
Block RAM / DSP48A Slice
IOBs
IOBs
DS610-1_01_031207
Notes:
1.
2.
The XC3SD1800A and XC3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top and
bottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer Block RAM/DSP48A
columns of the 4 or 5 columns in the selected device, as shown in the diagram above.
A detailed diagram of the DSP48A can be found in UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide.
Figure 1: Spartan-3A DSP Family Architecture
DS610 (v3.0) October 4, 2010
Product Specification
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3
Spartan-3A DSP FPGA Family: Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3A DSP FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
The Spartan-3A DSP FPGA SelectIO interface supports
many popular single-ended and differential standards.
Table 2 shows the number of user I/Os as well as the
number of differential I/O pairs available for each
device/package combination. Some of the user I/Os are
unidirectional input-only pins as indicated in Table 2.
Spartan-3A DSP FPGAs support the following single-ended
standards:
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Master Serial from a Xilinx Platform Flash PROM
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3.3V low-voltage TTL (LVTTL)
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Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
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Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
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Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
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3.3V PCI at 33 MHz or 66 MHz
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Slave Serial, typically downloaded from a processor
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HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
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Slave Parallel, typically downloaded from a processor
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Boundary Scan (JTAG), typically downloaded from a
processor or system tester
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
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Spartan-3A DSP FPGAs support the following
differential standards:
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LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
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Bus LVDS I/O at 2.5V
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TMDS I/O at 3.3V
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Differential HSTL and SSTL I/O
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LVPECL inputs at 2.5V or 3.3V
Furthermore, Spartan-3A DSP FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Additionally, each Spartan-3A DSP FPGA contains a
unique, factory-programmed Device DNA identifier useful
for tracking purposes, anti-cloning designs, or IP protection.
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
CS484
CSG484
Device
XC3SD1800A
XC3SD3400A
FG676
FGG676
User
Diff
User
Diff
309(1)
(60)
140
(78)
519
(110)
227
(131)
309
(60)
140
(78)
469
(60)
213
(117)
Notes:
1.
The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of
input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O
banks that are restricted to differential inputs.
DS610 (v3.0) October 4, 2010
Product Specification
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4
Spartan-3A DSP FPGA Family: Introduction and Ordering Information
Package Marking
Figure 2 shows the top marking for Spartan-3A DSP FPGAs. The “5C” and “4I” Speed Grade/Temperature Range part
combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C or -4I devices. Devices
with a single mark are only guaranteed for the marked speed grade and temperature range.
X-Ref Target - Figure 2
Mask Revision
BGA Ball A1
R
SPARTAN
Device Type
Package
Low-Power
(optional)
Speed Grade
R
XC3SD1800A
CSG484XGQ####
X#######X
L4 I
Fabrication/
Process Code
Date Code
Lot Code
Operating Range
DS610-1_02_070607
Figure 2: Spartan-3A DSP FPGA Package Marking Example
Ordering Information
Spartan-3A DSP FPGAs are available in both standard and Pb-free packaging options for all device/package combinations.
The Pb-free packages include a ‘G’ character in the ordering code.
Example: XC3SD1800A -4 CS 484 LI
Device Type
Power/Temperature Range
Number of Pins
Speed Grade
Package Type
DS610-1_05_021009
Device
Speed Grade
Package Type / Number of Pins
Power/Temperature Range
(TJ )
XC3SD1800A -4 Standard Performance CS484/ 484-ball Chip-Scale Ball Grid Array (CSBGA)
CSG484
C Commercial (0°C to 85°C)
XC3SD3400A -5 High Performance(1)
I Industrial (–40°C to 100°C)
FG676/ 676-ball Fine-Pitch Ball Grid Array (FBGA)
FGG676
LI Low-power Industrial
(–40°C to 100°C)(2)
Notes:
1.
2.
3.
The -5 speed grade is exclusively available in the Commercial temperature range.
The low-power option (LI) is exclusively available in the CS(G)484 package and industrial temperature range.
See DS705, XA Spartan-3A DSP Automotive FPGA Family Data Sheet for the XA Automotive Spartan-3A DSP FPGAs.
DS610 (v3.0) October 4, 2010
Product Specification
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5
Spartan-3A DSP FPGA Family: Introduction and Ordering Information
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
04/02/07
1.0
05/25/07
1.0.1
06/18/07
1.2
Updated for Production release.
07/16/07
2.0
Added Low-power options.
06/02/08
2.1
Added reference to SCD 4103 for 750 Mbps performance. Add dual mark clarification to Package
Marking. Updated links.
03/11/09
2.2
Simplified ordering information. Removed reference to SCD 4103.
10/04/10
3.0
Updated the Notice of Disclaimer section.
Initial Xilinx release.
Minor edits.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
DS610 (v3.0) October 4, 2010
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8
Spartan-3A DSP FPGA Family:
Functional Description
DS610 (v3.0) October 4, 2010
Product Specification
Spartan-3A DSP FPGA Design Documentation
The functionality of the Spartan®-3A DSP FPGA family is described in the following documents. The topics covered in each
guide are listed.
•
DS706: Extended Spartan-3A Family Overview
•
UG331: Spartan-3 Generation FPGA User Guide
•
•
•
•
•
•
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
• I/O Resources
• Programmable Interconnect
• ISE® Software Design Tools
• IP Cores
• Embedded Processing and Control Solutions
• Pin Types and Package Overview
• Package Drawings
• Powering FPGAs
• Power Management
UG332: Spartan-3 Generation Configuration User
Guide
•
•
•
•
•
UG431: XtremeDSP DSP48A for Spartan-3A DSP
FPGAs User Guide
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XtremeDSP DSP48A Slices
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XtremeDSP DSP48A Pre-Adder
For specific hardware examples, please see the Spartan-3A
DSP FPGA Starter Kit board web pages.
Configuration Overview
- Configuration Pins and Behavior
- Bitstream Sizes
Detailed Descriptions by Mode
- Master Serial Mode using Xilinx Platform Flash
PROM
- Master SPI Mode using Commodity SPI Serial
Flash PROM
- Master BPI Mode using Commodity Parallel
NOR Flash PROM
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
•
XtremeDSP Starter Platform—Spartan-3A DSP
1800A Edition
http://www.xilinx.com/products/devkits
/HW-SD1800A-DSP-SB-UNI-G.htm
•
XtremeDSP Starter Kit—Spartan-3A DSP 1800A
Edition
http://www.xilinx.com/products/devkits
/DO-SD1800A-DSP-SK-UNI-G.htm
•
XtremeDSP Video Starter Kit—Spartan-3A DSP
Edition
http://www.xilinx.com/products/devkits
/DO-S3ADSP-VIDEO-SK-UNI-G.htm
•
Embedded Development HW/SW Kit—Spartan-3A
DSP S3D1800A MicroBlaze Processor Edition
http://www.xilinx.com/products/devkits
/DO-SD1800A-EDK-DK-UNI-G.htm
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
•
Sign Up for Alerts on Xilinx.com
https://secure.xilinx.com/webreg/register.do?group=my
profile&languageID=1
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS610 (v3.0) October 4, 2010
Product Specification
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7
Spartan-3A DSP FPGA Family: Functional Description
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
04/02/07
1.0
05/25/07
1.0.1
06/18/07
1.2
Updated for Production release.
07/16/07
2.0
Added Low-power options; no changes to this module.
06/02/08
2.1
Updated links.
03/11/09
2.2
Added link to DS706 on Extended Spartan-3A family.
10/04/10
3.0
Updated link to sign up for Alerts and updated Notice of Disclaimer.
Initial Xilinx release.
Minor edits.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
CRITICAL APPLICATIONS DISCLAIMER
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE
FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR
SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE
DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE,
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A
VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF
SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE
OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX
PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY
APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL
APPLICATIONS.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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61
Spartan-3A DSP FPGA Family:
DC and Switching Characteristics
DS610 (v3.0) October 4, 2010
Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan®-3A DSP devices. AC and DC
characteristics are specified using the same numbers
for both commercial and industrial grades.
Absolute Maximum Ratings
Stresses beyond those listed under Table 3: Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
Table 3: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Max
Units
VCCINT
Internal supply voltage
–0.5
1.32
V
VCCAUX
Auxiliary supply voltage
–0.5
3.75
V
VCCO
Output driver supply voltage
–0.5
3.75
V
VREF
Input reference voltage
–0.5
VCCO + 0.5
V
Voltage applied to all User I/O pins and
Dual-Purpose pins
–0.95
4.6
V
–0.5
4.6
V
–
±100
mA
VIN
Driver in a high-impedance state
Voltage applied to all Dedicated pins
(1)
IIK
Input clamp current per I/O pin
–0.5V < VIN < (VCCO + 0.5V)
VESD
Electrostatic Discharge Voltage
Human body model
–
±2000
V
Charged device model
–
±500
V
Machine model
–
±200
V
TJ
Junction temperature
–
125
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1.
2.
Upper clamp applies only when using PCI IOSTANDARDs.
For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
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9
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Power Supply Specifications
Table 4: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
1.0
2.0
V
VCCO2T
Threshold for the VCCO Bank 2 supply
1.0
2.0
V
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI
Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
Apply VCCINT last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more
information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 5: Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
VCCINTR
Ramp rate from GND to valid VCCINT supply level
0.2
100
ms
VCCAUXR
Ramp rate from GND to valid VCCAUX supply level
0.2
100
ms
VCCO2R
Ramp rate from GND to valid VCCO Bank 2 supply level
0.2
100
ms
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI
Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source.
Apply VCCINT last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more
information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 6: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data
Symbol
Description
Min
Units
VDRINT
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
1.0
V
VDRAUX
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
2.0
V
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10
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
General Recommended Operating Conditions
Table 7: General Recommended Operating Conditions
Symbol
TJ
Description
Min
Nominal
Max
Units
0
–
85
°C
–40
–
100
°C
Internal supply voltage
1.14
1.20
1.26
V
Output driver supply voltage
1.10
–
3.60
V
VCCAUX = 2.5
2.25
2.50
2.75
V
VCCAUX = 3.3
3.00
3.30
3.60
V
PCI™ IOSTANDARD
–0.5
–
VCCO+0.5
V
IP or IO_#
–0.5
–
4.10
V
IO_Lxxy_#(4)
–0.5
–
4.10
V
–
–
500
ns
Junction temperature
Commercial
Industrial
VCCINT
VCCO
(1)
VCCAUX
VIN(3)
Auxiliary supply
voltage(2)
Input voltage
All other
IOSTANDARDs
TIN
Input signal transition
time(5)
Notes:
1.
2.
3.
4.
5.
This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 10 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 12 lists that specific to the differential standards.
Define VCCAUX selection using CONFIG VCCAUX constraint.
See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations.
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11
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
General DC Characteristics for I/O Pins
Table 8: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (1)
Symbol
IL
(2)
IHS
Description
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Test Conditions
Min
Typ
Max
Units
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10
–
+10
µA
–10
–
+10
µA
Leakage current on pins during All pins except INIT_B, PROG_B, DONE, and JTAG pins
hot socketing, FPGA unpowered when PUDC_B = 1.
Add IHS + IRPU
INIT_B, PROG_B, DONE, and JTAG pins or other pins
when PUDC_B = 0.
IRPU(3)
RPU(3)
IRPD
(3)
RPD(3)
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
VCCAUX.
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPU per Note 2)
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPD per Note 2)
VIN = GND
VCCO or VCCAUX = 3.0V to 3.6V
–151
–315
–710
µA
VCCO or VCCAUX = 2.3V to 2.7V
–82
–182
–437
µA
VCCO = 1.7V to 1.9V
–36
–88
–226
µA
VCCO = 1.4V to 1.6V
–22
–56
–148
µA
VCCO = 1.14V to 1.26V
–11
–31
–83
µA
VCCO = 3.0V to 3.6V
5.1
11.4
23.9
kΩ
VCCO = 2.3V to 2.7V
6.2
14.8
33.1
kΩ
VCCO = 1.7V to 1.9V
8.4
21.6
52.6
kΩ
VCCO = 1.4V to 1.6V
10.8
28.4
74.0
kΩ
VCCO = 1.14V to 1.26V
15.3
41.1
119.4
kΩ
VCCAUX = 3.0V to 3.6V
167
346
659
µA
100
225
457
µA
VIN = 3.0V to 3.6V
5.5
10.4
20.8
kΩ
VIN = 2.3V to 2.7V
4.1
7.8
15.7
kΩ
VIN = 1.7V to 1.9V
3.0
5.7
11.1
kΩ
VIN = 1.4V to 1.6V
2.7
5.1
9.6
kΩ
VIN = 1.14V to 1.26V
2.4
4.5
8.1
kΩ
VIN = 3.0V to 3.6V
7.9
16.0
35.0
kΩ
VIN = 2.3V to 2.7V
5.9
12.0
26.3
kΩ
VIN = 1.7V to 1.9V
4.2
8.5
18.6
kΩ
VIN = 1.4V to 1.6V
3.6
7.2
15.7
kΩ
VIN = 1.14V to 1.26V
3.0
6.0
12.5
kΩ
All VCCO levels
–10
–
+10
µA
–
–
–
10
pF
VCCO = 3.3V ± 10%
LVDS_33, MINI_LVDS_33,
RSDS_33
90
100
115
Ω
VCCO = 2.5V ± 10%
LVDS_25, MINI_LVDS_25,
RSDS_25
90
110
–
Ω
VIN = GND
VIN = VCCO
VCCAUX = 2.25V to 2.75V
VCCAUX = 3.0V to 3.6V
VCCAUX = 2.25V to 2.75V
IREF
VREF current per pin
CIN
Input capacitance
RDT
Resistance of optional
differential termination circuit
within a differential I/O pair. Not
available on Input-only pairs.
µA
Notes:
1.
2.
3.
The numbers in this table are based on the conditions set forth in Table 7.
For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.5V is supported but can cause increased leakage
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
This parameter is based on characterization. The pull-up resistance RPU = VCCO/IRPU. The pull-down resistance RPD = VIN / IRPD.
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Quiescent Current Requirements
Table 9: Quiescent Supply Current Characteristics(1)
Symbol
ICCINTQ
Description
Quiescent VCCINT supply current
Device
Power
XC3SD1800A
Quiescent VCCO supply current
Quiescent VCCAUX supply current
Industrial
Maximum(2)
Units
41
390
500
mA
LI
36
–
175
mA
C,I
64
550
725
mA
LI
55
–
300
mA
C,I
0.4
4
5
mA
LI
0.2
–
5
mA
C,I
0.4
4
5
mA
LI
0.2
–
5
mA
XC3SD1800A
C,I
25
90
110
mA
LI
24
–
72
mA
XC3SD3400A
C,I
39
130
160
mA
LI
38
–
105
mA
XC3SD1800A
XC3SD3400A
ICCAUXQ
Commercial
Maximum(2)
C,I
XC3SD3400A
ICCOQ
Typical(2)
Notes:
1.
2.
3.
4.
5.
The numbers in this table are based on the conditions set forth in Table 7.
Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX
= 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage
limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design
with no functional elements instantiated). For conditions other than those described above (for example, a design including functional
elements), measured quiescent current levels will be different than the values in the table.
For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power
consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3A DSP FPGA XPower Estimator provides quick, approximate,
typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as
well as more accurate typical estimates.
The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
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13
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Single-Ended I/O Standards
Table 10: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
VCCO for Drivers(2)
VREF
Min (V)
Nom (V)
Max (V)
LVTTL
3.0
3.3
LVCMOS33(4)
3.0
LVCMOS25(4,5)
Min (V)
Nom (V)
VIL
Max (V)
VIH(3)
Max (V)
Min (V)
3.6
0.8
2.0
3.3
3.6
0.8
2.0
2.3
2.5
2.7
0.7
1.7
LVCMOS18
1.65
1.8
1.95
0.4
0.8
LVCMOS15
1.4
1.5
1.6
0.4
0.8
LVCMOS12
1.1
1.2
1.3
0.4
0.7
PCI33_3(6)
3.0
3.3
3.6
0.3 • VCCO
0.5 • VCCO
PCI66_3(6)
3.0
3.3
3.6
0.3 • VCCO
0.5 • VCCO
HSTL_I
1.4
1.5
1.6
0.68
0.75
0.9
VREF – 0.1
VREF + 0.1
HSTL_III
1.4
1.5
1.6
–
0.9
–
VREF – 0.1
VREF + 0.1
HSTL_I_18
1.7
1.8
1.9
0.8
0.9
1.1
VREF – 0.1
VREF + 0.1
HSTL_II_18
1.7
1.8
1.9
–
0.9
–
VREF – 0.1
VREF + 0.1
HSTL_III_18
1.7
1.8
1.9
–
1.1
–
VREF – 0.1
VREF + 0.1
SSTL18_I
1.7
1.8
1.9
0.833
0.900
0.969
VREF – 0.125
VREF + 0.125
SSTL18_II
1.7
1.8
1.9
0.833
0.900
0.969
VREF – 0.125
VREF + 0.125
SSTL2_I
2.3
2.5
2.7
1.13
1.25
1.38
VREF – 0.150
VREF + 0.150
SSTL2_II
2.3
2.5
2.7
1.13
1.25
1.38
VREF – 0.150
VREF + 0.150
SSTL3_I
3.0
3.3
3.6
1.3
1.5
1.7
VREF – 0.2
VREF + 0.2
SSTL3_II
3.0
3.3
3.6
1.3
1.5
1.7
VREF – 0.2
VREF + 0.2
VREF is not used for
these I/O standards
Notes:
1.
2.
3.
4.
5.
6.
Descriptions of the symbols used in this table are as follows:
VCCO—the supply voltage for output drivers
VREF—the reference voltage for setting the input switching threshold
VIL—the input voltage that indicates a Low logic level
VIH—the input voltage that indicates a High logic level
In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when VCCAUX = 3.3V range
and for PCI I/O standards.
For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 7.
There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS25 or
LVCMOS33 standard depending on VCCAUX. The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When
using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as
throughout configuration.
For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
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14
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 11: DC Characteristics of User I/Os Using
Single-Ended Standards (Cont’d)
Table 11: DC Characteristics of User I/Os Using
Single-Ended Standards
IOSTANDARD
Attribute
LVTTL(3)
LVCMOS33(3)
LVCMOS25(3)
LVCMOS18(3)
LVCMOS15(3)
LVCMOS12(3)
Test
Conditions
IOL
IOH
(mA) (mA)
Logic Level
Characteristics
VOL
Max (V)
VOH
Min (V)
0.4
2.4
IOSTANDARD
Attribute
Test
Conditions
IOH
IOL
(mA) (mA)
Logic Level
Characteristics
VOL
Max (V)
VOH
Min (V)
PCI33_3(4)
1.5
–0.5
10% VCCO
90% VCCO
–4
PCI66_3(4)
1.5
–0.5
10% VCCO
90% VCCO
–6
HSTL_I (5)
8
–8
0.4
VCCO – 0.4
24
–8
0.4
VCCO – 0.4
2
2
–2
4
4
6
6
(5)
8
8
–8
HSTL_III
12
12
–12
HSTL_I_18
8
–8
0.4
VCCO – 0.4
16
16
–16
HSTL_II_18(5)
16
–16
0.4
VCCO – 0.4
24
24
–24
HSTL_III_18
24
–8
0.4
VCCO – 0.4
2
2
–2
SSTL18_I
6.7
–6.7
4
4
–4
SSTL18_II(5)
13.4 –13.4 VTT – 0.603 VTT + 0.603
6
6
–6
SSTL2_I
8.1
–8.1
VTT – 0.61
VTT + 0.61
8
8
–8
SSTL2_II(5)
16.2 –16.2
VTT – 0.81
VTT + 0.81
12
12
–12
SSTL3_I
8
–8
VTT – 0.6
VTT + 0.6
16
–16
VTT – 0.8
VTT + 0.8
0.4
VCCO – 0.4
16
16
–16
SSTL3_II(5)
24(5)
24
–24
Notes:
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16(5)
16
–16
24(5)
24
–24
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12(5)
12
–12
16(5)
16
–16
2
2
–2
4
4
–4
6
6
–6
8(5)
8
–8
12(5)
12
–12
2
2
–2
4(5)
4
–4
6(5)
6
–6
DS610 (v3.0) October 4, 2010
Product Specification
0.4
VCCO – 0.4
1.
2.
3.
4.
0.4
VCCO – 0.4
5.
0.4
VCCO – 0.4
0.4
VCCO – 0.4
VTT – 0.475 VTT + 0.475
The numbers in this table are based on the conditions set forth in
Table 7 and Table 10.
Descriptions of the symbols used in this table are as follows:
IOL—the output current condition under which VOL is tested
IOH—the output current condition under which VOH is tested
VOL— the output voltage that indicates a Low logic level
VOH—the output voltage that indicates a High logic level
VCCO—the supply voltage for output drivers
VTT—the voltage applied to a resistor termination
For the LVCMOS and LVTTL standards: the same VOL and VOH
limits apply for the Fast, Slow, and QUIETIO slew attributes.
Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/products/
design_resources/conn_central/protocols/pci_pcix.htm. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the Using I/O
Resources chapter in UG331.
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15
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Differential I/O Standards
Differential Input Pairs
X-Ref Target - Figure 3
VINP
Internal
Logic
VINN
VINN
VID
50%
VINP
Differential
I/O Pair Pins
P
N
VICM
GND level
VICM = Input common mode voltage =
VINP + VINN
2
VID = Differential input voltage = VINP - VINN
DS610-3_03_061507
Figure 3: Differential Input Voltages
Table 12: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
Min (V)
VICM(2)
Nom (V)
LVDS_25(3)
2.25
2.5
2.75
100
350
600
0.3
1.25
2.35
LVDS_33(3)
3.0
3.3
3.6
100
350
600
0.3
1.25
2.35
BLVDS_25(4)
2.25
2.5
2.75
100
300
–
0.3
1.3
2.35
MINI_LVDS_25(3)
2.25
2.5
2.75
200
–
600
0.3
1.2
1.95
MINI_LVDS_33(3)
3.0
3.3
3.6
200
–
600
0.3
1.2
1.95
IOSTANDARD Attribute
VCCO for Drivers(1)
Min (V)
Nom (V)
Max (V)
VID
Min (mV) Nom (mV) Max (mV)
Max (V)
LVPECL_25(5)
Inputs Only
100
800
1000
0.3
1.2
1.95
LVPECL_33(5)
Inputs Only
100
800
1000
0.3
1.2
2.8(6)
1.5
RSDS_25(3)
2.25
2.5
2.75
100
200
–
0.3
1.2
RSDS_33(3)
3.0
3.3
3.6
100
200
–
0.3
1.2
1.5
TMDS_33(3,4,7)
3.14
3.3
3.47
150
–
1200
2.7
–
3.23
PPDS_25(3)
2.25
2.5
2.75
100
–
400
0.2
–
2.3
PPDS_33(3)
3.0
3.3
3.6
100
–
400
0.2
–
2.3
DIFF_HSTL_I_18
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_II_18(8)
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_III_18
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_I
1.4
1.5
1.6
100
–
–
0.68
–
0.9
DIFF_HSTL_III
1.4
1.5
1.6
100
–
–
–
0.9
–
DIFF_SSTL18_I
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL18_II(8)
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL2_I
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL2_II(8)
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL3_I
3.0
3.3
3.6
100
–
–
1.1
–
1.9
DIFF_SSTL3_II
3.0
3.3
3.6
100
–
–
1.1
–
1.9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The VCCO rails supply only differential output drivers, not input circuits.
VICM must be less than VCCAUX.
These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
See "External Termination Requirements for Differential I/O."
LVPECL is supported on inputs only, not outputs. LVPECL_33 requires VCCAUX = 3.3V ± 10%.
LVPECL_33 maximum VICM = the lower of 2.8V or VCCAUX – (VID/2).
Requires VCCAUX = 3.3V ±10%. (VCCAUX - 300 mV) ≤ VICM ≤ (VCCAUX - 37 mV).
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint.
DS610 (v3.0) October 4, 2010
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16
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Differential Output Pairs
X-Ref Target - Figure 4
VOUTP
Internal
Logic
Differential
I/O Pair Pins
P
N
VOUTN
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
VOCM = Output common mode voltage =
VOUTP + VOUTN
2
VOD = Output differential voltage = VOUTP - VOUTN
VOH = Output voltage indicating a High logic level
VOL = Output voltage indicating a Low logic level
DS312-3_03_090510
Figure 4: Differential Output Voltages
Table 13: DC Characteristics of User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VOD
VOCM
VOH
VOL
Min (mV)
Typ (mV)
Max (mV)
Min (V)
Typ (V)
Max (V)
Min (V)
Max (V)
LVDS_25
247
350
454
1.125
–
1.375
–
–
LVDS_33
247
350
454
1.125
–
1.375
–
–
BLVDS_25
240
350
460
–
1.30
–
–
–
MINI_LVDS_25
300
–
600
1.0
–
1.4
–
–
MINI_LVDS_33
300
–
600
1.0
–
1.4
–
–
RSDS_25
100
–
400
1.0
–
1.4
–
–
RSDS_33
100
–
400
1.0
–
1.4
–
–
TMDS_33
400
–
800
VCCO – 0.405
–
VCCO – 0.190
–
–
PPDS_25
100
–
400
0.5
0.8
1.4
–
–
PPDS_33
100
–
400
0.5
0.8
1.4
–
–
DIFF_HSTL_I_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_II_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_III_18
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_I
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_III
–
–
–
–
–
–
VCCO – 0.4
0.4
DIFF_SSTL18_I
–
–
–
–
–
–
VTT + 0.475
VTT – 0.475
DIFF_SSTL18_II
–
–
–
–
–
–
VTT + 0.603
VTT – 0.603
DIFF_SSTL2_I
–
–
–
–
–
–
VTT + 0.61
VTT – 0.61
DIFF_SSTL2_II
–
–
–
–
–
–
VTT + 0.81
VTT – 0.81
DIFF_SSTL3_I
–
–
–
–
–
–
DIFF_SSTL3_II
–
–
–
–
–
–
VTT + 0.6
VTT + 0.8
VTT - 0.6
VTT - 0.8
Notes:
1.
2.
3.
4.
The numbers in this table are based on the conditions set forth in Table 7 and Table 12.
See "External Termination Requirements for Differential I/O."
Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the differential signal pair.
At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25, PPDS_25 when
VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when VCCO = 3.3V
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17
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
X-Ref Target - Figure 5
Bank 0 and 2
Any Bank
Bank 0
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
Bank 1
1/4 th of Bourns
Part Number
Z0 = 50Ω CAT16-PT4F4
Bank 2
VCCO = 3.3V
Bank 3
Bank 0
No VCCO Restrictions
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
Bank 2
100Ω
Z0 = 50Ω
DIFF_TERM=No
a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
RDT
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
DIFF_TERM=Yes
b) Differential pairs using DIFF_TERM=Yes constraint
DS529-3_09_020107
Figure 5: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
X-Ref Target - Figure 6
Any Bank
Any Bank
Bank 0
Bank 3
Bank 2
VCCO = 2.5V
1/4 th of Bourns
Part Number
CAT16-PT4F4
Z0 = 50Ω
165Ω
140Ω
BLVDS_25
Z0 = 50Ω
Bank 1
Bank 1
1/4 th of Bourns
Part Number
CAT16-LV4F12
Bank 3
Bank 0
Bank 2
No VCCO Requirement
100Ω
BLVDS_25
165Ω
DS529-3_07_020107
Figure 6: External Output and Input Termination Resistors for BLVDS_25 I/O Standard
TMDS_33 I/O Standard
X-Ref Target - Figure 7
Any Bank
Bank 0 and 2
Bank 0
3.3V
Bank 2
50Ω
Bank 1
Bank 3
Bank 0
50Ω
Bank 2
VCCAUX = 3.3V
VCCO = 3.3V
TMDS_33
TMDS_33
DVI/HDMI cable
DS529-3_08_020107
Figure 7: External Input Resistors Required for TMDS_33 I/O Standard
Device DNA Read Endurance
Table 14: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
30,000,000
Read
cycles
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18
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Switching Characteristics
All Spartan-3A DSP FPGAs ship in two speed grades: –4
and the higher performance –5. Switching characteristics in
this document are designated as Advance, Preliminary, or
Production, as shown in Table 15. Each category is defined
as follows:
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
•
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http://www.xilinx.com/support/answers/18683.htm
Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3A DSP FPGA speed files (v1.32), part of the
Xilinx Development Software, are the original source for
many but not all of the values. The speed grade
designations for these files are shown in Table 15. For more
complete, more precise, and worst-case data, use the
values reported by the Xilinx static timing analyzer (TRACE
in the Xilinx development software) and back-annotated to
the simulation netlist.
Table 15: Spartan-3A DSP v1.32 Speed Grade
Designations
Device
Advance
Preliminary
Production
XC3SD1800A
-4, -5
XC3SD3400A
-4, -5
Table 16 provides the recent history of the Spartan-3A DSP
FPGA speed files.
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGAs designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Preview, Advance, or Preliminary should
not be used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the
FPGA design incorporates the latest timing information and
software updates.
Production designs will require updating the Xilinx ISE
development software with a future version and/or Service
Pack.
Table 16: Spartan-3A DSP Speed File Version History
Version
ISE
Release
Description
1.32
Updated DSP timing model to reflect
ISE 10.1.02 higher performance for some
implementations
1.31
ISE 10.1
Added Automotive support
1.30
ISE 9.2.03i
Added absolute minimum values
1.29
ISE 9.2.01i
Production Speed Files for -4 and -5
speed grades
1.28
ISE 9.2i
Minor updates
1.27
ISE 9.1.03i
Advance Speed Files for -4 speed grade
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3A DSP devices. AC and DC
characteristics are specified using the same numbers
for both commercial and industrial grades.
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19
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 17: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Max
Max
Units
Clock-to-Output Times
TICKOFDCM
TICKOF
LVCMOS25(2), 12 mA
output drive, Fast slew
rate, with DCM(3)
XC3SD1800A
3.28
3.51
ns
XC3SD3400A
3.36
3.82
ns
When reading from OFF, the time LVCMOS25(2), 12 mA
from the active transition on the
output drive, Fast slew
Global Clock pin to data appearing rate, without DCM
at the Output pin. The DCM is not
in use.
XC3SD1800A
5.23
5.58
ns
XC3SD3400A
5.51
6.13
ns
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 22. If the latter is true, add the appropriate Output adjustment from Table 25.
DCM output jitter is included in all measurements.
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Pin-to-Pin Setup and Hold Times
Table 18: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Max
Max
Units
Setup Times
TPSDCM
TPSFD
LVCMOS25(2),
When writing to the Input
Flip-Flop (IFF), the time from
IFD_DELAY_VALUE = 0,
the setup of data at the Input pin with DCM(4)
to the active transition at a
Global Clock pin. The DCM is in
use. No Input Delay is
programmed.
XC3SD1800A
2.65
3.11
ns
XC3SD3400A
2.25
2.49
ns
LVCMOS25(2),
IFD_DELAY_VALUE = 6,
without DCM
XC3SD1800A
2.98
3.39
ns
XC3SD3400A
2.78
3.08
ns
LVCMOS25(3),
When writing to IFF, the time
from the active transition at the IFD_DELAY_VALUE = 0,
Global Clock pin to the point
with DCM(4)
when data must be held at the
Input pin. The DCM is in use.
No Input Delay is programmed.
XC3SD1800A
–0.38
–0.38
ns
XC3SD3400A
–0.26
–0.26
ns
LVCMOS25(3),
IFD_DELAY_VALUE = 6,
without DCM
XC3SD1800A
–0.71
–0.71
ns
XC3SD3400A
–0.65
–0.65
ns
When writing to IFF, the time
from the setup of data at the
Input pin to an active transition
at the Global Clock pin. The
DCM is not in use. The Input
Delay is programmed.
Hold Times
TPHDCM
TPHFD
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not in
use. The Input Delay is
programmed.
Notes:
1.
2.
3.
4.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 22. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 22. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
DS610 (v3.0) October 4, 2010
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21
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Input Setup and Hold Times
Table 19: Setup and Hold Times for the IOB Input Path
Symbol
Description
DELAY_
VALUE
Conditions
Device
Speed
-5
-4
Units
Min
Min
XC3SD1800A
1.65
1.81
ns
XC3SD3400A
1.51
1.88
ns
XC3SD1800A
2.09
2.24
ns
2
2.67
2.83
ns
3
3.25
3.64
ns
4
3.75
4.20
ns
5
3.69
4.16
ns
6
4.47
5.09
ns
7
5.27
6.02
ns
8
5.79
6.63
ns
2.07
2.44
ns
2
2.57
3.02
ns
3
3.44
3.81
ns
4
4.01
4.39
ns
5
3.89
4.26
ns
6
4.43
5.08
ns
7
5.20
5.95
ns
8
5.70
6.55
ns
XC3SD1800A –0.63 –0.52
ns
XC3SD3400A –0.56 –0.56
ns
Setup Times
TIOPICK
TIOPICKD
Time from the setup of data at the Input LVCMOS25(2)
pin to the active transition at the ICLK
input of the Input Flip-Flop (IFF). No Input
Delay is programmed.
Time from the setup of data at the Input
pin to the active transition at the ICLK
input of the Input Flip-Flop (IFF). The
Input Delay is programmed.
IFD_DELAY_VALUE=0
LVCMOS25(2)
1
1
XC3SD3400A
Hold Times
TIOICKP
Time from the active transition at the
LVCMOS25(3)
ICLK input of the Input Flip-Flop (IFF) to
the point where data must be held at the
Input pin. No Input Delay is programmed.
DS610 (v3.0) October 4, 2010
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22
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 19: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
Description
Conditions
Time from the active transition at the
ICLK input of the Input Flip-Flop (IFF) to
the point where data must be held at the
Input pin. The Input Delay is
programmed.
LVCMOS25(3)
DELAY_
VALUE
Device
Speed
-5
-4
Min
TIOICKPD
Units
Min
1
XC3SD1800A –1.40 –1.40
ns
2
–2.11 –2.11
ns
3
–2.48 –2.48
ns
4
–2.77 –2.77
ns
5
–2.62 –2.62
ns
6
–3.06 –3.06
ns
7
–3.42 –3.42
ns
8
–3.65 –3.65
ns
1
XC3SD3400A –1.31 –1.31
ns
2
–1.88 –1.88
ns
3
–2.44 –2.44
ns
4
–2.89 –2.89
ns
5
–2.83 –2.83
ns
6
–3.33 –3.33
ns
7
–3.63 –3.63
ns
8
–3.96 –3.96
ns
1.33
ns
Set/Reset Pulse Width
TRPW_IOB Minimum pulse width to SR control input
on IOB
–
–
All
1.61
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 22.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 22. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 20: Sample Window (Source Synchronous)
Symbol
TSAMP
Description
Setup and hold
capture window of
an IOB flip-flop.
DS610 (v3.0) October 4, 2010
Product Specification
Max
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
• Answer Record 30879
Units
ps
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23
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Input Propagation Times
Table 21: Propagation Times for the IOB Input Path
Speed
Grade
Symbol
Description
Conditions
DELAY_VALUE
Device
Units
-5
-4
Max
Max
XC3SD1800A
0.51
0.53
ns
XC3SD3400A
0.73
0.93
ns
XC3SD1800A
1.29
1.62
ns
2
1.67
2.08
ns
3
1.92
2.36
ns
4
2.38
2.89
ns
5
2.61
3.17
ns
6
2.98
3.55
ns
7
3.30
3.92
ns
8
3.63
4.37
ns
9
3.31
4.02
ns
10
3.69
4.47
ns
11
3.94
4.77
ns
12
4.41
5.27
ns
13
4.67
5.56
ns
14
5.03
5.94
ns
15
5.36
6.31
ns
16
5.64
6.73
ns
1.56
1.99
ns
2
1.92
2.44
ns
3
2.18
2.72
ns
4
2.66
3.19
ns
5
2.91
3.43
ns
6
3.27
3.81
ns
7
3.59
4.17
ns
8
3.87
4.58
ns
9
3.52
4.22
ns
10
3.87
4.65
ns
11
4.14
4.94
ns
12
4.68
5.40
ns
13
4.93
5.66
ns
14
5.29
6.06
ns
15
5.61
6.43
ns
16
5.88
6.80
ns
Propagation Times
TIOPI
TIOPID
The time it takes for data to travel from
the Input pin to the I output with no input
delay programmed
LVCMOS25(2)
The time it takes for data to travel from
the Input pin to the I output with the input
delay programmed
LVCMOS25(2)
IBUF_DELAY_VALUE=0
1
1
DS610 (v3.0) October 4, 2010
Product Specification
XC3SD3400A
www.xilinx.com
24
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 21: Propagation Times for the IOB Input Path (Cont’d)
Speed
Grade
Symbol
TIOPLI
TIOPLID
Description
Conditions
The time it takes for data to travel from
the Input pin through the IFF latch to the
I output with no input delay programmed
LVCMOS25(2)
DELAY_VALUE
The time it takes for data to travel from
LVCMOS25(2)
the Input pin through the IFF latch to the
I output with the input delay programmed
Device
Units
-5
-4
Max
Max
XC3SD1800A
1.79
2.04
ns
XC3SD3400A
1.65
2.11
ns
XC3SD1800A
2.23
2.47
ns
2
2.81
3.06
ns
3
3.39
3.86
ns
4
3.89
4.43
ns
5
3.83
4.39
ns
6
4.61
5.32
ns
7
5.40
6.24
ns
8
5.93
6.86
ns
2.21
2.67
ns
2
2.71
3.25
ns
3
3.58
4.04
ns
4
4.15
4.62
ns
5
4.03
4.49
ns
6
4.57
5.31
ns
7
5.34
6.18
ns
8
5.84
6.78
ns
0
1
1
XC3SD3400A
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 22.
DS610 (v3.0) October 4, 2010
Product Specification
www.xilinx.com
25
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Input Timing Adjustments
Table 22: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
Units
-4
Table 22: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment Below
Speed Grade
-5
-4
Units
Differential Standards
Single-Ended Standards
LVTTL
0.62
0.62
ns
LVDS_25
0.76
0.76
ns
LVCMOS33
0.54
0.54
ns
LVDS_33
0.79
0.79
ns
LVCMOS25
0.00
0.00
ns
BLVDS_25
0.79
0.79
ns
0.78
0.78
ns
LVCMOS18
0.83
0.83
ns
MINI_LVDS_25
LVCMOS15
0.60
0.60
ns
MINI_LVDS_33
0.79
0.79
ns
LVCMOS12
0.31
0.31
ns
LVPECL_25
0.78
0.78
ns
0.79
0.79
ns
PCI33_3
0.41
0.41
ns
LVPECL_33
PCI66_3
0.41
0.41
ns
RSDS_25
0.79
0.79
ns
0.77
0.77
ns
HSTL_I
0.72
0.72
ns
RSDS_33
HSTL_III
0.77
0.77
ns
TMDS_33
0.79
0.79
ns
HSTL_I_18
0.69
0.69
ns
PPDS_25
0.79
0.79
ns
0.79
0.79
ns
0.74
0.74
ns
HSTL_II_18
0.69
0.69
ns
PPDS_33
HSTL_III_18
0.79
0.79
ns
DIFF_HSTL_I_18
SSTL18_I
0.71
0.71
ns
DIFF_HSTL_II_18
0.72
0.72
ns
1.05
1.05
ns
SSTL18_II
0.71
0.71
ns
DIFF_HSTL_III_18
SSTL2_I
0.68
0.68
ns
DIFF_HSTL_I
0.72
0.72
ns
1.05
1.05
ns
SSTL2_II
0.68
0.68
ns
DIFF_HSTL_III
SSTL3_I
0.78
0.78
ns
DIFF_SSTL18_I
0.71
0.71
ns
SSTL3_II
0.78
0.78
ns
DIFF_SSTL18_II
0.71
0.71
ns
DIFF_SSTL2_I
0.74
0.74
ns
DIFF_SSTL2_II
0.75
0.75
ns
DIFF_SSTL3_I
1.06
1.06
ns
DIFF_SSTL3_II
1.06
1.06
ns
Notes:
1.
2.
DS610 (v3.0) October 4, 2010
Product Specification
The numbers in this table are tested using the methodology
presented in Table 26 and are based on the operating conditions
set forth in Table 7, Table 10, and Table 12.
These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
www.xilinx.com
26
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Output Propagation Times
Table 23: Timing for the IOB Output Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Max
Max
Units
Clock-to-Output Times
TIOCKP
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.87
3.13
ns
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.78
2.91
ns
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
3.63
3.89
ns
8.62
9.65
ns
Propagation Times
TIOOP
The time it takes for data to travel from
the IOB’s O input to the Output pin
Set/Reset Times
TIOSRP
TIOGSRQ
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 25.
DS610 (v3.0) October 4, 2010
Product Specification
www.xilinx.com
27
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Three-State Output Propagation Times
Table 24: Timing for the IOB Three-State Path
Speed Grade
Symbol
Description
Conditions
Device
-5
-4
Max
Max
Units
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK
LVCMOS25, 12 mA
input of the Three-state Flip-Flop (TFF) to when output drive, Fast slew
the Output pin enters the high-impedance state rate
All
1.13
1.39
ns
TIOCKON(2)
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
All
3.08
3.35
ns
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
9.47
10.36
ns
Time from asserting TFF’s SR input to when the LVCMOS25, 12 mA
Output pin enters a high-impedance state
output drive, Fast slew
rate
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
All
1.61
1.86
ns
All
3.57
3.82
ns
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
Set/Reset Times
TIOSRHZ
TIOSRON(2)
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 7 and Table 10.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 25.
DS610 (v3.0) October 4, 2010
Product Specification
www.xilinx.com
28
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Output Timing Adjustments
Table 25: Output Timing Adjustments for IOB (Cont’d)
Table 25: Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment
Below
Units
Speed Grade
-5
-4
LVCMOS33
Single-Ended Standards
LVTTL
Slow
Fast
QuietIO
Convert Output Time from
LVCMOS25 with 12mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Slow
Add the
Adjustment
Below
Units
Speed Grade
-5
-4
2 mA
5.58
5.58
ns
2 mA
5.58
5.58
ns
4 mA
3.17
3.17
ns
4 mA
3.16
3.16
ns
6 mA
3.17
3.17
ns
6 mA
3.17
3.17
ns
8 mA
2.09
2.09
ns
8 mA
2.09
2.09
ns
12 mA
1.24
1.24
ns
12 mA
1.62
1.62
ns
16 mA
1.15
1.15
ns
24 mA
2.55(3)
2.55(3)
ns
2 mA
3.02
3.02
ns
16 mA
1.24
1.24
ns
24 mA
2.74(3)
2.74(3)
ns
2 mA
3.03
3.03
ns
4 mA
1.71
1.71
ns
4 mA
1.71
1.71
ns
6 mA
1.72
1.72
ns
6 mA
1.71
1.71
ns
8 mA
0.53
0.53
ns
8 mA
0.53
0.53
ns
12 mA
0.59
0.59
ns
12 mA
0.53
0.53
ns
16 mA
0.59
0.59
ns
16 mA
0.59
0.59
ns
24 mA
0.51
0.51
ns
24 mA
0.60
0.60
ns
2 mA
27.67
27.67
ns
2 mA
27.67
27.67
ns
4 mA
27.67
27.67
ns
4 mA
27.67
27.67
ns
6 mA
27.67
27.67
ns
6 mA
27.67
27.67
ns
8 mA
16.71
16.71
ns
8 mA
16.71
16.71
ns
12 mA
16.29
16.29
ns
12 mA
16.67
16.67
ns
16 mA
16.18
16.18
ns
16 mA
16.22
16.22
ns
24 mA
12.11
12.11
ns
24 mA
12.11
12.11
ns
DS610 (v3.0) October 4, 2010
Product Specification
Fast
QuietIO
www.xilinx.com
29
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 25: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
LVCMOS25
Slow
Fast
QuietIO
Add the
Adjustment
Below
Table 25: Output Timing Adjustments for IOB (Cont’d)
Units
Speed Grade
-5
-4
2 mA
5.33
5.33
ns
4 mA
2.81
2.81
6 mA
2.82
8 mA
Convert Output Time from
LVCMOS25 with 12mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment
Below
Units
Speed Grade
-5
-4
2 mA
4.48
4.48
ns
ns
4 mA
3.69
3.69
ns
2.82
ns
6 mA
2.91
2.91
ns
1.14
1.14
ns
8 mA
1.99
1.99
ns
12 mA
1.10
1.10
ns
12 mA
1.57
1.57
ns
16 mA
0.83
0.83
ns
16 mA
1.19
1.19
ns
24 mA
2.26(3)
2.26(3)
ns
2 mA
3.96
3.96
ns
2 mA
4.36
4.36
ns
4 mA
2.57
2.57
ns
4 mA
1.76
1.76
ns
6 mA
1.90
1.90
ns
6 mA
1.25
1.25
ns
8 mA
1.06
1.06
ns
8 mA
0.38
0.38
ns
12 mA
0.83
0.83
ns
12 mA
0.00
0.00
ns
16 mA
0.63
0.63
ns
16 mA
0.01
0.01
ns
2 mA
24.97
24.97
ns
24 mA
0.01
0.01
ns
4 mA
24.97
24.97
ns
2 mA
25.92
25.92
ns
6 mA
24.08
24.08
ns
4 mA
25.92
25.92
ns
8 mA
16.43
16.43
ns
6 mA
25.92
25.92
ns
12 mA
14.52
14.52
ns
8 mA
15.57
15.57
ns
16 mA
13.41
13.41
ns
12 mA
15.59
15.59
ns
2 mA
5.82
5.82
ns
16 mA
14.27
14.27
ns
4 mA
3.97
3.97
ns
24 mA
11.37
11.37
ns
6 mA
3.21
3.21
ns
8 mA
2.53
2.53
ns
12 mA
2.06
2.06
ns
2 mA
5.23
5.23
ns
4 mA
3.05
3.05
ns
6 mA
1.95
1.95
ns
8 mA
1.60
1.60
ns
12 mA
1.30
1.30
ns
2 mA
34.11
34.11
ns
4 mA
25.66
25.66
ns
6 mA
24.64
24.64
ns
8 mA
22.06
22.06
ns
12 mA
20.64
20.64
ns
LVCMOS18
Slow
Fast
QuietIO
LVCMOS15
Slow
Fast
QuietIO
DS610 (v3.0) October 4, 2010
Product Specification
www.xilinx.com
30
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 25: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Add the
Adjustment
Below
Table 25: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12mA Drive
and Fast Slew Rate to the
Following Signal Standard
(IOSTANDARD)
Units
Speed Grade
-4
LVDS_25
1.16
1.16
ns
ns
LVDS_33
0.46
0.46
ns
6.77
ns
BLVDS_25
0.11
0.11
ns
5.02
5.02
ns
MINI_LVDS_25
0.75
0.75
ns
6 mA
4.09
4.09
ns
MINI_LVDS_33
0.40
0.40
ns
2 mA
50.76
50.76
ns
LVPECL_25
4 mA
43.17
43.17
ns
LVPECL_33
6 mA
37.31
37.31
ns
RSDS_25
1.42
1.42
ns
PCI33_3
0.34
0.34
ns
RSDS_33
0.58
0.58
ns
PCI66_3
0.34
0.34
ns
TMDS_33
0.46
0.46
ns
HSTL_I
0.78
0.78
ns
PPDS_25
1.07
1.07
ns
HSTL_III
1.16
1.16
ns
PPDS_33
0.63
0.63
ns
HSTL_I_18
0.35
0.35
ns
DIFF_HSTL_I_18
0.43
0.43
ns
HSTL_II_18
0.30
0.30
ns
DIFF_HSTL_II_18
0.41
0.41
ns
HSTL_III_18
0.47
0.47
ns
DIFF_HSTL_III_18
0.36
0.36
ns
SSTL18_I
0.40
0.40
ns
DIFF_HSTL_I
1.01
1.01
ns
SSTL18_II
0.30
0.30
ns
DIFF_HSTL_III
0.54
0.54
ns
SSTL2_I
0.00
0.00
ns
DIFF_SSTL18_I
0.49
0.49
ns
SSTL2_II
–0.05
–0.05
ns
DIFF_SSTL18_II
0.41
0.41
ns
SSTL3_I
0.00
0.00
ns
DIFF_SSTL2_I
0.82
0.82
ns
SSTL3_II
0.17
0.17
ns
DIFF_SSTL2_II
0.09
0.09
ns
DIFF_SSTL3_I
1.16
1.16
ns
DIFF_SSTL3_II
0.28
0.28
ns
Slow
Fast
QuietIO
-4
2 mA
7.14
7.14
ns
Differential Standards
4 mA
4.87
4.87
ns
6 mA
5.67
5.67
2 mA
6.77
4 mA
Units
Speed Grade
-5
LVCMOS12
-5
Add the
Adjustment
Below
Inputs Only
Notes:
1.
2.
3.
DS610 (v3.0) October 4, 2010
Product Specification
The numbers in this table are tested using the methodology
presented in Table 26 and are based on the operating conditions
set forth in Table 7, Table 10, and Table 12.
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Note that 16 mA drive is faster than 24 mA drive for the Slow
slew rate.
www.xilinx.com
31
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Timing Measurement Methodology
LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an
open connection, and VT is set to zero. The same
measurement point (VM) that was used at the Input is also
used at the Output.
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 26 lists the conditions to use for each
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (VM) is commonly located halfway between VL
and VH.
X-Ref Target - Figure 8
VT (VREF)
FPGA Output
RT (RREF)
VM (VMEAS)
CL (CREF)
The Output test setup is shown in Figure 8. A termination
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard,
RT and VT generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
DS312-3_04_102406
Notes:
1.
The names shown in parentheses are
used in the IBIS file.
Figure 8: Output Test Setup
Table 26: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Inputs and
Outputs
Outputs(2)
Inputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
LVTTL
–
0
3.3
1M
0
1.4
LVCMOS33
–
0
3.3
1M
0
1.65
LVCMOS25
–
0
2.5
1M
0
1.25
LVCMOS18
–
0
1.8
1M
0
0.9
LVCMOS15
–
0
1.5
1M
0
0.75
LVCMOS12
–
0
1.2
1M
0
0.6
–
Note 3
Note 3
25
0
0.94
25
3.3
2.03
25
0
0.94
25
3.3
2.03
Single-Ended
PCI33_3
Rising
Falling
PCI66_3
Rising
–
Note 3
Note 3
Falling
HSTL_I
0.75
VREF – 0.5
VREF + 0.5
50
0.75
VREF
HSTL_III
0.9
VREF – 0.5
VREF + 0.5
50
1.5
VREF
HSTL_I_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
HSTL_II_18
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
SSTL18_I
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
SSTL2_I
1.25
VREF – 0.75
VREF + 0.75
50
1.25
VREF
SSTL2_II
1.25
VREF – 0.75
VREF + 0.75
25
1.25
VREF
SSTL3_I
1.5
VREF – 0.75
VREF + 0.75
50
1.5
VREF
SSTL3_II
1.5
VREF – 0.75
VREF + 0.75
25
1.5
VREF
DS610 (v3.0) October 4, 2010
Product Specification
www.xilinx.com
32
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 26: Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard
(IOSTANDARD)
Inputs and
Outputs
Outputs(2)
Inputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
LVDS_25
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVDS_33
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
BLVDS_25
–
VICM – 0.125
VICM + 0.125
1M
0
VICM
MINI_LVDS_25
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
MINI_LVDS_33
–
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVPECL_25
–
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
LVPECL_33
–
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
RSDS_25
–
VICM – 0.1
VICM + 0.1
50
1.2
VICM
RSDS_33
–
VICM – 0.1
VICM + 0.1
50
1.2
VICM
TMDS_33
–
VICM – 0.1
VICM + 0.1
50
3.3
VICM
PPDS_25
–
VICM – 0.1
VICM + 0.1
50
0.8
VICM
PPDS_33
–
VICM – 0.1
VICM + 0.1
50
0.8
VICM
DIFF_HSTL_I_18
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_II_18
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_III_18
–
VICM – 0.5
VICM + 0.5
50
1.8
VICM
DIFF_HSTL_I
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_HSTL_III
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL18_I
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL18_II
–
VICM – 0.5
VICM + 0.5
50
0.9
VICM
DIFF_SSTL2_I
–
VICM – 0.5
VICM + 0.5
50
1.25
VICM
DIFF_SSTL2_II
–
VICM – 0.5
VICM + 0.5
50
1.25
VICM
DIFF_SSTL3_I
–
VICM – 0.5
VICM + 0.5
50
1.5
VICM
DIFF_SSTL3_II
–
VICM – 0.5
VICM + 0.5
50
1.5
VICM
Differential
Notes:
1.
2.
3.
Descriptions of the relevant symbols are:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
VT – Termination voltage
The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
According to the PCI specification. For information on PCI IP solutions, see www.xilinx.com/pci. The PCIX IOSTANDARD is available and
has equivalent characteristics but no PCI-X IP is supported.
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
DS610 (v3.0) October 4, 2010
Product Specification
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33
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (VREF, RREF, and VMEAS) correspond directly
with the parameters used in Table 26 (VT, RT, and VM). Do
not confuse VREF (the termination voltage) from the IBIS
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
www.xilinx.com/support/download/index.htm
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 8.
Use parameter values VT, RT, and VM from Table 26.
CREF is zero.
2. Record the time to VM.
3. Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including VREF, RREF, CREF,
and VMEAS values) or capacitive value to represent the
load.
4. Record the time to VMEAS.
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 25) to
yield the worst-case delay of the PCB trace.
Simultaneously Switching Output
Guidelines
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 27 and Table 28 provide the essential SSO
guidelines. For each device/package combination, Table 27
provides the number of equivalent VCCO/GND pairs. The
equivalent number of pairs is based on characterization and
may not match the physical number of pairs. For each
output signal standard and drive strength, Table 28
recommends the maximum number of SSOs, switching in
the same direction, allowed per VCCO/GND pair within an
I/O bank. The guidelines in Table 28 are categorized by
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
Multiply the appropriate numbers from Table 27 and
Table 28 to calculate the maximum number of SSOs
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table 27 x Table 28
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The SSO values assume that the VCCAUX is powered at
3.3V. Setting VCCAUX to 2.5V provides better SSO
characteristics.
Table 27: Equivalent VCCO/GND Pairs per Bank
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Device
Package Style (including Pb-free)
CS484
FG676
XC3SD1800A
6
9
XC3SD3400A
6
10
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
DS610 (v3.0) October 4, 2010
Product Specification
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34
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 28: Recommended Simultaneously Switching
Outputs per VCCO/GND Pair (VCCAUX = 3.3V)
Table 28: Recommended Simultaneously Switching
Outputs per VCCO/GND Pair (VCCAUX = 3.3V) (Cont’d)
Package Type
Package Type
Signal Standard
(IOSTANDARD)
Top, Bottom
Left, Right
(Banks 0, 2)
(Banks 1, 3)
LVCMOS33
Single-Ended Standards
LVTTL
Slow
Fast
QuietIO
DS610 (v3.0) October 4, 2010
Product Specification
Signal Standard
(IOSTANDARD)
CS484, FG676
Slow
CS484, FG676
Top, Bottom
Left, Right
(Banks 0, 2)
(Banks 1, 3)
2
76
76
2
60
60
4
46
46
4
41
41
6
27
27
6
29
29
8
20
20
8
22
22
12
13
13
12
13
13
16
10
10
16
11
11
24
–
9
24
9
9
2
10
10
2
10
10
4
8
8
4
6
6
6
5
5
6
5
5
8
4
4
8
3
3
12
4
4
12
3
3
16
2
2
16
3
3
24
–
2
24
2
2
2
76
76
2
80
80
4
46
46
4
48
48
6
32
32
6
36
36
8
26
26
8
27
27
12
18
18
12
16
16
16
14
14
16
13
13
24
–
10
24
12
12
Fast
QuietIO
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35
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 28: Recommended Simultaneously Switching
Outputs per VCCO/GND Pair (VCCAUX = 3.3V) (Cont’d)
Table 28: Recommended Simultaneously Switching
Outputs per VCCO/GND Pair (VCCAUX = 3.3V) (Cont’d)
Package Type
Signal Standard
(IOSTANDARD)
LVCMOS25
Slow
Fast
QuietIO
Package Type
CS484, FG676
Top, Bottom
Left, Right
(Banks 0, 2)
(Banks 1, 3)
2
76
76
4
46
6
Signal Standard
(IOSTANDARD)
Top, Bottom
Left, Right
(Banks 0, 2)
(Banks 1, 3)
2
64
64
46
4
34
34
33
33
6
22
22
8
24
24
8
18
18
12
18
18
12
–
13
16
–
11
16
–
10
24
–
7
2
18
18
2
18
18
4
9
9
4
14
14
6
7
7
6
6
6
8
4
4
8
6
6
12
–
4
12
3
3
16
–
3
16
–
3
2
64
64
24
–
2
4
64
64
2
76
76
6
48
48
4
60
60
8
36
36
6
48
48
12
–
36
8
36
36
16
–
24
12
36
36
2
55
55
16
–
36
4
31
31
24
–
8
6
18
18
8
–
15
12
–
10
2
25
25
4
10
10
6
6
6
8
–
4
12
–
3
2
70
70
4
40
40
6
31
31
8
–
31
12
–
20
LVCMOS18
Slow
Fast
QuietIO
LVCMOS15
Slow
Fast
QuietIO
DS610 (v3.0) October 4, 2010
Product Specification
CS484, FG676
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36
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 28: Recommended Simultaneously Switching
Outputs per VCCO/GND Pair (VCCAUX = 3.3V) (Cont’d)
Table 28: Recommended Simultaneously Switching
Outputs per VCCO/GND Pair (VCCAUX = 3.3V) (Cont’d)
Package Type
Signal Standard
(IOSTANDARD)
Package Type
CS484, FG676
Signal Standard
(IOSTANDARD)
CS484, FG676
Top, Bottom
Left, Right
(Banks 0, 2)
(Banks 1, 3)
2
40
40
Differential Standards (Number of I/O Pairs or Channels)
4
–
25
LVDS_25
22
–
6
–
18
LVDS_33
27
–
2
31
31
BLVDS_25
4
4
4
–
13
MINI_LVDS_25
22
–
6
–
9
MINI_LVDS_33
27
–
2
55
55
LVPECL_25
Inputs Only
4
–
36
LVPECL_33
Inputs Only
6
–
36
RSDS_25
22
–
PCI33_3
16
16
RSDS_33
27
–
PCI66_3
–
13
TMDS_33
27
–
HSTL_I
–
20
PPDS_25
22
–
HSTL_III
–
8
PPDS_33
27
–
HSTL_I_18
17
17
DIFF_HSTL_I_18
8
8
HSTL_II_18
–
5
DIFF_HSTL_II_18
–
2
HSTL_III_18
10
8
DIFF_HSTL_III_18
5
4
SSTL18_I
7
15
DIFF_HSTL_I
–
10
SSTL18_II
–
9
DIFF_HSTL_III
–
4
SSTL2_I
18
18
DIFF_SSTL18_I
3
7
SSTL2_II
–
9
DIFF_SSTL18_II
–
4
SSTL3_I
8
10
DIFF_SSTL2_I
9
9
SSTL3_II
6
7
DIFF_SSTL2_II
–
4
DIFF_SSTL3_I
4
5
DIFF_SSTL3_II
3
3
LVCMOS12
Slow
Fast
QuietIO
Top, Bottom
Left, Right
(Banks 0, 2)
(Banks 1, 3)
Notes:
1.
2.
3.
DS610 (v3.0) October 4, 2010
Product Specification
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
The numbers in this table are recommendations that assume
sound board lay out practice. This table assumes the following
parasitic factors: combined PCB trace and land inductance per
VCCO and GND pin of 1.0 nH, receiver capacitive load of 15 pF.
Test limits are the VIL/VIH voltage limits for the respective I/O
standard.
If more than one signal standard is assigned to the I/Os of a
given bank, refer to XAPP689: Managing Ground Bounce in
Large FPGAs for information on how to perform weighted
average SSO calculations.
www.xilinx.com
37
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 29: CLB (SLICEM) Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
–
0.60
–
0.68
ns
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.18
–
0.36
–
ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
1.58
–
1.88
–
ns
TAH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
0.00
–
0.00
–
ns
TCKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
0.00
–
0.00
–
ns
TCH
The High pulse width of the CLB’s CLK signal
0.63
–
0.75
–
ns
TCL
The Low pulse width of the CLK signal
0.63
–
0.75
–
ns
FTOG
Toggle frequency (for export control)
0
770
0
667
MHz
The time it takes for data to travel from the CLB’s
F (G) input to the X (Y) output
–
0.62
–
0.71
ns
1.33
–
1.61
–
ns
Clock-to-Output Times
TCKO
Setup Times
Hold Times
Clock Timing
Propagation Times
TILO
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 7.
DS610 (v3.0) October 4, 2010
Product Specification
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 30: CLB Distributed RAM Switching Characteristics
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
–
1.44
–
1.72
ns
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
Setup Times
TDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
–0.07
–
–0.02
–
ns
TAS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
0.18
–
0.36
–
ns
TWS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
0.30
–
0.59
–
ns
TDH
Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM
0.13
–
0.13
–
ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
0.01
–
0.01
–
ns
0.88
–
1.01
–
ns
Hold Times
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
Table 31: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
–
4.11
–
4.82
ns
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.13
–
0.18
–
ns
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
0.16
–
0.16
–
ns
0.90
–
1.01
–
ns
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on
the shift register output
Setup Times
TSRLDS
Hold Times
TSRLDH
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
DS610 (v3.0) October 4, 2010
Product Specification
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39
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 32: Clock Distribution Switching Characteristics
Maximum
Symbol
Description
Minimum
Speed Grade
-5
-4
Units
TGIO
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
–
0.22
0.23
ns
TGSI
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
–
0.56
0.63
ns
FBUFG
Frequency of signals distributed on global buffers (all sides)
0
350
334
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 7.
DS610 (v3.0) October 4, 2010
Product Specification
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40
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Block RAM Timing
Table 33: Block RAM Timing
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
TRCKO_DOA_NC When reading from block RAM, the delay from the active transition at
the CLK input to data appearing at the DOUT output
–
2.38
–
2.80
ns
TRCKO_DOA
–
1.24
–
1.45
ns
Clock-to-Output Times
Clock CLK to DOUT output (with output register)
Setup Times
TRCCK_ADDR
Setup time for the ADDR inputs before the active transition at the CLK
input of the block RAM
0.40
–
0.46
–
ns
TRDCK_DIB
Setup time for data at the DIN inputs before the active transition at the
CLK input of the block RAM
0.29
–
0.33
–
ns
TRCCK_ENB
Setup time for the EN input before the active transition at the CLK input
of the block RAM
0.51
–
0.60
–
ns
TRCCK_WEB
Setup time for the WE input before the active transition at the CLK input
of the block RAM
0.64
–
0.75
–
ns
TRCCK_REGCE
Setup time for the CE input before the active transition at the CLK input
of the block RAM
0.34
–
0.40
–
ns
TRCCK_RST
Setup time for the RST input before the active transition at the CLK
input of the block RAM
0.22
–
0.25
–
ns
TRCKC_ADDR
Hold time on the ADDR inputs after the active transition at the CLK
input
0.09
–
0.10
–
ns
TRCKC_DIB
Hold time on the DIN inputs after the active transition at the CLK input
0.09
–
0.10
–
ns
TRCKC_ENB
Hold time on the EN input after the active transition at the CLK input
0.09
–
0.10
–
ns
TRCKC_WEB
Hold time on the WE input after the active transition at the CLK input
0.09
–
0.10
–
ns
TRCKC_REGCE
Hold time on the CE input after the active transition at the CLK input
0.09
–
0.10
–
ns
TRCKC_RST
Hold time on the RST input after the active transition at the CLK input
0.09
–
0.10
–
ns
TBPWH
High pulse width of the CLK signal
1.56
–
1.79
–
ns
TBPWL
Low pulse width of the CLK signal
1.56
–
1.79
–
ns
0
320
0
280
MHz
Hold Times
Clock Timing
Clock Frequency
FBRAM
Block RAM clock frequency
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 7.
DS610 (v3.0) October 4, 2010
Product Specification
www.xilinx.com
41
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DSP48A Timing
To reference the DSP48A block diagram, see UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide.
Table 34: Setup Times for the DSP48A
Speed Grade
Symbol
Description
Pre-adder
Multiplier
Post-adder
-5
-4
Min
Min
Units
Setup Times of Data/Control Pins to the Input Register Clock
TDSPDCK_AA
A input to A register CLK
–
–
–
0.04
0.04
ns
TDSPDCK_DB
D input to B register CLK
Yes
–
–
1.64
1.88
ns
TDSPDCK_CC
C input to C register CLK
–
–
–
0.05
0.05
ns
TDSPDCK_DD
D input to D register CLK
–
–
–
0.04
0.04
ns
TDSPDCK_OPB
OPMODE input to B register CLK
Yes
–
–
0.37
0.42
ns
TDSPDCK_OPOP
OPMODE input to OPMODE register CLK
–
–
–
0.06
0.06
ns
Setup Times of Data Pins to the Pipeline Register Clock
TDSPDCK_AM
A input to M register CLK
–
Yes
–
3.30
3.79
ns
TDSPDCK_BM
B input to M register CLK
Yes
Yes
–
4.33
4.97
ns
No
Yes
–
3.30
3.79
ns
TDSPDCK_DM
D input to M register CLK
Yes
Yes
–
4.41
5.06
ns
TDSPDCK_OPM
OPMODE to M register CLK
Yes
Yes
–
4.72
5.42
ns
Setup Times of Data/Control Pins to the Output Register Clock
TDSPDCK_AP
A input to P register CLK
–
Yes
Yes
4.78
5.49
ns
TDSPDCK_BP
B input to P register CLK
Yes
Yes
Yes
5.87
6.74
ns
No
Yes
Yes
4.77
5.48
ns
TDSPDCK_DP
D input to P register CLK
Yes
Yes
Yes
5.95
6.83
ns
TDSPDCK_CP
C input to P register CLK
–
–
Yes
1.90
2.18
ns
TDSPDCK_OPP
OPMODE input to P register CLK
Yes
Yes
Yes
6.25
7.18
ns
Notes:
1.
2.
"Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not
applicable.
The numbers in this table are based on the operating conditions set forth in Table 7.
DS610 (v3.0) October 4, 2010
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42
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 35: Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A
Speed Grade
Symbol
Description
Pre-adder
Multiplier Post-adder
-5
-4
Max
Max
Units
Clock to Out from Output Register Clock to Output Pin
TDSPCKO_PP
CLK (PREG) to P output
–
–
–
1.26
1.44
ns
–
Yes
Yes
3.16
3.63
ns
–
Yes
No
1.94
2.23
ns
Clock to Out from Pipeline Register Clock to Output Pins
TDSPCKO_PM
CLK (MREG) to P output
Clock to Out from Input Register Clock to Output Pins
TDSPCKO_PA
CLK (AREG) to P output
–
Yes
Yes
6.33
7.27
ns
TDSPCKO_PB
CLK (BREG) to P output
Yes
Yes
Yes
7.45
8.56
ns
TDSPCKO_PC
CLK (CREG) to P output
–
–
Yes
3.37
3.87
ns
TDSPCKO_PD
CLK (DREG) to P output
Yes
Yes
Yes
7.33
8.42
ns
–
No
Yes
2.78
3.19
ns
–
Yes
No
4.60
5.28
ns
–
Yes
Yes
5.65
6.49
ns
Yes
No
No
3.49
4.01
ns
Yes
Yes
No
5.79
6.65
ns
Yes
Yes
Yes
6.74
7.74
ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_AP
TDSPDO_BP
TDSPDO_BP
A or B input to P output
B input to P output
TDSPDO_CP
C input to P output
–
–
Yes
2.76
3.17
ns
TDSPDO_DP
D input to P output
Yes
Yes
Yes
6.81
7.82
ns
TDSPDO_OPP
OPMODE input to P output
Yes
Yes
Yes
7.12
8.18
ns
Yes
Yes
Yes
287
250
MHz
Maximum Frequency
FMAX
All registers used
Notes:
1.
2.
3.
To reference the DSP48A block diagram, see UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide.
"Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not
applicable.
The numbers in this table are based on the operating conditions set forth in Table 7.
DS610 (v3.0) October 4, 2010
Product Specification
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43
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Aspects of DLL operation play a role in all DCM
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
DLL tables (Table 36 and Table 37) apply to any application
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
(Table 38 through Table 41) supersede any corresponding
ones in the DLL tables. DLL specifications that do not
change with the addition of DFS or PS functions are
presented in Table 36 and Table 37.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469:
Spread-Spectrum Clocking Reception for Displays for
details.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Delay-Locked Loop (DLL)
Table 36: Recommended Operating Conditions for the DLL
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
Frequency of the CLKIN clock input
5(2)
280(3)
5(2)
250(3)
MHz
CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN < 150 MHz
40%
60%
40%
60%
–
FCLKIN > 150 MHz
45%
55%
45%
55%
–
FCLKIN < 150 MHz
–
±300
–
±300
ps
FCLKIN > 150 MHz
–
±150
–
±150
ps
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Input Pulse Requirements
CLKIN_PULSE
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
Cycle-to-cycle jitter at the
CLKIN input
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input
–
±1
–
±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay
from the DCM output to the CLKFB input
–
±1
–
±1
ns
Notes:
1.
2.
3.
4.
5.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 38.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
DS610 (v3.0) October 4, 2010
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 37: Switching Characteristics for the DLL
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
5
280
5
250
MHz
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and CLK180 outputs
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and CLK270 outputs
5
200
5
200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
10
334
10
334
MHz
0.3125
186
0.3125
166
MHz
–
±100
–
±100
ps
CLKOUT_FREQ_DV
Output Clock Jitter
All
Frequency for the CLKDV output
(2)(3)(4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output
All
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output
–
±150
–
±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
–
±[0.5%
of
CLKIN
period
+ 100]
–
±[0.5%
of
CLKIN
period
+ 100]
ps
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output when performing
integer division
–
±150
–
±150
ps
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing
non-integer division
–
±[0.5%
of
CLKIN
period
+ 100]
–
±[0.5%
of
CLKIN
period
+ 100]
ps
All
–
±[1% of
CLKIN
period
+ 350]
–
±[1% of
CLKIN
period
+ 350]
ps
All
–
±150
–
±150
ps
CLK0 to CLK2X
(not CLK2X180)
–
±[1% of
CLKIN
period
+ 100]
–
±[1% of
CLKIN
period
+ 100]
ps
All others
–
±[1% of
CLKIN
period
+ 150]
–
±[1% of
CLKIN
period
+ 150]
ps
–
5
–
5
ms
–
600
–
600
µs
Duty Cycle (4)
CLKOUT_DUTY_CYCLE_ Duty cycle variation for the CLK0, CLK90, CLK180,
DLL
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
Phase Alignment (4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN and CLKFB inputs
CLKOUT_PHASE_DLL
Phase offset between DLL
outputs
Lock Time
LOCK_DLL(3)
When using the DLL alone:
The time from deassertion at
the DCM’s Reset input to the
rising transition at its LOCKED
output. When the DCM is
locked, the CLKIN and CLKFB
signals are in phase
DS610 (v3.0) October 4, 2010
Product Specification
5 MHz < FCLKIN <
15 MHz
FCLKIN > 15 MHz
All
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 37: Switching Characteristics for the DLL (Cont’d)
Speed Grade
Symbol
Description
Device
-5
-4
Units
Min
Max
Min
Max
15
35
15
35
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, averaged over all steps
All
ps
Notes:
1.
2.
3.
4.
5.
The numbers in this table are based on the operating conditions set forth in Table 7 and Table 36.
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of ±[1% of CLKIN period + 150]. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps, averaged over all steps.
The typical delay step size is 23 ps.
Digital Frequency Synthesizer (DFS)
Table 38: Recommended Operating Conditions for the DFS
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
0.2
333(5)
0.2
333(5)
MHz
FCLKFX < 150 MHz
–
±300
–
±300
ps
FCLKFX > 150 MHz
–
±150
–
±150
ps
–
±1
–
±1
ns
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Input Clock Jitter
Frequency for the CLKIN input
Tolerance(3)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
Notes:
1.
2.
3.
4.
5.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 36.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
DS610 (v3.0) October 4, 2010
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46
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Table 39: Switching Characteristics for the DFS
Speed Grade
Symbol
Description
-5
Device
-4
Units
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX (2)
Output Clock Jitter
Frequency for the CLKFX and CLKFX180 outputs
All
5
350
5
311
Period jitter at the CLKFX and
CLKFX180 outputs.
All
Typ
Max
Typ
Max
MHz
(3)(4)
CLKOUT_PER_JITT_FX
≤
CLKIN
20 MHz
Use the Spartan-3A Jitter Calculator:
ps
www.xilinx.com/support/documentation/
data_sheets/s3a_jitter_calc.zip
CLKIN
> 20 MHz
±[1% of ±[1% of ±[1% of ±[1% of
CLKFX CLKFX CLKFX CLKFX
period period period period
+ 100] + 200] + 100] + 200]
ps
Duty Cycle (5)(6)
CLKOUT_DUTY_CYCLE_ Duty cycle precision for the CLKFX and CLKFX180
FX
outputs, including the BUFGMUX and clock tree
duty-cycle distortion
All
–
±[1% of
CLKFX
period
+ 350]
–
±[1% of
CLKFX
period
+ 350]
ps
Phase offset between the DFS CLKFX output and the
DLL CLK0 output when both the DFS and DLL are used
All
–
±200
–
±200
ps
CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and
the DLL CLK0 output when both the DFS and DLL are
used
All
–
±[1% of
CLKFX
period
+ 200]
–
±[1% of
CLKFX
period
+ 200]
ps
All
–
5
–
5
ms
–
450
–
450
µs
Phase Alignment (6)
CLKOUT_PHASE_FX
Lock Time
LOCK_FX (2)(3)
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
valid. If using both the DLL and the
DFS, use the longer locking time.
5 MHz < FCLKIN
< 15 MHz
FCLKIN >
15 MHz
Notes:
1.
2.
3.
4.
5.
6.
The numbers in this table are based on the operating conditions set forth in Table 7 and Table 38.
DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching)
on an FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization,
CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system
application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
DS610 (v3.0) October 4, 2010
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
Symbol
Description
-5
-4
Units
Min
Max
Min
Max
1
167
1
167
MHz
40%
60%
40%
60%
–
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK)
Frequency for the PSCLK input
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
Table 41: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shift Amount
Units
CLKIN < 60 MHz
±[INTEGER(10 • (TCLKIN – 3 ns))]
steps
CLKIN ≥ 60 MHz
±[INTEGER(15 • (TCLKIN – 3 ns))]
Phase Shifting Range
MAX_STEPS (2,3)
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double
the effective clock period.
Minimum guaranteed delay for variable phase shifting
±[MAX_STEPS •
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
±[MAX_STEPS •
DCM_DELAY_STEP_MAX]
ns
FINE_SHIFT_RANGE_MIN
Notes:
1.
2.
3.
The numbers in this table are based on the operating conditions set forth in Table 7 and Table 40.
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of Table 37.
Miscellaneous DCM Timing
Table 42: Miscellaneous DCM Timing
Symbol
DCM_RST_PW_MIN
DS610 (v3.0) October 4, 2010
Product Specification
Description
Minimum duration of a RST pulse width
Min
Max
Units
3
–
CLKIN
cycles
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
DNA Port Timing
Table 43: DNA_PORT Interface Timing
Symbol
Description
Min
Max
Units
TDNASSU
Setup time on SHIFT before the rising edge of CLK
1.0
–
ns
TDNASH
Hold time on SHIFT after the rising edge of CLK
0.5
–
ns
TDNADSU
Setup time on DIN before the rising edge of CLK
1.0
–
ns
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
–
ns
TDNARSU
Setup time on READ before the rising edge of CLK
5.0
10,000
ns
TDNARH
Hold time on READ after the rising edge of CLK
0.0
–
ns
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
0.5
1.5
ns
TDNACLKF
CLK frequency
0.0
100
MHz
TDNACLKH
CLK High time
1.0
∞
ns
TDNACLKL
CLK Low time
1.0
∞
ns
Notes:
1.
The minimum READ pulse width is 5 ns, and the maximum READ pulse width is 10 μs.
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Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Suspend Mode Timing
X-Ref Target - Figure 9
Entering Suspend Mode
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
SUSPEND Input
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
AWAKE Output
tAWAKE_GWE
tSUSPEND_GWE
Flip-Flops, Block RAM,
Distributed RAM
Write Protected
tAWAKE_GTS
tSUSPEND_GTS
Defined by SUSPEND constraint
FPGA Outputs
tSUSPEND_DISABLE
FPGA Inputs,
Interconnect
tSUSPEND_ENABLE
Blocked
DS610-3_08_061207
Figure 9: Suspend Mode Timing
Table 44: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max
Units
–
7
–
ns
+160
+300
+600
ns
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–
10
–
ns
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–
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