55
Spartan-6 FPGA Data Sheet:
DC and Switching Characteristics
DS162 (v1.1) August 26, 2009
Advance Product Specification
Spartan-6 FPGA Electrical Characteristics
Spartan®-6 FPGAs are available in -3, -2, -1L speed
grades, with -3 having the highest performance.
Spartan-6 FPGA DC and AC characteristics are specified
for both commercial and industrial grades. Except the
operating temperature range or unless otherwise noted, all
the DC and AC electrical parameters are the same for a
particular speed grade (that is, the timing characteristics of
a -2 speed grade industrial device are the same as for a -2
speed grade commercial device). However, only selected
speed grades and/or devices might be available in the
industrial range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
This Spartan-6 FPGA data sheet, part of an overall set of
documentation on the Spartan-6 family of FPGAs, is
available on the Xilinx website.
All specifications are subject to change without notice.
Spartan-6 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings
Symbol
Description
Units
VCCINT
Internal supply voltage relative to GND
–0.5 to 1.32
V
VCCAUX
Auxiliary supply voltage relative to GND
–0.5 to 3.75
V
VCCO
Output drivers supply voltage relative to GND
–0.5 to 3.75
V
VBATT
Key memory battery backup supply (XC6SLX75, XC6SLX75T,
XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only)
–0.5 to 4.05
V
VFS
External voltage supply for eFUSE programming (XC6SLX75, XC6SLX75T,
XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only).(5)
–0.5 to 3.75
V
VREF
Input reference voltage
–0.5 to 3.75
V
VIN(2)
I/O input voltage relative to GND(3) (user and dedicated I/Os)
–0.95 to 4.4
V
VTS
Voltage applied to 3-state output (user and dedicated I/Os)
–0.95 to 4.4
V
TSTG
Storage temperature (ambient)
–65 to 150
°C
Maximum soldering temperature(4)
(TQG144, CSG225, CSG324, and FTG256)
+260
°C
Maximum soldering temperature(4) (Pb-free packages: FGG484 and FGG676)
+250
°C
+220
°C
+125
°C
TSOL
Maximum soldering
TJ
Maximum junction
temperature(4)
(Pb packages: FT256, FG484, FG676)
temperature(4)
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. I/O absolute maximum limit applied to DC and AC signals.
3. For I/O operation, refer to the Spartan-6 FPGA SelectIO Resources User Guide.
4. For soldering guidelines and thermal considerations, see Spartan-6 FPGA Packaging and Pinout Specification.
5. When not programming eFUSE, connect VFS to VCCAUX.
© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.
All other trademarks are the property of their respective owners.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
1
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 2: Recommended Operating Conditions
Symbol
Description
Internal supply voltage relative to GND, TJ = 0°C to
+85°C
VCCINT
Internal supply voltage relative to GND, TJ = –40°C to
+100°C
Temperature
Range
Speed
Grade
Min
Typ
Max
Units
Commercial
-3, -2
1.14
1.2
1.26
V
Industrial
-2
1.14
1.2
1.26
V
-1L
0.95
1.0
1.05
V
2.375
2.5
2.625
V
3.15
3.3
3.45
V
1.1
3.45
V
– 0.5
4.1
V
1.0
3.6
V
Auxiliary supply voltage relative to GND when
VCCAUX = 2.5V, TJ = 0°C to +85°C
Commercial
-3, -2
Auxiliary supply voltage relative to GND when
VCCAUX = 2.5V, TJ = –40°C to +100°C
Industrial
-2, -1L
Auxiliary supply voltage relative to GND when
VCCAUX = 3.3V, TJ = 0°C to +85°C
Commercial
-3, -2
Auxiliary supply voltage relative to GND when
VCCAUX = 3.3V, TJ = –40°C to +100°C
Industrial
-2, -1L
Commercial
-3, -2
Industrial
-2, -1L
Commercial
-3, -2
Industrial
-2, -1L
Battery voltage relative to GND, TJ = 0°C to +85°C
(XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T,
XC6SLX150, and XC6SLX150T only)
Commercial
-3, -2
Battery voltage relative to GND, TJ = –40°C to +100°C
(XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T,
XC6SLX150, and XC6SLX150T only)
Industrial
-2, -1L
External voltage supply for eFUSE programming
(XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T,
XC6SLX150, and XC6SLX150T only).(6)
All
All
3.2
3.3
3.4
V
VFS
External resistor for eFUSE programming
(XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T,
XC6SLX150, and XC6SLX150T only).
All
All
1129
1140
1151
Ω
RFUSE
VCCAUX(1)
VCCO(2,3)
VIN
VBATT(4)
Output supply voltage relative to GND, TJ = 0°C to
+85°C
Output supply voltage relative to GND, TJ = –40°C to
+100°C
Input voltage relative to GND, TJ = 0°C to +85°C
Input voltage relative to GND, TJ = –40°C to +100°C
Notes:
1. Recommended maximum voltage droop for VCCAUX is 10 mV/ms.
2. Configuration data is retained even if VCCO drops to 0V.
3. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
4. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either GND or VCCAUX.
5. All voltages are relative to ground.
6. When not programming eFUSE, connect VFS to VCCAUX.
Table 3: DC Characteristics Over Recommended Operating Conditions
Description
Speed
Grade
Min
Data retention VCCINT voltage (below which configuration data might be lost)
-3, -2
0.8
V
-1L
0.8
V
Data retention VCCAUX voltage (below which configuration data might be lost)
2.0
V
VREF leakage current per pin
–10
10
µA
Input or output leakage current per pin (sample-tested)
–10
10
µA
10
pF
Symbol
VDRINT
VDRAUX
IREF
IL
CIN
Input capacitance (sample-tested)
DS162 (v1.1) August 26, 2009
Advance Product Specification
Typ
Max
Units
www.xilinx.com
2
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)
Symbol
IRPU(1)
IRPU(1)
IRPD(1)
IRPD(1)
IBATT(2)
Speed
Grade
Description
Min
Typ
Max
Units
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V or VCCAUX = 3.3V
332
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V or VCCAUX = 2.5V
217
µA
123
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
87
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
56
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
-3, -2
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V or VCCAUX = 3.3V
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V or VCCAUX = 2.5V
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
-1L
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
µA
Pad pull-down (when selected) @ VCCO = 2.5V, VCCAUX = 3.3V
-3, -2
Pad pull-down (when selected) @ VCCO = 2.5V, VCCAUX = 2.5V
Pad pull-down (when selected) @ VCCO = 2.5V, VCCAUX = 3.3V
341
µA
229
µA
µA
-1L
Pad pull-down (when selected) @ VCCO = 2.5V, VCCAUX = 2.5V
µA
Battery supply current (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150,
and XC6SLX150T only)
150
nA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Maximum value specified for worst case process at 25°C.
Important Note
Typical values for quiescent supply current are specified at nominal voltage, 25°C junction temperatures (Tj). Xilinx
recommends analyzing static power consumption at Tj = 25°C. Quiescent supply current is specified by speed grade for
Spartan-6 devices. Xilinx recommends analyzing static power consumption using the XPOWER™ Estimator (XPE) tool
(download at http://www.xilinx.com/power) for conditions other than those specified in Table 4.
Table 4: Typical Quiescent Supply Current
Symbol
ICCINTQ
Description
Quiescent VCCINT supply current
Device
Speed Grade
-2
-1L
XC6SLX4
4.0
4.0
2.4
mA
XC6SLX9
4.0
4.0
2.4
mA
XC6SLX16
6.0
6.0
3.6
mA
XC6SLX25
11.0
11.0
6.6
mA
XC6SLX25T
11.0
11.0
N/A
mA
XC6SLX45
18.0
18.0
10.8
mA
XC6SLX45T
18.0
18.0
N/A
mA
XC6SLX75
mA
XC6SLX75T
DS162 (v1.1) August 26, 2009
Advance Product Specification
Units
-3
N/A
mA
XC6SLX100
36.0
36.0
21.6
mA
XC6SLX100T
36.0
36.0
N/A
mA
XC6SLX150
51.0
51.0
30.6
mA
XC6SLX150T
51.0
51.0
N/A
mA
www.xilinx.com
3
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 4: Typical Quiescent Supply Current (Cont’d)
Symbol
ICCOQ
Description
Quiescent VCCO supply current
Speed Grade
Device
-2
-1L
XC6SLX4
1.0
1.0
1.0
mA
XC6SLX9
1.0
1.0
1.0
mA
XC6SLX16
2.0
2.0
2.0
mA
XC6SLX25
2.0
2.0
2.0
mA
XC6SLX25T
2.0
2.0
N/A
mA
XC6SLX45
3.0
3.0
3.0
mA
XC6SLX45T
3.0
3.0
N/A
mA
XC6SLX75
mA
XC6SLX75T
ICCAUXQ
Quiescent VCCAUX supply current
Units
-3
N/A
mA
XC6SLX100
5.0
5.0
5.0
mA
XC6SLX100T
5.0
5.0
N/A
mA
XC6SLX150
7.0
7.0
7.0
mA
XC6SLX150T
7.0
7.0
N/A
mA
XC6SLX4
3.0
3.0
3.0
mA
XC6SLX9
3.0
3.0
3.0
mA
XC6SLX16
3.0
3.0
3.0
mA
XC6SLX25
4.0
4.0
4.0
mA
XC6SLX25T
4.0
4.0
N/A
mA
XC6SLX45
5.0
5.0
5.0
mA
XC6SLX45T
5.0
5.0
N/A
mA
XC6SLX75
mA
XC6SLX75T
N/A
mA
XC6SLX100
8.0
8.0
8.0
mA
XC6SLX100T
8.0
8.0
N/A
mA
XC6SLX150
12.0
12.0
12.0
mA
XC6SLX150T
12.0
12.0
N/A
mA
Notes:
1. Typical values are specified at nominal voltage, 25°C junction temperatures (Tj). Industrial (I) grade devices have the same typical values as
commercial (C) grade devices at 25°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.
3. If differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
Table 5: Power Supply Ramp Time
Symbol
VCCINTR
Description
Speed Grade
Ramp Time
Units
-3, -2
0.20 to 50.0
ms
-1L
0.20 to 40.0
ms
Internal supply voltage ramp time
VCCOR
Output drivers supply voltage ramp time
All
0.20 to 50.0
ms
VCCAUXR
Auxiliary supply voltage ramp time
All
0.20 to 50.0
ms
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
4
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
SelectIO™ Interface DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
Table 6: Single-Ended I/O Standard DC Input and Output Levels
I/O Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Max
V, Min
mA
mA
LVTTL
–0.5
0.8
2.0
4.1
0.4
2.4
Note(2)
Note(2)
LVCMOS33
–0.5
0.8
2.0
4.1
0.4
VCCO – 0.4
Note(2)
Note(2)
LVCMOS25
–0.5
0.7
1.7
4.1
0.4
VCCO – 0.4
Note(2)
Note(2)
LVCMOS18
–0.5
0.38
0.8
4.1
0.45
VCCO – 0.45
Note(2)
Note(2)
LVCMOS18_JEDEC
–0.5
35% VCCO
65% VCCO
4.1
0.45
VCCO – 0.45
Note(2)
Note(2)
LVCMOS15
–0.5
0.38
0.8
4.1
25% VCCO
75% VCCO
Note(3)
Note(3)
LVCMOS15_JEDEC
–0.5
35% VCCO
65% VCCO
4.1
25% VCCO
75% VCCO
Note(3)
Note(3)
LVCMOS12
–0.5
0.38
0.8
4.1
0.4
VCCO – 0.4
Note(4)
Note(4)
LVCMOS12_JEDEC
–0.5
35% VCCO
65% VCCO
4.1
0.4
VCCO – 0.4
Note(4)
Note(4)
PCI33_3(5)
–0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
Note(5)
Note(5)
PCI66_3(5)
–0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
Note(5)
Note(5)
I2C
–0.5
30% VCCO
70% VCCO
4.1
20% VCCO
–
3
–
SMBUS
–0.5
0.8
2.1
4.1
0.4
–
4
–
SDIO
–0.5
12.5% VCCO
75% VCCO
4.1
12.5% VCCO
75% VCCO
0.1
–0.1
MOBILE_DDR
–0.5
20% VCCO
80% VCCO
4.1
10% VCCO
90% VCCO
0.1
–0.1
HSTL_I
–0.5
VREF – 0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
8
–8
HSTL_II
–0.5
VREF – 0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
16
–16
HSTL_III
–0.5
VREF – 0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
24
–8
HSTL_I_18
–0.5
VREF – 0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
11
–11
HSTL_II_18
–0.5
VREF – 0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
22
–22
HSTL_III_18
–0.5
VREF – 0.1
VREF + 0.1
4.1
0.4
VCCO – 0.4
30
–11
SSTL3_I
–0.5
VREF – 0.2
VREF + 0.2
4.1
VTT – 0.6
VTT + 0.6
8
–8
SSTL3_II
–0.5
VREF – 0.2
VREF + 0.2
4.1
VTT – 0.8
VTT + 0.8
16
–16
SSTL2_I
–0.5
VREF – 0.15
VREF + 0.15
4.1
VTT – 0.61
VTT + 0.61
8.1
–8.1
SSTL2_II
–0.5
VREF – 0.15
VREF + 0.15
4.1
VTT – 0.81
VTT + 0.81
16.2
–16.2
SSTL18_I
–0.5
VREF – 0.125
VREF + 0.125
4.1
VTT – 0.47
VTT + 0.47
6.7
–6.7
SSTL18_II
–0.5
VREF – 0.125
VREF + 0.125
4.1
VTT – 0.60
VTT + 0.60
13.4
–13.4
SSTL15_II
–0.5
VREF – 0.1
VREF + 0.1
4.1
VTT – 0.4
VTT + 0.4
13.4
–13.4
Notes:
1. Tested according to relevant specifications.
2. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
3. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
4. Using drive strengths of 2, 4, 6, 8, or 12 mA.
5. For more information on PCI33_3 and PCI66_3 refer to refer to the Spartan-6 FPGA SelectIO Resources User Guide.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
5
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 7: Differential I/O Standard DC Input and Output Levels
VID
I/O Standard
VICM
mV, Min mV, Max
VOD
V, Min
V, Max
VOCM
mV, Min mV, Max
VOH
VOL
V, Min
V, Max
V, Min
V, Max
LVDS_33
100
600
0.3
2.35
247
454
1.125
1.375
–
–
LVDS_25
100
600
0.3
2.35
247
454
1.125
1.375
–
–
BLVDS_25
100
–
0.3
2.35
240
460
Typical 50% VCCO
–
–
MINI_LVDS_33
200
600
0.3
1.95
300
600
1.0
1.4
–
–
MINI_LVDS_25
200
600
0.3
1.95
300
600
1.0
1.4
–
–
LVPECL_33
100
1000
0.3
2.8
Inputs only
LVPECL_25
100
1000
0.3
1.95
Inputs only
RSDS_33
100
–
0.3
1.5
100
400
1.0
1.4
–
–
RSDS_25
100
–
0.3
1.5
100
400
1.0
1.4
–
–
TMDS_33
150
1200
2.7
3.23
400
600
–
–
PPDS_33
100
400
0.2
2.3
100
400
0.5
1.4
–
–
PPDS_25
100
400
0.2
2.3
100
400
0.5
1.4
–
–
DISPLAY_PORT
190
1260
0.3
2.35
–
–
–
–
DIFF_HSTL_I
100
–
0.68
0.9
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_II
100
–
0.68
0.9
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_III
100
–
0.68
0.9
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_I_18
100
–
0.8
1.1
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_II_18
100
–
0.8
1.1
–
–
–
–
VCCO – 0.4
0.4
DIFF_HSTL_III_18
100
–
0.8
1.1
–
–
–
–
VCCO – 0.4
0.4
DIFF_SSTL3_I
100
–
1.0
1.9
–
–
–
–
VTT + 0.6
VTT – 0.6
DIFF_SSTL3_II
100
–
1.0
1.9
–
–
–
–
VTT + 0.8
VTT – 0.8
DIFF_SSTL2_I
100
–
1.0
1.5
–
–
–
–
VTT + 0.61 VTT – 0.61
DIFF_SSTL2_II
100
–
1.0
1.5
–
–
–
–
VTT + 0.81 VTT – 0.81
DIFF_SSTL18_I
100
–
0.7
1.1
–
–
–
–
VTT + 0.47 VTT – 0.47
DIFF_SSTL18_II
100
–
0.7
1.1
–
–
–
–
VTT + 0.6
VTT – 0.6
DIFF_SSTL15_II
100
–
0.55
0.95
–
–
–
–
VTT + 0.4
VTT – 0.4
VCCO – 0.3 VCCO – 0.19
Typical 50% VCCO
Table 8: eFUSE Read Endurance
Symbol
Description
DNA_CYCLES
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
AES_CYCLES
Number of JTAG FUSE_KEY or FUSE_CNTL read command
operations. Unaffected by SHIFT operations.
DS162 (v1.1) August 26, 2009
Advance Product Specification
Speed Grade
-3
-2
30,000,000
30,000,000
-1L
Units
Read
Cycles
Read
Cycles
www.xilinx.com
6
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
GTP Transceiver Specifications
GTP Transceiver DC Characteristics
Table 9: Absolute Maximum Ratings for GTP Transceivers
Symbol
Specification
Units
Analog supply voltage for the GTP transmitter and receiver circuits relative to
GND
–0.5 to 1.32
V
MGTAVTTTX
Analog supply voltage for the GTP transmitter termination circuit relative to GND
–0.5 to 1.32
V
MGTAVTTRX
Analog supply voltage for the GTP receiver termination circuit relative to GND
–0.5 to 1.32
V
MGTAVCCPLL
Analog supply voltage for the GTP transmitter and receiver PLL circuits relative
to GND
–0.5 to 1.32
V
MGTAVTTRCAL
Analog supply voltage for the resistor calibration circuit of the GTP transceiver
bank (top or bottom)
–0.5 to 1.32
V
MGTAVCC
VIN
VMGTREFCLK
Description
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
V
Reference clock absolute input voltage
V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 10: Recommended Operating Conditions for GTP Transceivers(1)(2)
Symbol
Description
Min
Max
Units
MGTAVCC
Analog supply voltage for the GTP transmitter and receiver circuits relative to
GND
1.14
1.26
V
MGTAVTTTX
Analog supply voltage for the GTP transmitter termination circuit relative to
GND
1.14
1.26
V
MGTAVTTRX
Analog supply voltage for the GTP receiver termination circuit relative to GND
1.14
1.26
V
Analog supply voltage for the GTP transmitter and receiver PLL circuits
relative to GND
1.14
1.26
V
Analog supply voltage for the resistor calibration circuit of the GTP transceiver
bank (top or bottom)
1.14
1.26
V
MGTAVCCPLL
MGTAVTTRCAL
Notes:
1. Each voltage listed requires the filter circuit described in Spartan-6 FPGA GTP Transceiver User Guide.
2. Voltages are specified for the temperature range of TJ = –40°C to +100°C.
Table 11: DC Characteristics Over Recommended Operating Conditions for GTP Transmitters(1)
Symbol
IMGTAVCC
Description
Min
Typ
Max
Units
GTP transceiver internal analog supply current
mA
IMGTAVTTTX
GTP transmitter termination supply current(2)
mA
IMGTAVTTRX
GTP receiver termination supply current(2)
mA
IMGTAVCCPLL
GTP transmitter and receiver PLL supply current
mA
IMGTAVTTRCAL
GTP transceiver resistor termination calibration supply current
mA
MGTRREF
Precision reference resistor for internal calibration termination
50.0 ± 1% tolerance
Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 3.125 Gb/s line rate.
2. ICC numbers are given per GTP transceiver operating with default settings.
3. Values for currents other than the values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA)
tools.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
7
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 12: GTP Transceiver Quiescent Supply Current
Symbol
Typ(1)
Description
Max
Units
IAVTTQ
Quiescent MGTAVTT (transmitter termination) supply current
mA
IAVCCQ
Quiescent MGTAVCC (analog) supply current
mA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Device powered and unconfigured.
3. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA)
tools.
4. GTP transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTP
transceivers.
GTP Transceiver DC Input and Output Levels
Table 13 summarizes the DC output specifications of the GTP transceivers in Spartan-6 FPGAs. Figure 1 shows the singleended output voltage swing. Figure 2 shows the peak-to-peak differential output voltage.
Consult the Spartan-6 FPGA GTP Transceiver User Guide for further details.
Table 13: GTP Transceiver DC Specifications
Symbol
DC Parameter
DVPPIN
VIN
VCMIN
Conditions
Min
Typ
Max
Units
Differential peak-to-peak input
voltage
External AC coupled
125
2000
mV
Input voltage
DC coupled
MGTAVTTRX = 1.2V
–400
MGTAVTTRX
mV
Common mode input voltage
DC coupled
MGTAVTTRX = 1.2V
2/3
MGTAVTTRX
mV
Differential peak-to-peak output
voltage (1)
1000
mV
VSEOUT
Single-ended output voltage
swing (1)
500
mV
VCMOUT
Common mode output voltage
DVPPOUT
RIN
ROUT
TOSKEW
Equation based
MGTAVTTTX – VSEOUT/2
mV
Differential input resistance
100
Ω
Differential output resistance
100
Ω
Transmitter output skew
ps
Recommended external AC coupling capacitor(2)
CEXT
75
100
200
nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in Spartan-6 FPGA GTP Transceiver User Guide and can
result in values lower than reported in this table.
2. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 1
+V
P
VSEOUT
N
0
ds162_01_042109
Figure 1: Single-Ended Output Voltage Swing
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
8
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 2
+V
DVPPOUT
0
–V
P–N
ds162_02_082609
Figure 2: Peak-to-Peak Differential Output Voltage
Table 14 summarizes the DC specifications of the clock input of the GTP transceiver. Figure 3 shows the single-ended input
voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult the Spartan-6 FPGA GTP
Transceiver User Guide for further details.
Table 14: GTP Transceiver Clock DC Input Level Specification(1)
Symbol
VIDIFF
DC Parameter
Conditions
Min
Typ
Max
Units
Differential peak-to-peak input voltage
800
mV
VISE
Single-ended input voltage
400
mV
RIN
Differential input resistance
100
Ω
Required external AC coupling capacitor
100
nF
CEXT
Notes:
1. VMIN = 0V and VMAX = MGTAVCC
X-Ref Target - Figure 3
+V
P
VISE
N
0
ds162_03_042109
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 4
+V
P–N
VIDIFF
0
–V
ds162_04_042109
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
9
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
GTP Transceiver Switching Characteristics
Consult the Spartan-6 FPGA GTP Transceiver User Guide for further information.
Table 15: GTP Transceiver Performance
Symbol
Speed Grade
Description
-3
-2
-1L
Units
FGTPMAX
Maximum GTP transceiver data rate
3.125
2.7
N/A
Gb/s
FGPLLMAX
Maximum PLL frequency
1.62
1.62
N/A
GHz
FGPLLMIN
Minimum PLL frequency
1.2
1.2
N/A
GHz
Table 16: Dynamic Reconfiguration Port (DRP) in the GTP Transceiver Switching Characteristics
Symbol
FGTPDRPCLK
Speed Grade
Description
GTPDRPCLK maximum frequency
-3
-2
-1L
100
100
N/A
Units
MHz
Table 17: GTP Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
All Speed Grades
Min
Typ
60
Max
FGCLK
Reference clock frequency range
TRCLK
Reference clock rise time
20% – 80%
200
ps
TFCLK
Reference clock fall time
80% – 20%
200
ps
TDCREF
Reference clock duty cycle
Transceiver PLL only
TLOCK
Clock recovery frequency acquisition
time
Initial PLL lock
TPHASE
Clock recovery phase acquisition time Lock to data after PLL has locked to
the reference clock
45
160
Units
50
MHz
55
%
1
ms
µs
X-Ref Target - Figure 5
TRCLK
80%
20%
TFCLK
ds162_05_042109
Figure 5: Reference Clock Timing Parameters
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
10
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 18: GTP Transceiver User Clock Switching Characteristics(1)
Symbol
FTXOUT
Description
TXOUTCLK maximum frequency
Conditions
Speed Grade
-3
-2
-1L
Units
Internal 10-bit data path
N/A
MHz
Internal 8-bit data path
N/A
MHz
FRXREC
RXRECCLK maximum frequency
N/A
MHz
TRX
RXUSRCLK maximum frequency
N/A
MHz
TRX2
RXUSRCLK2 maximum frequency
1 byte interface
N/A
MHz
2 byte interface
N/A
MHz
4 byte interface
N/A
MHz
N/A
MHz
TTX
TXUSRCLK maximum frequency
TTX2
TXUSRCLK2 maximum frequency
TDCUSRCLK
TXUSRCLK, TXUSRCLK2, RXUSRCLK,
and RXUSRCLK2 duty cycle
1 byte interface
N/A
MHz
2 byte interface
N/A
MHz
4 byte interface
N/A
MHz
1 byte interface
N/A
%
2 byte interface
N/A
%
4 byte interface
N/A
%
Notes:
1. Clocking must be implemented as described in Spartan-6 FPGA GTP Transceiver User Guide.
Table 19: GTP Transceiver Transmitter Switching Characteristics
Symbol
FGTPTX
Description
Condition
Serial data rate range
Min
0.600
Typ
Max
Units
FGTPMAX
Gb/s
TRTX
TX Rise time
20%–80%
ps
TFTX
TX Fall time
80%–20%
ps
TLLSKEW
TX lane-to-lane skew(1)
VTXOOBVDPP
Electrical idle amplitude
TTXOOBTRANSITION
Jitter(2)
TJ3.125
Total
Deterministic Jitter(2)
Total
Jitter(2)
2.5 Gb/s
TJ1.62
Total
Jitter(2)
DJ1.62
Deterministic Jitter(2)
Total
1.25 Gb/s
Deterministic
TJ614
Total
Jitter(2)
DJ614
Deterministic Jitter(2)
UI
UI
Jitter(2)
DJ1.25
UI
UI
1.62 Gb/s
Jitter(2)
UI
UI
Jitter(2)
Deterministic
mV
ns
3.125 Gb/s
DJ2.5
TJ1.25
20
Electrical idle transition time
DJ3.125
TJ2.5
ps
UI
UI
614 Mb/s
UI
UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP transceiver sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
11
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 20: GTP Transceiver Receiver Switching Characteristics
Symbol
FGTPRX
Description
Min
Serial data rate
TRXELECIDLE
Time for RXELECIDLE to
respond to loss or
restoration of data
RXOOBVDPP
OOB detect threshold
peak-to-peak
0.600
Typ
Max
Units
FGTPMAX
Gb/s
ns
60
150
mV
RXSST
Receiver spread-spectrum
tracking(1)
Modulated @ 33 KHz
RXRL
Run length (CID)
Internal AC capacitor bypassed
Data/REFCLK PPM offset
tolerance
CDR 2nd-order loop disabled
JT_SJ3.125
Sinusoidal Jitter(3)
3.125 Gb/s
UI
JT_SJ2.5
Sinusoidal Jitter(3)
2.5 Gb/s
UI
JT_SJ1.62
Sinusoidal
Jitter(3)
1.62 Gb/s
UI
JT_SJ1.25
Sinusoidal
Jitter(3)
1.25 Gb/s
UI
JT_SJ614
Sinusoidal Jitter(3)
614 Mb/s
UI
3.125 Gb/s
UI
RXPPMTOL
SJ Jitter
CDR
2nd-order
loop enabled
ppm
UI
ppm
ppm
Tolerance(2)
SJ Jitter Tolerance with Stressed Eye(2)
JT_TJSE3.125
Total Jitter with Stressed
Eye
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a Bit Error Ratio of 1e–12.
3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
12
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Endpoint Block for PCI Express Designs Switching Characteristics
Consult Spartan-6 FPGA Integrated Endpoint Block for PCI Express for further information.
Table 21: Maximum Performance for PCI Express Designs
Symbol
FPCIEUSER
Description
User clock maximum frequency
Speed Grade
-3
-2
-1L
62.5
62.5
N/A
Units
MHz
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values
are subject to the same guidelines as the Switching Characteristics, page 14.
Table 22: Interface Performances
Speed Grade
Description
-3
-2
-1L
Networking Applications
SDR LVDS transmitter (using IOB SDR register)
DDR LVDS transmitter (using IOB ODDR2 register)
SDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8)
DDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8)
SDR LVDS receiver (1:7 / 7:1 video link (LDI
1.05 Gb/s
interface))(1)
Memory Interfaces (Implemented using the Spartan-6 FPGA Memory Controller Block)
DDR
400 Mb/s
DDR2
800 Mb/s
DDR3
800 Mb/s
Mobile_DDR
400 Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific DPA algorithms dominate deterministic performance. Please refer to
actual application notes for details.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
13
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on an
advanced speed specification (version 1.0). Switching
characteristics are specified on a per-speed-grade basis
and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance
These specifications are based on simulations only and are
typically available soon after device design specifications
are frozen. Although speed grades with this designation are
considered relatively stable and conservative, some underreporting might still occur.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device.
Table 23 correlates the current status of each Spartan-6
device on a per speed grade basis.
Table 23: Spartan-6 Device Speed Grade Designations
Device
Preliminary
Speed Grade Designations
Advance
These specifications are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
XC6SLX4
-2
XC6SLX9
-2
XC6SLX16
-2
XC6SLX25
-2
XC6SLX25T
-2
Production
XC6SLX45
-2
These specifications are released once enough production
silicon of a particular device family member has been
characterized to provide full correlation between
specifications and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
XC6SLX45T
-2
XC6SLX75
-2
XC6SLX75T
-2
XC6SLX100
-2
XC6SLX100T
-2
XC6SLX150
-2
XC6SLX150T
-2
Preliminary
Production
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Spartan-6 devices.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
14
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed
grade) is released to production before a speed
specification is released with the correct label (Advance,
Preliminary, Production). Any labeling discrepancies are
corrected in subsequent speed specification releases.
Table 24 lists the production released Spartan-6 family
member, speed grade, and the minimum corresponding
supported speed specification version and ISE software
revisions. The ISE™ software and speed specifications
listed are the minimum releases required for production. All
subsequent releases of software and speed specifications
are valid.
Table 24: Spartan-6 Device Production Software
and Speed Specification Release
Speed Grade Designations
Device
-3
-2
-1L
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
N/A
XC6SLX25T
XC6SLX45
N/A
XC6SLX45T
XC6SLX75
N/A
XC6SLX75T
XC6SLX100
N/A
XC6SLX100T
XC6SLX150
N/A
XC6SLX150T
Notes:
1. Blank entries indicate a device and/or speed grade in advance or
preliminary status.
IOB Pad Input/Output/3-State Switching Characteristics
Table 25 summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
TIOPI is described as the delay from IOB pad through the
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
TIOOP is described as the delay from the O pin to the IOB
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
TIOTP is described as the delay from the T pin to the IOB
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 26 summarizes the value of TIOTPHZ. TIOTPHZ is
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
Table 25: IOB Switching Characteristics
I/O Standard
-3
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
-2
-1L
-3
-2
-1L
-3
-2
Units
-1L
LVDS_33
1.50
1.90
1.90
ns
LVDS_25
1.36
2.03
2.03
ns
BLVDS_25
1.36
2.18
2.18
ns
MINI_LVDS_33
1.50
1.89
1.89
ns
MINI_LVDS_25
1.36
2.03
2.03
ns
LVPECL_33
1.50
N/A
N/A
ns
LVPECL_25
1.36
N/A
N/A
ns
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
15
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 25: IOB Switching Characteristics (Cont’d)
I/O Standard
-3
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
-2
-1L
-3
-2
-1L
-3
-2
Units
-1L
RSDS_33 (point to point)
1.50
1.90
1.90
ns
RSDS_25 (point to point)
1.36
2.02
2.02
ns
TMDS_33
1.53
1.85
1.85
ns
PPDS_33
1.50
1.90
1.90
ns
PPDS_25
1.36
2.03
2.03
ns
DISPLAY_PORT
1.36
3.32
3.32
ns
I2C
1.66
6.39
6.39
ns
SMBUS
1.66
6.39
6.39
ns
SDIO
1.69
3.03
3.03
ns
MOBILE_DDR
1.26
2.83
2.83
ns
HSTL_I
1.22
1.99
1.99
ns
HSTL_II
1.22
1.98
1.98
ns
HSTL_III
1.28
2.01
2.01
ns
HSTL_I _18
1.27
2.02
2.02
ns
HSTL_II _18
1.27
2.05
2.05
ns
HSTL_III _18
1.32
1.94
1.94
ns
SSTL3_I
1.92
1.98
1.98
ns
SSTL3_II
1.92
2.02
2.02
ns
SSTL2_I
1.63
1.94
1.94
ns
SSTL2_II
1.64
1.99
1.99
ns
SSTL18_I
1.23
1.89
1.89
ns
SSTL18_II
1.22
1.92
1.92
ns
SSTL15_II
1.20
1.95
1.95
ns
DIFF_HSTL_I
1.27
2.03
2.03
ns
DIFF_HSTL_II
1.27
1.99
1.99
ns
DIFF_HSTL_III
1.27
1.97
1.97
ns
DIFF_HSTL_I_18
1.31
2.05
2.05
ns
DIFF_HSTL_II_18
1.30
1.97
1.97
ns
DIFF_HSTL_III_18
1.31
1.99
1.99
ns
DIFF_SSTL3_I
1.50
2.03
2.03
ns
DIFF_SSTL3_II
1.50
2.06
2.06
ns
DIFF_SSTL2_I
1.36
2.05
2.05
ns
DIFF_SSTL2_II
1.36
2.03
2.03
ns
DIFF_SSTL18_I
1.31
1.97
1.97
ns
DIFF_SSTL18_II
1.31
1.97
1.97
ns
DIFF_SSTL15_II
1.28
1.95
1.95
ns
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
16
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 25: IOB Switching Characteristics (Cont’d)
I/O Standard
-3
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
-2
-1L
-3
-2
-1L
-3
-2
Units
-1L
LVTTL, QUIETIO, 2 mA
1.69
5.68
5.68
ns
LVTTL, QUIETIO, 4 mA
1.69
4.55
4.55
ns
LVTTL, QUIETIO, 6 mA
1.69
4.07
4.07
ns
LVTTL, QUIETIO, 8 mA
1.69
3.59
3.59
ns
LVTTL, QUIETIO, 12 mA
1.69
3.60
3.60
ns
LVTTL, QUIETIO, 16 mA
1.69
3.31
3.31
ns
LVTTL, QUIETIO, 24 mA
1.69
3.10
3.10
ns
LVTTL, Slow, 2 mA
1.69
4.73
4.73
ns
LVTTL, Slow, 4 mA
1.69
3.57
3.57
ns
LVTTL, Slow, 6 mA
1.69
3.18
3.18
ns
LVTTL, Slow, 8 mA
1.69
3.03
3.03
ns
LVTTL, Slow, 12 mA
1.69
2.94
2.94
ns
LVTTL, Slow, 16 mA
1.69
2.81
2.81
ns
LVTTL, Slow, 24 mA
1.69
2.53
2.53
ns
LVTTL, Fast, 2 mA
1.69
4.16
4.16
ns
LVTTL, Fast, 4 mA
1.69
2.97
2.97
ns
LVTTL, Fast, 6 mA
1.69
2.60
2.60
ns
LVTTL, Fast, 8 mA
1.69
2.42
2.42
ns
LVTTL, Fast, 12 mA
1.69
2.29
2.29
ns
LVTTL, Fast, 16 mA
1.69
2.25
2.25
ns
LVTTL, Fast, 24 mA
1.69
2.25
2.25
ns
LVCMOS33, QUIETIO, 2 mA
1.69
5.68
5.68
ns
LVCMOS33, QUIETIO, 4 mA
1.69
4.40
4.40
ns
LVCMOS33, QUIETIO, 6 mA
1.69
3.89
3.89
ns
LVCMOS33, QUIETIO, 8 mA
1.69
3.69
3.69
ns
LVCMOS33, QUIETIO, 12 mA
1.69
3.30
3.30
ns
LVCMOS33, QUIETIO, 16 mA
1.69
3.17
3.17
ns
LVCMOS33, QUIETIO, 24 mA
1.69
3.03
3.03
ns
LVCMOS33, Slow, 2 mA
1.69
4.73
4.73
ns
LVCMOS33, Slow, 4 mA
1.69
3.41
3.41
ns
LVCMOS33, Slow, 6 mA
1.69
3.02
3.02
ns
LVCMOS33, Slow, 8 mA
1.69
3.03
3.03
ns
LVCMOS33, Slow, 12 mA
1.69
2.77
2.77
ns
LVCMOS33, Slow, 16 mA
1.69
2.77
2.77
ns
LVCMOS33, Slow, 24 mA
1.69
2.52
2.52
ns
LVCMOS33, Fast, 2 mA
1.69
4.18
4.18
ns
LVCMOS33, Fast, 4 mA
1.69
2.98
2.98
ns
LVCMOS33, Fast, 6 mA
1.69
2.60
2.60
ns
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
17
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 25: IOB Switching Characteristics (Cont’d)
I/O Standard
-3
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
-2
-1L
-3
-2
-1L
-3
-2
Units
-1L
LVCMOS33, Fast, 8 mA
1.69
2.40
2.40
ns
LVCMOS33, Fast, 12 mA
1.69
2.17
2.17
ns
LVCMOS33, Fast, 16 mA
1.69
2.17
2.17
ns
LVCMOS33, Fast, 24 mA
1.69
2.17
2.17
ns
LVCMOS25, QUIETIO, 2 mA
1.18
5.15
5.15
ns
LVCMOS25, QUIETIO, 4 mA
1.18
4.07
4.07
ns
LVCMOS25, QUIETIO, 6 mA
1.18
3.77
3.77
ns
LVCMOS25, QUIETIO, 8 mA
1.18
3.53
3.53
ns
LVCMOS25, QUIETIO, 12 mA
1.18
3.21
3.21
ns
LVCMOS25, QUIETIO, 16 mA
1.18
3.04
3.04
ns
LVCMOS25, QUIETIO, 24 mA
1.18
2.89
2.89
ns
LVCMOS25, Slow, 2 mA
1.18
4.17
4.17
ns
LVCMOS25, Slow, 4 mA
1.18
3.22
3.22
ns
LVCMOS25, Slow, 6 mA
1.18
3.14
3.14
ns
LVCMOS25, Slow, 8 mA
1.18
2.91
2.91
ns
LVCMOS25, Slow, 12 mA
1.18
2.49
2.49
ns
LVCMOS25, Slow, 16 mA
1.18
2.49
2.49
ns
LVCMOS25, Slow, 24 mA
1.18
2.29
2.29
ns
LVCMOS25, Fast, 2 mA
1.18
3.76
3.76
ns
LVCMOS25, Fast, 4 mA
1.18
2.75
2.75
ns
LVCMOS25, Fast, 6 mA
1.18
2.35
2.35
ns
LVCMOS25, Fast, 8 mA
1.18
2.28
2.28
ns
LVCMOS25, Fast, 12 mA
1.18
2.10
2.10
ns
LVCMOS25, Fast, 16 mA
1.18
2.10
2.10
ns
LVCMOS25, Fast, 24 mA
1.18
2.10
2.10
ns
LVCMOS18, QUIETIO, 2 mA
1.38
6.06
6.06
ns
LVCMOS18, QUIETIO, 4 mA
1.38
4.91
4.91
ns
LVCMOS18, QUIETIO, 6 mA
1.38
4.30
4.30
ns
LVCMOS18, QUIETIO, 8 mA
1.38
4.03
4.03
ns
LVCMOS18, QUIETIO, 12 mA
1.38
3.67
3.67
ns
LVCMOS18, QUIETIO, 16 mA
1.38
3.52
3.52
ns
LVCMOS18, QUIETIO, 24 mA
1.38
3.38
3.38
ns
LVCMOS18, Slow, 2 mA
1.38
4.88
4.88
ns
LVCMOS18, Slow, 4 mA
1.38
4.02
4.02
ns
LVCMOS18, Slow, 6 mA
1.38
3.41
3.41
ns
LVCMOS18, Slow, 8 mA
1.38
2.67
2.67
ns
LVCMOS18, Slow, 12 mA
1.38
2.42
2.42
ns
LVCMOS18, Slow, 16 mA
1.38
2.42
2.42
ns
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
18
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 25: IOB Switching Characteristics (Cont’d)
I/O Standard
-3
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
-2
-1L
-3
-2
-1L
-3
-2
Units
-1L
LVCMOS18, Slow, 24 mA
1.38
2.37
2.37
ns
LVCMOS18, Fast, 2 mA
1.38
3.96
3.96
ns
LVCMOS18, Fast, 4 mA
1.38
2.87
2.87
ns
LVCMOS18, Fast, 6 mA
1.38
2.26
2.26
ns
LVCMOS18, Fast, 8 mA
1.38
2.22
2.22
ns
LVCMOS18, Fast, 12 mA
1.38
2.14
2.14
ns
LVCMOS18, Fast, 16 mA
1.38
2.14
2.14
ns
LVCMOS18, Fast, 24 mA
1.38
2.14
2.14
ns
LVCMOS18_JEDEC, QUIETIO, 2 mA
1.26
6.02
6.02
ns
LVCMOS18_JEDEC, QUIETIO, 4 mA
1.26
4.91
4.91
ns
LVCMOS18_JEDEC, QUIETIO, 6 mA
1.26
4.29
4.29
ns
LVCMOS18_JEDEC, QUIETIO, 8 mA
1.26
4.02
4.02
ns
LVCMOS18_JEDEC, QUIETIO, 12 mA
1.26
3.67
3.67
ns
LVCMOS18_JEDEC, QUIETIO, 16 mA
1.26
3.52
3.52
ns
LVCMOS18_JEDEC, QUIETIO, 24 mA
1.26
3.38
3.38
ns
LVCMOS18_JEDEC, Slow, 2 mA
1.26
4.87
4.87
ns
LVCMOS18_JEDEC, Slow, 4 mA
1.26
4.00
4.00
ns
LVCMOS18_JEDEC, Slow, 6 mA
1.26
3.41
3.41
ns
LVCMOS18_JEDEC, Slow, 8 mA
1.26
2.67
2.67
ns
LVCMOS18_JEDEC, Slow, 12 mA
1.26
2.42
2.42
ns
LVCMOS18_JEDEC, Slow, 16 mA
1.26
2.42
2.42
ns
LVCMOS18_JEDEC, Slow, 24 mA
1.26
2.37
2.37
ns
LVCMOS18_JEDEC, Fast, 2 mA
1.26
3.95
3.95
ns
LVCMOS18_JEDEC, Fast, 4 mA
1.26
2.86
2.86
ns
LVCMOS18_JEDEC, Fast, 6 mA
1.26
2.25
2.25
ns
LVCMOS18_JEDEC, Fast, 8 mA
1.26
2.21
2.21
ns
LVCMOS18_JEDEC, Fast, 12 mA
1.26
2.14
2.14
ns
LVCMOS18_JEDEC, Fast, 16 mA
1.26
2.14
2.14
ns
LVCMOS18_JEDEC, Fast, 24 mA
1.26
2.14
2.14
ns
LVCMOS15, QUIETIO, 2 mA
1.23
5.62
5.62
ns
LVCMOS15, QUIETIO, 4 mA
1.23
4.81
4.81
ns
LVCMOS15, QUIETIO, 6 mA
1.23
4.32
4.32
ns
LVCMOS15, QUIETIO, 8 mA
1.23
4.16
4.16
ns
LVCMOS15, QUIETIO, 12 mA
1.23
3.89
3.89
ns
LVCMOS15, QUIETIO, 16 mA
1.23
3.69
3.69
ns
LVCMOS15, Slow, 2 mA
1.23
4.48
4.48
ns
LVCMOS15, Slow, 4 mA
1.23
3.78
3.78
ns
LVCMOS15, Slow, 6 mA
1.23
2.71
2.71
ns
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
19
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 25: IOB Switching Characteristics (Cont’d)
I/O Standard
-3
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
-2
-1L
-3
-2
-1L
-3
-2
Units
-1L
LVCMOS15, Slow, 8 mA
1.23
2.73
2.73
ns
LVCMOS15, Slow, 12 mA
1.23
2.48
2.48
ns
LVCMOS15, Slow, 16 mA
1.23
2.47
2.47
ns
LVCMOS15, Fast, 2 mA
1.23
3.67
3.67
ns
LVCMOS15, Fast, 4 mA
1.23
2.73
2.73
ns
LVCMOS15, Fast, 6 mA
1.23
2.16
2.16
ns
LVCMOS15, Fast, 8 mA
1.23
2.14
2.14
ns
LVCMOS15, Fast, 12 mA
1.23
2.07
2.07
ns
LVCMOS15, Fast, 16 mA
1.23
2.05
2.05
ns
LVCMOS15_JEDEC, QUIETIO, 2 mA
1.36
5.61
5.61
ns
LVCMOS15_JEDEC, QUIETIO, 4 mA
1.36
4.80
4.80
ns
LVCMOS15_JEDEC, QUIETIO, 6 mA
1.36
4.32
4.32
ns
LVCMOS15_JEDEC, QUIETIO, 8 mA
1.36
4.18
4.18
ns
LVCMOS15_JEDEC, QUIETIO, 12 mA
1.36
3.89
3.89
ns
LVCMOS15_JEDEC, QUIETIO, 16 mA
1.36
3.69
3.69
ns
LVCMOS15_JEDEC, Slow, 2 mA
1.36
4.49
4.49
ns
LVCMOS15_JEDEC, Slow, 4 mA
1.36
3.78
3.78
ns
LVCMOS15_JEDEC, Slow, 6 mA
1.36
2.72
2.72
ns
LVCMOS15_JEDEC, Slow, 8 mA
1.36
2.73
2.73
ns
LVCMOS15_JEDEC, Slow, 12 mA
1.36
2.47
2.47
ns
LVCMOS15_JEDEC, Slow, 16 mA
1.36
2.47
2.47
ns
LVCMOS15_JEDEC, Fast, 2 mA
1.36
3.67
3.67
ns
LVCMOS15_JEDEC, Fast, 4 mA
1.36
2.74
2.74
ns
LVCMOS15_JEDEC, Fast, 6 mA
1.36
2.15
2.15
ns
LVCMOS15_JEDEC, Fast, 8 mA
1.36
2.14
2.14
ns
LVCMOS15_JEDEC, Fast, 12 mA
1.36
2.08
2.08
ns
LVCMOS15_JEDEC, Fast, 16 mA
1.36
2.05
2.05
ns
LVCMOS12, QUIETIO, 2 mA
1.10
6.39
6.39
ns
LVCMOS12, QUIETIO, 4 mA
1.10
5.15
5.15
ns
LVCMOS12, QUIETIO, 6 mA
1.10
4.84
4.84
ns
LVCMOS12, QUIETIO, 8 mA
1.10
4.54
4.54
ns
LVCMOS12, QUIETIO, 12 mA
1.10
4.30
4.30
ns
LVCMOS12, Slow, 2 mA
1.10
5.18
5.18
ns
LVCMOS12, Slow, 4 mA
1.10
3.27
3.27
ns
LVCMOS12, Slow, 6 mA
1.10
3.17
3.17
ns
LVCMOS12, Slow, 8 mA
1.10
2.78
2.78
ns
LVCMOS12, Slow, 12 mA
1.10
2.57
2.57
ns
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
20
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 25: IOB Switching Characteristics (Cont’d)
I/O Standard
-3
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
-2
-1L
-3
-2
-1L
-3
-2
Units
-1L
LVCMOS12, Fast, 2 mA
1.10
3.84
3.84
ns
LVCMOS12, Fast, 4 mA
1.10
2.81
2.81
ns
LVCMOS12, Fast, 6 mA
1.10
2.25
2.25
ns
LVCMOS12, Fast, 8 mA
1.10
2.16
2.16
ns
LVCMOS12, Fast, 12 mA
1.10
2.08
2.08
ns
LVCMOS12_JEDEC, QUIETIO, 2 mA
1.67
6.39
6.39
ns
LVCMOS12_JEDEC, QUIETIO, 4 mA
1.67
5.15
5.15
ns
LVCMOS12_JEDEC, QUIETIO, 6 mA
1.67
4.83
4.83
ns
LVCMOS12_JEDEC, QUIETIO, 8 mA
1.67
4.52
4.52
ns
LVCMOS12_JEDEC, QUIETIO, 12 mA
1.67
4.30
4.30
ns
LVCMOS12_JEDEC, Slow, 2 mA
1.67
5.19
5.19
ns
LVCMOS12_JEDEC, Slow, 4 mA
1.67
3.27
3.27
ns
LVCMOS12_JEDEC, Slow, 6 mA
1.67
3.17
3.17
ns
LVCMOS12_JEDEC, Slow, 8 mA
1.67
2.78
2.78
ns
LVCMOS12_JEDEC, Slow, 12 mA
1.67
2.57
2.57
ns
LVCMOS12_JEDEC, Fast, 2 mA
1.67
3.85
3.85
ns
LVCMOS12_JEDEC, Fast, 4 mA
1.67
2.81
2.81
ns
LVCMOS12_JEDEC, Fast, 6 mA
1.67
2.25
2.25
ns
LVCMOS12_JEDEC, Fast, 8 mA
1.67
2.16
2.16
ns
LVCMOS12_JEDEC, Fast, 12 mA
1.67
2.08
2.08
ns
Table 26: IOB 3-state ON Output Switching Characteristics (TIOTPHZ)
Symbol
TIOTPHZ
DS162 (v1.1) August 26, 2009
Advance Product Specification
Description
T input to Pad high-impedance
Speed Grade
-3
-2
1.59
-1L
Units
ns
www.xilinx.com
21
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 27 shows the test setup parameters used for measuring input delay.
Table 27: Input Delay Measurement Methodology
Description
I/O Standard Attribute
VL (1)
VH (1)
VMEAS
VREF
(3,4)
(2,4)
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVTTL
0
3.0
1.4
–
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
0
3.3
1.65
–
LVCMOS, 2.5V
LVCMOS25
0
2.5
1.25
–
LVCMOS, 1.8V
LVCMOS18
0
1.8
0.9
–
LVCMOS, 1.5V
LVCMOS15
0
1.5
0.75
–
LVCMOS, 1.2V
LVCMOS12
0
1.2
0.6
–
PCI (Peripheral Component Interface),
33 MHz, 3.3V
PCI33_3
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL_I, HSTL_II
VREF – 0.5
VREF + 0.5
VREF
0.75
HSTL, Class III
HSTL_III
VREF – 0.5
VREF + 0.5
VREF
0.90
HSTL, Class I & II, 1.8V
HSTL_I_18, HSTL_II_18
VREF – 0.5
VREF + 0.5
VREF
0.90
HSTL, Class III 1.8V
HSTL_III_18
VREF – 0.5
VREF + 0.5
VREF
1.08
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL3_I, SSTL3_II
VREF – 0.75
VREF + 0.75
VREF
1.5
SSTL, Class I & II, 2.5V
SSTL2_I, SSTL2_II
VREF – 0.75
VREF + 0.75
VREF
1.25
SSTL, Class I & II, 1.8V
SSTL18_I, SSTL18_II
VREF – 0.5
VREF + 0.5
VREF
0.90
SSTL, Class II, 1.5V
SSTL15_II
VREF – 0.2
VREF + 0.2
VREF
0.75
1.25 – 0.125
1.25 + 0.125
0(5)
1.2 – 0.3
1.2 – 0.3
0(5)
Per PCI Specification
–
LVDS (Low-Voltage Differential Signaling),
2.5V & 3.3V
LVDS_25, LVDS_33
LVPECL (Low-Voltage Positive Emitter-Coupled
Logic), 2.5V & 3.3V
LVPECL_25, LVPECL_33
BLVDS (Bus LVDS), 2.5V
BLVDS_25
1.3 – 0.125
1.3 + 0.125
0(5)
Mini-LVDS, 2.5V & 3.3V
MINI_LVDS_25,
MINI_LVDS_33
1.2 – 0.125
1.2 + 0.125
0(5)
RSDS (Reduced Swing Differential Signaling),
2.5V & 3.3V
RSDS_25, RSDS_33
1.2 – 0.1
1.2 + 0.1
0(5)
TMDS (Transition Minimized Differential Signaling),
3.3V
TMDS_33
3.0 – 0.1
3.0 + 0.1
0(5)
PPDS (Point-to-Point Differential Signaling,
2.5V & 3.3V
PPDS_25, PPDS_33
1.25 – 0.1
1.25 + 0.1
0(5)
Notes:
1. Input waveform switches between VL and VH.
2. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values
listed are typical.
3. Input voltage level from which measurement starts.
4. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 6.
5. The value given is the differential input voltage.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
22
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
X-Ref Target - Figure 7
FPGA Output
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 6 and Figure 7.
+
RREF VMEAS
CREF
–
ds162_07_011309
X-Ref Target - Figure 6
Figure 7: Differential Test Setup
VREF
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters VREF, RREF, CREF, and VMEAS fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
RREF
FPGA Output
VMEAS
(voltage level when taking
delay measurement)
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 28.
CREF
(probe capacitance)
2. Record the time to VMEAS .
ds162_06_011309
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
Figure 6: Single-Ended Test Setup
4. Record the time to VMEAS .
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
Table 28: Output Delay Measurement Methodology
I/O Standard
Attribute
Description
RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVTTL (all)
1M
0
1.4
0
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
1M
0
1.65
0
LVCMOS, 2.5V
LVCMOS25
1M
0
1.25
0
LVCMOS, 1.8V
LVCMOS18
1M
0
0.9
0
LVCMOS, 1.5V
LVCMOS15
1M
0
0.75
0
LVCMOS, 1.2V
LVCMOS12
1M
0
0.75
0
PCI33_3 (rising edge)
25
10 (2)
0.94
0
PCI33_3 (falling edge)
25
10 (2)
2.03
3.3
HSTL (High-Speed Transceiver Logic), Class I
HSTL_I
50
0
VREF
0.75
HSTL, Class II
HSTL_II
25
0
VREF
0.75
HSTL, Class III
HSTL_III
50
0
0.9
1.5
HSTL, Class I, 1.8V
HSTL_I_18
50
0
VREF
0.9
HSTL, Class II, 1.8V
HSTL_II_18
25
0
VREF
0.9
HSTL, Class III, 1.8V
HSTL_III_18
50
0
1.1
1.8
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL18_I
50
0
VREF
0.9
SSTL, Class II, 1.8V
SSTL18_II
25
0
VREF
0.9
SSTL, Class I, 2.5V
SSTL2_I
50
0
VREF
1.25
PCI (Peripheral Component Interface), 33 MHz, 3.3V
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
23
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 28: Output Delay Measurement Methodology (Cont’d)
I/O Standard
Attribute
Description
RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
SSTL, Class II, 2.5V
SSTL2_II
25
0
VREF
1.25
SSTL, Class II, 1.5V
SSTL15_II
25
0
VREF
0.75
0
0(3)
1.2
0
0(3)
0
100
0
0(3)
RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, RSDS_33
100
0
0(3)
TMDS (Transition Minimized Differential Signaling), 3.3V
TMDS_33
100
0
0(3)
PPDS (Point-to-Point Differential Signaling, 2.5V & 3.3V
PPDS_25, PPDS_33
100
0
0(3)
LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V
BLVDS (Bus LVDS), 2.5V
LVDS_25, LVDS_33
100
BLVDS_25
Mini-LVDS, 2.5V & 3.3V
100
MINI_LVDS_25, MINI_LVDS_33
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. Per PCI specifications.
3. The value given is the differential input voltage.
Input/Output Logic Switching Characteristics
Table 29: ILOGIC2 Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1L
Units
Setup/Hold
TICE0CK/TICKCE0
CE0 pin Setup/Hold with respect to CLK
1.04
–0.58
ns
TISRCK/TICKSR
SR pin Setup/Hold with respect to CLK
1.09
–0.51
ns
TIDOCK/TIOCKD
D pin Setup/Hold with respect to CLK without Delay
1.73
–1.38
ns
TIDOCKD/TIOCKDD
DDLY pin Setup/Hold with respect to CLK (using IODELAY2)
0.51
–0.25
ns
TIDI
D pin to O pin propagation delay, no Delay
1.77
ns
TIDID
DDLY pin to O pin propagation delay (using IODELAY2)
0.53
ns
TIDLO
D pin to Q1 pin using flip-flop as a latch without Delay
2.80
ns
TIDLOD
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY2)
1.58
ns
TICKQ
CLK to Q outputs
1.38
ns
TRQ
SR pin to OQ/TQ out
2.54
ns
TGSRQ
Global Set/Reset to Q outputs
Combinatorial
Sequential Delays
ns
Set/Reset
TRPW
Minimum Pulse Width, SR inputs
DS162 (v1.1) August 26, 2009
Advance Product Specification
ns, Min
www.xilinx.com
24
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 30: OLOGIC2 Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1L
Units
Setup/Hold
TODCK/TOCKD
D1/D2 pins Setup/Hold with respect to CLK
0.96
–0.26
ns
TOOCECK/TOCKOCE
OCE pin Setup/Hold with respect to CLK
0.47
–0.22
ns
TOSRCK/TOCKSR
SR pin Setup/Hold with respect to CLK
0.91
–0.47
ns
TOTCK/TOCKT
T1/T2 pins Setup/Hold with respect to CLK
0.72
–0.18
ns
TOTCECK/TOCKTCE
TCE pin Setup/Hold with respect to CLK
0.39
–0.13
ns
Combinatorial
TDOQ
D1 to OQ out or T1 to TQ out
ns
Sequential Delays
TOCKQ
CLK to OQ/TQ out
0.81
ns
TRQ
SR pin to OQ/TQ out
2.54
ns
TGSRQ
Global Set/Reset to Q outputs
ns
Set/Reset
TRPW
Minimum Pulse Width, SR inputs
ns, Min
Input Serializer/Deserializer Switching Characteristics
Table 31: ISERDES2 Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1L
Units
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to CLKDIV
0.31
–0.14
ns
TISCCK_CE / TISCKC_CE
CE pin Setup/Hold with respect to CLK
1.16
–0.71
ns
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
1.60
–1.00
ns
TISDCK_DDLY /TISCKD_DDLY
DDLY pin Setup/Hold with respect to CLK (using
IODELAY2)
–0.37
0.56
ns
TISDCK_D_DDR /TISCKD_D_DDR
D pin Setup/Hold with respect to CLK at DDR mode
1.61
–1.00
ns
TISDCK_DDLY_DDR/
TISCKD_DDLY_DDR
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY2)
–0.44
0.69
ns
CLKDIV to out at Q pin
2.02
ns
D input to DO output pin
2.06
ns
Setup/Hold for Data Lines
Sequential Delays
TISCKO_Q
Propagation Delays
TISDO_DO
Notes:
1. Recorded at 0 tap value.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
25
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 32: OSERDES2 Switching Characteristics
Symbol
Speed Grade
Description
-3
-2
-1L
Units
Setup/Hold
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
0.19
0.01
ns
TOSDCK_T/TOSCKD_T(1)
T input Setup/Hold with respect to CLK
0.23
–0.02
ns
TOSDCK_T2/TOSCKD_T2(1)
T input Setup/Hold with respect to CLKDIV
TOSCCK_OCE/TOSCKC_OCE
OCE input Setup/Hold with respect to CLK
TOSCCK_S
SR (Reset) input Setup with respect to CLKDIV
TOSCCK_TCE/TOSCKC_TCE
TCE input Setup/Hold with respect to CLK
0.27
–0.15
ns
TOSCKO_OQ
Clock to out from CLK to OQ
1.89
ns
TOSCKO_TQ
Clock to out from CLK to TQ
1.91
ns
ns
0.24
–0.16
ns
ns
Sequential Delays
Combinatorial
TOSDO_TTQ
T input to TQ Out
TOSCO_OQ
Asynchronous Reset to OQ
1.89
ns
TOSCO_TQ
Asynchronous Reset to TQ
1.91
ns
ns
Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report.
Input/Output Delay Switching Characteristics
Table 33: IODELAY2 Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1L
Units
TIODCCK_CAL / TIODCKC_CAL
CAL pin Setup/Hold with respect to CK
0.48
–0.22
ns
TIODCCK_CE / TIODCKC_CE
CE pin Setup/Hold with respect to CK
0.25
–0.02
ns
TIODCCK_INC/ TIODCKC_INC
INC pin Setup/Hold with respect to CK
0.18
0.06
ns
TIODCCK_RST/ TIODCKC_RST
RST pin Setup/Hold with respect to CK
0.22
–0.01
ns
TIODDO_T
TSCONTROL delay to MUXE/MUXF switching
and through IODELAY2
Note 1
Note 1
Note 1
TIODDO_IDATAIN
Propagation delay through IODELAY2
Note 1
Note 1
Note 1
TIODDO_ODATAIN
Propagation delay through IODELAY2
Note 1
Note 1
Note 1
Notes:
1. Delay depends on IODELAY2 tap setting. See TRACE report for actual values.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
26
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics (SLICEM Only)
Table 34: CLB Switching Characteristics (SLICEM Only)
Symbol
Description
Speed Grade
-3
-2
-1L
Units
Combinatorial Delays
TILO
An – Dn LUT address to A to D outputs
0.48
ns, Max
TILO
An – Dn LUT address through F7AMUX/F7BMUX
to AMUX/CMUX
0.77
ns, Max
TOPAB
An – Dn LUT address through F7AMUX or F7BMUX and
F8MUX to BMUX
0.79
ns, Max
TITO
An – Dn inputs to A – D Q outputs
1.36
ns, Max
TTITO_LOGIC
An – Dn inputs to A – D Q outputs (Latch as Logic)
1.36
ns, Max
TOPCYA
An input to COUT output
0.84
ns, Max
TOPCYB
Bn input to COUT output
0.81
ns, Max
TOPCYC
Cn input to COUT output
0.62
ns, Max
TOPCYD
Dn input to COUT output
0.58
ns, Max
TAXCY
AX input to COUT output
0.41
ns, Max
TBXCY
BX input to COUT output
0.30
ns, Max
TCXCY
CX input to COUT output
0.16
ns, Max
TDXCY
DX input to COUT output
0.14
ns, Max
TBYP
CIN input to COUT output
0.10
ns, Max
TCINA
CIN input to AMUX output
0.41
ns, Max
TCINB
CIN input to BMUX output
0.50
ns, Max
TCINC
CIN input to CMUX output
0.49
ns, Max
TCIND
CIN input to DMUX output
0.56
ns, Max
Clock to AQ – DQ outputs
0.63
ns, Max
Sequential Delays
TCKO
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TDICK/TCKDI
A – D input to CLK on A – D flip-flops
0.79
0.46
ns, Min
TCECK/TCKCE
CE input to CLK on A – D flip-flops
0.59
–0.15
ns, Min
TSRCK/TCKSR
SR input to CLK on A – D flip-flops
0.55
–0.28
ns, Min
TCINCK/TCKCIN
CIN input to CLK on A – D flip-flops
0.62
0.33
ns, Min
Set/Reset
TSRMIN
SR input minimum pulse width
TRQ
Delay from SR input to AQ – DQ flip-flops
2.54
ns, Max
TCEO
Delay from CE input to AQ – DQ flip-flops
1.15
ns, Max
FTOG
Toggle frequency (for export control)
ns, Min
MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is listed,
there is no positive hold time.
2. These items are of interest for Carry Chain applications.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
27
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 35: CLB Distributed RAM Switching Characteristics (SLICEM Only)
Symbol
Description
Speed Grade
-3
-2
Units
-1L
Sequential Delays
TSHCKO
Clock to A – D outputs
2.06
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS/TDH
A – D inputs to CLK
1.04
0.37
ns, Min
TAS/TAH
Address An inputs to clock
1.21
0.67
ns, Min
TWS/TWH
WE input to clock
0.59
–0.15
ns, Min
TCECK/TCKCE
CE input to CLK
0.59
–0.15
ns, Min
Clock CLK
TMPW
Minimum pulse width
ns, Min
TMCP
Minimum clock period
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is listed,
there is no positive hold time.
2. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 36: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1L
Units
Sequential Delays
TREG
Clock to A – D outputs
2.34
ns,
Max
TREG_MUX
Clock to AMUX – DMUX output
ns,
Max
TREG_M31
Clock to DMUX output via M31 output
ns,
Max
Setup and Hold Times Before/After Clock CLK
TWS/TWH
WE input to CLK
0.59
–0.15
ns, Min
TCECK/TCKCE
CE input to CLK
0.59
–0.15
ns, Min
TDS/TDH
A – D inputs to CLK
1.04
0.37
ns, Min
Clock CLK
TMPW
Minimum pulse width
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is listed,
there is no positive hold time.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
28
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Block RAM Switching Characteristics
Table 37: Block RAM Switching Characteristics
Symbol
Speed Grade
Description
-3
-2
Units
-1L
Block RAM Clock to Out Delays
Clock CLK to DOUT output (without output register)(1)
TRCKO_DO
TRCKO_DO_REG
Clock CLK to DOUT output (with output
register)(2)
3.00
ns, Max
1.60
ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDR/TRCKC_ADDR
ADDR inputs(3)
0.40
0.10
ns, Min
TRDCK_DI/TRCKD_DI
DIN inputs(4)
0.30
0.10
ns, Min
TRCCK_EN/TRCKC_EN
Block RAM Enable (EN) input
0.20
0.05
ns, Min
TRCCK_REGCE/TRCKC_REGCE
CE input of output register
0.20
0.08
ns, Min
TRCCK_WE/TRCKC_WE
Write Enable (WE) input
0.20
0.10
ns, Min
Block RAM in all modes
260
MHz
Maximum Frequency
FMAX
Notes:
1. TRCKO_DO includes TRCKO_DOA and TRCKO_DOPA as well as the B port equivalent timing parameters.
2. TRCKO_DO_REG includes TRCKO_DOA_REG and TRCKO_DOPA_REG as well as the B port equivalent timing parameters.
3. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
4. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.
DSP48A1 Switching Characteristics
Table 38: DSP48A1 Switching Characteristics
Symbol
Preadder
Description
Multiplier
Postadder
Speed Grade
-3
-2
-1L
Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_A_A1REG/
TDSPCKD_A_A1REG
A input to A1 register CLK
N/A
N/A
N/A
0.03
0.09
ns
TDSPDCK_D_B1REG/
TDSPCKD_D_B1REG
D input to B1 register CLK
Yes
N/A
N/A
1.99
–0.07
ns
TDSPDCK_C_CREG/
TDSPCKD_C_CREG
C input to C register CLK
N/A
N/A
N/A
–0.03
0.09
ns
TDSPDCK_D_DREG/
TDSPCKD_D_DREG
D input to D register CLK
N/A
N/A
N/A
–0.06
0.12
ns
TDSPDCK_OPMODE_B1REG/
TDSPCKD_OPMODE_B1REG
OPMODE input to B1 register CLK
Yes
N/A
N/A
2.01
0.00
ns
N/A
N/A
N/A
0.28
0.12
ns
TDSPDCK_OPMODE_OPMODEREG/ OPMODE input to OPMODE
TDSPCKD_OPMODE_OPMODEREG register CLK
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
29
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 38: DSP48A1 Switching Characteristics (Cont’d)
Symbol
Description
Preadder
Multiplier
Postadder
Speed Grade
-3
-2
-1L
Units
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_A_MREG/
TDSPCKD_A_MREG
A input to M register CLK
N/A
Yes
N/A
2.88
–0.40
ns
TDSPDCK_B_MREG/
TDSPCKD_B_MREG
B input to M register CLK
Yes
Yes
N/A
4.93
–0.68
ns
No
Yes
N/A
3.22
–0.57
ns
TDSPDCK_D_MREG/
TDSPCKD_D_MREG
D input to M register CLK
Yes
Yes
N/A
4.82
–0.56
ns
TDSPDCK_OPMODE_MREG/
TDSPCKD_OPMODE_MREG
OPMODE to M register CLK
Yes
Yes
N/A
4.84
–0.43
ns
No
Yes
N/A
3.02
–0.43
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_A_PREG/
TDSPCKD_A_PREG
A input to P register CLK
N/A
Yes
Yes
5.38
–0.76
ns
TDSPDCK_B_PREG/
TDSPCKD_B_PREG
B input to P register CLK
Yes
Yes
Yes
7.43
–1.05
ns
No
Yes
Yes
5.72
–0.93
ns
TDSPDCK_C_PREG/
TDSPCKD_C_PREG
C input to P register CLK
N/A
N/A
Yes
2.30
–0.23
ns
TDSPDCK_D_PREG/
TDSPCKD_D_PREG
D input to P register CLK
Yes
Yes
Yes
7.32
–0.92
ns
TDSPDCK_OPMODE_PREG/
TDSPCKD_OPMODE_PREG
OPMODE input to P register CLK
Yes
Yes
Yes
7.43
–0.43
ns
No
Yes
Yes
5.42
–0.43
ns
No
No
Yes
2.46
–0.39
ns
N/A
N/A
N/A
1.32
ns
N/A
N/A
Yes
4.33
ns
Clock to Out from Output Register Clock to Output Pin
TDSPCKO_P_PREG
CLK (PREG) to P output
Clock to Out from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG
CLK (MREG) to P output
Clock to Out from Input Register Clock to Output Pins
TDSPCKO_P_A1REG
CLK (A1REG) to P output
N/A
Yes
Yes
6.65
ns
TDSPCKO_P_B1REG
CLK (B1REG) to P output
N/A
Yes
Yes
6.64
ns
TDSPCKO_P_CREG
CLK (CREG) to P output
N/A
N/A
Yes
3.68
ns
TDSPCKO_P_DREG
CLK (DREG) to P output
Yes
Yes
Yes
8.99
ns
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
30
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 38: DSP48A1 Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Preadder
Multiplier
Postadder
N/A
No
Yes
3.68
ns
N/A
Yes
No
5.10
ns
N/A
Yes
Yes
6.65
ns
Yes
No
No
3.84
ns
Yes
Yes
No
6.81
ns
Yes
Yes
Yes
8.41
ns
-3
-2
-1L
Units
Combinatorial Delays from Input Pins to Output Pins
A or B input to P output
TDSPDO_A_P
TDSPDO_B_P
TDSPDO_B_P
B input to P output
TDSPDO_C_P
C input to P output
N/A
N/A
Yes
3.28
ns
TDSPDO_D_P
D input to P output
Yes
Yes
Yes
8.30
ns
TDSPDO_OPMODE_P
OPMODE input to P output
Yes
Yes
Yes
8.27
ns
No
Yes
Yes
6.50
ns
No
No
Yes
3.68
ns
Yes
Yes
Yes
250
MHz
Maximum Frequency
FMAX
All registers used
Notes:
1. A Yes signifies that the component is in the path. A No signifies that the component is being bypassed. N/A signifies not applicable because no path
exists.
Table 39: Device DNA Interface Port Switching Characteristics
Symbol
Description
TDNASSU
Setup time on SHIFT before the rising edge of CLK
TDNASH
Speed Grade
-3
-2
-1L
Units
1
ns, min
Hold time on SHIFT after the rising edge of CLK
0.5
ns, min
TDNADSU
Setup time on DIN before the rising edge of CLK
1
ns, min
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
ns, min
TDNARSU
Setup time on READ before the rising edge of CLK
5
ns, min
10,000
ns, max
0
ns, min
0.5
ns, min
1.5
ns, max
TDNARH
Hold time on READ after the rising edge of CLK
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
TDNACLKF
CLK frequency
33
MHz, max
TDNACLKL
CLK High time
10
ns, min
TDNACLKH
CLK Low time
10
ns, min
Notes:
1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 ms.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
31
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 40: Suspend Mode Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1L
Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE
Rising edge of SUSPEND pin to falling edge of AWAKE pin without
glitch filter (suspend_filter:No)
7 (typical)
ns
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch
filter enabled (suspend_filter:Yes)
300 (typical)
ns
TSUSPEND_GWE
Rising edge of SUSPEND pin until FPGA output pins drive their
defined SUSPEND constraint behavior
10 (typical)
ns
TSUSPEND_GTS
Rising edge of SUSPEND pin to write-protect lock on all writable
clocked elements
300 MHz
All
45/55
%
FVCOMIN
Minimum PLL VCO Frequency
All
MHz
FVCOMAX
Maximum PLL VCO Frequency
FBANDWIDTH
TSTAPHAOFFSET
TOUTJITTER
TOUTDUTY
TLOCKMAX
150 MHz
45
55
%
Input Frequency Ranges
CLKIN_FREQ_DLL
Input Pulse Requirements
CLKIN_PULSE
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
Cycle-to-cycle jitter at the CLKIN input
for CLKIN_FREQ_DLL < 150 MHz
±300
ps
CLKIN_CYC_JITT_DLL_HF
Cycle-to-cycle jitter at the CLKIN input
for CLKIN_FREQ_DLL > 150 MHz.
±150
ps
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input.
±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of the off-chip feedback delay
from the DCM output to the CLKFB input.
±1
ns
Notes:
1. DLL specifications apply when using any of the DLL outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV.
2. When operating independently of the DLL, the DFS supports lower CLKIN_FREQ_DLL frequencies. See Table 47.
3. To support double the maximum effective CLKIN_FREQ_DLL limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the
incoming clock period by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN_FREQ_DLL input.
4. CLKIN_FREQ_DLL input jitter beyond these limits can cause the DCM to lose LOCK, indicated by the LOCKED output deasserting. The user must
then reset the DCM.
5. When using both DCMs in a CMT, both DCMs must be LOCKED.
Table 46: Switching Characteristics for the Delay-Locked Loop (DLL) (1)
Speed Grade
Symbol
Description
-3
Min
-2
Max
-1L
Min
Max
Min
Units
Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and
CLK180 outputs.
5
250
MHz
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and
CLK270 outputs.
5
200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and
CLK2X180 outputs.
10
334
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output.
0.3125
166
MHz
Output Clock
Jitter(2,3,4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output.
–
–
±100
–
ps
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output.
–
–
±150
–
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180
output.
–
–
±150
–
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270
output.
–
–
±150
–
ps
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
38
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 46: Switching Characteristics for the Delay-Locked Loop (DLL) (1) (Cont’d)
Speed Grade
Symbol
Description
-3
Min
-2
Max
-1L
Min
Max
Min
Units
Max
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and
CLK2X180 outputs.
–
–
±[0.5% of CLKIN
period + 100]
–
ps
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output
when performing integer division.
–
–
±150
–
ps
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output
when performing non-integer
division.
–
–
±[0.5% of CLKIN
period + 100]
–
ps
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0,
CLK90, CLK180, CLK270,
CLK2X, CLK2X180, and CLKDV
outputs, including the BUFGMUX
and clock tree duty-cycle
distortion.
–
–
±[1% of CLKIN
period + 350]
–
ps
±150
–
ps
–
ps
–
ps
Duty Cycle(4)
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN
and CLKFB inputs.
–
–
CLKOUT_PHASE_DLL
Phase offset between DLL
outputs for CLK0 to CLK2X (not
CLK2X180).
–
–
Phase offset between DLL
outputs for all others.
–
LOCK_DLL(3)
–
±[1% of CLKIN
period + 100]
When using the DLL alone: The
time from deassertion at the
DCM’s reset input to the rising
transition at its LOCKED output.
When the DCM is locked, the
CLKIN and CLKFB signals are in
phase.
5 MHz < CLKIN_FREQ_DLL
< 15 MHz.
–
5
–
ms
When using the DLL alone: The
time from deassertion at the
DCM’s reset input to the rising
transition at its LOCKED output.
When the DCM is locked, the
CLKIN and CLKFB signals are in
phase.
CLKIN_FREQ_DLL > 15 MHz
–
0.60
–
ms
Finest delay resolution, averaged
over all steps.
10
40
Delay Lines
DCM_DELAY_STEP(5)
ps
Notes:
1. The values in this table are based on the operating conditions described in Table 2 and Table 45.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster LOCK time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, this data sheet specifies a maximum jitter of
±(1% of CLKIN period + 150 ps). Assuming that the CLKIN frequency is 100 MHz, the equivalent CLKIN period is 10 ns. Since 1% of 10 ns is 0.1 ns
or 100 ps, the maximum jitter is ±(100 ps + 150 ps) = ±250 ps.
5. A typical delay step size is 23 ps.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
39
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 47: Recommended Operating Conditions for the Digital Frequency Synthesizer (DFS) (1)
Speed Grade
Symbol
Description
-3
Min
-2
Max
-1L
Min
Max
0.5
333
Min
Units
Max
Input Frequency Ranges(2)
CLKIN_FREQ_FX
Frequency for the CLKIN input. Also described
as FCLKIN.
MHz
Input Clock Jitter Tolerance(3)
Cycle-to-cycle jitter at the CLKIN input, based
on CLKFX output frequency:
FCLKFX < 150 MHz.
–
–
±300
–
ps
CLKIN_CYC_JITT_FX_HF Cycle-to-cycle jitter at the CLKIN input, based
on CLKFX output frequency:
FCLKFX > 150 MHz.
–
–
±150
–
ps
CLKIN_PER_JITT_FX
–
–
±1
–
ns
CLKIN_CYC_JITT_FX_LF
Period jitter at the CLKIN input.
Notes:
1. DFS specifications apply when using either of the DFS outputs (CLKFX, CLKFXDV, or CLKFX180).
2. When using both DFS and DLL outputs on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 45.
3. CLKIN input jitter beyond these limits can cause the DCM to lose LOCK.
Table 48: Switching Characteristics for the Digital Frequency Synthesizer (DFS) (1)
Speed Grade
Symbol
Description
-3
Min
-2
Max
-1L
Min
Units
Min
Max
Max
5
320
MHz
160
MHz
Output Frequency Ranges
CLKOUT_FREQ_FX
Frequency for the CLKFX and
CLKFX180 outputs
CLKOUT_FREQ_FXDV
Frequency for the CLKFXDV
output
0.15625
Period jitter at the CLKFX,
CLKFX180, and CLKFXDV
outputs. When CLKIN < 20 MHz
Use the Jitter Calculator
ps
Period jitter at the CLKFX,
CLKFX180, and CLKFXDV
outputs. When CLKIN > 20 MHz
±(1% of
±(1% of
CLKFX period CLKFX period
+ 100)
+ 200)
ps
Output Clock Jitter(2,3)
CLKOUT_PER_JITT_FX
Duty Cycle(4,5)
Duty cycle precision for the
CLKFX, CLKFX180, and
CLKOUT_DUTY_CYCLE_FX CLKFXDV outputs, including the
BUFGMUX and clock tree dutycycle distortion
–
±(1% of
CLKFX period
+ 350)
–
ps
–
±200
–
ps
CLKOUT_PHASE_FX
Phase offset between the DFS
CLKFX or CLKFXDV output and
the DLL CLK0 output when both
the DFS and DLL are used
Phase offset between the DFS
CLKFX180 output and the DLL
CLK0 output when both the DFS
and DLL are used
–
±(1% of
CLKFX period
+ 200)
–
ps
CLKOUT_PHASE_FX180
Phase Alignment(5)
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
40
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 48: Switching Characteristics for the Digital Frequency Synthesizer (DFS) (1) (Cont’d)
Speed Grade
Symbol
Description
-3
Min
-2
Max
-1L
Min
Max
Min
Units
Max
LOCKED Time
LOCK_FX(2)
When 5 MHz < FCLKIN < 15 MHz,
the time from deassertion at the
DCM’s reset input to the rising
transition at its LOCKED output.
The DFS asserts LOCKED when
the CLKFX, CLKFX180, and
CLKFXDV signals are valid. When
using both the DLL and the DFS,
use the longer locking time.
–
–
5
–
ms
When FCLKIN > 15 MHz, the time
from deassertion at the DCM’s
reset input to the rising transition at
its LOCKED output. The DFS
asserts LOCKED when the
CLKFX, CLKFX180, and
CLKFXDV signals are valid. When
using both the DLL and the DFS,
use the longer locking time.
–
–
0.45
–
ms
Notes:
1. The values in this table are based on the operating conditions described in Table 2 and Table 47.
2. For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute.
3. Maximum output jitter is characterized using a reasonable noise environment (40 SSOs and 25% CLB switching). Output jitter strongly depends on
the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power
supply, and PCB design. The actual maximum output jitter depends on the system application.
4. The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%.
5. Some duty cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum
CLKFX jitter of ±(1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and
1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is ±(100 ps + 200 ps) = ±300 ps.
Table 49: Recommended Operating Conditions for the Phase-Shift Clock in Variable Phase Mode
Speed Grade
Symbol
Description
-3
Min
-2
Max
-1L
Min
Units
Min
Max
Max
1
167
MHz
40
60
%
Operating Frequency Ranges
PSCLK_FREQ
Frequency for the PSCLK input.
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK
period.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
41
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 50: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode(1)
Symbol
Description
Amount of Phase Shift
Units
When CLKIN < 60 MHz, the maximum allowed
number of DCM_DELAY_STEP steps for a
given CLKIN clock period, where T = CLKIN
clock period in ns. When using
CLKIN_DIVIDE_BY_2 = TRUE, double the
clock-effective clock period.
±(INTEGER(10 x (TCLKIN – 3 ns)))
steps
When CLKIN ≥ 60 MHz, the maximum allowed
number of DCM_DELAY_STEP steps for a
given CLKIN clock period, where T = CLKIN
clock period in ns. When using
CLKIN_DIVIDE_BY_2 = TRUE, double the
clock-effective clock period.
±(INTEGER(15 x (TCLKIN – 3 ns)))
steps
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase
shifting.
±(MAX_STEPS x DCM_DELAY_STEP_MIN)
ns
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase
shifting
±(MAX_STEPS x DCM_DELAY_STEP_MAX)
ns
Phase Shifting Range
MAX_STEPS(2)
Notes:
1. The values in this table are based on the operating conditions described in Table 45 and Table 49.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM has no initial fixed-phase shifting, that is, the PHASE_SHIFT
attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the end of Table 46.
Table 51: Miscellaneous DCM Timing Parameters(1)
Symbol
Description
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
Min
Max
Units
3
–
CLKIN cycles
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM
DFS outputs (CLKFX, CLKFXDV, CLKFX180) are unaffected.
Table 52: Frequency Synthesis
Attribute
Min
Max
CLKFX_MULTIPLY
2
32
CLKFX_DIVIDE
1
32
Table 53: DCM Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1L
Units
TDMCCK_PSEN/ TDMCKC_PSEN
PSEN Setup/Hold
0.03/
0.00
ns
TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC
PSINCDEC Setup/Hold
0.03/
0.00
ns
TDMCKO_PSDONE
Clock to out of PSDONE
0.05
ns
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
42
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Spartan-6 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 54. Values are expressed in nanoseconds unless otherwise noted.
Table 54: Global Clock Input to Output Delay Without DCM or PLL
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL
TICKOF
Global Clock and OUTFF without DCM or PLL
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
43
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 55: Global Clock Input to Output Delay With DCM in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in System-Synchronous Mode.
TICKOFDCM
Global Clock and OUTFF with DCM
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
44
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 56: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in Source-Synchronous Mode.
TICKOFDCM_0
Global Clock and OUTFF with DCM
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
ns
ns
XC6SLX45T
N/A
XC6SLX75
ns
ns
XC6SLX75T
N/A
XC6SLX100
ns
ns
XC6SLX100T
N/A
XC6SLX150
ns
ns
XC6SLX150T
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
Table 57: Global Clock Input to Output Delay With PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode.
TICKOFPLL
Global Clock and OUTFF with PLL
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
45
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 58: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode.
TICKOFPLL_0
Global Clock and OUTFF with PLL
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
ns
ns
XC6SLX45T
N/A
XC6SLX75
ns
ns
XC6SLX75T
N/A
XC6SLX100
ns
ns
XC6SLX100T
N/A
XC6SLX150
ns
ns
XC6SLX150T
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
Table 59: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in System-Synchronous Mode.
TICKOFDCM_PLL
Global Clock and OUTFF with DCM and PLL
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
46
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 60: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in Source-Synchronous Mode.
TICKOFDCM0_PLL
Global Clock and OUTFF with DCM and PLL
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
47
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Spartan-6 Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 61. Values are expressed in nanoseconds unless otherwise noted.
Table 61: Global Clock Setup and Hold Without DCM or PLL
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSFD/ TPHFD
Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF(2) without DCM or PLL
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed,
there is no positive hold time.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
48
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 62: Global Clock Setup and Hold With DCM in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCM/ TPHDCM
No Delay Global Clock and IFF(2) with DCM in
System-Synchronous Mode
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
ns
ns
XC6SLX45T
N/A
XC6SLX75
ns
ns
XC6SLX75T
N/A
XC6SLX100
ns
ns
XC6SLX100T
N/A
XC6SLX150
ns
ns
XC6SLX150T
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 63: Global Clock Setup and Hold With DCM in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in
Source-Synchronous Mode
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
49
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 64: Global Clock Setup and Hold With PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSPLL/ TPHPLL
No Delay Global Clock and IFF(2) with PLL in
System-Synchronous Mode
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
ns
ns
XC6SLX45T
N/A
XC6SLX75
ns
ns
XC6SLX75T
N/A
XC6SLX100
ns
ns
XC6SLX100T
N/A
XC6SLX150
ns
ns
XC6SLX150T
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 65: Global Clock Setup and Hold With PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSPLL0/ TPHPLL0
No Delay Global Clock and IFF(2) with PLL in
Source-Synchronous Mode
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
50
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 66: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCMPLL/
TPHDCMPLL
No Delay Global Clock and IFF(2) with
DCM and PLL in System-Synchronous Mode
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0
driving BUFG.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
51
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 67: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1L
Units
Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM, PLL, and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics, page 15.
TPSDCMPLL_0/
TPHDCMPLL_0
No Delay Global Clock and IFF (2) with DCM and
PLL in Source-Synchronous Mode
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
XC6SLX45T
ns
N/A
XC6SLX75
XC6SLX75T
N/A
ns
ns
N/A
XC6SLX150
XC6SLX150T
ns
ns
XC6SLX100
XC6SLX100T
ns
ns
ns
N/A
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM.
These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package skew is not included in these
measurements.
2. IFF = Input Flip-Flop
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
52
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Spartan-6 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 68: Duty Cycle Distortion and Clock-Tree Skew
Symbol
TDCD_CLK
TCKSKEW
Description
Device
Global Clock Tree Duty Cycle Distortion (1)
Global Clock Tree Skew
(2)
Speed Grade
-3
-2
-1L
Units
All
ns
XC6SLX4
ns
XC6SLX9
ns
XC6SLX16
ns
XC6SLX25
ns
XC6SLX25T
N/A
XC6SLX45
ns
ns
XC6SLX45T
N/A
XC6SLX75
ns
ns
XC6SLX75T
N/A
XC6SLX100
ns
ns
XC6SLX100T
N/A
XC6SLX150
ns
ns
XC6SLX150T
N/A
ns
TDCD_BUFIO
I/O clock tree duty cycle distortion
All
ns
TBUFIOSKEW
I/O clock tree skew across one clock region
All
ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where
other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists
for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
Table 69: Package Skew
Symbol
TPKGSKEW
Description
Package
Device
Skew(1)
XC6SLX4
XC6SLX9
XC6SLX16
DS162 (v1.1) August 26, 2009
Advance Product Specification
Package(3)
Value
Units
TQG144
ps
CPG196
ps
CSG225
ps
TQG144
ps
CPG196
ps
CSG225
ps
FT(G)256
ps
CSG324
ps
CPG196
ps
CSG225
ps
FT(G)256
ps
CSG324
ps
www.xilinx.com
53
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 69: Package Skew (Cont’d)
Symbol
TPKGSKEW
Description
Device
Package Skew(1)
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
Package(3)
Value
Units
FT(G)256
ps
CSG324
ps
FG(G)484
ps
CSG324
ps
FG(G)484
ps
CSG324
ps
CSG484
ps
FG(G)484
ps
FG(G)676
ps
CSG324
ps
CSG484
ps
FG(G)484
ps
CSG324
ps
CSG484
ps
FG(G)676
ps
CSG324
ps
CSG484
ps
FG(G)676
ps
CSG484
ps
FG(G)484
ps
FG(G)676
ps
CSG484
ps
FG(G)484
ps
FG(G)676
ps
FG(G)900
ps
CSG484
ps
FG(G)484
ps
FG(G)676
ps
FG(G)900
ps
CSG484
ps
FG(G)484
ps
FG(G)676
ps
FG(G)900
ps
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time from Pad
to Ball (7.0 ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
3. Some of these devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
54
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 70: Sample Window
Symbol
Description
Device
Sampling Error at Receiver Pins(1)
TSAMP
TSAMP_BUFIO
Sampling Error at Receiver Pins using
BUFIO(2)
Speed Grade
-3
-2
-1L
Units
All
ps
All
ps
Notes:
1. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 71: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Speed Grade
Description
-3
-2
-1L
Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
TPSCS/TPHCS
Setup/Hold of I/O clock
ns
Pin-to-Pin Clock-to-Out Using BUFIO
Clock-to-Out of I/O clock
TICKOFCS
ns
Revision History
The following table shows the revision history for this document.
Date
Version
Description of Revisions
06/24/09
1.0
Initial Xilinx release.
08/26/09
1.1
Added VFS to Table 1and Table 2. Added RFUSE to Table 2. Added XC6SLX75 and XC6SLX75T to
VBATT and IBATT in Table 1, Table 2, and Table 3. Corrected the quiescent supply current for the
XC6SLX4 in Table 4. Updated Table 8. Removed DVPPIN from Figure 2. Removed FPCIECORE from
Table 21 and added values to FPCIEUSER. Added more networking applications to Table 22. Updated
values for TSUSPENDLOW_AWAKE, TSUSPEND_ENABLE, and TSCP_AWAKE in Table 40. Numerous changes
to Table 41, page 33 including the addition of new values to various specifications, revising the
TSMCKCSO description, and changing the units of TPOR. Also, removed Dynamic Reconfiguration Port
(DRP) for DCM and PLL Before and After DCLK section from Table 41 and updated all the notes. In
Table 44, added to FINMAX, revised FOUTMAX, and removed PLL Maximum Output Frequency for
BUFIO2. Revised values for DCM_DELAY_STEP in Table 46. Updated CLKIN_FREQ_FX values in
Table 47.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS162 (v1.1) August 26, 2009
Advance Product Specification
www.xilinx.com
55
