XC6VCX130T

52 Virtex-6 CXT Family Data Sheet DS153 (v1.6) February 11, 2011 Product Specification General Description Virtex®-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1 slices, enhanced mixed-mode clock management blocks, PCI Express® (GEN 1) compatible integrated blocks, a tri-mode Ethernet media access controller (MAC), up to 241K logic cells, and strong IP support. Using the third generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-6 CXT family also contains SelectIO™ technology with built-in digitally controlled impedance, ChipSync™ source-synchronous interface blocks, enhanced mixed-mode clock management blocks, and advanced configuration options. Customers needing higher transceiver speeds, greater I/O performance, additional Ethernet MACs, or greater capacity should instead use the Virtex-6 LXT or SXT families. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 CXT FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 CXT FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Summary of Virtex-6 CXT FPGA Features • Advanced, high-performance, FPGA Logic • Real 6-input look-up table (LUT) technology • Dual LUT5 (5-input LUT) option • LUT/dual flip-flop pair for applications requiring rich register mix • Improved routing efficiency • 64-bit (or 32 x 2-bit) distributed LUT RAM option • SRL32/dual SRL16 with registered outputs option Powerful mixed-mode clock managers (MMCM) • MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, input-jitter filtering, and phase-matched clock division 36-Kb block RAM/FIFOs • Dual-port RAM blocks • Programmable Dual-port widths up to 36 bits Simple dual-port widths up to 72 bits • Enhanced programmable FIFO logic • Built-in optional error-correction circuitry • Optionally use each block as two independent 18 Kb blocks High-performance parallel SelectIO technology • 1.2 to 2.5V I/O operation • Source-synchronous interfacing using ChipSync™ technology • Digitally controlled impedance (DCI) active termination • Flexible fine-grained I/O banking • High-speed memory interface support with integrated write-leveling capability • Advanced DSP48E1 slices • 25 x 18, two's complement multiplier/accumulator • Optional pipelining • New optional pre-adder to assist filtering applications • Optional bitwise logic functionality • Dedicated cascade connections Flexible configuration options • SPI and Parallel Flash interface • Multi-bitstream support with dedicated fallback reconfiguration logic • Automatic bus width detection Integrated interface blocks for PCI Express designs • Compliant to the PCI Express Base Specification 2.0 • Gen1 Endpoint (2.5 Gb/s) support with GTX transceivers • x1, x2, x4, or x8 lane support per block • One virtual channel, eight traffic classes GTX transceivers: 150 Mb/s to 3.75 Gb/s Integrated 10/100/1000 Mb/s Ethernet MAC block • Supports 1000BASE-X PCS/PMA and SGMII using GTX transceivers • Supports MII, GMII, and RGMII using SelectIO technology resources 40 nm copper CMOS process technology 1.0V core voltage Two speed grades (-1 and -2) Two temperature grades (commercial and industrial) High signal-integrity flip-chip packaging available in standard or Pb-free package options Compatibility across sub-families: CXT, LXT, and SXT devices are footprint compatible in the same package • • • • • • • • • • • • • © 2009–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 1 Virtex-6 CXT Family Data Sheet Virtex-6 CXT FPGA Feature Summary Table 1: Virtex-6 CXT FPGA Feature Summary by Device Configurable Logic Blocks (CLBs) Device Logic Cells Slices(1) Max Distributed RAM (Kb) DSP48E1 Slices(2) Block RAM Blocks MMCMs(4) 18 Kb(3) 36 Kb Max (Kb) Interface Maximum Ethernet Blocks for GTX MACs(5) PCI Express Transceivers Total I/O Banks(6) Max User I/O(7) XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T 74,496 128,000 199,680 241,152 11,640 20,000 31,200 37,680 1,045 1,740 3,040 3,650 288 480 640 768 312 528 688 832 156 264 344 416 5,616 9,504 12,384 14,976 6 10 10 12 1 2 2 2 1 1 1 1 12 16 16 16 9 15 15 18 360 600 600 600 Notes: 1. 2. 3. 4. 5. 6. 7. Each Virtex-6 CXT FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs. Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks. Each CMT contains two mixed-mode clock managers (MMCM). This table lists individual Ethernet MACs per device. Does not include configuration Bank 0. This number does not include GTX transceivers. Virtex-6 CXT FPGA Device-Package Combinations and Maximum I/Os Virtex-6 CXT FPGA package combinations with the maximum available I/Os per package are shown in Table 2. Table 2: Virtex-6 CXT FPGA Device-Package Combinations and Maximum Available I/Os Package Size (mm) Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T GTs 8 GTXs 8 GTXs FF484 FFG484 23 x 23 I/O 240 240 GTs 12 GTXs 12 GTXs 12 GTXs 12 GTXs FF784 FFG784 29 x 29 I/O 360 400 400 400 16 GTXs 16 GTXs 16 GTXs 600 600 600 GTs FF1156 FFG1156 35 x 35 I/O Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). Virtex-6 CXT FPGA Ordering Information The Virtex-6 CXT FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free. X-Ref Target - Figure 1 Example: XC6VCX240T-1FFG1156C Device Type Speed Grade (-1, -2) Temperature Range: C = Commercial (TJ = 0°C to +85°C) I = Industrial (TJ = –40°C to +100°C) Number of Pins Pb-Free Package Type DS153_01_062109 Figure 1: Virtex-6 CXT FPGA Ordering Information DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 2 Virtex-6 CXT Family Data Sheet Virtex-6 CXT FPGA Documentation In addition to the data sheet information found herein, complete and up-to-date documentation of the Virtex-6 family of FPGAs is available on the Xilinx website and available for download: Virtex-6 FPGA Configuration Guide (UG360) This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques. Virtex-6 FPGA SelectIO Resources User Guide (UG361) This guide describes the SelectIO™ resources available in all the Virtex-6 CXT devices. Virtex-6 FPGA Clocking Resources User Guide (UG362) This guide describes the clocking resources available in all the Virtex-6 CXT devices, including the MMCM and clock buffers. Virtex-6 FPGA Memory Resources User Guide (UG363) This guide describes the Virtex-6 CXT device block RAM and FIFO capabilities. Virtex-6 FPGA CLB User Guide (UG364) This guide describes the capabilities of the configurable logic blocks (CLB) available in all Virtex-6 CXT devices. Virtex-6 FPGA DSP48E1 Slice User Guide (UG369) This guide describes the architecture of the DSP48E1 slice in Virtex-6 CXT FPGAs and provides configuration examples. Virtex-6 FPGA Packaging and Pinout Specifications (UG365) These specifications includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications of the Virtex-6 LXT and SXT families. Reference these specifications when considering device migration to the Virtex-6 LXT and SXT families. Virtex-6 FPGA GTX Transceivers User Guide (UG366) This guide describes the GTX transceivers available in all the Virtex-6 CXT FPGAs. Virtex-6 FPGA Tri-Mode Ethernet MAC User Guide (UG368) This guide describes the dedicated tri-mode Ethernet media access controller (TEMAC) available in all the Virtex-6 CXT FPGAs. Virtex-6 FPGA Data Sheet: DC and Switching Characteristics (DS152) Reference this data sheet when considering device migration to the Virtex-6 LXT and SXT families. It contains the DC and Switching Characteristic specifications specifically for the Virtex-6 LXT and SXT families. Configuration Bitstream Overview for CXT Devices This section contains two tables similar to those in the Virtex-6 FPGA Configuration Guide only updated for the CXT family. The Virtex-6 CXT FPGA bitstream contains commands to the FPGA configuration logic as well as configuration data. Table 3 gives a typical bitstream length and Table 4 gives the specific device ID codes for the Virtex-6 CXT devices. Table 3: Virtex-6 CXT FPGA Bitstream Length Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Table 4: Virtex-6 CXT FPGA Device ID Codes Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Total Number of Configuration Bits 26,239,328 43,719,776 61,552,736 73,859,552 ID Code (Hex) 0x042C4093 0x042CA093 0x042CC093 0x042D0093 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 3 Virtex-6 CXT Family Data Sheet CLB Overview for CXT Devices Table 5, updated specifically for the CXT family from a similar table in the Virtex-6 FPGA CLB User Guide, shows the available resources in all Virtex-6 CXT FPGA CLBs. Table 5: Virtex-6 CXT FPGA Logic Resources Available in All CLBs Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Total Slices 11,640 20,000 31,200 37,680 SLICELs SLICEMs 7,460 13,040 19,040 23,080 4,180 6,960 12,160 14,600 Number of 6-Input LUTs 46,560 80,000 124,800 150,720 Maximum Distributed RAM (Kb) 1045 1740 3140 3770 Shift Register (Kb) 522.5 870 1570 1885 Number of Flip-Flops 93,120 160,000 249,600 301,440 Regional Clock Management for CXT Devices Table 6, updated from the Virtex-6 FPGA Clocking Resources User Guide specifically for the CXT family, shows the number of clock regions in all Virtex-6 CXT FPGA CLBs. Table 6: Virtex-6 CXT FPGA Clock Regions Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Number of Clock Regions 6 10 10 12 CXT Packaging Specifications Table 7, updated from the Virtex-6 FPGA Packaging and Pinout Specifications specifically for the CXT family, shows the number of GTX transceiver I/O channels. Table 8 shows the number of available I/Os and the number of differential I/O pairs for each Virtex-6 device/package combination. Table 7: Number of Serial Transceivers (GTs) I/O Channels/Device I/O Channels MGTRXP MGTRXN MGTTXP MGTTXN Notes: 1. 2. 3. 4. The XC6VCX75T has 8 GTX I/O channels in the FF484/FFG484 package and 12 GTX I/O channels in the FF784/FFG784 package. The XC6VCX130T has 8 GTX I/O channels in the FF484/FFG484 package, 12 GTX I/O channels in the FF784/FFG784 package, and 16 GTX I/O channels in the FF1156/FFG1156 package. The XC6VCX195T has 12 GTX I/O channels in the FF784/FFG784 package and 16 GTX I/O channels in the FF1156/FFG1156 package. The XC6VCX240T has 12 GTX I/O channels in the FF784/FFG784 package and 16 GTX I/O channels in the FF1156/FFG1156 package. Device CX75T(1) 8 or 12 8 or 12 8 or 12 8 or 12 CX130T(2) 8, 12, or 16 8, 12, or 16 8, 12, or 16 8, 12, or 16 CX195T(3) 12 or 16 12 or 16 12 or 16 12 or 16 CX240T(4) 12 or 16 12 or 16 12 or 16 12 or 16 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 4 Virtex-6 CXT Family Data Sheet Table 8: Available I/O Pin/Device/Package Combinations Virtex-6 CXT Device Virtex-6 CXT FPGA Package User I/O Pins FF484 Available User I/Os XC6VCX75T Differential I/O Pairs Available User I/Os XC6VCX130T Differential I/O Pairs Available User I/Os XC6VCX195T Differential I/O Pairs Available User I/Os XC6VCX240T Differential I/O Pairs – – – FF784 360 180 400 200 400 200 400 200 FF1156 – – 240 120 240 120 – 600 300 600 300 600 300 GTX Transceivers in CXT Devices CXT devices have between 8 to 16 gigabit transceiver circuits. Each GTX transceiver is a combined transmitter and receiver capable of operating at a data rate between 480 Mb/s and 3.75 Gb/s. Lower data rates can be achieved using FPGA logicbased oversampling. The transmitter and receiver are independent circuits that use separate PLLs to multiply the reference frequency input by certain programmable numbers between 2 and 25, to become the bit-serial data clock. Each GTX transceiver has a large number of user-definable features and parameters. All of these can be defined during device configuration, and many can also be modified during operation. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 5 Virtex-6 CXT Family Data Sheet FF484 Package Placement Diagrams Figure 2 and Figure 3 show the placement diagrams for the GTX transceivers in the FF484 package. Note: Unbonded locations in the FF484 package are: • • X-Ref Target - Figure 2 CX75T: X0Y8, X0Y9, X0Y10, X0Y11 CX130T: X0Y0, X0Y1, X0Y2, X0Y3, and X0Y12, X0Y13, X0Y14, X0Y15 X-Ref Target - Figure 3 B1 B2 CX75T: GTXE1_X0Y7 CX130T: GTXE1_X0Y11 D1 D2 MGTRXP3_115 MGTRXN3_115 CX75T: GTXE1_X0Y3 CX130T: GTXE1_X0Y7 MGTTXP3_115 MGTTXN3_115 W3 W4 MGTRXP3_114 MGTRXN3_114 M1 M2 MGTTXP3_114 MGTTXN3_114 C3 C4 CX75T: GTXE1_X0Y6 CX130T: GTXE1_X0Y10 F1 F2 J4 J3 QUAD_115 L4 L3 E3 E4 CX75T: GTXE1_X0Y5 CX130T: GTXE1_X0Y9 H1 H2 MGTRXP2_115 MGTRXN2_115 CX75T: GTXE1_X0Y2 CX130T: GTXE1_X0Y6 MGTTXP2_115 MGTTXN2_115 Y1 Y2 MGTRXP2_114 MGTRXN2_114 P1 P2 R4 R3 QUAD_114 MGTTXP2_114 MGTTXN2_114 MGTREFCLK1P_115 MGTREFCLK1N_115 MGTREFCLK1P_114 MGTREFCLK1N_114 MGTREFCLK0P_115 MGTREFCLK0N_115 U4 U3 AA3 AA4 CX75T: GTXE1_X0Y1 CX130T: GTXE1_X0Y5 MGTREFCLK0P_114 MGTREFCLK0N_114 MGTRXP1_115 MGTRXN1_115 MGTRXP1_114 MGTRXN1_114 MGTTXP1_115 MGTTXN1_115 T1 T2 MGTTXP1_114 MGTTXN1_114 G3 G4 CX75T: GTXE1_X0Y4 CX130T: GTXE1_X0Y8 K1 K2 MGTRXP0_115 MGTRXN0_115 CX75T: GTXE1_X0Y0 CX130T: GTXE1_X0Y4 MGTTXP0_115 MGTTXN0_115 ds153_02_041510 AB1 AB2 MGTRXP0_114 MGTRXN0_114 V1 V2 MGTTXP0_114 MGTTXN0_114 ds153_03_041510 Figure 2: Placement Diagram for the FF484 Package (1 of 2) Figure 3: Placement Diagram for the FF484 Package (2 of 2) DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 6 Virtex-6 CXT Family Data Sheet FF784 Package Placement Diagrams Figure 4 through Figure 6 show the placement diagrams for the GTX transceivers in the FF784 package. Note: Unbonded locations in the FF784 package are: • • • X-Ref Target - Figure 4 CX130T: X0Y0, X0Y1, X0Y2, X0Y3 CX195T: X0Y0, X0Y1, X0Y2, X0Y3 CX240T: X0Y0, X0Y1, X0Y2, X0Y3 X-Ref Target - Figure 5 A3 CX75T: GTXE1_X0Y11 CX130T: GTXE1_X0Y15 CX195T: GTXE1_X0Y15 CX240T: GTXE1_X0Y15 A4 MGTRXP3_116 MGTRXN3_116 CX75T: GTXE1_X0Y7 CX130T: GTXE1_X0Y11 CX195T: GTXE1_X0Y11 CX240T: GTXE1_X0Y11 L3 L4 MGTRXP3_115 MGTRXN3_115 D1 D2 MGTTXP3_116 MGTTXN3_116 M1 M2 MGTTXP3_115 MGTTXN3_115 B1 CX75T: GTXE1_X0Y10 CX130T: GTXE1_X0Y14 CX195T: GTXE1_X0Y14 CX240T: GTXE1_X0Y14 B2 MGTRXP2_116 MGTRXN2_116 CX75T: GTXE1_X0Y6 CX130T: GTXE1_X0Y10 CX195T: GTXE1_X0Y10 CX240T: GTXE1_X0Y10 N3 N4 MGTRXP2_115 MGTRXN2_115 F1 F2 G4 G3 MGTTXP2_116 MGTTXN2_116 P1 P2 P6 P5 MGTTXP2_115 MGTTXN2_115 MGTREFCLK1P_116 MGTREFCLK1N_116 QUAD_115 MGTREFCLK1P_115 MGTREFCLK1N_115 QUAD_116 J4 J3 C3 CX75T: GTXE1_X0Y9 CX130T: GTXE1_X0Y13 CX195T: GTXE1_X0Y13 CX240T: GTXE1_X0Y13 C4 MGTREFCLK0P_116 MGTREFCLK0N_116 T6 T5 R3 CX75T: GTXE1_X0Y5 CX130T: GTXE1_X0Y9 CX195T: GTXE1_X0Y9 CX240T: GTXE1_X0Y9 R4 MGTREFCLK0P_115 MGTREFCLK0N_115 MGTRXP1_116 MGTRXN1_116 MGTRXP1_115 MGTRXN1_115 H1 H2 MGTTXP1_116 MGTTXN1_116 T1 T2 MGTTXP1_115 MGTTXN1_115 E3 CX75T: GTXE1_X0Y8 CX130T: GTXE1_X0Y12 CX195T: GTXE1_X0Y12 CX240T: GTXE1_X0Y12 E4 MGTRXP0_116 MGTRXN0_116 CX75T: GTXE1_X0Y4 CX130T: GTXE1_X0Y8 CX195T: GTXE1_X0Y8 CX240T: GTXE1_X0Y8 U3 U4 MGTRXP0_115 MGTRXN0_115 K1 K2 MGTTXP0_116 MGTTXN0_116 ds153_04_041510 V1 V2 MGTTXP0_115 MGTTXN0_115 ds153_05_041510 Figure 4: Placement Diagram for the FF784 Package (1 of 3) Figure 5: Placement Diagram for the FF784 Package (2 of 3) DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 7 Virtex-6 CXT Family Data Sheet X-Ref Target - Figure 6 AC3 CX75T: GTXE1_X0Y3 CX130T: GTXE1_X0Y7 CX195T: GTXE1_X0Y7 CX240T: GTXE1_X0Y7 AC4 MGTRXP3_114 MGTRXN3_114 Y1 Y2 MGTTXP3_114 MGTTXN3_114 AE3 CX75T: GTXE1_X0Y2 CX130T: GTXE1_X0Y6 CX195T: GTXE1_X0Y6 CX240T: GTXE1_X0Y6 AE4 MGTRXP2_114 MGTRXN2_114 AB1 AB2 W4 W3 MGTTXP2_114 MGTTXN2_114 MGTREFCLK1P_114 MGTREFCLK1N_114 QUAD_114 AA4 AA3 AG3 CX75T: GTXE1_X0Y1 CX130T: GTXE1_X0Y5 CX195T: GTXE1_X0Y5 CX240T: GTXE1_X0Y5 AG4 MGTREFCLK0P_114 MGTREFCLK0N_114 MGTRXP1_114 MGTRXN1_114 AD1 AD2 MGTTXP1_114 MGTTXN1_114 AH1 CX75T: GTXE1_X0Y0 CX130T: GTXE1_X0Y4 CX195T: GTXE1_X0Y4 CX240T: GTXE1_X0Y4 AH2 MGTRXP0_114 MGTRXN0_114 AF1 AF2 MGTTXP0_114 MGTTXN0_114 ds153_06_041510 Figure 6: Placement Diagram for the FF784 Package (3 of 3) DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 8 Virtex-6 CXT Family Data Sheet FF1156 Package Placement Diagrams Figure 7 through Figure 10 show the placement diagrams for the GTX transceivers in the FF1156 package. X-Ref Target - Figure 7 X-Ref Target - Figure 8 B5 CX130T: GTXE1_X0Y15 CX195T: GTXE1_X0Y15 CX240T: GTXE1_X0Y15 B6 MGTRXP3_116 MGTRXN3_116 CX130T: GTXE1_X0Y11 CX195T: GTXE1_X0Y11 CX240T: GTXE1_X0Y11 J3 J4 MGTRXP3_115 MGTRXN3_115 A3 A4 MGTTXP3_116 MGTTXN3_116 F1 F2 MGTTXP3_115 MGTTXN3_115 D5 CX130T: GTXE1_X0Y14 CX195T: GTXE1_X0Y14 CX240T: GTXE1_X0Y14 D6 MGTRXP2_116 MGTRXN2_116 CX130T: GTXE1_X0Y10 CX195T: GTXE1_X0Y10 CX240T: GTXE1_X0Y10 K5 K6 MGTRXP2_115 MGTRXN2_115 B1 B2 F6 F5 MGTTXP2_116 MGTTXN2_116 H1 H2 M6 M5 MGTTXP2_115 MGTTXN2_115 MGTREFCLK1P_116 MGTREFCLK1N_116 QUAD_115 MGTREFCLK1P_115 MGTREFCLK1N_115 QUAD_116 H6 H5 E3 CX130T: GTXE1_X0Y13 CX195T: GTXE1_X0Y13 CX240T: GTXE1_X0Y13 E4 MGTREFCLK0P_116 MGTREFCLK0N_116 P6 P5 L3 CX130T: GTXE1_X0Y9 CX195T: GTXE1_X0Y9 CX240T: GTXE1_X0Y9 L4 MGTREFCLK0P_115 MGTREFCLK0N_115 MGTRXP1_116 MGTRXN1_116 MGTRXP1_115 MGTRXN1_115 C3 C4 MGTTXP1_116 MGTTXN1_116 K1 K2 MGTTXP1_115 MGTTXN1_115 G3 CX130T: GTXE1_X0Y12 CX195T: GTXE1_X0Y12 CX240T: GTXE1_X0Y12 G4 MGTRXP0_116 MGTRXN0_116 CX130T: GTXE1_X0Y8 CX195T: GTXE1_X0Y8 CX240T: GTXE1_X0Y8 N3 N4 MGTRXP0_115 MGTRXN0_115 D1 D2 MGTTXP0_116 MGTTXN0_116 ds153_07_020210 M1 M2 MGTTXP0_115 MGTTXN0_115 ds153_08_020210 Figure 7: Placement Diagram for the FF1156 Package (1 of 4) Figure 8: Placement Diagram for the FF1156 Package (2 of 4) DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 9 Virtex-6 CXT Family Data Sheet X-Ref Target - Figure 9 X-Ref Target - Figure 10 R3 CX130T: GTXE1_X0Y7 CX195T: GTXE1_X0Y7 CX240T: GTXE1_X0Y7 R4 MGTRXP3_114 MGTRXN3_114 CX130T: GTXE1_X0Y3 CX195T: GTXE1_X0Y3 CX240T: GTXE1_X0Y3 AC3 AC4 MGTRXP3_113 MGTRXN3_113 P1 P2 MGTTXP3_114 MGTTXN3_114 AB1 AB2 MGTTXP3_113 MGTTXN3_113 U3 CX130T: GTXE1_X0Y6 CX195T: GTXE1_X0Y6 CX240T: GTXE1_X0Y6 U4 MGTRXP2_114 MGTRXN2_114 CX130T: GTXE1_X0Y2 CX195T: GTXE1_X0Y2 CX240T: GTXE1_X0Y2 AE3 AE4 MGTRXP2_113 MGTRXN2_113 T1 T2 T6 T5 MGTTXP2_114 MGTTXN2_114 AD1 AD2 AB6 AB5 MGTTXP2_113 MGTTXN2_113 MGTREFCLK1P_114 MGTREFCLK1N_114 QUAD_113 MGTREFCLK1P_113 MGTREFCLK1N_113 QUAD_114 V6 V5 W3 CX130T: GTXE1_X0Y5 CX195T: GTXE1_X0Y5 CX240T: GTXE1_X0Y5 W4 MGTREFCLK0P_114 MGTREFCLK0N_114 AD6 AD5 AF5 CX130T: GTXE1_X0Y1 CX195T: GTXE1_X0Y1 CX240T: GTXE1_X0Y1 AF6 MGTREFCLK0P_113 MGTREFCLK0N_113 MGTRXP1_114 MGTRXN1_114 MGTRXP1_113 MGTRXN1_113 V1 V2 MGTTXP1_114 MGTTXN1_114 AF1 AF2 MGTTXP1_113 MGTTXN1_113 AA3 CX130T: GTXE1_X0Y4 CX195T: GTXE1_X0Y4 CX240T: GTXE1_X0Y4 AA4 MGTRXP0_114 MGTRXN0_114 CX130T: GTXE1_X0Y0 CX195T: GTXE1_X0Y0 CX240T: GTXE1_X0Y0 AG3 AG4 MGTRXP0_113 MGTRXN0_113 Y1 Y2 MGTTXP0_114 MGTTXN0_114 ds153_09_020210 AH1 AH2 MGTTXP0_113 MGTTXN0_113 ds153_10_020210 Figure 9: Placement Diagram for the FF1156 Package (3 of 4) Figure 10: Placement Diagram for the FF1156 Package (4 of 4) DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 10 Virtex-6 CXT Family Data Sheet Virtex-6 CXT FPGA Electrical Characteristics Introduction Virtex-6 CXT FPGAs are available in -2 and -1 speed grades, with -2 having the highest performance. Virtex-6 CXT FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. All specifications are subject to change without notice. Virtex-6 CXT FPGA DC Characteristics Table 9: Absolute Maximum Ratings(1) Symbol VCCINT VCCAUX VCCO VBATT VFS VREF VIN (3) Description Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply External voltage supply for eFUSE Input reference voltage 2.5V or below I/O input voltage relative to Voltage applied to 3-state 2.5V or below Storage temperature (ambient) Maximum soldering Maximum junction temperature(5) temperature(5) GND(4) (user and dedicated I/Os) (user and dedicated I/Os) output(4) programming(2) –0.5 to 1.1 –0.5 to 3.0 –0.5 to 3.0 –0.5 to 3.0 –0.5 to 3.0 –0.5 to 3.0 –0.5 to VCCO  0.5 –0.5 to VCCO  0.5 –65 to 150 220 125 Units V V V V V V V V °C °C °C VTS TSTG TSOL Tj Notes: 1. 2. 3. 4. 5. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. When not programming eFUSE, connect VFS to GND. 2.5V I/O absolute maximum limit applied to DC and AC signals. For I/O operation, refer to the Virtex-6 FPGA SelectIO Resources User Guide. For soldering guidelines and thermal considerations, see Virtex-6 FPGA Packaging and Pinout Specification. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 11 Virtex-6 CXT Family Data Sheet Table 10: Recommended Operating Conditions Symbol VCCINT VCCAUX VCCO(1)(2)(3) Description Internal supply voltage relative to GND, Tj = 0C to +85C Internal supply voltage relative to GND, Tj = –40C to +100C Auxiliary supply voltage relative to GND, Tj = 0C to +85C Auxiliary supply voltage relative to GND, Tj = –40C to +100C Supply voltage relative to GND, Tj = 0C to +85C Supply voltage relative to GND, Tj = –40C to +100C 2.5V supply voltage relative to GND, Tj = 0C to +85C 2.5V supply voltage relative to GND, Tj = –40C to +100C 2.5V and below supply voltage relative to GND, Tj = 0C to +85C 2.5V and below supply voltage relative to GND, Tj = –40C to +100C Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. Battery voltage relative to GND, Tj = 0C to +85C Battery voltage relative to GND, Tj = –40C to +100C External voltage supply for eFUSE programming Min 0.95 0.95 2.375 2.375 1.14 1.14 GND – 0.20 GND – 0.20 GND – 0.20 GND – 0.20 – 1.0 1.0 2.375 Max 1.05 1.05 2.625 2.625 2.625 2.625 2.625 2.625 VCCO  0.2 VCCO  0.2 10 2.5 2.5 2.625 Units V V V V V V V V V V mA V V V VIN IIN(4) VBATT(5) VFS(6) Notes: 1. 2. 3. 4. 5. 6. 7. Configuration data is retained even if VCCO drops to 0V. Includes VCCO of 1.2V, 1.5V, 1.8V, and 2.5V. The configuration supply voltage VCC_CONFIG is also known as VCCO_0. A total of 100 mA per bank should not be exceeded. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX. When not programming eFUSE, connect VFS to GND. All voltages are relative to ground. Table 11: DC Characteristics Over Recommended Operating Conditions(1)(2) Symbol VDRINT VDRI IREF IL CIN(3) Description Data retention VCCINT voltage (below which configuration data might be lost) Data retention VCCAUX voltage (below which configuration data might be lost) VREF leakage current per pin Input or output leakage current per pin (sample-tested) Die input capacitance at the pad Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V Min 0.75 2.0 – – – 20 8 5 1 3 – – – Typ – – – – – – – – – – – 1.0002 5 Max – – 10 10 8 80 40 30 20 80 150 – – Units V V µA µA pF µA µA µA µA µA nA n  IRPU Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V Pad pull-down (when selected) @ VIN = 2.5V Battery supply current Temperature diode ideality factor Series resistance IRPD IBATT n r Notes: 1. 2. 3. Typical values are specified at nominal voltage, 25°C. Maximum value specified for worst case process at 25°C. This measurement represents the die capacitance at the pad, not including the package. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 12 Virtex-6 CXT Family Data Sheet Quiescent Supply Current: Important Note Typical values for quiescent supply current are specified at nominal voltage, 85°C junction temperatures (Tj). Xilinx recommends analyzing static power consumption at Tj = 85°C because the majority of designs operate near the high end of the commercial temperature range. Quiescent supply current is specified by speed grade for Virtex-6 CXT devices. Use the XPOWER™ Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for conditions other than those specified in Table 12. Table 12: Typical Quiescent Supply Current Symbol Description Device XC6VCX75T ICCINTQ Quiescent VCCINT supply current XC6VCX130T XC6VCX195T XC6VCX240T XC6VCX75T ICCOQ Quiescent VCCO supply current XC6VCX130T XC6VCX195T XC6VCX240T XC6VCX75T ICCAUXQ Quiescent VCCAUX supply current XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. 2. 3. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj). Industrial (I) grade devices have the same typical values as commercial (C) grade devices at 85°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. Speed and Temperature Grade -2 (C & I) 927 1563 2059 2478 1 1 1 2 45 75 113 135 Units mA mA mA mA mA mA mA mA mA mA mA mA -1 (C & I) 927 1563 2059 2478 1 1 1 2 45 75 113 135 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 13 Virtex-6 CXT Family Data Sheet Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. Virtex-6 CXT devices require a power-on sequence of VCCINT, VCCAUX, and VCCO. If the requirement can not be met, then VCCAUX must always be powered prior to VCCO. VCCAUX and VCCO can be powered by the same supply, therefore, both VCCAUX and VCCO are permitted to ramp simultaneously. Similarly, for the power-down sequence, VCCO must be powered down prior to VCCAUX or if powered by the same supply, VCCAUX and VCCO power-down simultaneously. Table 13 shows the minimum current, in addition to ICCQ, that are required by Virtex-6 CXT devices for proper power-on and configuration. If the current minimums shown in Table 12 and Table 13 are met, the device powers on after all three supplies have passed through their power-on reset threshold voltages. The FPGA must be configured after VCCINT is applied. Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies. Table 13: Power-On Current for Virtex-6 CXT Devices Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. 2. Typical values are specified at nominal voltage, 25°C. Use the XPOWER™ Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents. ICCINTMIN Typ(1) See ICCINTQ in Table 12 See ICCINTQ in Table 12 See ICCINTQ in Table 12 See ICCINTQ in Table 12 ICCAUXMIN Typ(1) ICCAUXQ + 10 ICCAUXQ + 10 ICCAUXQ + 40 ICCAUXQ + 40 ICCOMIN Typ(1) ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank ICCOQ + 30 mA per bank Units mA mA mA mA Table 14: Power Supply Ramp Time Symbol VCCINT VCCO VCCAUX Description Internal supply voltage relative to GND Output drivers supply voltage relative to GND Auxiliary supply voltage relative to GND Ramp Time 0.20 to 50.0 0.20 to 50.0 0.20 to 50.0 Units ms ms ms DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 14 Virtex-6 CXT Family Data Sheet SelectIO™ DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 15: SelectIO DC Input and Output Levels I/O Standard LVCMOS25, LVDCI25 LVCMOS18, LVDCI18 LVCMOS15, LVDCI15 LVCMOS12 HSTL I_12 HSTL I(2) HSTL II(2) HSTL III(2) DIFF HSTL I(2) DIFF HSTL II(2) SSTL2 I SSTL2 II DIFF SSTL2 I DIFF SSTL2 II SSTL18 I SSTL18 II DIFF SSTL18 I DIFF SSTL18 II SSTL15 Notes: 1. 2. 3. 4. 5. 6. Tested according to relevant specifications. Applies to both 1.5V and 1.8V HSTL. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. Supported drive strengths of 2, 4, 6, or 8 mA. For detailed interface specific DC voltage levels, see the Virtex-6 FPGA SelectIO Resources User Guide. VIL V, Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 VIH V, Max 0.7 VOL V, Max VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VCCO + 0.3 VOH V, Min VCCO – 0.4 VCCO – 0.45 75% VCCO 75% VCCO 75% VCCO VCCO – 0.4 VCCO – 0.4 VCCO – 0.4 – – VTT + 0.61 VTT + 0.81 – – VTT + 0.47 VTT + 0.60 – – VTT + 0.175 IOL mA Note(3) Note(4) Note(4) Note(5) 6.3 8 16 24 – – 8.1 16.2 – – 6.7 13.4 – – 14.3 IOH mA Note(3) Note(4) Note(4) Note(5) 6.3 –8 –16 –8 – – –8.1 –16.2 – – –6.7 –13.4 – – 14.3 V, Min 1.7 65% VCCO 65% VCCO 65% VCCO VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 V, Max 0.4 0.45 25% VCCO 25% VCCO 25% VCCO 0.4 0.4 0.4 – – VTT – 0.61 VTT – 0.81 – – VTT – 0.47 VTT – 0.60 – – VTT – 0.175 35% VCCO 35% VCCO 35% VCCO VREF – 0.1 VREF – 0.1 VREF – 0.1 VREF – 0.1 50% VCCO – 0.1 50% VCCO + 0.1 50% VCCO – 0.1 50% VCCO + 0.1 VREF – 0.15 VREF – 0.15 50% VCCO – 0.15 50% VCCO – 0.15 VREF – 0.125 VREF – 0.125 50% VCCO – 0.125 50% VCCO – 0.125 VREF – 0.1 VREF + 0.15 VREF + 0.15 50% VCCO + 0.15 50% VCCO + 0.15 VREF + 0.125 VREF + 0.125 50% VCCO + 0.125 50% VCCO + 0.125 VREF + 0.1 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 15 Virtex-6 CXT Family Data Sheet HT DC Specifications (HT_25) Table 16: HT DC Specifications Symbol VCCO VOD  VOD VOCM  VOCM VID  VID VICM  VICM DC Parameter Supply Voltage Differential Output Voltage Change in VOD Magnitude Output Common Mode Voltage Change in VOCM Magnitude Input Differential Voltage Change in VID Magnitude Input Common Mode Voltage Change in VICM Magnitude Conditions RT = 100  across Q and Q signals RT = 100  across Q and Q signals Min 2.38 480 –15 480 –15 200 –15 440 –15 Typ 2.5 600 – 600 – 600 – 600 – Max 2.63 885 15 885 15 1000 15 780 15 Units V mV mV mV mV mV mV mV mV LVDS DC Specifications (LVDS_25) Table 17: LVDS DC Specifications Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q – Q), Q = High (Q – Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q – Q), Q = High (Q – Q), Q = High Input Common-Mode Voltage Conditions RT = 100  across Q and Q signals RT = 100  across Q and Q signals RT = 100  across Q and Q signals RT = 100  across Q and Q signals Min 2.38 – 0.825 247 1.075 100 0.3 Typ 2.5 – – 350 1.250 350 1.2 Max 2.63 1.675 – 600 1.425 600 2.2 Units V V V mV V mV V Extended LVDS DC Specifications (LVDSEXT_25) Table 18: Extended LVDS DC Specifications Symbol VCCO VOH VOL VODIFF VOCM VIDIFF VICM DC Parameter Supply Voltage Output High Voltage for Q and Q Output Low Voltage for Q and Q Differential Output Voltage (Q – Q), Q = High (Q – Q), Q = High Output Common-Mode Voltage Differential Input Voltage (Q – Q), Q = High (Q – Q), Q = High Input Common-Mode Voltage Conditions RT = 100  across Q and Q signals RT = 100  across Q and Q signals RT = 100  across Q and Q signals RT = 100  across Q and Q signals Common-mode input voltage = 1.25V Differential input voltage = ±350 mV Min 2.38 – 0.715 350 1.075 100 0.3 Typ 2.5 – – – 1.250 – 1.2 Max 2.63 1.785 – 840 1.425 1000 2.2 Units V V V mV V mV V DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 16 Virtex-6 CXT Family Data Sheet LVPECL DC Specifications (LVPECL_25) These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. Table 19 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see the Virtex-6 FPGA SelectIO Resources User Guide. Table 19: LVPECL DC Specifications Symbol VOH VOL VICM VIDIFF Notes: 1. 2. Recommended input maximum voltage not to exceed VCCAUX + 0.2V. Recommended input minimum voltage not to go below –0.5V. DC Parameter Output High Voltage Output Low Voltage Input Common-Mode Voltage Differential Input Voltage(1)(2) Min VCC – 1.025 VCC – 1.81 0.6 0.100 Typ 1.545 0.795 – – Max VCC – 0.88 VCC – 1.62 2.2 1.5 Units V V V V eFUSE Read Endurance Table 20 lists the maximum number of read cycle operations expected. For more information, see the Virtex-6 FPGA Configuration User Guide. Table 20: eFUSE Read Endurance Symbol DNA_CYCLES AES_CYCLES Description Number of DNA_PORT READ operations or JTAG ISC_DNA read command operations. Unaffected by SHIFT operations. Number of JTAG FUSE_KEY or FUSE_CNTL read command operations. Unaffected by SHIFT operations. Speed Grade -3 -2 -1 -1L Units Read Cycles Read Cycles 30,000,000 30,000,000 GTX Transceiver Specifications GTX Transceiver DC Characteristics Table 21: Absolute Maximum Ratings for GTX Transceivers(1) Symbol MGTAVCC MGTAVTT MGTAVTTRCAL VIN VMGTREFCLK Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Description Analog supply voltage for the GTX transmitter and receiver circuits relative to GND Analog supply voltage for the GTX transmitter and receiver termination circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTX transceiver column Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage Reference clock absolute input voltage Min –0.5 –0.5 –0.5 –0.5 –0.5 Max 1.1 1.32 1.32 1.32 1.32 Units V V V V V DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 17 Virtex-6 CXT Family Data Sheet Table 22: Recommended Operating Conditions for GTX Transceivers(1)(2) Symbol MGTAVCC MGTAVTT MGTAVTTRCAL Notes: 1. 2. Each voltage listed requires the filter circuit described in Virtex-6 FPGA GTX Transceivers User Guide. Voltages are specified for the temperature range of Tj = –40°C to +100°C. Description Analog supply voltage for the GTX transmitter and receiver circuits relative to GND Analog supply voltage for the GTX transmitter and receiver termination circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTX transceiver column Min 0.95 1.14 1.14 Typ 1.0 1.2 1.2 Max 1.06 1.26 1.26 Units V V V Table 23: GTX Transceiver Supply Current (per Lane) (1)(2) Symbol IMGTAVTT IMGTAVCC MGTRREF Notes: 1. 2. Typical values are specified at nominal voltage, 25°C, with a 3.125 Gb/s line rate. Values for currents other than the values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. Description MGTAVTT supply current for one GTX transceiver MGTAVCC supply current for one GTX transceiver Precision reference resistor for internal calibration termination Typ 55.9 56.1 Max Note 2 Units mA mA  100.0 ± 1% tolerance Table 24: GTX Transceiver Quiescent Supply Current (per Lane)(1)(2)(3) Symbol IMGTAVTTQ IMGTAVCCQ Notes: 1. 2. 3. 4. Device powered and unconfigured. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. GTX transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTX transceivers. Typical values are specified at nominal voltage, 25°C. Description Quiescent MGTAVTT supply current for one GTX transceiver Quiescent MGTAVCC supply current for one GTX transceiver Typ(4) 0.9 3.5 Max Note 2 Units mA mA DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 18 Virtex-6 CXT Family Data Sheet GTX Transceiver DC Input and Output Levels Table 25 summarizes the DC output specifications of the GTX transceivers in Virtex-6 CXT FPGAs. Consult the Virtex-6 FPGA GTX Transceivers User Guide for further details. Table 25: GTX Transceiver DC Specifications Symbol DVPPIN VIN VCMIN DVPPOUT VCMOUTDC RIN ROUT TOSKEW CEXT Notes: 1. 2. The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-6 FPGA GTX Transceivers User Guide and can result in values lower than reported in this table. Other values can be used as appropriate to conform to specific protocols and standards. DC Parameter Differential peak-to-peak input voltage Absolute input voltage Common mode input voltage Differential peak-to-peak output voltage (1) Conditions External AC coupled DC coupled MGTAVTT = 1.2V DC coupled MGTAVTT = 1.2V Transmitter output swing is set to maximum setting Min 125 –400 – – Typ – – 2/3 MGTAVTT – Max 2000 MGTAVTT – 1000 Units mV mV mV mV mV   ps nF DC common mode output voltage Equation based Differential input resistance Differential output resistance Transmitter output pair (TXP and TXN) intra-pair skew Recommended external AC coupling capacitor(2) 80 80 – – MGTAVTT – DVPPOUT/4 100 100 2 100 130 120 8 – X-Ref Target - Figure 11 +V P Single-Ended Voltage ds153_11_041410 N 0 Figure 11: Single-Ended Peak-to-Peak Voltage X-Ref Target - Figure 12 +V 0 Differential Voltage –V P–N ds153_12_041410 Figure 12: Differential Peak-to-Peak Voltage DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 19 Virtex-6 CXT Family Data Sheet Table 26 summarizes the DC specifications of the clock input of the GTX transceiver. Consult theVirtex-6 FPGA GTX Transceivers User Guide for further details. Table 26: GTX Transceiver Clock DC Input Level Specification Symbol VIDIFF RIN CEXT DC Parameter Differential peak-to-peak input voltage Differential input resistance Required external AC coupling capacitor Conditions Min 210 90 – Typ 800 100 100 Max 2000 130 – Units mV  nF GTX Transceiver Switching Characteristics Consult Virtex-6 FPGA GTX Transceivers User Guide for further information. Table 27: GTX Transceiver Performance Symbol FGTXMAX FGPLLMAX FGPLLMIN Description Maximum GTX transceiver data rate Maximum PLL frequency Minimum PLL frequency Speed Grade -2 3.75 2.5 1.2 Units Gb/s GHz GHz -1 3.75 2.5 1.2 Table 28: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Symbol FGTXDRPCLK Description GTXDRPCLK maximum frequency Speed Grade -2 100 Units -1 MHz 100 Table 29: GTX Transceiver Reference Clock Switching Characteristics Symbol FGCLK TRCLK TFCLK TDCREF TLOCK TPHASE X-Ref Target - Figure 13 Description Reference clock frequency range Reference clock rise time Reference clock fall time Reference clock duty cycle Clock recovery frequency acquisition time Clock recovery phase acquisition time Conditions All Speed Grades Min 67.5 Typ – 200 200 50 – – Max 375 – – 55 1 200 Units MHz ps ps % ms µs 20% – 80% 80% – 20% Transceiver PLL only Initial PLL lock Lock to data after PLL has locked to the reference clock – – 45 – – TRCLK 80% 20% TFCLK d s 153_13_041410 Figure 13: Reference Clock Timing Parameters DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 20 Virtex-6 CXT Family Data Sheet Table 30: GTX Transceiver User Clock Switching Characteristics(1) Symbol FTXOUT FRXREC TRX TRX2 TTX TTX2 Description TXOUTCLK maximum frequency RXRECCLK maximum frequency RXUSRCLK maximum frequency Conditions Internal 20-bit data path Internal 16-bit data path Internal 20-bit data path Internal 16-bit data path 1 byte interface Speed Grade -2 187.5 234.38 187.5 234.38 234.38 376 234.38 117.19 234.38 376 234.38 117.19 -1 187.5 234.38 187.5 234.38 234.38 312.5 234.38 117.19 234.38 312.5 234.38 117.19 Units MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz RXUSRCLK2 maximum frequency TXUSRCLK maximum frequency 2 byte interface 4 byte interface 1 byte interface TXUSRCLK2 maximum frequency 2 byte interface 4 byte interface Notes: 1. Clocking must be implemented as described in Virtex-6 FPGA GTX Transceivers User Guide. Table 31: GTX Transceiver Transmitter Switching Characteristics Symbol FGTXTX TRTX TFTX TLLSKEW VTXOOBVDPP TTXOOBTRANSITION TJ3.75 DJ3.75 TJ3.125 DJ3.125 TJ3.125L DJ3.125L TJ2.5 DJ2.5 TJ1.25 DJ1.25 TJ600 DJ600 TX Rise time TX Fall time TX lane-to-lane skew(1) Description Serial data rate range Condition Min 0.480 – – – – – Typ – 120 120 – – – – – – – – – – – – – – – Max FGTXMAX – – 350 15 75 0.34 0.16 0.2 0.1 0.35 0.16 0.20 0.08 0.15 0.06 0.1 0.03 Units Gb/s ps ps ps mV ns UI UI UI UI UI UI UI UI UI UI UI UI 20%–80% 80%–20% Electrical idle amplitude Electrical idle transition time Total Total Total Total Total Total Jitter(2)(3) Jitter(2)(3) 3.125 Gb/s 3.125 2.5 Gb/s(4) Jitter(2)(3) Jitter(2)(3) Jitter(2)(3) Gb/s(5) Gb/s(6) Jitter(2)(3) Jitter(2)(3) Jitter(2)(3) 600 Mb/s Jitter(2)(3) 3.75 Gb/s Deterministic – – – – – – – – – – – – Deterministic Jitter(2)(3) Deterministic Deterministic Jitter(2)(3) 1.25 Deterministic Deterministic Jitter(2)(3) DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 21 Virtex-6 CXT Family Data Sheet Table 31: GTX Transceiver Transmitter Switching Characteristics (Cont’d) Symbol TJ480 DJ480 Notes: 1. 2. 3. 4. 5. 6. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX transceiver sites. Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. All jitter values are based on a bit-error ratio of 1e-12. PLL frequency at 1.5625 GHz and OUTDIV = 1. PLL frequency at 2.5 GHz and OUTDIV = 2. PLL frequency at 2.5 GHz and OUTDIV = 4. Description Total Jitter(2)(3) Jitter(2)(3) Deterministic Condition 480 Mb/s Min – – Typ – – Max 0.1 0.03 Units UI UI Table 32: GTX Transceiver Receiver Switching Characteristics Symbol FGTXRX TRXELECIDLE RXOOBVDPP RXSST RXRL RXPPMTOL Serial data rate Description RX oversampler not enabled RX oversampler enabled Min 0.600 0.480 – 60 –5000 – –200 –2000 0.44 0.45 0.45 0.5 0.5 0.4 0.4 0.70 0.1 Typ – – 75 – – – – – – – – – – – – – – Max FGTXMAX 0.600 – 150 0 512 200 2000 – – – – – – – – – Units Gb/s Gb/s ns mV ppm UI ppm ppm UI UI UI UI UI UI UI UI UI TIme for RXELECIDLE to respond to loss or restoration of data OOB detect threshold peak-to-peak Receiver spread-spectrum tracking(1) Run length (CID) Data/REFCLK PPM offset tolerance Modulated @ 33 KHz Internal AC capacitor bypassed CDR 2nd-order loop disabled CDR 2nd-order loop enabled SJ Jitter Tolerance(2) Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Sinusoidal Jitter(3) Jitter(3) 3.75 Gb/s 3.125 Gb/s 3.125 2.5 Gb/s(4) Gb/s(5) JT_SJ3.75 JT_SJ3.125 JT_SJ3.125L JT_SJ2.5 JT_SJ1.25 JT_SJ675 JT_SJ480 Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Jitter(3) 1.25 Gb/s(6) 675 Mb/s 480 Mb/s 3.125 Gb/s 3.125 Gb/s SJ Jitter Tolerance with Stressed JT_TJSE3.125 JT_SJSE3.125 Notes: 1. 2. 3. 4. 5. 6. 7. Eye(2) Total Jitter with Stressed Eye(7) Sinusoidal Jitter with Stressed Eye(7) Using PLL_RXDIVSEL_OUT = 1, 2, and 4. All jitter values are based on a bit-error ratio of 1e–12. The frequency of the injected sinusoidal jitter is 80 MHz. PLL frequency at 1.5625 GHz and OUTDIV = 1. PLL frequency at 2.5 GHz and OUTDIV = 2. PLL frequency at 2.5 GHz and OUTDIV = 4. Composite jitter with RX equalizer enabled. DFE disabled. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 22 Virtex-6 CXT Family Data Sheet Ethernet MAC Switching Characteristics Consult Virtex-6 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information. Table 33: Maximum Ethernet MAC Performance Symbol Description Conditions 10 Mb/s – 8-bit width FTEMACCLIENT Client interface maximum frequency 100 Mb/s – 8-bit width 1000 Mb/s – 8-bit width 1000 Mb/s – 16-bit width 10 Mb/s – 4-bit width FTEMACPHY Physical interface maximum frequency 100 Mb/s – 4-bit width 1000 Mb/s – 8-bit width Notes: 1. 2. When not using clock enable, the FMAX is lowered to 1.25 MHz. When not using clock enable, the FMAX is lowered to 12.5 MHz. Speed Grade -2 2.5(1) 25(2) 125 62.5 2.5 25 125 Units MHz MHz MHz MHz MHz MHz MHz -1 2.5(1) 25(2) 125 62.5 2.5 25 125 Integrated Interface Block for PCI Express Designs Switching Characteristics More information and documentation on solutions for PCI Express designs can be found at: http://www.xilinx.com/technology/protocols/pciexpress.htm Table 34: Maximum Performance for PCI Express Designs Symbol FPIPECLK FUSERCLK FDRPCLK Pipe clock maximum frequency User clock maximum frequency DRP clock maximum frequency Description Speed Grade -2 125 250 250 Units MHz MHz MHz -1 125 250 250 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 23 Virtex-6 CXT Family Data Sheet Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-6 CXT devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the Switching Characteristics, page 25. Table 35: Interface Performances Description Networking Applications SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 10) SDR LVDS receiver DDR LVDS receiver (SFI-4.1)(1) (SFI-4.2)(1) Interfaces(2)(3) 666 Mb/s 800 Mb/s 250 MHz 666 Mb/s 666 Mb/s 250 MHz 650 Mb/s 1.25 Gb/s 650 Mb/s 1.0 Gb/s 625 Mb/s 1.0 Gb/s 625 Mb/s 0.9 Gb/s Speed Grade -2 -1 Maximum Physical Interface (PHY) Rate for Memory DDR2 DDR3 QDR II + SRAM Notes: 1. 2. 3. LVDS receivers are typically bounded with certain applications where specific DPA algorithms dominate deterministic performance. Based on Xilinx memory characterization platforms designed according to the guidelines in the Virtex-6 FPGA Memory Interface Solutions User Guide. Consult the Virtex-6 FPGA Memory Interface Solutions Data Sheet for performance and feature information on memory interface cores (controller plus PHY). DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 24 Virtex-6 CXT Family Data Sheet Switching Characteristics All values represented in this data sheet are based on the speed specification (version 1.08). Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. Preliminary These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 36 correlates the current status of each Virtex-6 CXT device on a per speed grade basis. Table 36: Virtex-6 CXT Device/Speed Grade Designations Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Speed Grade Designations Advance Preliminary Production -2, -1 -2, -1 -2, -1 -2, -1 Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-6 CXT devices. Production Silicon and ISE Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 37 lists the production released Virtex-6 family member, speed grade, and the minimum corresponding supported speed specification version and ISE software revisions. The ISE® software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 37: Virtex-6 CXT Device/Production Software and Speed Specification Release Device XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status. Speed Grade Designations -2 -1 ISE 12.2 (with speed file patch) v1.06 ISE 12.1 v1.04 ISE 12.2 (with speed file patch) v1.06 ISE 12.1 v1.04 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 25 Virtex-6 CXT Family Data Sheet IOB Pad Input/Output/3-State Switching Characteristics Table 38 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. Table 38: IOB Switching Characteristics TIOPI I/O Standard Speed Grade -2 LVDS_25 LVDSEXT_25 HT_25 BLVDS_25 RSDS_25 (point to point) HSTL_I HSTL_II HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL2_I SSTL2_II SSTL15 LVCMOS25, Slow, 2 mA LVCMOS25, Slow, 4 mA LVCMOS25, Slow, 6 mA LVCMOS25, Slow, 8 mA LVCMOS25, Slow, 12 mA LVCMOS25, Slow, 16 mA LVCMOS25, Slow, 24 mA LVCMOS25, Fast, 2 mA LVCMOS25, Fast, 4 mA LVCMOS25, Fast, 6 mA LVCMOS25, Fast, 8 mA LVCMOS25, Fast, 12 mA LVCMOS25, Fast, 16 mA LVCMOS25, Fast, 24 mA 1.09 1.09 1.09 1.09 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 39 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOOP Speed Grade -2 1.68 1.84 1.78 1.67 1.68 1.73 1.74 1.71 1.75 1.81 1.71 1.77 1.72 1.71 6.01 3.79 3.08 2.72 2.17 2.29 2.02 6.04 3.82 2.99 2.65 2.08 2.13 1.99 TIOTP Speed Grade -2 1.68 1.84 1.78 1.67 1.68 1.73 1.74 1.71 1.75 1.81 1.71 1.77 1.72 1.71 6.01 3.79 3.08 2.72 2.17 2.29 2.02 6.04 3.82 2.99 2.65 2.08 2.13 1.99 Units -1 1.09 1.09 1.09 1.09 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 0.66 -1 1.68 1.84 1.78 1.67 1.68 1.73 1.74 1.71 1.75 1.81 1.71 1.77 1.72 1.71 6.01 3.79 3.08 2.72 2.17 2.29 2.02 6.04 3.82 2.99 2.65 2.08 2.13 1.99 -1 1.68 1.84 1.78 1.67 1.68 1.73 1.74 1.71 1.75 1.81 1.71 1.77 1.72 1.71 6.01 3.79 3.08 2.72 2.17 2.29 2.02 6.04 3.82 2.99 2.65 2.08 2.13 1.99 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 26 Virtex-6 CXT Family Data Sheet Table 38: IOB Switching Characteristics (Cont’d) TIOPI I/O Standard Speed Grade -2 LVCMOS18, Slow, 2 mA LVCMOS18, Slow, 4 mA LVCMOS18, Slow, 6 mA LVCMOS18, Slow, 8 mA LVCMOS18, Slow, 12 mA LVCMOS18, Slow, 16 mA LVCMOS18, Fast, 2 mA LVCMOS18, Fast, 4 mA LVCMOS18, Fast, 6 mA LVCMOS18, Fast, 8 mA LVCMOS18, Fast, 12 mA LVCMOS18, Fast, 16 mA LVCMOS15, Slow, 2 mA LVCMOS15, Slow, 4 mA LVCMOS15, Slow, 6 mA LVCMOS15, Slow, 8 mA LVCMOS15, Slow, 12 mA LVCMOS15, Slow, 16 mA LVCMOS15, Fast, 2 mA LVCMOS15, Fast, 4 mA LVCMOS15, Fast, 6 mA LVCMOS15, Fast, 8 mA LVCMOS15, Fast, 12 mA LVCMOS15, Fast, 16 mA LVCMOS12, Slow, 2 mA LVCMOS12, Slow, 4 mA LVCMOS12, Slow, 6 mA LVCMOS12, Slow, 8 mA LVCMOS12, Fast, 2 mA LVCMOS12, Fast, 4 mA LVCMOS12, Fast, 6 mA LVCMOS12, Fast, 8 mA LVDCI_25 LVDCI_18 LVDCI_15 LVDCI_DV2_25 LVDCI_DV2_18 LVDCI_DV2_15 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.93 0.93 0.93 0.93 0.93 0.93 0.93 0.93 0.66 0.71 0.85 0.66 0.71 0.85 TIOOP Speed Grade -2 4.87 3.21 2.64 2.27 2.15 2.11 4.57 2.97 2.46 2.13 1.97 1.91 4.29 3.10 2.68 2.23 2.13 2.04 4.28 2.78 2.42 2.11 1.97 1.96 3.75 2.93 2.41 2.25 3.39 2.51 2.11 2.02 2.26 2.47 2.24 2.01 2.00 1.91 TIOTP Speed Grade -2 4.87 3.21 2.64 2.27 2.15 2.11 4.57 2.97 2.46 2.13 1.97 1.91 4.29 3.10 2.68 2.23 2.13 2.04 4.28 2.78 2.42 2.11 1.97 1.96 3.75 2.93 2.41 2.25 3.39 2.51 2.11 2.02 2.26 2.47 2.24 2.01 2.00 1.91 Units -1 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.71 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.85 0.93 0.93 0.93 0.93 0.93 0.93 0.93 0.93 0.66 0.71 0.85 0.66 0.71 0.85 -1 4.87 3.21 2.64 2.27 2.15 2.11 4.57 2.97 2.46 2.13 1.97 1.91 4.29 3.10 2.68 2.23 2.13 2.04 4.28 2.78 2.42 2.11 1.97 1.96 3.75 2.93 2.41 2.25 3.39 2.51 2.11 2.02 2.26 2.47 2.24 2.01 2.00 1.91 -1 4.87 3.21 2.64 2.27 2.15 2.11 4.57 2.97 2.46 2.13 1.97 1.91 4.29 3.10 2.68 2.23 2.13 2.04 4.28 2.78 2.42 2.11 1.97 1.96 3.75 2.93 2.41 2.25 3.39 2.51 2.11 2.02 2.26 2.47 2.24 2.01 2.00 1.91 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 27 Virtex-6 CXT Family Data Sheet Table 38: IOB Switching Characteristics (Cont’d) TIOPI I/O Standard Speed Grade -2 LVPECL_25 HSTL_I_12 HSTL_I_DCI HSTL_II_DCI HSTL_II_T_DCI HSTL_III_DCI HSTL_I_DCI_18 HSTL_II_DCI_18 HSTL_II _T_DCI_18 HSTL_III_DCI_18 DIFF_HSTL_I_18 DIFF_HSTL_I_DCI_18 DIFF_HSTL_I DIFF_HSTL_I_DCI DIFF_HSTL_II_18 DIFF_HSTL_II_DCI_18 DIFF_HSTL_II _T_DCI_18 DIFF_HSTL_II DIFF_HSTL_II_DCI SSTL2_I_DCI SSTL2_II_DCI SSTL2_II_T_DCI SSTL18_I SSTL18_II SSTL18_I_DCI SSTL18_II_DCI SSTL18_II_T_DCI SSTL15_T_DCI SSTL15_DCI DIFF_SSTL2_I DIFF_SSTL2_I_DCI DIFF_SSTL2_II DIFF_SSTL2_II_DCI DIFF_SSTL2_II_T_DCI DIFF_SSTL18_I DIFF_SSTL18_I_DCI DIFF_SSTL18_II DIFF_SSTL18_II_DCI 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 TIOOP Speed Grade -2 1.65 1.78 1.66 1.68 1.66 1.62 1.68 1.62 1.68 1.69 1.75 1.68 1.73 1.66 1.81 1.62 1.68 1.74 1.68 1.70 1.67 1.70 1.75 1.67 1.67 1.63 1.67 1.68 1.68 1.77 1.70 1.72 1.67 1.70 1.75 1.67 1.67 1.63 TIOTP Speed Grade -2 1.65 1.78 1.66 1.68 1.66 1.62 1.68 1.62 1.68 1.69 1.75 1.68 1.73 1.66 1.81 1.62 1.68 1.74 1.68 1.70 1.67 1.70 1.75 1.67 1.67 1.63 1.67 1.68 1.68 1.77 1.70 1.72 1.67 1.70 1.75 1.67 1.67 1.63 Units -1 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 1.09 -1 1.65 1.78 1.66 1.68 1.66 1.62 1.68 1.62 1.68 1.69 1.75 1.68 1.73 1.66 1.81 1.62 1.68 1.74 1.68 1.70 1.67 1.70 1.75 1.67 1.67 1.63 1.67 1.68 1.68 1.77 1.70 1.72 1.67 1.70 1.75 1.67 1.67 1.63 -1 1.65 1.78 1.66 1.68 1.66 1.62 1.68 1.62 1.68 1.69 1.75 1.68 1.73 1.66 1.81 1.62 1.68 1.74 1.68 1.70 1.67 1.70 1.75 1.67 1.67 1.63 1.67 1.68 1.68 1.77 1.70 1.72 1.67 1.70 1.75 1.67 1.67 1.63 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 28 Virtex-6 CXT Family Data Sheet Table 38: IOB Switching Characteristics (Cont’d) TIOPI I/O Standard Speed Grade -2 DIFF_SSTL18_II_T_DCI DIFF_SSTL15 DIFF_SSTL15_DCI DIFF_SSTL15_T_DCI 1.09 1.06 1.06 1.06 TIOOP Speed Grade -2 1.67 1.71 1.68 1.68 TIOTP Speed Grade -2 1.67 1.71 1.68 1.68 Units -1 1.09 1.06 1.06 1.06 -1 1.67 1.71 1.68 1.68 -1 1.67 1.71 1.68 1.68 ns ns ns ns Table 39: IOB 3-state ON Output Switching Characteristics (TIOTPHZ) Symbol TIOTPHZ Description -2 T input to Pad high-impedance Speed Grade -1 0.99 Units ns 0.99 I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 40 shows the test setup parameters used for measuring input delay. Table 40: Input Delay Measurement Methodology Description LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V HSTL (High-Speed Transceiver Logic), Class I & II HSTL, Class III HSTL, Class I & II, 1.8V HSTL, Class III 1.8V SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL, Class I & II, 2.5V SSTL, Class I & II, 1.8V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V HT (HyperTransport), 2.5V Notes: 1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards. Input waveform switches between VLand VH. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. Input voltage level from which measurement starts. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 14. The value given is the differential output voltage. I/O Standard Attribute LVCMOS25 LVCMOS18 LVCMOS15 HSTL_I, HSTL_II HSTL_III HSTL_I_18, HSTL_II_18 HSTL_III_18 SSTL3_I, SSTL3_II SSTL2_I, SSTL2_II SSTL18_I, SSTL18_II LVDS_25 LVDSEXT_25 LDT_25 VL (1)(2) 0 0 0 VREF – 0.5 VREF – 0.5 VREF – 0.5 VREF – 0.5 VREF – 1.00 VREF – 0.75 VREF – 0.5 1.2 – 0.125 1.2 – 0.125 0.6 – 0.125 VH (1)(2) 2.5 1.8 1.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 1.00 VREF + 0.75 VREF + 0.5 1.2 + 0.125 1.2 + 0.125 0.6 + 0.125 VMEAS (1,4,5) VREF (1,3,5) 1.25 0.9 0.75 VREF VREF VREF VREF VREF VREF VREF 0(6) 0(6) 0(6) – – – 0.75 0.90 0.90 1.08 1.5 1.25 0.90 – – – 2. 3. 4. 5. 6. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 29 Virtex-6 CXT Family Data Sheet Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 14 and Figure 15. X-Ref Target - Figure 14 X-Ref Target - Figure 15 FPGA Output + CREF RREF VMEAS – ds152_07_042109 VREF Figure 15: Differential Test Setup Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 41. 2. Record the time to VMEAS . ds152_06_042109 FPGA Output RREF VMEAS (voltage level when taking delay measurement) CREF (probe capacitance) Figure 14: Single Ended Test Setup 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS . 5. Compare the results of steps 2 and 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. Table 41: Output Delay Measurement Methodology Description LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V HSTL (High-Speed Transceiver Logic), Class I HSTL, Class II HSTL, Class III HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended Mode), 2.5V BLVDS (Bus LVDS), 2.5V I/O Standard Attribute LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 HSTL_I HSTL_II HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I SSTL2_II LVDS_25 LVDS_25 BLVDS_25 RREF ( ) 1M 1M 1M 1M 50 25 50 50 25 50 50 25 50 25 100 100 100 CREF(1) ( pF) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMEAS (V) 1.25 0.9 0.75 0.75 VREF VREF 0.9 VREF VREF 1.1 VREF VREF VREF VREF 0(2) 0(2) 0(2) VREF (V) 0 0 0 0 0.75 0.75 1.5 0.9 0.9 1.8 0.9 0.9 1.25 1.25 1.2 1.2 0 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 30 Virtex-6 CXT Family Data Sheet Table 41: Output Delay Measurement Methodology (Cont’d) Description HT (HyperTransport), 2.5V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVDCI/HSLVDCI, 2.5V LVDCI/HSLVDCI, 1.8V LVDCI/HSLVDCI, 1.5V LDT_25 LVPECL_25 LVDCI_25, HSLVDCI_25 LVDCI_18, HSLVDCI_18 LVDCI_15, HSLVDCI_15 I/O Standard Attribute RREF ( ) 100 100 1M 1M 1M 50 50 50 50 50 50 CREF(1) ( pF) 0 0 0 0 0 0 0 0 0 0 0 VMEAS (V) 0(2) 0(2) 1.25 0.9 0.75 VREF 0.9 VREF 1.1 VREF VREF VREF (V) 0.6 0 0 0 0 0.75 1.5 0.9 1.8 0.9 1.25 HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI HSTL, Class III, with DCI HSTL, Class I & II, 1.8V, with DCI HSTL, Class III, 1.8V, with DCI HSTL_III_DCI HSTL_I_DCI_18, HSTL_II_DCI_18 HSTL_III_DCI_18 SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI SSTL, Class I & II, 2.5V, with DCI Notes: 1. 2. CREF is the capacitance of the probe, nominally 0 pF. The value given is the differential output voltage. SSTL2_I_DCI, SSTL2_II_DCI Input/Output Logic Switching Characteristics Table 42: ILOGIC Switching Characteristics Symbol Setup/Hold TICE1CK/TICKCE1 TISRCK/TICKSR TIDOCK/TIOCKD TIDOCKD/TIOCKDD Combinatorial TIDI TIDID Sequential Delays TIDLO TIDLOD TICKQ TRQ_ILOGIC TGSRQ_ILOGIC Set/Reset TRPW_ILOGIC Minimum Pulse Width, SR inputs 1.20 1.20 ns, Min D pin to Q1 pin using flip-flop as a latch without Delay DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY) CLK to Q outputs SR pin to OQ/TQ out Global Set/Reset to Q outputs 0.64 0.68 0.71 1.15 10.51 0.64 0.68 0.71 1.15 10.51 ns ns ns ns ns D pin to O pin propagation delay, no Delay DDLY pin to O pin propagation delay (using IODELAY) 0.20 0.25 0.20 0.25 ns ns CE1 pin Setup/Hold with respect to CLK SR pin Setup/Hold with respect to CLK D pin Setup/Hold with respect to CLK without Delay DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.27/0.04 0.96/–0.10 0.10/0.54 0.14/0.42 0.27/0.04 0.96/–0.10 0.10/0.54 0.14/0.40 ns ns ns ns Description Speed Grade -2 -1 Units DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 31 Virtex-6 CXT Family Data Sheet Table 43: OLOGIC Switching Characteristics Symbol Setup/Hold TODCK/TOCKD TOOCECK/TOCKOCE TOSRCK/TOCKSR TOTCK/TOCKT TOTCECK/TOCKTCE Combinatorial TDOQ Sequential Delays TOCKQ TRQ TGSRQ Set/Reset TRPW Minimum Pulse Width, SR inputs 1.20 1.20 ns, Min CLK to OQ/TQ out SR pin to OQ/TQ out Global Set/Reset to Q outputs 0.71 1.05 10.51 0.71 1.05 10.51 ns ns ns D1 to OQ out or T1 to TQ out 1.01 1.01 ns D1/D2 pins Setup/Hold with respect to CLK OCE pin Setup/Hold with respect to CLK SR pin Setup/Hold with respect to CLK T1/T2 pins Setup/Hold with respect to CLK TCE pin Setup/Hold with respect to CLK 0.54/–0.11 0.22/–0.05 0.71/–0.29 0.56/–0.10 0.21/–0.05 0.54/–0.11 0.22/–0.05 0.71/–0.29 0.56/–0.10 0.21/–0.05 ns ns ns ns ns Description Speed Grade -2 -1 Units Input Serializer/Deserializer Switching Characteristics Table 44: ISERDES Switching Characteristics Symbol Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP TISCCK_CE / TISCKC_CE TISCCK_CE2 / (2) Description Speed Grade -2 -1 Units BITSLIP pin Setup/Hold with respect to CLKDIV CE pin Setup/Hold with respect to CLK (for CE1) CE pin Setup/Hold with respect to CLKDIV (for CE2) 0.09/0.17 0.27/0.04 –0.06/0.31 0.09/0.17 0.27/0.04 –0.06/0.31 ns ns ns TISCKC_CE2(2) Setup/Hold for Data Lines TISDCK_D /TISCKD_D TISDCK_DDLY /TISCKD_DDLY TISDCK_D_DDR /TISCKD_D_DDR TISDCK_DDLY_DDR TISCKD_DDLY_DDR Sequential Delays TISCKO_Q Propagation Delays TISDO_DO Notes: 1. 2. Recorded at 0 tap value. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in a TRACE report. D pin Setup/Hold with respect to CLK DDLY pin Setup/Hold with respect to CLK (using IODELAY)(1) D pin Setup/Hold with respect to CLK at DDR mode D pin Setup/Hold with respect to CLK at DDR mode (using IODELAY)(1) 0.09/0.11 0.14/0.07 0.09/0.11 0.14/0.07 0.09/0.11 0.14/0.07 0.09/0.11 0.14/0.07 ns ns ns ns CLKDIV to out at Q pin 0.75 0.75 ns D input to DO output pin 0.25 0.25 ns DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 32 Virtex-6 CXT Family Data Sheet Output Serializer/Deserializer Switching Characteristics Table 45: OSERDES Switching Characteristics Symbol Setup/Hold TOSDCK_D/TOSCKD_D TOSDCK_T/TOSCKD_T(1) TOSDCK_T2/TOSCKD_T2(1) TOSCCK_OCE/TOSCKC_OCE TOSCCK_S TOSCCK_TCE/TOSCKC_TCE Sequential Delays TOSCKO_OQ TOSCKO_TQ Combinatorial TOSDO_TTQ Notes: 1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the TRACE report. Description Speed Grade -2 -1 Units D input Setup/Hold with respect to CLKDIV T input Setup/Hold with respect to CLK T input Setup/Hold with respect to CLKDIV OCE input Setup/Hold with respect to CLK SR (Reset) input Setup with respect to CLKDIV TCE input Setup/Hold with respect to CLK 0.31/–0.12 0.56/–0.08 0.31/–0.08 0.22/–0.05 0.07 0.21/–0.05 0.31/–0.12 0.56/–0.08 0.31/–0.08 0.22/–0.05 0.07 0.21/–0.05 ns ns ns ns ns ns Clock to out from CLK to OQ Clock to out from CLK to TQ 0.82 0.82 0.82 0.82 ns ns T input to TQ Out 0.97 0.97 ns DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 33 Virtex-6 CXT Family Data Sheet Input/Output Delay Switching Characteristics Table 46: Input/Output Delay Switching Characteristics Symbol IDELAYCTRL TDLYCCO_RDY FIDELAYCTRL_REF TIDELAYCTRL_RPW IODELAY TIDELAYRESOLUTION IODELAY Chain Delay Resolution Pattern dependent period jitter in delay chain for clock pattern.(1) TIDELAYPAT_JIT Pattern dependent period jitter in delay chain for random data pattern.(2) Pattern dependent period jitter in delay chain for random data pattern.(3) TIODELAY_CLK_MAX TIODCCK_CE / TIODCKC_CE TIODCK_INC/ TIODCKC_INC TIODCCK_RST/ TIODCKC_RST TIODDO_T TIODDO_IDATAIN TIODDO_ODATAIN Notes: 1. 2. 3. 4. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. When HIGH_PERFORMANCE mode is set to TRUE When HIGH_PERFORMANCE mode is set to FALSE. Delay depends on IODELAY tap setting. See the TRACE report for actual values. Description -2 Speed Grade -1 Units Reset to Ready for IDELAYCTRL REFCLK frequency 3 200 ±10 50 3 200 ±10 50 µs MHz MHz ns IDELAYCTRL_REF_PRECISION REFCLK precision Minimum Reset pulse width 1/(32 x 2 x FREF) 0 ±5 ±9 300 0.65/–0.09 0.31/–0.00 0.69/–0.08 Note 4 Note 4 Note 4 0 ±5 ±9 300 0.65/–0.09 0.31/–0.00 0.69/–0.08 Note 4 Note 4 Note 4 ps ps per tap ps per tap ps per tap MHz ns ns ns ps ps ps Maximum frequency of CLK input to IODELAY CE pin Setup/Hold with respect to CK INC pin Setup/Hold with respect to CK RST pin Setup/Hold with respect to CK TSCONTROL delay to MUXE/MUXF switching and through IODELAY Propagation delay through IODELAY Propagation delay through IODELAY CLB Switching Characteristics Table 47: CLB Switching Characteristics Symbol Combinatorial Delays TILO An – Dn LUT address to A An – Dn LUT address to AMUX/CMUX An – Dn LUT address to BMUX_A TITO TAXA TAXB TAXC TAXD An – Dn inputs to A – D Q outputs AX inputs to AMUX output AX inputs to BMUX output AX inputs to CMUX output AX inputs to DMUX output 0.08 0.23 0.37 0.79 0.42 0.47 0.52 0.55 0.08 0.25 0.41 0.91 0.48 0.53 0.60 0.63 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max Description Speed Grade -2 -1 Units DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 34 Virtex-6 CXT Family Data Sheet Table 47: CLB Switching Characteristics (Cont’d) Symbol TBXB TBXD TCXB TCXD TDXD TOPCYA TOPCYB TOPCYC TOPCYD TAXCY TBXCY TCXCY TDXCY TBYP TCINA TCINB TCINC TCIND Sequential Delays TCKO TSHCKO TDICK/TCKDI TCECK_CLB/ TCKCE_CLB TSRCK/TCKSR TCINCK/TCKCIN Set/Reset TSRMIN TRQ TCEO FTOG Notes: 1. 2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is listed, there is no positive hold time. These items are of interest for Carry Chain applications. Description BX inputs to BMUX output BX inputs to DMUX output CX inputs to CMUX output CX inputs to DMUX output DX inputs to DMUX output An input to COUT output Bn input to COUT output Cn input to COUT output Dn input to COUT output AX input to COUT output BX input to COUT output CX input to COUT output DX input to COUT output CIN input to COUT output CIN input to AMUX output CIN input to BMUX output CIN input to CMUX output CIN input to DMUX output Speed Grade -2 0.39 0.50 0.34 0.40 0.38 0.42 0.42 0.35 0.33 0.33 0.28 0.20 0.19 0.08 0.28 0.29 0.30 0.33 -1 0.45 0.58 0.38 0.45 0.44 0.47 0.47 0.39 0.37 0.38 0.32 0.23 0.22 0.09 0.32 0.34 0.34 0.38 Units ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max Clock to AQ – DQ outputs Clock to AMUX – DMUX outputs 0.39 0.47 0.44 0.54 ns, Max ns, Max Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK A – D input to CLK on A – D Flip Flops CE input to CLK on A – D Flip Flops SR input to CLK on A – D Flip Flops CIN input to CLK on A – D Flip Flops 0.43/0.20 0.32/–0.01 0.52/–0.08 0.24/0.17 0.50/0.23 0.37/–0.01 0.60/–0.08 0.27/0.19 ns, Min ns, Min ns, Min ns, Min SR input minimum pulse width Delay from SR input to AQ – DQ flip-flops Delay from CE input to AQ – DQ flip-flops Toggle frequency (for export control) 0.97 0.68 0.59 1098.00 0.97 0.78 0.67 1098.00 ns, Min ns, Max ns, Max MHz DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 35 Virtex-6 CXT Family Data Sheet CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 48: CLB Distributed RAM Switching Characteristics Symbol Sequential Delays TSHCKO TSHCKO_1 TDS/TDH TAS/TAH TWS/TWH TCECK/TCKCE Clock CLK TMPW TMCP Notes: 1. 2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is listed, there is no positive hold time. TSHCKO also represents the CLK to XMUX output. Refer to the TRACE report for the CLK to XMUX path. Description Speed Grade -2 -1 Units Clock to A – B outputs Clock to AMUX – BMUX outputs 1.36 1.71 1.56 1.96 ns, Max ns, Max Setup and Hold Times Before/After Clock CLK A – D inputs to CLK Address An inputs to clock WE input to clock CE input to CLK 0.88/0.22 0.27/0.70 0.40/–0.01 0.41/–0.02 1.01/0.26 0.31/0.80 0.46/0.00 0.48/–0.01 ns, Min ns, Min ns, Min ns, Min Minimum pulse width Minimum clock period 1.00 2.00 1.15 2.30 ns, Min ns, Min CLB Shift Register Switching Characteristics (SLICEM Only) Table 49: CLB Shift Register Switching Characteristics Symbol Sequential Delays TREG TREG_MUX TREG_M31 TWS/TWH TCECK/TCKCE TDS/TDH Clock CLK TMPW Notes: 1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is listed, there is no positive hold time. Description Speed Grade -2 -1 Units Clock to A – D outputs Clock to AMUX – DMUX output Clock to DMUX output via M31 output 1.58 1.93 1.55 1.82 2.22 1.78 ns, Max ns, Max ns, Max Setup and Hold Times Before/After Clock CLK WE input CE input to CLK A – D inputs to CLK 0.09/–0.01 0.10/–0.02 0.94/0.24 0.10/0.00 0.11/–0.01 1.08/0.28 ns, Min ns, Min ns, Min Minimum pulse width 0.85 0.98 ns, Min DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 36 Virtex-6 CXT Family Data Sheet Block RAM and FIFO Switching Characteristics Table 50: Block RAM and FIFO Switching Characteristics Symbol Block RAM and FIFO Clock-to-Out Delays TRCKO_DO and TRCKO_DO_REG(1) Clock CLK to DOUT output (without output register)(2)(3) Clock CLK to DOUT output (with output TRCKO_DO_ECC and TRCKO_DO_ECC_REG TRCKO_CASC and TRCKO_CASC_REG TRCKO_FLAGS TRCKO_POINTERS TRCKO_RDCOUNT TRCKO_WRCOUNT TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG TRCKO_PARITY_ECC TRCKO_RDADDR_ECC and TRCKO_RDADDR_ECC_REG Clock CLK to DOUT output with ECC (without output register)(2)(3) Clock CLK to DOUT output with ECC (with output register)(4)(5) Clock CLK to DOUT output with Cascade (without output register)(2) Clock CLK to DOUT output with Cascade (with output register)(4) Clock CLK to FIFO flags outputs(6) outputs(7) register)(4)(5) 2.08 0.75 3.30 0.86 3.18 1.58 0.91 1.09 1.09 1.09 0.76 2.84 1.06 0.90 0.92 2.39 0.86 3.79 0.98 3.65 1.81 1.05 1.25 1.25 1.25 0.87 3.26 1.21 1.03 1.06 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max Description Speed Grade -2 -1 Units Clock CLK to FIFO pointers Clock CLK to FIFO Read Counter Clock CLK to FIFO Write Counter Clock CLK to BITERR (with output register) Clock CLK to BITERR (without output register) Clock CLK to ECCPARITY in ECC encode only mode Clock CLK to RDADDR output with ECC (without output register) Clock CLK to RDADDR output with ECC (with output register) ADDR inputs(8) DIN inputs(9) mode(9) only(9) Setup and Hold Times Before/After Clock CLK TRCCK_ADDR/TRCKC_ADDR TRDCK_DI/TRCKD_DI TRDCK_DI_ECC/TRCKD_DI_ECC 0.62/0.32 1.11/0.34 0.59/0.34 0.85/0.34 1.02/0.34 1.20/0.29 0.41/0.30 0.22/0.31 0.28/0.26 0.41/0.27 0.52/0.35 0.55/0.30 0.55/0.30 0.72/0.37 1.28/0.39 0.68/0.39 0.97/0.39 1.17/0.39 1.38/0.33 0.47/0.34 0.25/0.35 0.32/0.29 0.47/0.31 0.60/0.40 0.64/0.34 0.63/0.34 ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min ns, Min DIN inputs with block RAM ECC in standard DIN inputs with block RAM ECC encode DIN inputs with FIFO ECC in standard mode(9) TRCCK_CLK/TRCKC_CLK TRCCK_RDEN/TRCKC_RDEN TRCCK_REGCE/TRCKC_REGCE TRCCK_RSTREG/TRCKC_RSTREG TRCCK_RSTRAM/TRCKC_RSTRAM TRCCK_WE/TRCKC_WE TRCCK_WREN/TRCKC_WREN TRCCK_RDEN/TRCKC_RDEN Reset Delays TRCO_FLAGS TRCCK_RSTREG/TRCKC_RSTREG Inject single/double bit error in ECC mode Block RAM Enable (EN) input CE input of output register Synchronous RSTREG input Synchronous RSTRAM input Write Enable (WE) input (block RAM only) WREN FIFO inputs RDEN FIFO inputs Reset RST to FIFO Flags/Pointers(10) FIFO reset timing(11) 1.10 0.28/0.26 1.27 0.32/0.29 ns, Max ns, Min DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 37 Virtex-6 CXT Family Data Sheet Table 50: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Maximum Frequency FMAX Block RAM (Write First and No Change modes) Block RAM (Read First mode) Block RAM (SDP FMAX_CASCADE mode)(12) 400 400 400 400 350 400 325 350 347 347 347 304 350 282 MHz MHz MHz MHz MHz MHz MHz Description Speed Grade -2 -1 Units Block RAM Cascade (Write First and No Change modes) Block RAM Cascade (Read First mode) FMAX_FIFO FMAX_ECC Notes: 1. 2. 3. 4. 5. 6. 7. 8. FIFO in all modes Block RAM and FIFO in ECC configuration TRACE will report all of these parameters as TRCKO_DO. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. These parameters also apply to synchronous FIFO with DO_REG = 0. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 9. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B. 10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 11. The FIFO reset must be asserted for at least three positive clock edges. 12. When using ISE software v12.4 or later, if the RDARRDR_COLLISION_HWCONFIG attribute is set to PERFORMANCE or the block RAM is in single-port operation, then the faster FMAX for WRITE_FIRST/NO_CHANGE modes apply. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 38 Virtex-6 CXT Family Data Sheet DSP48E1 Switching Characteristics Table 51: DSP48E1 Switching Characteristics Symbol Description Speed Grade -2 -1 Units Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}/ TDSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG} TDSPDCK_C_CREG/TDSPCKD_C_CREG TDSPDCK_D_DREG/TDSPCKD_D_DREG TDSPDCK_{A, ACIN, B, BCIN}_PREG_MULT/ TDSPCKD_{A, ACIN, B, BCIN}_PREG_MULT TDSPDCK_{A, D}_ADREG/ TDSPCKD_{A, D}_ADREG TDSPDCK_{A, ACIN, B, BCIN}_PREG_MULT/ TDSPCKD_{A, ACIN, B, BCIN}_PREG_MULT TDSPDCK_D_DREG_MULT/ TDSPCKD_D_DREG_MULT TDSPDCK_{A, ACIN, B, BCIN}_PREG/ TDSPCKD_{A, ACIN, B, BCIN}_PREG TDSPDCK_C_PREG/ TDSPCKD_C_PREG TDSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG/ TDSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG {A, ACIN, B, BCIN} input to {A, B} register CLK C input to C register CLK D input to D register CLK 0.35/0.34 0.22/0.24 0.15/0.39 0.41/0.39 0.26/0.27 0.17/0.44 ns ns ns Setup and Hold Times of Data Pins to the Pipeline Register Clock {A, ACIN, B, BCIN} input to M register CLK {A, D} input to AD register CLK 3.21/0.02 1.69/0.13 3.69/0.02 1.94/0.15 ns ns Setup and Hold Times of Data/Control Pins to the Output Register Clock {A, ACIN, B, BCIN} input to P register CLK using multiplier D input to P register CLK {A, ACIN, B, BCIN} input to P register CLK not using multiplier C input to P register CLK {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK 5.20/–0.19 5.97/–0.22 4.90/–0.65 5.63/–0.75 2.15/–0.19 2.47/–0.22 1.91/–0.14 2.19/–0.17 1.67/–0.04 1.92/–0.05 ns ns ns ns ns Setup and Hold Times of the CE Pins TDSPDCK_{CEA; CEB}_{AREG; BREG}/ TDSPCKD_{CEA; CEB}_{AREG; BREG} TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG {CEA; CEB} input to {A; B} register CLK CEC input to C register CLK CED input to D register CLK CEM input to M register CLK CEP input to P register CLK 0.22/0.25 0.24/0.23 0.31/0.14 0.26/0.25 0.46/0.03 0.25/0.29 0.28/0.27 0.35/0.16 0.30/0.28 0.53/0.03 ns ns ns ns ns Setup and Hold Times of the RST Pins TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG} TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG TDSPDO_{A, B}_{P, CARRYOUT}_MULT TDSPDO_D_{P, CARRYOUT}_MULT TDSPDO_{A, B}_{P, CARRYOUT} TDSPDO_{C, CARRYIN}_{P, CARRYOUT} {RSTA, RSTB} input to {A, B} register CLK RSTC input to C register CLK RSTD input to D register CLK RSTM input to M register CLK RSTP input to P register CLK 0.38/0.22 0.23/0.09 0.38/0.19 0.26/0.30 0.33/0.05 0.43/0.25 0.27/0.11 0.44/0.21 0.30/0.35 0.41/0.06 ns ns ns ns ns Combinatorial Delays from Input Pins to Output Pins {A, B} input to {P, CARRYOUT} output using multiplier D input to {P, CARRYOUT} output using multiplier {A, B} input to {P, CARRYOUT} output not using multiplier {C, CARRYIN} input to {P, CARRYOUT} output 5.08 4.82 2.07 1.83 5.84 5.54 2.38 2.10 ns ns ns ns DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 39 Virtex-6 CXT Family Data Sheet Table 51: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade -2 -1 Units Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{A; B}_{ACOUT; BCOUT} TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MULT TDSPDO_D_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MULT TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT} TDSPDO__{C, CARRYIN}_{PCOUT, CARRYCASCOUT,MULTSIGNOUT} TDSPDO_{ACIN, BCIN}_{P, CARRYOUT}_MULT TDSPDO_{ACIN, BCIN}_{P, CARRYOUT TDSPDO_{ACIN; BCIN}_{ACOUT; BCOUT} TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MULT {A, B} input to {ACOUT, BCOUT} output {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier D input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier {C, CARRYIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 0.65 5.24 4.94 2.19 1.95 0.75 6.03 5.68 2.52 2.25 ns ns ns ns ns Combinatorial Delays from Cascading Input Pins to All Output Pins {ACIN, BCIN} input to {P, CARRYOUT} output using multiplier {ACIN, BCIN} input to {P, CARRYOUT} output not using multiplier {ACIN, BCIN} input to {ACOUT, BCOUT} output {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier {PCIN, CARRYCASCIN, MULTSIGNIN} input to {P, CARRYOUT} output {PCIN, CARRYCASCIN, MULTSIGNIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 4.97 1.92 0.49 5.10 5.72 2.21 0.57 5.86 ns ns ns ns TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT} 2.05 2.35 ns TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_ {P, CARRYOUT} TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_ {PCOUT, CARRYCASCOUT, MULTSIGNOUT} 1.60 1.72 1.83 1.98 ns ns Clock to Outs from Output Register Clock to Output Pins TDSPCKO_{P, CARRYOUT}_PREG TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_PREG TDSPCKO_{P, CARRYOUT}_MREG TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MREG TDSPCKO_{P, CARRYOUT}_ADREG_MULT TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_ADREG_MULT TDSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT TDSPCKO_{P, CARRYOUT}_{AREG, BREG} TDSPCKO_{P, CARRYOUT}_CREG TDSPCKO_{P, CARRYOUT}_DREG_MULT CLK (PREG) to {P, CARRYOUT} output CLK (PREG) to {CARRYCASCOUT, PCOUT, MULTSIGNOUT} output 0.50 0.50 0.57 0.66 ns ns Clock to Outs from Pipeline Register Clock to Output Pins CLK (MREG) to {P, CARRYOUT} output CLK (MREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output CLK (ADREG) to {P, CARRYOUT} output CLK (ADREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 2.30 2.43 3.72 3.84 2.65 2.79 4.72 4.42 ns ns ns ns Clock to Outs from Input Register Clock to Output Pins CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier CLK (AREG, BREG) to {P, CARRYOUT} output not using multiplier CLK (CREG) to {P, CARRYOUT} output CLK (DREG) to {P, CARRYOUT} output 5.36 2.27 2.27 5.25 6.16 2.61 2.61 6.04 ns ns ns ns DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 40 Virtex-6 CXT Family Data Sheet Table 51: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade -2 -1 Units Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG} TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_{AREG, BREG}_MULT TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_{AREG, BREG} TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_DREG_MULT TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_CREG CLK (AREG, BREG) to {P, CARRYOUT} output CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier CLK (DREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier CLK (CREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 0.89 5.49 1.02 6.31 ns ns 2.40 2.76 ns 5.38 2.40 6.18 2.76 ns ns Maximum Frequency FMAX FMAX_PATDET FMAX_MULT_NOMREG FMAX_MULT_NOMREG_PATDET FMAX_PREADD_MULT_NOADREG FMAX_PREADD_MULT_NOADREG_PATDET FMAX_NOPIPELINEREG FMAX_NOPIPELINEREG_PATDET With all registers used With pattern detector Two register multiply without MREG Two register multiply without MREG with pattern detect Without ADREG Without ADREG with pattern detect Without pipeline registers (MREG, ADREG) Without pipeline registers (MREG, ADREG) with pattern detect 350 350 262 241 292 292 196 184 275 275 227 209 253 253 170 160 MHz MHz MHz MHz MHz MHz MHz MHz DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 41 Virtex-6 CXT Family Data Sheet Configuration Switching Characteristics Table 52: Configuration Switching Characteristics Symbol Power-up Timing Characteristics TPL(1) TPOR(1) TICCK TPROGRAM TDCCK/TCCKD TDSCCK/TSCCKD TCCO FMCCK FMCCKTOL FMSCCK TSMDCCK/TSMCCKD TSMCSCCK/TSMCCKCS TSMCCKW/TSMWCCK TSMCKCSO TSMCO TSMCKBY FSMCCK FRBCCK FMCCKTOL TTAPTCK/TTCKTAP TTCKTDO FTCK FTCKB_MIN Program Latency Power-on-Reset CCLK (output) delay Program Pulse Width 3 15/55 400 250 3 15/55 400 250 ms, Max ms, Min/Max ns, Min ns, Min Description Speed Grade -2 -1 Units Master/Slave Serial Mode Programming Switching(1) DIN Setup/Hold, slave mode DIN Setup/Hold, master mode DOUT at 2.5V DOUT at 1.8V Maximum CCLK frequency, serial modes Frequency Tolerance, master mode with respect to nominal CCLK Slave mode external CCLK 4.0/0.0 4.0/0.0 6 6 100 55 100 4.0/0.0 4.0/0.0 6 6 100 55 100 ns, Min ns, Min ns, Max ns, Max MHz, Max % MHz SelectMAP Mode Programming Switching SelectMAP Data Setup/Hold CSI_B Setup/Hold RDWR_B Setup/Hold CSO_B clock to out (330  pull-up resistor required) CCLK to DATA out in readback at 2.5V CCLK to DATA out in readback at 1.8V CCLK to BUSY out in readback at 2.5V CCLK to BUSY out in readback at 1.8V Maximum Frequency with respect to nominal CCLK Maximum Readback Frequency with respect to nominal CCLK Frequency Tolerance with respect to nominal CCLK 4.0/0.0 4.0/0.0 10.0/0.0 7 8 8 6 6 100 100 55 4.0/0.0 4.0/0.0 10.0/0.0 7 8 8 6 6 100 100 55 ns, Min ns, Min ns, Min ns, Min ns, Max ns, Max ns, Max ns, Max MHz, Max MHz, Max % Boundary-Scan Port Timing Specifications TMS and TDI Setup time before TCK/ Hold time after TCK TCK falling edge to TDO output valid at 2.5V TCK falling edge to TDO output valid at 1.8V Maximum configuration TCK clock frequency Minimum boundary-scan TCK clock frequency when using IEEE Std 1149.6 (AC-JTAG). Minimum operating temperature for IEEE Std 1149.6 is 0°C. Maximum boundary-scan TCK clock frequency 3.0/2.0 6 6 66 15 3.0/2.0 6 6 66 15 ns, Min ns, Max ns, Max MHz, Max MHz, Min FTCKB 66 66 MHz, Max DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 42 Virtex-6 CXT Family Data Sheet Table 52: Configuration Switching Characteristics (Cont’d) Symbol BPI Master Flash Mode Programming Switching TBPICCO(2) ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge at 2.5V ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge at 1.8V TBPIDCC/TBPICCD TINITADDR TSPIDCC/TSPIDCCD TSPICCM TSPICCFC TFSINIT/TFSINITH CCLK Output (Master Modes) TMCCKL TMCCKH CCLK Input (Slave Modes) TSCCKL TSCCKH FDCK TMMCMDCK_DADDR/ TMMCMCKD_DADDR TMMCMDCK_DI/TMMCMCKD_DI TMMCMDCK_DEN/TMMCMCKD_DEN TMMCMDCK_DWE/TMMCMCKD_DWE TMMCMCKO_DO TMMCMCKO_DRDY Notes: 1. 2. 3. To support longer delays in configuration, use the design solutions described in Virtex-6 FPGA Configuration Guide. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O. DO will hold until next DRP operation. Description Speed Grade -2 -1 Units 6 6 4.0/0.0 3 6 6 4.0/0.0 3 ns ns ns CCLK cycles Setup/Hold on D[15:0] data input pins Minimum period of initial ADDR[25:0] address cycles SPI Master Flash Mode Programming Switching DIN Setup/Hold before/after the rising CCLK edge MOSI clock to out at 2.5V MOSI clock to out at 1.8V FCS_B clock to out at 2.5V FCS_B clock to out at 1.8V FS[2:0] to INIT_B rising edge Setup and Hold 3.0/0.0 6 6 6 6 2 3.0/0.0 6 6 6 6 2 ns ns ns ns ns µs Master CCLK clock Low time duty cycle Master CCLK clock High time duty cycle 45/55 45/55 45/55 45/55 %, Min/Max %, Min/Max Slave CCLK clock minimum Low time Slave CCLK clock minimum High time 2.5 2.5 2.5 2.5 ns, Min ns, Min Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK Maximum frequency for DCLK DADDR Setup/Hold DI Setup/Hold DEN Setup/Hold time DWE Setup/Hold time CLK to out of DO(3) CLK to out of DRDY 200 200 MHz ns ns ns ns ns ns 1.63/0.00 1.63/0.00 1.63/0.00 1.63/0.00 1.63/0.00 1.63/0.00 1.63/0.00 1.63/0.00 3.64 0.38 3.64 0.38 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 43 Virtex-6 CXT Family Data Sheet Clock Buffers and Networks Table 53: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol TBCCCK_CE/TBCCKC_CE(1) TBCCCK_S/TBCCKC_S(1) TBCCKO_O(2) Maximum Frequency FMAX Notes: 1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. Description CE pins Setup/Hold S pins Setup/Hold BUFGCTRL delay from I0/I1 to O Speed Grade -2 0.16/0.00 0.16/0.00 0.10 Units ns ns ns -1 0.16/0.00 0.16/0.00 0.10 Global clock tree (BUFG) 700 700 MHz 2. Table 54: Input/Output Clock Switching Characteristics (BUFIO) Symbol TBIOCKO_O Maximum Frequency FMAX I/O clock tree (BUFIO) 710 710 MHz Description Clock to out delay from I to O Speed Grade -2 0.18 Units ns -1 0.18 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 44 Virtex-6 CXT Family Data Sheet Table 55: Regional Clock Switching Characteristics (BUFR) Symbol Description Speed Grade -2 0.75 TBRCKO_O Clock to out delay from I to O 0.75 0.75 0.75 0.37 TBRCKO_O_BYP Clock to out delay from I to O with Divide Bypass attribute set 0.37 0.37 0.37 TBRDO_O Maximum Frequency FMAX Regional clock tree (BUFR) 300 300 MHz Propagation delay from CLR to O 0.83 Units ns ns ns ns ns ns ns ns ns -1 0.75 0.75 0.75 0.75 0.37 0.37 0.37 0.37 0.83 Table 56: Horizontal Clock Buffer Switching Characteristics (BUFH) Symbol TBHCKO_O TBHCCK_CE/TBHCKC_CE Maximum Frequency FMAX Horizontal clock buffer (BUFH) 700 700 MHz BUFH delay from I to O CE pin Setup and Hold Description Speed Grade -2 0.13 0.05/0.05 Units ns ns -1 0.13 0.05/0.05 MMCM Switching Characteristics Table 57: MMCM Specification Symbol FINMAX FINMIN FINJITTER FINDUTY Description -2 Maximum Input Clock Frequency(1) Minimum Input Clock Frequency Maximum Input Clock Period Jitter Allowable Input Duty Cycle: 10—49 MHz Allowable Input Duty Cycle: 50—199 MHz Allowable Input Duty Cycle: 200—399 MHz Allowable Input Duty Cycle: 400—499 MHz Allowable Input Duty Cycle: >500 MHz 700 10 Speed Grade -1 700 10 Units MHz MHz < 20% of clock input period or 1 ns Max 25/75 30/70 35/65 40/60 45/55 0.01 450 600 1200 1.00 4.00 0.01 450 600 1200 1.00 4.00 % % % % % MHz MHz MHz MHz MHz MHz FMIN_PSCLK FMAX_PSCLK FVCOMIN FVCOMAX FBANDWIDTH Minimum Dynamic Phase Shift Clock Frequency Maximum Dynamic Phase Shift Clock Frequency Minimum MMCM VCO Frequency Maximum MMCM VCO Frequency Low MMCM Bandwidth at Typical(2) High MMCM Bandwidth at Typical(2) DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 45 Virtex-6 CXT Family Data Sheet Table 57: MMCM Specification (Cont’d) Symbol TSTATPHAOFFSET TOUTJITTER TOUTDUTY TLOCKMAX FOUTMAX FOUTMIN TEXTFDVAR RSTMINPULSE FPFDMAX Description -2 Static Phase Offset of the MMCM Outputs(3) MMCM Output Jitter(4) Precision(5) 0.20 100 700 4.69 0.12 Speed Grade -1 0.12 Note 1 0.20 100 700 4.69 Units ns MMCM Output Clock Duty Cycle MMCM Maximum Lock Time ns µs MHz MHz MMCM Maximum Output Frequency MMCM Minimum Output Frequency(6)(7) External Clock Feedback Variation Minimum Reset Pulse Width Maximum Frequency at the Phase Frequency Detector with Bandwidth Set to High or Optimized(8) Maximum Frequency at the Phase Frequency Detector with Bandwidth Set to Low < 20% of clock input period or 1 ns Max 1.5 450 300 135 10.00 1.5 450 300 135 10.00 ns MHz MHz MHz MHz FPFDMIN Minimum Frequency at the Phase Frequency Detector with Bandwidth Set to High or Optimized Minimum Frequency at the Phase Frequency Detector with Bandwidth Set to Low TFBDELAY TMMCMDCK_PSEN/ TMMCMCKD_PSEN TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC TMMCMCKO_PSDONE Notes: 1. 2. 3. 4. 5. 6. 7. 8. Maximum Delay in the Feedback Path Setup and Hold of Phase Shift Enable Setup and Hold of Phase Shift Increment/Decrement Phase Shift Clock-to-Out of PSDONE 3 ns Max or one CLKIN cycle 1.04/0.00 1.04/0.00 0.38 1.04/0.00 1.04/0.00 0.38 ns ns ns When DIVCLK_DIVIDE = 3 or 4, FINMAX is 315 MHz. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any MMCM outputs with identical phase. Values for this parameter are available in the Architecture Wizard. Includes global clock buffer. Calculated as FVCO/128 assuming output duty cycle is 50%. When CASCADE4_OUT = TRUE, FOUTMIN is 0.036 MHz. In ISE software 12.3 (or earlier versions supporting the Virtex-6 family), the phase frequency detector Optimized bandwidth setting is equivalent to the High bandwidth setting. Starting with ISE software 12.4, the Optimized bandwidth setting is automatically adjusted to Low when the software can determine that the phase frequency detector input is less than 135 MHz. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 46 Virtex-6 CXT Family Data Sheet Virtex-6 CXT Device Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 58. Values are expressed in nanoseconds unless otherwise noted. Table 58: Global Clock Input to Output Delay Without MMCM Symbol Description Device Speed Grade -2 LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM. TICKOF Global Clock input and OUTFF without MMCM XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Units -1 5.88 6.00 6.13 6.13 5.88 6.00 6.13 6.13 ns ns ns ns Table 59: Global Clock Input to Output Delay With MMCM Symbol Description Device Speed Grade -2 LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM. TICKOFMMCMGC Global Clock Input and OUTFF with MMCM XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation. Units -1 2.77 2.78 2.78 2.79 2.77 2.78 2.78 2.79 ns ns ns ns Table 60: Clock-Capable Clock Input to Output Delay With MMCM Symbol Description Device Speed Grade -2 LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable Clock Input and OUTFF with MMCM XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation. Units -1 2.63 2.65 2.65 2.65 2.63 2.65 2.65 2.65 ns ns ns ns DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 47 Virtex-6 CXT Family Data Sheet Virtex-6 CXT Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 61. Values are expressed in nanoseconds unless otherwise noted. Table 61: Global Clock Input Setup and Hold Without MMCM Symbol Description Device -2 Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) Global Clock Input and IFF(2) without MMCM XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. Speed Grade -1 Units 1.75/–0.01 1.88/–0.11 1.97/–0.14 1.97/–0.14 1.75/–0.01 1.88/–0.11 1.97/–0.14 1.97/–0.14 ns ns ns ns 2. 3. Table 62: Global Clock Input Setup and Hold With MMCM Symbol Description Device -2 Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSMMCMGC/ TPHMMCMGC No Delay Global Clock Input and IFF(2) with MMCM XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch. Use IBIS to determine any duty-cycle distortion incurred using various standards. Speed Grade -1 Units 1.72/–0.22 1.81/–0.21 1.82/–0.20 1.82/–0.20 1.72/–0.22 1.81/–0.21 1.82/–0.20 1.82/–0.20 ns ns ns ns 2. 3. Table 63: Clock-Capable Clock Input Setup and Hold With MMCM Symbol Description Device -2 Input Setup and Hold Time Relative to Clock-capable Clock Input Signal for LVCMOS25 Standard.(1) TPSMMCMCC/ TPHMMCMCC No Delay Clock-capable Clock Input and IFF(2) with MMCM XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch. Use IBIS to determine any duty-cycle distortion incurred using various standards. Speed Grade -1 Units 1.86/–0.28 1.93/–0.28 1.96/–0.27 1.96/–0.27 1.86/–0.28 1.93/–0.28 1.96/–0.27 1.96/–0.27 ns ns ns ns 2. 3. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 48 Virtex-6 CXT Family Data Sheet Clock Switching Characteristics The parameters in this section provide the necessary values for calculating timing budgets for Virtex-6 CXT FPGA clock transmitter and receiver data-valid windows. Table 64: Duty Cycle Distortion and Clock-Tree Skew Symbol TDCD_CLK TCKSKEW Description Global Clock Tree Duty Cycle Distortion(1) Global Clock Tree Skew(2) Device All XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Speed Grade -2 0.12 0.18 0.29 0.31 0.31 0.08 0.03 0.22 0.15 Units ns ns ns ns ns ns ns ns ns -1 0.12 0.18 0.29 0.31 0.31 0.08 0.03 0.22 0.15 TDCD_BUFIO TBUFIOSKEW TBUFIOSKEW2 TDCD_BUFR Notes: 1. I/O clock tree duty cycle distortion I/O clock tree skew across one clock region I/O clock tree skew across three clock regions Regional clock tree duty cycle distortion All All All All 2. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. Table 65: Package Skew Symbol TPKGSKEW Package Description Skew(1) Device XC6VCX75T Package FF484 FF784 Value Units ps ps XC6VCX130T FF484 FF784 FF1156 95 146 165 ps ps ps ps ps XC6VCX195T FF784 FF1156 XC6VCX240T FF784 FF1156 146 182 ps ps Notes: 1. 2. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time from Pad to Ball (7.0 ps per mm). Package trace length information is available for these device/package combinations. This information can be used to deskew the package. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 49 Virtex-6 CXT Family Data Sheet Table 66: Sample Window Symbol TSAMP TSAMP_BUFIO Notes: 1. This parameter indicates the total sampling error of Virtex-6 CXT FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. This parameter indicates the total sampling error of Virtex-6 CXT FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. Description Sampling Error at Receiver Pins(1) Sampling Error at Receiver Pins using BUFIO(2) Device -2 All All Speed Grade -1 610 400 Units ps ps 610 400 2. Table 67: Pin-to-Pin Setup/Hold and Clock-to-Out Symbol Description -2 Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO TPSCS/TPHCS TICKOFCS Setup/Hold of I/O clock –0.33/1.31 –0.33/1.31 ns Speed Grade -1 Units Pin-to-Pin Clock-to-Out Using BUFIO Clock-to-Out of I/O clock 5.19 5.19 ns Revision History The following table shows the revision history for this document: Date 07/08/09 02/05/10 Version 1.0 1.1 Initial Xilinx release. Description of Revisions Removed Figure 11: Placement Diagram for the FF1156 Package (5 of 5) from page 11 as there are only 16 GTX transceivers in the FF1156 package. Corrected the placement diagrams in Figure 2 through Figure 10. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 50 Virtex-6 CXT Family Data Sheet Date 06/08/10 Version 1.2 Description of Revisions Revised GTX Transceivers in CXT Devices, page 5. Added VFS and revised the VIN and VTS values in Table 9, page 11. Added VFS and note 6 to Table 10. Revised description of CIN in Table 11, including adding note 3. Updated Table 13 including adding note 2. Removed DIFF SSTL15 and added values to SSTL15 in Table 15. Updated Table 16 through Table 19. Added eFUSE Read Endurance section. Updated entire GTX Transceivers in CXT Devices section. Changed specifications of PCI Express in Table 34. In Table 35, removed RLDRAM II and revised and added values to other interface performance specifications. Updated speed specification to v1.04 with appropriate changes to Table 36. Revised the IOB switching characteristics in Table 38. Updated values in Table 39 and note 4 in Table 41. ILOGIC (Table 42), OLOGIC (Table 43), ISERDES (Table 44), and OSERDES (Table 45) switching characteristics changes. Revised TIODELAY_CLK_MAX and TIDELAYPAT_JIT in Table 46. Revised CLB switching characteristics and added TSHCKO to Table 47and revised CLB switching characteristics in Table 48 and Table 49. In Table 50, removed TRCKO_RDCOUNT and TRCKO_WRCOUNT, removed TRCKO_PARITY_ECC: Clock CLK to ECCPARITY in standard ECC mode, revised TRDCK_DI_ECC/TRCKD_DI_ECC, TRCKO_POINTERS, and revised FMAX and FMAX_CASCADE switching characteristics. Multiple changes to configuration specifications in Table 52. Revised switching characteristics and global clock tree (BUFG) FMAX in Table 53. Revised switching characteristics and I/O clock tree (BUFIO) FMAX in Table 54. Added note 1 to Table 55. Revised the FMAX horizontal clock tree (BUFH) in Table 56. Multiple changes to MMCM specifications in Table 57 including FINMAX and FOUTMAX. Updated switching characteristics in Table 58 through Table 63. Removed TDCD_BUFH and TBUFHSKEW from Table 64. Production release of XC6VCX130T and XC6VCX240T in Table 36 and Table 37. Updated -1 speed grade SDR values in Table 35. Updated BUFIO FMAX specification in Table 54. Added Note 6 to Table 57. Production release of XC6VCX75T and XC6VCX195T in Table 36 and Table 37 using ISE 12.2 software with speed file v1.06 using the Speed File Patch. Updated PCI compliance on page 1. Added values to Table 13. In Table 25, update VCMOUTDC equation to MGTAVTT – DVPPOUT/4. Updated FMAX in Table 53, Table 54, and Table 56. Updated FINMAX and FOUTMAX in Table 57. Updated values in Table 61, Table 62, and Table 63. Moved data sheet to Production status on the first page. Updated speed file with ISE 12.3 software with speed file v1.08 using the Speed File Patch. In Table 51, updated values for TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_PREG. Updated Table 10 to include the industrial range specifications. Added Note 12 to Table 50. Revised TBPICCO values in Table 52. Updated range description for FINDUTY in Table 57 and added note 8. The following revisions are due to specification changes as described in XCN11009, Virtex-6 FPGA: Data Sheet, User Guides, and JTAG ID Updates. In Table 52, updated the values for TSMCCKW, TSPIDCC, TSPICCM, and TSPICCFC. In Table 57: MMCM Specification, added bandwidth settings to FPFDMIN and added note 1. 06/30/10 1.3 07/28/10 1.4 10/14/10 1.5 02/11/11 1.6 DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 51 Virtex-6 CXT Family Data Sheet Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. CRITICAL APPLICATIONS DISCLAIMER XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAILSAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. AUTOMOTIVE APPLICATIONS DISCLAIMER XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAILSAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS153 (v1.6) February 11, 2011 Product Specification www.xilinx.com 52