Kintex-7 FPGAs Data Sheet:
DC and AC Switching Characteristics
DS182 (v2.18) June 28, 2019
Product Specification
Introduction
Kintex®-7 FPGAs are available in -3, -2, -1, -1L, and -2L
speed grades, with -3 having the highest performance. The
-2L devices are screened for lower maximum static power
and can operate at lower core voltages for lower dynamic
power than the -2 devices. The -2L industrial (I) temperature
devices operate only at VCCINT = 0.95V. The -2L extended (E)
temperature devices can operate at either VCCINT = 0.9V or
1.0V. The -2LE devices when operated at VCCINT = 1.0V, and
the -2LI devices when operated at VCCINT = 0.95V, have the
same speed specifications as the -2 speed grade, except
where noted. When the -2LE devices are operated at
VCCINT = 0.9V, the speed specifications, static power, and
dynamic power are reduced. The -1L military (M)
temperature devices have the same speed specifications as
the -1 military temperature devices and are screened for
lower maximum static power.
Kintex-7 FPGA DC and AC characteristics are specified in
commercial, extended, industrial, expanded (-1Q), and
military (-1M) temperature ranges. Except for the operating
temperature range or unless otherwise noted, all the DC
and AC electrical parameters are the same for a particular
speed grade (that is, the timing characteristics of a -1 speed
grade military temperature device are the same as for a -1
speed grade commercial temperature device). However,
only selected speed grades and/or devices are available in
each temperature range. For example, -1M is only available
in the defense-grade Kintex-7Q family, and -1Q is only
available in XA Kintex-7 FPGAs.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parameters
included are common to popular designs and typical
applications.
Available device and package combinations can be found in:
•
7 Series FPGAs Overview (DS180)
•
Defense-Grade 7 Series FPGAs Overview (DS185)
•
XA Kintex-7 FPGA Data Sheet: Overview (DS175)
This Kintex-7 FPGA data sheet, part of an overall set of
documentation on the 7 series FPGAs, is available on the
Xilinx website at www.xilinx.com/documentation.
DC Characteristics
Table 1: Absolute Maximum Ratings (1)
Symbol
Description
Min
Max
Units
FPGA Logic
VCCINT
Internal supply voltage
–0.5
1.1
V
VCCAUX
Auxiliary supply voltage
–0.5
2.0
V
VCCBRAM
Supply voltage for the block RAM memories
–0.5
1.1
V
Output drivers supply voltage for HR I/O banks
–0.5
3.6
V
Output drivers supply voltage for HP I/O banks
–0.5
2.0
V
VCCAUX_IO
Auxiliary supply voltage
–0.5
2.06
V
VREF
Input reference voltage
–0.5
2.0
V
I/O input voltage for HR I/O banks
–0.40
VCCO + 0.55
V
I/O input voltage for HP I/O banks
–0.55
VCCO + 0.55
V
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except
TMDS_33(5)
–0.40
2.625
V
Key memory battery backup supply
–0.5
2.0
V
VCCO
VIN(2)(3)(4)
VCCBATT
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 1: Absolute Maximum Ratings (1) (Cont’d)
Symbol
Description
Min
Max
Units
GTX Transceiver
VMGTAVCC
Analog supply voltage for the GTX transmitter and receiver circuits
–0.5
1.1
V
VMGTAVTT
Analog supply voltage for the GTX transmitter and receiver termination circuits
–0.5
1.32
V
VMGTVCCAUX
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers
–0.5
1.935
V
VMGTREFCLK
GTX transceiver reference clock absolute input voltage
–0.5
1.32
V
VMGTAVTTRCAL
Analog supply voltage for the resistor calibration circuit of the GTX transceiver
column
–0.5
1.32
V
VIN
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
–0.5
1.26
V
IDCIN-FLOAT
DC input current for receiver input pins DC coupled RX termination = floating
–
14
mA
IDCIN-MGTAVTT
DC input current for receiver input pins DC coupled RX termination = VMGTAVTT
–
12
mA
IDCIN-GND
DC input current for receiver input pins DC coupled RX termination = GND
–
6.5
mA
IDCOUT-FLOAT
DC output current for transmitter pins DC coupled RX termination = floating
–
14
mA
IDCOUT-MGTAVTT
DC output current for transmitter pins DC coupled RX termination = VMGTAVTT
–
12
mA
XADC
VCCADC
XADC supply relative to GNDADC
–0.5
2.0
V
VREFP
XADC reference input relative to GNDADC
–0.5
2.0
V
Storage temperature (ambient)
–65
150
°C
–
+220
°C
–
+260
°C
–
+125
°C
Temperature
TSTG
TSOL
Maximum soldering temperature for Pb/Sn component bodies (6)
Maximum soldering temperature for Pb-free component bodies
Maximum junction
Tj
(6)
temperature(6)
Notes:
1.
2.
3.
4.
5.
6.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
The lower absolute voltage specification always applies.
For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471).
The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5.
See Table 10 for TMDS_33 specifications.
For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475).
Table 2: Recommended Operating Conditions (1)(2)
Symbol
Description
Min
Typ
Max
Units
For -3, -2, -2LE (1.0V), -1, -1M, -1LM, -1Q devices: internal supply voltage
0.97
1.00
1.03
V
For -2LE (0.9V) devices: internal supply voltage
0.87
0.90
0.93
V
For -2LI (0.95V) devices: internal supply voltage
0.93
0.95
0.97
V
For -3, -2, -2LE (1.0V), -1, -1M, -1LM, -1Q devices: block RAM supply voltage
0.97
1.00
1.03
V
For -2LE (0.9V) devices: block RAM supply voltage
0.87
0.90
1.03
V
For -2LI (0.95V) devices: block RAM supply voltage
0.93
0.95
0.97
V
Auxiliary supply voltage
1.71
1.80
1.89
V
Supply voltage for HR I/O banks
1.14
–
3.465
V
Supply voltage for HP I/O banks
1.14
–
1.89
V
FPGA Logic
VCCINT(3)
VCCBRAM(3)
VCCAUX
VCCO(4)(5)
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 2: Recommended Operating Conditions (1)(2) (Cont’d)
Symbol
VCCAUX_IO(6)
Description
Min
Typ
Max
Units
Auxiliary supply voltage when set to 1.8V
1.71
1.80
1.89
V
Auxiliary supply voltage when set to 2.0V
1.94
2.00
2.06
V
I/O input voltage
–0.20
–
VCCO + 0.2
V
VIN(7)
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards
except TMDS_33(8)
–0.20
–
2.625
V
IIN(9)
Maximum current through any pin in a powered or unpowered bank when
forward biasing the clamp diode.
–
–
10
mA
VCCBATT(10)
Battery voltage
1.0
–
1.89
V
Analog supply voltage for the GTX transceiver QPLL frequency range
≤ 10.3125 GHz(12)(13)
0.97
1.0
1.08
V
Analog supply voltage for the GTX transceiver QPLL frequency range
> 10.3125 GHz
1.02
1.05
1.08
V
VMGTAVTT(11)
Analog supply voltage for the GTX transmitter and receiver termination
circuits
1.17
1.2
1.23
V
VMGTVCCAUX(11)
Auxiliary analog QPLL voltage supply for the transceivers
1.75
1.80
1.85
V
VMGTAVTTRCAL(11)
Analog supply voltage for the resistor calibration circuit of the GTX
transceiver column
1.17
1.2
1.23
V
VCCADC
XADC supply relative to GNDADC
1.71
1.80
1.89
V
VREFP
Externally supplied reference voltage
1.20
1.25
1.30
V
Junction temperature operating range for commercial (C) temperature
devices
0
–
85
°C
Junction temperature operating range for extended (E) temperature devices
0
–
100
°C
Junction temperature operating range for industrial (I) temperature devices
–40
–
100
°C
Junction temperature operating range for military (M) temperature devices
–55
–
125
°C
Junction temperature operating range for expanded (Q) temperature devices
–40
–
125
°C
GTX Transceiver
VMGTAVCC(11)
XADC
Temperature
Tj
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
All voltages are relative to ground.
For the design of the power distribution system, consult the 7 Series FPGAs PCB Design and Pin Planning Guide (UG483).
VCCINT and VCCBRAM should be connected to the same supply.
Configuration data is retained even if VCCO drops to 0V.
Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), and 3.3V (HR I/O only) at ±5%.
For more information, refer to the VCCAUX_IO section of 7 Series FPGAs SelectIO Resources User Guide (UG471).
The lower absolute voltage specification always applies.
See Table 10 for TMDS_33 specifications.
A total of 200 mA per bank should not be exceeded.
VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.
Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
For data rates ≤ 10.3125 Gb/s, VMGTAVCC should be 1.0V ±3% for lower power consumption.
For lower power consumption, VMGTAVCC should be 1.0V ±3% over the entire CPLL frequency range.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
Typ(1)
Max
Units
VDRINT
Data retention VCCINT voltage (below which configuration data might be lost)
0.75
–
–
V
VDRI
Data retention VCCAUX voltage (below which configuration data might be lost)
1.5
–
–
V
IREF
VREF leakage current per pin
–
–
15
µA
IL
Input or output leakage current per pin (sample-tested)
–
–
15
µA
CIN(2)
Die input capacitance at the pad
–
–
8
pF
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
90
–
330
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
68
–
250
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
34
–
220
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
23
–
150
µA
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
12
–
120
µA
Pad pull-down (when selected) @ VIN = 3.3V
68
–
330
µA
Pad pull-down (when selected) @ VIN = 1.8V
45
–
180
µA
ICCADC
Analog supply current, analog circuits in powered up state
–
–
25
mA
IBATT(3)
Battery supply current
–
–
150
nA
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_40)
28
40
55
Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_50)
35
50
65
Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_60)
44
60
83
Ω
n
Temperature diode ideality factor
–
1.010
–
–
r
Temperature diode series resistance
–
2
–
Ω
IRPU
IRPD
RIN_TERM(4)
Notes:
1.
2.
3.
4.
Typical values are specified at nominal voltage, 25°C.
This measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25°C.
Termination resistance to a VCCO/2 level.
Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2)
AC Voltage Overshoot
VCCO + 0.55
% of UI at –55°C to 125°C
AC Voltage Undershoot
% of UI at –55°C to 125°C
–0.40
100
–0.45
61.7
–0.50
25.8
–0.55
11.0
100
VCCO + 0.60
46.6
–0.60
4.77
VCCO + 0.65
21.2
–0.65
2.10
VCCO + 0.70
9.75
–0.70
0.94
VCCO + 0.75
4.55
–0.75
0.43
VCCO + 0.80
2.15
–0.80
0.20
VCCO + 0.85
1.02
–0.85
0.09
VCCO + 0.90
0.49
–0.90
0.04
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) (Cont’d)
AC Voltage Overshoot
% of UI at –55°C to 125°C
AC Voltage Undershoot
% of UI at –55°C to 125°C
VCCO + 0.95
0.24
–0.95
0.02
Notes:
1.
2.
A total of 200 mA per bank should not be exceeded.
The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values
in this table.
Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks(1)(2)
AC Voltage Overshoot
% of UI at –55°C to 125°C
AC Voltage Undershoot
% of UI at –55°C to 125°C
VCCO + 0.55
100
–0.55
100
VCCO + 0.60
50.0(3)
–0.60
50.0(3)
VCCO + 0.65
50.0(3)
–0.65
50.0(3)
VCCO + 0.70
47.0
–0.70
50.0(3)
VCCO + 0.75
21.2
–0.75
50.0(3)
VCCO + 0.80
9.71
–0.80
50.0(3)
VCCO + 0.85
4.51
–0.85
28.4
VCCO + 0.90
2.12
–0.90
12.7
VCCO + 0.95
1.01
–0.95
5.79
Notes:
1.
2.
3.
A total of 200 mA per bank should not be exceeded.
The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values
in this table.
For UI lasting less than 20 µs.
Table 6: Typical Quiescent Supply Current
Speed Grade
Symbol
ICCINTQ
Description
Quiescent VCCINT
supply current
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Device
1.0V
0.95V
0.9V
Units
-3
-2/-2LE
-1
-1LM
-1M
-1Q
-2LI
-2LE
XC7K70T
241
241
241
N/A
N/A
N/A
N/A
187
mA
XC7K160T
474
474
474
N/A
N/A
N/A
271
368
mA
XC7K325T
810
810
810
N/A
N/A
N/A
463
629
mA
XC7K355T
993
993
993
N/A
N/A
N/A
568
771
mA
XC7K410T
1080
1080
1080
N/A
N/A
N/A
618
838
mA
XC7K420T
1313
1313
1313
N/A
N/A
N/A
751
1019
mA
XC7K480T
1313
1313
1313
N/A
N/A
N/A
751
1019
mA
XA7K160T
N/A
N/A
N/A
N/A
N/A
474
N/A
N/A
mA
XQ7K325T
N/A
810
810
810
810
N/A
463
629
mA
XQ7K410T
N/A
1080
1080
N/A
1080
N/A
618
838
mA
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 6: Typical Quiescent Supply Current (Cont’d)
Speed Grade
Symbol
Description
Device
1.0V
0.95V
0.9V
Units
-3
-2/-2LE
-1
-1LM
-1M
-1Q
-2LI
-2LE
XC7K70T
1
1
1
N/A
N/A
N/A
N/A
1
mA
XC7K160T
1
1
1
N/A
N/A
N/A
1
1
mA
XC7K325T
1
1
1
N/A
N/A
N/A
1
1
mA
XC7K355T
1
1
1
N/A
N/A
N/A
1
1
mA
XC7K410T
1
1
1
N/A
N/A
N/A
1
1
mA
XC7K420T
1
1
1
N/A
N/A
N/A
1
1
mA
XC7K480T
1
1
1
N/A
N/A
N/A
1
1
mA
XA7K160T
N/A
N/A
N/A
N/A
N/A
1
N/A
N/A
mA
XQ7K325T
N/A
1
1
1
1
N/A
1
1
mA
XQ7K410T
N/A
1
1
N/A
1
N/A
1
1
mA
XC7K70T
21
21
21
N/A
N/A
N/A
N/A
21
mA
XC7K160T
40
40
40
N/A
N/A
N/A
36
40
mA
XC7K325T
68
68
68
N/A
N/A
N/A
61
68
mA
XC7K355T
75
75
75
N/A
N/A
N/A
67
75
mA
XC7K410T
85
85
85
N/A
N/A
N/A
76
85
mA
XC7K420T
99
99
99
N/A
N/A
N/A
89
99
mA
XC7K480T
99
99
99
N/A
N/A
N/A
89
99
mA
XA7K160T
N/A
N/A
N/A
N/A
N/A
40
N/A
N/A
mA
XQ7K325T
N/A
68
68
68
68
N/A
68
68
mA
XQ7K410T
N/A
85
85
N/A
85
N/A
85
85
mA
ICCAUX_IOQ Quiescent VCCAUX_IO XC7K70T
supply current
XC7K160T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
mA
2
2
2
N/A
N/A
N/A
1
2
mA
XC7K325T
2
2
2
N/A
N/A
N/A
1
2
mA
XC7K355T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
mA
XC7K410T
2
2
2
N/A
N/A
N/A
1
2
mA
XC7K420T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
mA
XC7K480T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
mA
XA7K160T
N/A
N/A
N/A
N/A
N/A
2
N/A
N/A
mA
XQ7K325T
N/A
2
2
2
2
N/A
2
2
mA
XQ7K410T
N/A
2
2
N/A
2
N/A
2
2
mA
ICCOQ
ICCAUXQ
Quiescent VCCO
supply current
Quiescent VCCAUX
supply current
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 6: Typical Quiescent Supply Current (Cont’d)
Speed Grade
Symbol
ICCBRAMQ
Description
Quiescent VCCBRAM
supply current
Device
1.0V
0.95V
0.9V
Units
-3
-2/-2LE
-1
-1LM
-1M
-1Q
-2LI
-2LE
XC7K70T
6
6
6
N/A
N/A
N/A
N/A
6
mA
XC7K160T
14
14
14
N/A
N/A
N/A
8
14
mA
XC7K325T
19
19
19
N/A
N/A
N/A
10
19
mA
XC7K355T
31
31
31
N/A
N/A
N/A
17
31
mA
XC7K410T
34
34
34
N/A
N/A
N/A
19
34
mA
XC7K420T
41
41
41
N/A
N/A
N/A
23
41
mA
XC7K480T
41
41
41
N/A
N/A
N/A
23
41
mA
XA7K160T
N/A
N/A
N/A
N/A
N/A
14
N/A
N/A
mA
XQ7K325T
N/A
19
19
19
19
N/A
19
19
mA
XQ7K410T
N/A
34
34
N/A
34
N/A
34
34
mA
Notes:
1.
2.
3.
Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO resources.
Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for
conditions other than those specified.
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw
and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on
sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply
and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be
powered by the same supply and ramped simultaneously.
For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
•
The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
•
The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is VCCINT, VMGTAVCC,
VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT
can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve
minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during powerup and power-down.
•
When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the VMGTAVTT
current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be
up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
•
When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current
draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to
0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
Table 7 shows the minimum current, in addition to ICCQ, that are required by Kintex-7 devices for proper power-on and
configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies
have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power)
to estimate current drain on these supplies.
Table 7: Power-On Current for Kintex-7 Devices
Device
ICCINTMIN
ICCAUXMIN
ICCOMIN
ICCAUX_IOMIN
ICCBRAMMIN
Units
XC7K70T
ICCINTQ + 450
ICCAUXQ + 40
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 40
mA
XC7K160T
ICCINTQ + 550
ICCAUXQ + 50
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 40
mA
XC7K325T
ICCINTQ + 600
ICCAUXQ + 80
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 40
mA
XC7K355T
ICCINTQ + 1450
ICCAUXQ + 109
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 81
mA
XC7K410T
ICCINTQ + 1500
ICCAUXQ + 125
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 90
mA
XC7K420T
ICCINTQ + 2200
ICCAUXQ + 180
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 108
mA
XC7K480T
ICCINTQ + 2200
ICCAUXQ + 180
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 108
mA
XA7K160T
ICCINTQ + 550
ICCAUXQ + 50
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 40
mA
XQ7K325T
ICCINTQ + 600
ICCAUXQ + 80
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 40
mA
XQ7K410T
ICCINTQ + 1500
ICCAUXQ + 125
ICCOQ + 40 mA per bank
ICCOAUXIOQ + 40 mA per bank
ICCBRAMQ + 90
mA
Table 8: Power Supply Ramp Time
Symbol
Description
Conditions
Min
Max
Units
TVCCINT
Ramp time from GND to 90% of VCCINT
0.2
50
ms
TVCCO
Ramp time from GND to 90% of VCCO
0.2
50
ms
TVCCAUX
Ramp time from GND to 90% of VCCAUX
0.2
50
ms
TVCCAUX_IO
Ramp time from GND to 90% of VCCAUX_IO
0.2
50
ms
TVCCBRAM
Ramp time from GND to 90% of VCCBRAM
ms
TVCCO2VCCAUX
Allowed time per power cycle for VCCO – VCCAUX > 2.625V
0.2
50
TJ =
125°C(1)
–
300
TJ =
100°C(1)
–
500
85°C(1)
–
800
TJ =
ms
TMGTAVCC
Ramp time from GND to 90% of VMGTAVCC
0.2
50
ms
TMGTAVTT
Ramp time from GND to 90% of VMGTAVTT
0.2
50
ms
TMGTVCCAUX
Ramp time from GND to 90% of VMGTVCCAUX
0.2
50
ms
Notes:
1.
Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH
voltage levels shown. Other standards are sample tested.
Table 9: SelectIO DC Input and Output Levels (1)(2)
I/O Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Max
V, Min
mA
mA
HSTL_I
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
8
–8
HSTL_I_12
–0.300
VREF – 0.080
VREF + 0.080
VCCO + 0.300
25% VCCO
75% VCCO
6.3
–6.3
HSTL_I_18
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
8
–8
HSTL_II
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
16
–16
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 9: SelectIO DC Input and Output Levels (1)(2) (Cont’d)
I/O Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Max
V, Min
mA
mA
HSTL_II_18
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300
0.400
VCCO – 0.400
16
–16
HSUL_12
–0.300
VREF – 0.130
VREF + 0.130
VCCO + 0.300
20% VCCO
80% VCCO
0.1
–0.1
LVCMOS12
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.400
VCCO – 0.400
Note 3
Note 3
LVCMOS15,
LVDCI_15
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
25% VCCO
75% VCCO
Note 4
Note 4
LVCMOS18,
LVDCI_18
–0.300
35% VCCO
65% VCCO
VCCO + 0.300
0.450
VCCO – 0.450
Note 5
Note 5
LVCMOS25
–0.300
0.700
1.700
VCCO + 0.300
0.400
VCCO – 0.400
Note 6
Note 6
LVCMOS33
–0.300
0.800
2.000
3.450
0.400
VCCO – 0.400
Note 6
Note 6
LVTTL
–0.300
0.800
2.000
3.450
0.400
2.400
Note 7
Note 7
MOBILE_DDR
–0.300
20% VCCO
80% VCCO
VCCO + 0.300
10% VCCO
90% VCCO
0.1
–0.1
PCI33_3
–0.400
30% VCCO
50% VCCO
VCCO + 0.500
10% VCCO
90% VCCO
1.5
–0.5
SSTL12
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150
14.25
–14.25
SSTL135
–0.300
VREF – 0.090
VREF + 0.090
VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150
13.0
–13.0
SSTL135_R
–0.300
VREF – 0.090
VREF + 0.090
VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150
8.9
–8.9
SSTL15
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175
13.0
–13.0
SSTL15_R
–0.300
VREF – 0.100
VREF + 0.100
VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175
8.9
–8.9
SSTL18_I
–0.300
VREF – 0.125
VREF + 0.125
VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470
8
–8
SSTL18_II
–0.300
VREF – 0.125
VREF + 0.125
VCCO + 0.300 VCCO/2 – 0.600 VCCO/2 + 0.600
13.4
–13.4
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Tested according to relevant specifications.
3.3V and 2.5V standards are only supported in HR I/O banks.
Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.
Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.
Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.
Supported drive strengths of 4, 8, 12, or 16 mA
Supported drive strengths of 4, 8, 12, 16, or 24 mA
For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471).
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 10: Differential SelectIO DC Input and Output Levels
I/O Standard
VICM(1)
V, Min V, Typ
BLVDS_25
VID(2)
VOCM(3)
V, Max V, Min V, Typ V, Max
VOD(4)
V, Min
V, Typ
V, Max
V, Min V, Typ V, Max
Note 5
0.300
1.200
1.425
0.100
–
–
–
1.250
–
MINI_LVDS_25 0.300
1.200
VCCAUX
0.200
0.400
0.600
1.000
1.200
1.400
0.300
0.450
0.600
PPDS_25
0.200
0.900
VCCAUX
0.100
0.250
0.400
0.500
0.950
1.400
0.100
0.250
0.400
RSDS_25
0.300
0.900
1.500
0.100
0.350
0.600
1.000
1.200
1.400
0.100
0.350
0.600
TMDS_33
2.700
2.965
3.230
0.150
0.675
1.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.400
0.600
0.800
Notes:
1.
2.
3.
4.
5.
6.
7.
VICM is the input common mode voltage.
VID is the input differential voltage (Q – Q).
VOCM is the output common mode voltage.
VOD is the output differential voltage (Q – Q).
VOD for BLVDS will vary significantly depending on topology and loading.
LVDS_25 is specified in Table 12.
LVDS is specified in Table 13.
Table 11: Complementary Differential SelectIO DC Input and Output Levels
I/O Standard
VICM(1)
VID(2)
VOL(3)
VOH(4)
IOL
IOH
V, Min
V, Typ
V, Max
V, Min
V, Max
V, Max
V, Min
mA, Max
mA, Min
DIFF_HSTL_I
0.300
0.750
1.125
0.100
–
0.400
VCCO–0.400
8.00
–8.00
DIFF_HSTL_I_18
0.300
0.900
1.425
0.100
–
0.400
VCCO–0.400
8.00
–8.00
DIFF_HSTL_II
0.300
0.750
1.125
0.100
–
0.400
VCCO–0.400
16.00
–16.00
DIFF_HSTL_II_18
0.300
0.900
1.425
0.100
–
0.400
VCCO–0.400
16.00
–16.00
DIFF_HSUL_12
0.300
0.600
0.850
0.100
–
20% VCCO
80% VCCO
0.100
–0.100
DIFF_MOBILE_DDR
0.300
0.900
1.425
0.100
–
10% VCCO
90% VCCO
0.100
–0.100
DIFF_SSTL12
0.300
0.600
0.850
0.100
–
(VCCO/2) – 0.150 (VCCO/2) + 0.150
14.25
–14.25
DIFF_SSTL135
0.300
0.675
1.000
0.100
–
(VCCO/2) – 0.150 (VCCO/2) + 0.150
13.0
–13.0
DIFF_SSTL135_R
0.300
0.675
1.000
0.100
–
(VCCO/2) – 0.150 (VCCO/2) + 0.150
8.9
–8.9
DIFF_SSTL15
0.300
0.750
1.125
0.100
–
(VCCO/2) – 0.175 (VCCO/2) + 0.175
13.0
–13.0
DIFF_SSTL15_R
0.300
0.750
1.125
0.100
–
(VCCO/2) – 0.175 (VCCO/2) + 0.175
8.9
–8.9
DIFF_SSTL18_I
0.300
0.900
1.425
0.100
–
(VCCO/2) – 0.470 (VCCO/2) + 0.470
8.00
–8.00
DIFF_SSTL18_II
0.300
0.900
1.425
0.100
–
(VCCO/2) – 0.600 (VCCO/2) + 0.600
13.4
–13.4
Notes:
1.
2.
3.
4.
VICM is the input common mode voltage.
VID is the input differential voltage (Q – Q).
VOL is the single-ended low-output voltage.
VOH is the single-ended high-output voltage.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
LVDS DC Specifications (LVDS_25)
The LVDS_25 standard is available in the HR I/O banks. See the 7 Series FPGAs SelectIO Resources User Guide (UG471) for
more information.
Table 12: LVDS_25 DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
2.375
2.500
2.625
V
VCCO
Supply Voltage
VOH
Output High Voltage for Q and Q
RT = 100 Ω across Q and Q signals
–
–
1.675
V
VOL
Output Low Voltage for Q and Q
RT = 100 Ω across Q and Q signals
0.700
–
–
V
Differential Output Voltage:
(Q – Q), Q = High
(Q – Q), Q = High
RT = 100 Ω across Q and Q signals
247
350
600
mV
VODIFF
VOCM
Output Common-Mode Voltage
RT = 100 Ω across Q and Q signals
1.000
1.250
1.425
V
Differential Input Voltage:
(Q – Q), Q = High
(Q – Q), Q = High
100
350
600
mV
VIDIFF
VICM
Input Common-Mode Voltage
0.300
1.200
1.500
V
Notes:
1.
Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Refer to the
7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.
LVDS DC Specifications (LVDS)
The LVDS standard is available in the HP I/O banks. See the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more
information.
Table 13: LVDS DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
1.710
1.800
1.890
V
VCCO
Supply Voltage
VOH
Output High Voltage for Q and Q
RT = 100 Ω across Q and Q signals
–
–
1.675
V
VOL
Output Low Voltage for Q and Q
RT = 100 Ω across Q and Q signals
0.825
–
–
V
Differential Output Voltage:
(Q – Q), Q = High
(Q – Q), Q = High
RT = 100 Ω across Q and Q signals
247
350
600
mV
VODIFF
VOCM
Output Common-Mode Voltage
RT = 100 Ω across Q and Q signals
1.000
1.250
1.425
V
Differential Input Voltage:
(Q – Q), Q = High
(Q – Q), Q = High
Common-mode input voltage = 1.25V
100
350
600
mV
VIDIFF
VICM
Input Common-Mode Voltage
Differential input voltage = ±350 mV
0.300
1.200
1.425
V
Notes:
1.
Differential inputs for LVDS can be placed in banks with VCCO levels that are different from the required level for outputs. Refer to the 7 Series
FPGAs SelectIO Resources User Guide (UG471) for more information.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite 2015.4 and
ISE® software 14.7 as outlined in Table 14.
Table 14: Kintex-7 FPGA Speed Specification Version By Device
Version In:
Typical VCCINT
Device
ISE 14.7
Vivado
2019.1.1
(Table 2)
1.10
1.12
1.0V
XC7K70T(1), XC7K160T(1), XC7K325T, XC7K355T, XC7K410T, XC7K420T,
XC7K480T
N/A
1.12
0.95V
XC7K160T(1), XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T
1.09
1.09
0.9V
XC7K70T, XC7K160T, XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T
N/A
1.02
1.0V
XA7K160T
1.05
1.09
1.0V
XQ7K325T, XQ7K410T
1.05
1.07
0.9V
XQ7K325T, XQ7K410T
Notes:
1.
GTX data rates greater than 6.6 Gb/s in the FBG484 package in the -3 and -2 speed grades require Vivado Design Suite 2017.1 or later.
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance Product Specification
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting
might still occur.
Preliminary Product Specification
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with
this designation are intended to give a better indication of the expected performance of production silicon. The probability
of under-reporting delays is greatly reduced as compared to Advance data.
Product Specification
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to production before faster speed grades.
Testing of AC Switching Characteristics
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are
representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex-7 FPGAs.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Speed Grade Designations
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device. Table 15 correlates the current status of each Kintex-7
device on a per speed grade basis.
Table 15: Kintex-7 Device Speed Grade Designations
Speed Grade Designations
Device
Advance
Preliminary
Production
XC7K70T
-3, -2, -2LE(1.0V), -1, and -2LE (0.9V)
XC7K160T
-3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K325T
-3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K355T
-3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K410T
-3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K420T
-3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K480T
-3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XA7K160T
-1Q
XQ7K325T
-2I, -2LE(1.0V), -1I, -2LE(0.9V), -2LI (0.95V), -1LM, and -1M
XQ7K410T
-2I, -2LE(1.0V), -1I, -2LE(0.9V), -2LI (0.95V), and -1M
Production Silicon and Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 16 lists the production released Kintex-7 device, speed grade, and the minimum corresponding supported speed
specification version and software revisions. The software and speed specifications listed are the minimum releases required
for production. All subsequent releases of software and speed specifications are valid.
Table 16: Kintex-7 Device Production Software and Speed Specification Release
Speed Grade Designations
Device
1.0V
-3
-2/-2LE
-1
0.95V
0.9V
-1M
-1LM
-1Q
-2LI
-2LE
XC7K70T
Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A
N/A
N/A
N/A
Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K160T
Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A
N/A
N/A
Vivado tools 2014.4
v1.12
Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K325T
Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A
N/A
N/A
Vivado tools 2014.4
v1.12
Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K355T
Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A
N/A
N/A
Vivado tools 2014.4
v1.12
Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K410T
Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A
N/A
N/A
Vivado tools 2014.4
v1.12
Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K420T
Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A
N/A
N/A
Vivado tools 2014.4
v1.12
Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K480T
Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A
N/A
N/A
Vivado tools 2014.4
v1.12
Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XA7K160T
N/A
N/A
N/A
Vivado tools
2019.1.1 v1.02
N/A
N/A
N/A
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13
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 16: Kintex-7 Device Production Software and Speed Specification Release (Cont’d)
Speed Grade Designations
Device
1.0V
-3
-2/-2LE
-1
-1M
0.95V
0.9V
-1LM
-1Q
-2LI
-2LE
XQ7K325T
N/A
Vivado tools 2013.1 v1.04
or ISE tools 14.5 v1.04
Vivado tools
2015.4 v1.09
N/A
Vivado tools 2015.4
v1.07
Vivado tools 2013.1 v1.04
or ISE tools 14.5 v1.04
XQ7K410T
N/A
Vivado tools 2013.1 v1.04
or ISE tools 14.5 v1.04
N/A
N/A
Vivado tools 2015.4
v1.07
Vivado tools 2013.1 v1.04
or ISE tools 14.5 v1.04
Selecting the Correct Speed Grade and Voltage in the Vivado Tools
It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.
To select the 1.0V speed specifications in the Vivado tools, select the Kintex-7, Defense Grade Kintex-7Q, or XA Kintex-7
sub-family, and then select the part name that is the device name followed by the package name followed by the speed
grade. For example, select the xc7k325tffg900-3 part name for the XC7K325T device in the FFG900 package and -3 (1.0V)
speed grade or select the xc7k325tffg900-2L part name for the XC7K325T device in the FFG900 package and -2LE (1.0V)
speed grade.
To select the -2LI (0.95V) speed specifications in the Vivado tools, select the Kintex-7 sub-family and then select the part
name that is the device name followed by an i followed by the package name followed by the speed grade. For example,
select the xc7k325tiffg900-2L part name for the XC7K325T device in the FFG900 package and -2LI (0.95V) speed grade. The
-2LI (0.95V) speed specifications are not supported in the ISE tools.
To select the -2LE (0.9V) speed specifications in the Vivado tools, select the Kintex-7 Low Voltage or Defense Grade
Kintex-7Q Low Voltage sub-family, and then select the part name that is the device name followed by an l followed by the
package name followed by the speed grade. For example, select the xc7k325tlffg900-2L part name for the XC7K325T
device in the FFG900 package and -2LE (0.9V) speed grade.
A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See
Table 16 for the subset of 7 series FPGAs supported in the ISE tools.
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Kintex-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to
the same guidelines as the AC Switching Characteristics, page 12. In each table, the I/O bank type is either High Performance
(HP) or High Range (HR).
Table 17: Networking Applications Interface Performances
Description
I/O
Bank
Type
Speed Grade
1.0V
0.95V
0.9V
-3
-2/-2LE
-1/-1M/-1LM/-1Q
-2LI
-2LE
Units
SDR LVDS transmitter (using OSERDES;
DATA_WIDTH = 4 to 8)
HR
710
710
625
710
625
Mb/s
HP
710
710
625
710
625
Mb/s
DDR LVDS transmitter (using OSERDES;
DATA_WIDTH = 4 to 14)
HR
1250
1250
950
1250
950
Mb/s
HP
1600
1400
1250
1400
1250
Mb/s
HR
710
710
625
710
625
Mb/s
HP
710
710
625
710
625
Mb/s
HR
1250
1250
950
1250
950
Mb/s
HP
1600
1400
1250
1400
1250
Mb/s
SDR LVDS receiver
(SFI-4.1)(1)
DDR LVDS receiver
(SPI-4.2)(1)
Notes:
1.
LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 18 and Table 19 provide the maximum data rates for applicable memory standards using the Kintex-7 FPGAs memory
PHY. The final performance of the memory interface is determined through a complete design implemented in the Vivado
or ISE Design Suite, following guidelines in the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide
(UG586), electrical analysis, and characterization of the system.
Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FF and RF Packages)(1)(2)
Speed Grade
Memory
Standard
I/O Bank
Type
1.0V
VCCAUX_IO
0.95V
0.9V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
Units
4:1 Memory Controllers
DDR3
DDR3L
DDR2
RLDRAM III
HP
2.0V
1866(3)
1866(3)
1600
1066
1600
1333
Mb/s
HP
1.8V
1600
1333
1066
800
1333
1066
Mb/s
HR
N/A
1066
1066
800
800
1066
800
Mb/s
HP
2.0V
1600
1600
1333
1066
1600
1066
Mb/s
HP
1.8V
1333
1066
800
800
1066
800
Mb/s
HR
N/A
800
800
667
N/A
800
667
Mb/s
HP
2.0V
800
800
800
667
800
800
Mb/s
HP
1.8V
800
800
800
667
800
800
Mb/s
HR
N/A
800
800
800
533
800
800
Mb/s
HP
2.0V
800
667
667
550
667
533
MHz
HP
1.8V
550
500
450
400
500
450
MHz
HR
N/A
N/A
2:1 Memory Controllers
DDR3
DDR3L
DDR2
QDR
II+(4)
RLDRAM II
HP
2.0V
1066
1066
800
667
1066
800
Mb/s
HP
1.8V
1066
1066
800
667
1066
800
Mb/s
HR
N/A
1066
1066
800
667
1066
800
Mb/s
HP
2.0V
1066
1066
800
667
1066
800
Mb/s
HP
1.8V
1066
1066
800
667
1066
800
Mb/s
HR
N/A
800
800
667
N/A
800
667
Mb/s
HP
2.0V
HP
1.8V
800
800
Mb/s
HR
N/A
HP
2.0V
HP
1.8V
HR
N/A
HP
2.0V
HP
1.8V
HR
N/A
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667
800
800
800
667
533
550
500
450
300
500
450
MHz
500
450
400
300
450
400
MHz
533
500
450
400
500
450
MHz
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FF and RF Packages)(1)(2) (Cont’d)
Speed Grade
Memory
Standard
LPDDR2
I/O Bank
Type
VCCAUX_IO
1.0V
0.95V
0.9V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
Units
HP
2.0V
667
667
667
533
667
667
Mb/s
HP
1.8V
667
667
667
533
667
667
Mb/s
HR
N/A
667
667
667
533
667
667
Mb/s
Notes:
1.
2.
3.
4.
VREF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide
(UG586).
When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
For designs using 1866 Mb/s components, contact Xilinx Technical Support.
The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
Table 19: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FB Packages)(1)(2)
Speed Grade
Memory
Standard
I/O Bank
Type
VCCAUX_IO(3)
1.0V
0.95V
0.9V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
Units
4:1 Memory Controllers
DDR3
DDR3L
DDR2
RLDRAM III
HP
N/A
1333
1066
800
800
1066
800
Mb/s
HR
N/A
1066
800
800
800
800
800
Mb/s
HP
N/A
1066
800
667
667
800
667
Mb/s
HR
N/A
800
800
667
N/A
800
667
Mb/s
HP
N/A
800
800
800
667
800
800
Mb/s
HR
N/A
800
667
667
533
667
667
Mb/s
HP
N/A
550
500
450
350
500
450
MHz
HR
N/A
N/A
2:1 Memory Controllers
DDR3
DDR3L
DDR2
QDR II+(4)
RLDRAM II
HP
N/A
1066
1066
800
667
1066
800
Mb/s
HR
N/A
1066
800
800
667
800
800
Mb/s
HP
N/A
1066
800
667
667
800
667
Mb/s
HR
N/A
800
800
667
N/A
800
667
Mb/s
HP
N/A
800
800
800
667
800
800
Mb/s
HR
N/A
800
667
667
533
667
667
Mb/s
HP
N/A
550
500
450
300
500
450
MHz
HR
N/A
450
400
350
300
400
350
MHz
HP
N/A
HR
N/A
533
500
450
400
500
450
MHz
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 19: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FB Packages)(1)(2) (Cont’d)
Speed Grade
Memory
Standard
LPDDR2
I/O Bank
Type
VCCAUX_IO
(3)
1.0V
0.95V
0.9V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
Units
HP
N/A
667
667
667
400
667
667
Mb/s
HR
N/A
667
667
533
400
667
533
Mb/s
Notes:
1.
2.
3.
4.
VREF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide
(UG586).
When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
FB packages do not have separate VCCAUX_IO supply pins to adjust the pre-driver voltage of the HP I/O banks.
The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
IOB Pad Input/Output/3-State
Table 20 (high-range IOB (HR)) and Table 21 (high-performance IOB (HP)) summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
•
TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
•
TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
•
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI
termination turn-on time is always faster than TIOTP when the DCITERMDISABLE pin is used. In HR I/O banks, the
IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
Table 20: IOB High Range (HR) Switching Characteristics
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
I/O Standard
-3
-2/
-2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI
-2LE
-1Q
LVTTL_S4
1.31 1.42 1.64 1.64
1.42
1.51 3.77 3.90 4.00 4.00
3.90
4.13 3.52 3.67 3.86
3.86
3.67
3.85
ns
LVTTL_S8
1.31 1.42 1.64 1.64
1.42
1.51 3.50 3.64 3.73 3.73
3.64
3.86 3.26 3.40 3.60
3.60
3.40
3.58
ns
LVTTL_S12
1.31 1.42 1.64 1.64
1.42
1.51 3.49 3.62 3.72 3.72
3.62
3.84 3.24 3.39 3.58
3.58
3.39
3.56
ns
LVTTL_S16
1.31 1.42 1.64 1.64
1.42
1.51 3.03 3.17 3.26 3.26
3.17
3.39 2.79 2.93 3.13
3.13
2.93
3.11
ns
LVTTL_S24
1.31 1.42 1.64 1.64
1.42
1.51 3.25 3.39 3.48 3.48
3.39
3.61 3.01 3.15 3.35
3.35
3.15
3.33
ns
LVTTL_F4
1.31 1.42 1.64 1.64
1.42
1.51 3.22 3.36 3.45 3.45
3.36
3.58 2.98 3.12 3.32
3.32
3.12
3.30
ns
LVTTL_F8
1.31 1.42 1.64 1.64
1.42
1.51 2.71 2.84 2.93 2.93
2.84
3.06 2.46 2.61 2.80
2.80
2.61
2.78
ns
LVTTL_F12
1.31 1.42 1.64 1.64
1.42
1.51 2.69 2.82 2.92 2.92
2.82
3.05 2.44 2.59 2.79
2.79
2.59
2.77
ns
LVTTL_F16
1.31 1.42 1.64 1.64
1.42
1.51 2.57 2.85 3.15 3.15
2.85
2.88 2.33 2.61 3.02
3.02
2.61
2.60
ns
LVTTL_F24
1.31 1.42 1.64 1.64
1.42
1.51 2.41 2.64 2.89 3.04
2.64
2.94 2.16 2.41 2.76
2.91
2.41
2.66
ns
LVDS_25
0.64 0.68 0.80 0.87
0.68
0.83 1.36 1.47 1.55 1.55
1.47
1.58 1.11 1.24 1.41
1.41
1.24
1.30
ns
MINI_LVDS_25
0.68 0.70 0.79 0.87
0.70
0.83 1.36 1.47 1.55 1.55
1.47
1.59 1.11 1.24 1.41
1.41
1.24
1.31
ns
BLVDS_25
0.65 0.69 0.80 0.85
0.69
0.83 1.83 2.02 2.20 2.57
2.02
2.16 1.59 1.79 2.07
2.44
1.79
1.88
ns
RSDS_25
(point to point)
0.63 0.68 0.79 0.87
0.68
0.83 1.36 1.48 1.55 1.55
1.48
1.59 1.11 1.24 1.41
1.41
1.24
1.31
ns
PPDS_25
0.65 0.69 0.80 0.87
0.69
0.83 1.36 1.49 1.58 1.58
1.49
1.59 1.11 1.25 1.45
1.45
1.25
1.31
ns
TMDS_33
0.72 0.76 0.86 0.90
0.76
0.83 1.43 1.54 1.60 1.60
1.54
1.70 1.18 1.31 1.47
1.47
1.31
1.42
ns
PCI33_3
1.28 1.41 1.65 1.65
1.41
1.50 2.71 3.08 3.52 3.52
3.08
3.42 2.46 2.84 3.39
3.39
2.84
3.14
ns
HSUL_12_S
0.63 0.64 0.71 0.85
0.64
0.79 1.77 1.90 2.00 2.00
1.90
2.13 1.52 1.67 1.86
1.86
1.67
1.85
ns
HSUL_12_F
0.63 0.64 0.71 0.85
0.64
0.79 1.26 1.40 1.50 1.50
1.40
1.61 1.01 1.16 1.37
1.37
1.16
1.33
ns
DIFF_HSUL_
12_S
0.58 0.61 0.70 0.84
0.61
0.81 1.55 1.68 1.78 1.78
1.68
1.92 1.30 1.45 1.65
1.65
1.45
1.64
ns
DIFF_HSUL_
12_F
0.58 0.61 0.70 0.84
0.61
0.81 1.16 1.28 1.35 1.35
1.28
1.50 0.92 1.04 1.21
1.21
1.04
1.22
ns
MOBILE_DDR_S 0.64 0.66 0.74 0.74
0.66
0.89 2.58 2.91 3.31 3.31
2.91
1.95 2.33 2.68 3.17
3.17
2.68
1.67
ns
MOBILE_DDR_F 0.64 0.66 0.74 0.74
0.66
0.89 1.91 2.13 2.36 2.36
2.13
1.69 1.66 1.89 2.23
2.23
1.89
1.41
ns
DIFF_MOBILE_
DDR_S
0.66
0.79 2.51 2.84 3.24 3.24
2.84
1.95 2.26 2.61 3.10
3.10
2.61
1.67
ns
0.63 0.66 0.75 0.75
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 20: IOB High Range (HR) Switching Characteristics (Cont’d)
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
I/O Standard
-3
-2/
-2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI
-2LE
-1Q
DIFF_MOBILE_
DDR_F
0.63 0.66 0.75 0.75
0.66
0.79 1.89 2.11 2.34 2.34
2.11
1.72 1.64 1.88 2.21
2.21
1.88
1.44
ns
HSTL_I_S
0.61 0.64 0.73 0.84
0.64
0.79 1.55 1.69 1.80 1.80
1.69
1.91 1.30 1.46 1.67
1.67
1.46
1.63
ns
HSTL_II_S
0.61 0.64 0.73 0.84
0.64
0.78 1.21 1.34 1.43 1.61
1.34
1.70 0.96 1.11 1.30
1.47
1.11
1.42
ns
HSTL_I_18_S
0.64 0.67 0.76 0.85
0.67
0.79 1.28 1.39 1.45 1.45
1.39
1.58 1.04 1.16 1.31
1.32
1.16
1.30
ns
HSTL_II_18_S
0.64 0.67 0.76 0.85
0.67
0.79 1.18 1.31 1.40 1.57
1.31
1.69 0.93 1.08 1.27
1.44
1.08
1.41
ns
DIFF_HSTL_I_S
0.63 0.67 0.77 0.84
0.67
0.78 1.42 1.54 1.61 1.78
1.54
1.84 1.17 1.31 1.48
1.65
1.31
1.56
ns
DIFF_HSTL_II_S 0.63 0.67 0.77 0.84
0.67
0.79 1.15 1.24 1.27 1.61
1.24
1.78 0.91 1.01 1.14
1.47
1.01
1.50
ns
DIFF_HSTL_I_
18_S
0.65 0.69 0.78 0.84
0.69
0.79 1.27 1.38 1.43 1.45
1.38
1.67 1.03 1.14 1.30
1.32
1.14
1.39
ns
DIFF_HSTL_II_
18_S
0.65 0.69 0.78 0.85
0.69
0.81 1.14 1.23 1.26 1.57
1.23
1.72 0.90 1.00 1.13
1.44
1.00
1.44
ns
HSTL_I_F
0.61 0.64 0.73 0.84
0.64
0.79 1.10 1.19 1.23 1.31
1.19
1.41 0.85 0.96 1.10
1.18
0.96
1.13
ns
HSTL_II_F
0.61 0.64 0.73 0.84
0.64
0.78 1.05 1.18 1.28 1.31
1.18
1.42 0.80 0.95 1.15
1.18
0.95
1.14
ns
HSTL_I_18_F
0.64 0.67 0.76 0.85
0.67
0.79 1.05 1.18 1.28 1.36
1.18
1.44 0.80 0.95 1.15
1.22
0.95
1.16
ns
HSTL_II_18_F
0.64 0.67 0.76 0.85
0.67
0.79 1.03 1.14 1.23 1.32
1.14
1.42 0.78 0.90 1.10
1.19
0.90
1.14
ns
DIFF_HSTL_I_F
0.63 0.67 0.77 0.84
0.67
0.78 1.09 1.18 1.22 1.31
1.18
1.48 0.84 0.95 1.09
1.18
0.95
1.20
ns
DIFF_HSTL_II_F 0.63 0.67 0.77 0.84
0.67
0.79 1.02 1.11 1.14 1.31
1.11
1.48 0.77 0.88 1.01
1.18
0.88
1.20
ns
DIFF_HSTL_I_
18_F
0.65 0.69 0.78 0.84
0.69
0.79 1.08 1.17 1.21 1.36
1.17
1.48 0.83 0.94 1.07
1.22
0.94
1.20
ns
DIFF_HSTL_II_
18_F
0.65 0.69 0.78 0.85
0.69
0.81 1.01 1.10 1.13 1.32
1.10
1.48 0.76 0.87 1.00
1.19
0.87
1.20
ns
LVCMOS33_S4
1.31 1.40 1.60 1.60
1.40
1.54 3.77 3.90 4.00 4.00
3.90
4.13 3.52 3.67 3.86
3.86
3.67
3.85
ns
LVCMOS33_S8
1.31 1.40 1.60 1.60
1.40
1.54 3.49 3.62 3.72 3.72
3.62
3.84 3.24 3.39 3.58
3.58
3.39
3.56
ns
LVCMOS33_S12 1.31 1.40 1.60 1.60
1.40
1.54 3.05 3.18 3.28 3.28
3.18
3.41 2.80 2.95 3.15
3.15
2.95
3.13
ns
LVCMOS33_S16 1.31 1.40 1.60 1.60
1.40
1.54 3.06 3.43 3.88 3.88
3.43
3.72 2.81 3.20 3.75
3.75
3.20
3.44
ns
LVCMOS33_F4
1.31 1.40 1.60 1.60
1.40
1.54 3.22 3.36 3.45 3.45
3.36
3.58 2.98 3.12 3.32
3.32
3.12
3.30
ns
LVCMOS33_F8
1.31 1.40 1.60 1.60
1.40
1.54 2.71 2.84 2.93 2.93
2.84
3.06 2.46 2.61 2.80
2.80
2.61
2.78
ns
LVCMOS33_F12 1.31 1.40 1.60 1.60
1.40
1.54 2.57 2.85 3.15 3.15
2.85
2.88 2.33 2.61 3.02
3.02
2.61
2.60
ns
LVCMOS33_F16 1.31 1.40 1.60 1.60
1.40
1.54 2.44 2.69 2.96 2.96
2.69
2.88 2.19 2.45 2.82
2.82
2.45
2.60
ns
LVCMOS25_S4
1.08 1.16 1.32 1.35
1.16
1.36 3.08 3.22 3.31 3.31
3.22
3.44 2.84 2.98 3.18
3.18
2.98
3.16
ns
LVCMOS25_S8
1.08 1.16 1.32 1.35
1.16
1.36 2.85 2.98 3.07 3.08
2.98
3.20 2.60 2.75 2.94
2.94
2.75
2.92
ns
LVCMOS25_S12 1.08 1.16 1.32 1.35
1.16
1.36 2.44 2.57 2.67 2.67
2.57
2.80 2.19 2.34 2.54
2.54
2.34
2.52
ns
LVCMOS25_S16 1.08 1.16 1.32 1.35
1.16
1.36 2.79 2.92 3.01 3.01
2.92
3.14 2.54 2.68 2.88
2.88
2.68
2.86
ns
LVCMOS25_F4
1.08 1.16 1.32 1.35
1.16
1.36 2.71 2.84 2.93 2.93
2.84
3.06 2.46 2.61 2.80
2.80
2.61
2.78
ns
LVCMOS25_F8
1.08 1.16 1.32 1.35
1.16
1.36 2.14 2.28 2.37 2.37
2.28
2.50 1.90 2.04 2.24
2.24
2.04
2.22
ns
LVCMOS25_F12 1.08 1.16 1.32 1.35
1.16
1.36 2.15 2.29 2.52 2.52
2.29
2.48 1.91 2.05 2.38
2.38
2.05
2.20
ns
LVCMOS25_F16 1.08 1.16 1.32 1.35
1.16
1.36 1.92 2.17 2.45 2.45
2.17
2.33 1.67 1.94 2.32
2.32
1.94
2.05
ns
LVCMOS18_S4
0.64 0.66 0.74 0.95
0.66
0.87 1.55 1.68 1.78 1.78
1.68
1.91 1.30 1.45 1.65
1.65
1.45
1.63
ns
LVCMOS18_S8
0.64 0.66 0.74 0.95
0.66
0.87 2.14 2.28 2.37 2.37
2.28
2.50 1.90 2.04 2.24
2.24
2.04
2.22
ns
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19
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 20: IOB High Range (HR) Switching Characteristics (Cont’d)
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
I/O Standard
-3
-2/
-2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI
-2LE
-1Q
LVCMOS18_S12 0.64 0.66 0.74 0.95
0.66
0.87 2.14 2.28 2.37 2.37
2.28
2.50 1.90 2.04 2.24
2.24
2.04
2.22
ns
LVCMOS18_S16 0.64 0.66 0.74 0.95
0.66
0.87 1.49 1.62 1.72 1.72
1.62
1.84 1.24 1.39 1.58
1.58
1.39
1.56
ns
LVCMOS18_S24 0.64 0.66 0.74 0.95
0.66
0.87 1.74 1.92 2.08 2.22
1.92
1.92 1.50 1.69 1.95
2.08
1.69
1.64
ns
LVCMOS18_F4
0.64 0.66 0.74 0.95
0.66
0.87 1.38 1.51 1.61 1.64
1.51
1.77 1.13 1.28 1.47
1.50
1.28
1.49
ns
LVCMOS18_F8
0.64 0.66 0.74 0.95
0.66
0.87 1.64 1.78 1.87 1.87
1.78
2.00 1.40 1.54 1.74
1.74
1.54
1.72
ns
LVCMOS18_F12 0.64 0.66 0.74 0.95
0.66
0.87 1.64 1.78 1.87 1.87
1.78
2.00 1.40 1.54 1.74
1.74
1.54
1.72
ns
LVCMOS18_F16 0.64 0.66 0.74 0.95
0.66
0.87 1.52 1.68 1.81 1.81
1.68
1.72 1.28 1.45 1.68
1.68
1.45
1.44
ns
LVCMOS18_F24 0.64 0.66 0.74 0.95
0.66
0.87 1.34 1.46 1.55 2.09
1.46
1.66 1.09 1.23 1.42
1.96
1.23
1.38
ns
LVCMOS15_S4
0.66 0.69 0.81 0.93
0.69
0.90 1.86 2.00 2.09 2.09
2.00
2.22 1.62 1.76 1.96
1.96
1.76
1.94
ns
LVCMOS15_S8
0.66 0.69 0.81 0.93
0.69
0.90 2.05 2.18 2.28 2.28
2.18
2.41 1.80 1.95 2.14
2.15
1.95
2.13
ns
LVCMOS15_S12 0.66 0.69 0.81 0.93
0.69
0.90 1.83 2.03 2.23 2.23
2.03
1.91 1.59 1.80 2.10
2.10
1.80
1.63
ns
LVCMOS15_S16 0.66 0.69 0.81 0.93
0.69
0.90 1.76 1.95 2.13 2.13
1.95
1.91 1.52 1.72 1.99
1.99
1.72
1.63
ns
LVCMOS15_F4
0.66 0.69 0.81 0.93
0.69
0.90 1.63 1.76 1.86 1.86
1.76
1.98 1.38 1.53 1.72
1.72
1.53
1.70
ns
LVCMOS15_F8
0.66 0.69 0.81 0.93
0.69
0.90 1.79 1.99 2.18 2.18
1.99
1.92 1.55 1.76 2.05
2.05
1.76
1.64
ns
LVCMOS15_F12 0.66 0.69 0.81 0.93
0.69
0.90 1.40 1.54 1.65 1.65
1.54
1.67 1.15 1.31 1.52
1.52
1.31
1.39
ns
LVCMOS15_F16 0.66 0.69 0.81 0.93
0.69
0.90 1.37 1.51 1.61 1.89
1.51
1.66 1.13 1.27 1.48
1.75
1.27
1.38
ns
LVCMOS12_S4
0.88 0.91 1.00 1.17
0.91
1.01 2.53 2.67 2.76 2.76
2.67
2.89 2.29 2.43 2.63
2.63
2.43
2.61
ns
LVCMOS12_S8
0.88 0.91 1.00 1.17
0.91
1.01 2.05 2.18 2.28 2.28
2.18
2.41 1.80 1.95 2.14
2.15
1.95
2.13
ns
LVCMOS12_S12 0.88 0.91 1.00 1.17
0.91
1.01 1.75 1.89 1.98 1.98
1.89
2.11 1.51 1.65 1.85
1.85
1.65
1.83
ns
LVCMOS12_F4
0.88 0.91 1.00 1.17
0.91
1.01 1.94 2.07 2.17 2.17
2.07
2.30 1.69 1.84 2.04
2.04
1.84
2.02
ns
LVCMOS12_F8
0.88 0.91 1.00 1.17
0.91
1.01 1.50 1.64 1.73 1.73
1.64
1.86 1.26 1.40 1.60
1.60
1.40
1.58
ns
LVCMOS12_F12 0.88 0.91 1.00 1.17
0.91
1.01 1.54 1.71 1.87 1.87
1.71
1.69 1.29 1.48 1.74
1.74
1.48
1.41
ns
SSTL135_S
0.61 0.64 0.73 0.85
0.64
0.79 1.27 1.40 1.50 1.53
1.40
1.64 1.02 1.17 1.36
1.40
1.17
1.36
ns
SSTL15_S
0.61 0.64 0.73 0.73
0.64
0.73 1.24 1.37 1.47 1.53
1.37
1.59 0.99 1.14 1.33
1.40
1.14
1.31
ns
SSTL18_I_S
0.64 0.67 0.76 0.84
0.67
0.79 1.59 1.74 1.85 1.85
1.74
1.95 1.34 1.50 1.72
1.72
1.50
1.67
ns
SSTL18_II_S
0.64 0.67 0.76 0.85
0.67
0.78 1.27 1.40 1.50 1.50
1.40
1.63 1.02 1.17 1.36
1.36
1.17
1.35
ns
DIFF_SSTL135_
0.59 0.61 0.73 0.85
S
0.61
0.79 1.27 1.40 1.50 1.53
1.40
1.64 1.02 1.17 1.36
1.40
1.17
1.36
ns
DIFF_SSTL15_S 0.63 0.67 0.77 0.85
0.67
0.79 1.24 1.37 1.47 1.53
1.37
1.59 0.99 1.14 1.33
1.40
1.14
1.31
ns
DIFF_SSTL18_
I_S
0.65 0.69 0.78 0.85
0.69
0.79 1.50 1.63 1.72 1.82
1.63
1.95 1.26 1.40 1.59
1.69
1.40
1.67
ns
DIFF_SSTL18_
II_S
0.65 0.69 0.78 0.85
0.69
0.79 1.13 1.22 1.25 1.50
1.22
1.66 0.88 0.99 1.12
1.36
0.99
1.38
ns
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20
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 20: IOB High Range (HR) Switching Characteristics (Cont’d)
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
I/O Standard
-3
-2/
-2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI
-2LE
-1Q
SSTL135_F
0.61 0.64 0.73 0.85
0.64
0.79 1.04 1.17 1.26 1.31
1.17
1.42 0.79 0.93 1.13
1.18
0.93
1.14
ns
SSTL15_F
0.61 0.64 0.73 0.73
0.64
0.73 1.04 1.17 1.26 1.26
1.17
1.39 0.79 0.93 1.13
1.13
0.93
1.11
ns
SSTL18_I_F
0.64 0.67 0.76 0.84
0.67
0.79 1.12 1.22 1.26 1.34
1.22
1.44 0.88 0.99 1.13
1.21
0.99
1.16
ns
SSTL18_II_F
0.64 0.67 0.76 0.85
0.67
0.78 1.05 1.18 1.28 1.32
1.18
1.42 0.80 0.95 1.15
1.19
0.95
1.14
ns
DIFF_SSTL135_
0.59 0.61 0.73 0.85
F
0.61
0.79 1.04 1.17 1.26 1.31
1.17
1.42 0.79 0.93 1.13
1.18
0.93
1.14
DIFF_SSTL15_F 0.63 0.67 0.77 0.85
0.67
0.79 1.04 1.17 1.26 1.26
1.17
1.39 0.79 0.93 1.13
1.13
0.93
1.11
DIFF_SSTL18_I_
0.65 0.69 0.78 0.85
F
0.69
0.79 1.10 1.19 1.23 1.34
1.19
1.52 0.85 0.96 1.10
1.21
0.96
1.24
DIFF_SSTL18_II
0.65 0.69 0.78 0.85
_F
0.69
0.79 1.02 1.10 1.14 1.32
1.10
1.50 0.77 0.87 1.00
1.19
0.87
1.22
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ns
ns
ns
ns
21
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 21: IOB High Performance (HP) Switching Characteristics
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
0.95V 0.9V
-2/ -1 -1M/
-3 -2LE
-1LM/ -2LI -2LE
-1Q
1.0V
-2/
-3 -2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI -2LE
-1Q
LVDS
0.75 0.79 0.92 0.96
0.79
0.89 1.05 1.17 1.24 1.26
1.17
1.43 0.88 1.01 1.08 1.10
1.01
1.32
ns
HSUL_12_S
0.69 0.72 0.82 0.98
0.72
0.95 1.65 1.84 2.05 2.05
1.84
1.80 1.48 1.68 1.89 1.89
1.68
1.70
ns
HSUL_12_F
0.69 0.72 0.82 0.98
0.72
0.95 1.39 1.54 1.68 1.68
1.54
1.49 1.22 1.38 1.52 1.52
1.38
1.39
ns
DIFF_HSUL_12_
S
0.69 0.72 0.82 0.98
0.72
0.92 1.65 1.84 2.05 2.05
1.84
1.47 1.48 1.68 1.89 1.89
1.68
1.37
ns
DIFF_HSUL_12_F 0.69 0.72 0.82 0.98
0.72
0.92 1.39 1.54 1.68 1.68
1.54
1.35 1.22 1.38 1.52 1.52
1.38
1.24
ns
DIFF_HSUL_12_
DCI_S
0.69 0.72 0.82 0.82
0.72
0.92 1.78 1.91 2.05 2.05
1.91
1.46 1.61 1.76 1.89 1.89
1.76
1.35
ns
DIFF_HSUL_12_
DCI_F
0.69 0.72 0.82 0.82
0.72
0.92 1.56 1.67 1.76 1.76
1.67
1.35 1.39 1.51 1.60 1.60
1.51
1.24
ns
HSTL_I_S
0.68 0.72 0.82 0.90
0.72
0.84 1.15 1.28 1.38 1.38
1.28
1.46 0.98 1.12 1.22 1.22
1.12
1.35
ns
HSTL_II_S
0.68 0.72 0.82 0.90
0.72
0.84 1.05 1.17 1.26 1.27
1.17
1.44 0.88 1.01 1.10 1.11
1.01
1.34
ns
HSTL_I_18_S
0.70 0.72 0.82 0.95
0.72
0.86 1.12 1.24 1.34 1.34
1.24
1.41 0.95 1.08 1.18 1.18
1.08
1.31
ns
HSTL_II_18_S
0.70 0.72 0.82 0.90
0.72
0.86 1.06 1.18 1.26 1.27
1.18
1.44 0.89 1.02 1.10 1.11
1.02
1.34
ns
HSTL_I_12_S
0.68 0.72 0.82 0.96
0.72
0.94 1.14 1.27 1.37 1.37
1.27
1.43 0.97 1.11 1.21 1.21
1.11
1.32
ns
HSTL_I_DCI_S
0.68 0.72 0.82 0.90
0.72
0.78 1.11 1.23 1.33 1.33
1.23
1.36 0.94 1.07 1.17 1.17
1.07
1.26
ns
HSTL_II_DCI_S
0.68 0.72 0.82 0.85
0.72
0.78 1.05 1.17 1.26 1.26
1.17
1.33 0.88 1.01 1.10 1.10
1.01
1.23
ns
HSTL_II_T_DCI_
S
0.70 0.72 0.82 0.82
0.72
0.76 1.15 1.28 1.38 1.38
1.28
1.40 0.98 1.12 1.22 1.22
1.12
1.29
ns
HSTL_I_DCI_18_
0.70 0.72 0.82 0.90
S
0.72
0.76 1.11 1.23 1.33 1.33
1.23
1.36 0.94 1.07 1.17 1.17
1.07
1.26
ns
HSTL_II_DCI_18_
0.70 0.72 0.82 0.82
S
0.72
0.76 1.05 1.16 1.24 1.24
1.16
1.32 0.88 1.00 1.08 1.08
1.00
1.21
ns
HSTL_II
_T_DCI_18_S
0.70 0.72 0.82 0.84
0.72
0.76 1.11 1.23 1.33 1.34
1.23
1.36 0.94 1.07 1.17 1.18
1.07
1.26
ns
DIFF_HSTL_I_S
0.75 0.79 0.92 1.02
0.79
0.89 1.15 1.28 1.38 1.38
1.28
1.47 0.98 1.12 1.22 1.22
1.12
1.37
ns
DIFF_HSTL_II_S
0.75 0.79 0.92 1.02
0.79
0.89 1.05 1.17 1.26 1.32
1.17
1.47 0.88 1.01 1.10 1.16
1.01
1.37
ns
DIFF_HSTL_I_
DCI_S
0.75 0.79 0.92 0.92
0.79
0.76 1.15 1.28 1.38 1.38
1.28
1.47 0.98 1.12 1.22 1.22
1.12
1.37
ns
DIFF_HSTL_II_
DCI_S
0.75 0.79 0.92 0.92
0.79
0.76 1.05 1.17 1.26 1.26
1.17
1.40 0.88 1.01 1.10 1.10
1.01
1.29
ns
DIFF_HSTL_I_
18_S
0.75 0.79 0.92 0.98
0.79
0.89 1.12 1.24 1.34 1.34
1.24
1.46 0.95 1.08 1.18 1.18
1.08
1.35
ns
DIFF_HSTL_II_
18_S
0.75 0.79 0.92 0.99
0.79
0.89 1.06 1.18 1.26 1.32
1.18
1.47 0.89 1.02 1.10 1.16
1.02
1.37
ns
DIFF_HSTL_I_
DCI_18_S
0.75 0.79 0.92 0.92
0.79
0.75 1.11 1.23 1.33 1.33
1.23
1.46 0.94 1.07 1.17 1.17
1.07
1.35
ns
DIFF_HSTL_II_
DCI_18_S
0.75 0.79 0.92 0.93
0.79
0.75 1.05 1.16 1.24 1.26
1.16
1.41 0.88 1.00 1.08 1.10
1.00
1.31
ns
DIFF_HSTL_II
_T_DCI_18_S
0.75 0.79 0.92 0.92
0.79
0.76 1.11 1.23 1.33 1.33
1.23
1.46 0.94 1.07 1.17 1.17
1.07
1.35
ns
HSTL_I_F
0.68 0.72 0.82 0.90
0.72
0.84 1.02 1.14 1.22 1.22
1.14
1.26 0.85 0.98 1.06 1.06
0.98
1.15
ns
HSTL_II_F
0.68 0.72 0.82 0.90
0.72
0.84 0.97 1.08 1.15 1.15
1.08
1.29 0.80 0.92 0.99 0.99
0.92
1.18
ns
HSTL_I_18_F
0.70 0.72 0.82 0.95
0.72
0.86 1.04 1.16 1.24 1.24
1.16
1.32 0.87 1.00 1.08 1.08
1.00
1.21
ns
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22
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
0.95V 0.9V
-1M/
-2/ -1 -1LM/
-2LI -2LE
-3 -2LE
-1Q
1.0V
-2/
-3 -2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI -2LE
-1Q
HSTL_II_18_F
0.70 0.72 0.82 0.90
0.72
0.86 0.98 1.09 1.16 1.20
1.09
1.35 0.81 0.94 1.00 1.03
0.94
1.24
ns
HSTL_I_12_F
0.68 0.72 0.82 0.96
0.72
0.94 1.02 1.13 1.21 1.21
1.13
1.26 0.85 0.97 1.05 1.05
0.97
1.15
ns
HSTL_I_DCI_F
0.68 0.72 0.82 0.90
0.72
0.78 1.04 1.16 1.24 1.24
1.16
1.30 0.87 1.00 1.08 1.08
1.00
1.20
ns
HSTL_II_DCI_F
0.68 0.72 0.82 0.85
0.72
0.78 0.97 1.08 1.15 1.15
1.08
1.22 0.80 0.92 0.99 0.99
0.92
1.12
ns
HSTL_II_T_DCI_F 0.70 0.72 0.82 0.82
0.72
0.76 1.02 1.14 1.22 1.22
1.14
1.26 0.85 0.98 1.06 1.06
0.98
1.15
ns
HSTL_I_DCI_
18_F
0.70 0.72 0.82 0.90
0.72
0.76 1.04 1.16 1.24 1.24
1.16
1.30 0.87 1.00 1.08 1.08
1.00
1.20
ns
HSTL_II_DCI_
18_F
0.70 0.72 0.82 0.82
0.72
0.76 0.98 1.09 1.16 1.16
1.09
1.27 0.81 0.93 1.00 1.00
0.93
1.17
ns
HSTL_II
_T_DCI_18_F
0.70 0.72 0.82 0.84
0.72
0.76 1.04 1.16 1.24 1.24
1.16
1.30 0.87 1.00 1.08 1.08
1.00
1.20
ns
DIFF_HSTL_I_F
0.75 0.79 0.92 1.02
0.79
0.89 1.02 1.14 1.22 1.22
1.14
1.35 0.85 0.98 1.06 1.06
0.98
1.24
ns
DIFF_HSTL_II_F
0.75 0.79 0.92 1.02
0.79
0.89 0.97 1.08 1.15 1.20
1.08
1.35 0.80 0.92 0.99 1.03
0.92
1.24
ns
DIFF_HSTL_I_
DCI_F
0.75 0.79 0.92 0.92
0.79
0.76 1.02 1.14 1.22 1.22
1.14
1.35 0.85 0.98 1.06 1.06
0.98
1.24
ns
DIFF_HSTL_II_
DCI_F
0.75 0.79 0.92 0.92
0.79
0.76 0.97 1.08 1.15 1.15
1.08
1.30 0.80 0.92 0.99 0.99
0.92
1.20
ns
DIFF_HSTL_I_
18_F
0.75 0.79 0.92 0.98
0.79
0.89 1.04 1.16 1.24 1.24
1.16
1.38 0.87 1.00 1.08 1.08
1.00
1.28
ns
DIFF_HSTL_II_
18_F
0.75 0.79 0.92 0.99
0.79
0.89 0.98 1.09 1.16 1.24
1.09
1.40 0.81 0.94 1.00 1.08
0.94
1.29
ns
DIFF_HSTL_I_
DCI_18_F
0.75 0.79 0.92 0.92
0.79
0.75 1.04 1.16 1.24 1.24
1.16
1.38 0.87 1.00 1.08 1.08
1.00
1.28
ns
DIFF_HSTL_II_
DCI_18_F
0.75 0.79 0.92 0.93
0.79
0.75 0.98 1.09 1.16 1.18
1.09
1.33 0.81 0.93 1.00 1.02
0.93
1.23
ns
DIFF_HSTL_II
_T_DCI_18_F
0.75 0.79 0.92 0.92
0.79
0.76 1.04 1.16 1.24 1.24
1.16
1.38 0.87 1.00 1.08 1.08
1.00
1.28
ns
LVCMOS18_S2
0.47 0.50 0.60 0.90
0.50
0.87 3.95 4.28 4.85 4.85
4.28
3.40 3.78 4.13 4.69 4.69
4.13
3.29
ns
LVCMOS18_S4
0.47 0.50 0.60 0.90
0.50
0.87 2.67 2.98 3.43 3.43
2.98
2.69 2.50 2.82 3.27 3.27
2.82
2.59
ns
LVCMOS18_S6
0.47 0.50 0.60 0.90
0.50
0.87 2.14 2.38 2.72 2.72
2.38
2.18 1.97 2.22 2.56 2.56
2.22
2.07
ns
LVCMOS18_S8
0.47 0.50 0.60 0.90
0.50
0.87 1.98 2.21 2.52 2.52
2.21
2.02 1.81 2.05 2.36 2.36
2.05
1.92
ns
LVCMOS18_S12
0.47 0.50 0.60 0.90
0.50
0.87 1.70 1.91 2.17 2.17
1.91
1.85 1.53 1.75 2.01 2.01
1.75
1.74
ns
LVCMOS18_S16
0.47 0.50 0.60 0.90
0.50
0.87 1.57 1.75 1.97 1.97
1.75
1.76 1.40 1.59 1.81 1.81
1.59
1.65
ns
LVCMOS18_F2
0.47 0.50 0.60 0.90
0.50
0.87 3.50 3.87 4.48 4.48
3.87
2.85 3.33 3.71 4.32 4.32
3.71
2.74
ns
LVCMOS18_F4
0.47 0.50 0.60 0.90
0.50
0.87 2.23 2.50 2.87 2.87
2.50
2.26 2.06 2.34 2.71 2.71
2.34
2.15
ns
LVCMOS18_F6
0.47 0.50 0.60 0.90
0.50
0.87 1.80 2.00 2.26 2.26
2.00
1.52 1.63 1.84 2.09 2.09
1.84
1.42
ns
LVCMOS18_F8
0.47 0.50 0.60 0.90
0.50
0.87 1.46 1.72 2.04 2.04
1.72
1.51 1.29 1.56 1.88 1.88
1.56
1.40
ns
LVCMOS18_F12
0.47 0.50 0.60 0.90
0.50
0.87 1.26 1.40 1.53 1.53
1.40
1.46 1.09 1.24 1.37 1.37
1.24
1.35
ns
LVCMOS18_F16
0.47 0.50 0.60 0.90
0.50
0.87 1.19 1.33 1.44 1.66
1.33
1.46 1.02 1.17 1.28 1.50
1.17
1.35
ns
LVCMOS15_S2
0.59 0.62 0.73 0.88
0.62
0.86 3.55 3.89 4.45 4.45
3.89
3.11 3.38 3.73 4.29 4.29
3.73
3.01
ns
LVCMOS15_S4
0.59 0.62 0.73 0.88
0.62
0.86 2.45 2.70 3.06 3.06
2.70
2.46 2.28 2.54 2.90 2.90
2.54
2.35
ns
LVCMOS15_S6
0.59 0.62 0.73 0.88
0.62
0.86 2.24 2.51 2.88 2.88
2.51
2.33 2.07 2.35 2.72 2.72
2.35
2.23
ns
DS182 (v2.18) June 28, 2019
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23
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
0.95V 0.9V
-1M/
-2/ -1 -1LM/
-2LI -2LE
-3 -2LE
-1Q
1.0V
-2/
-3 -2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI -2LE
-1Q
LVCMOS15_S8
0.59 0.62 0.73 0.88
0.62
0.86 1.91 2.16 2.49 2.49
2.16
2.05 1.74 2.00 2.32 2.32
2.00
1.95
ns
LVCMOS15_S12
0.59 0.62 0.73 0.88
0.62
0.86 1.77 1.98 2.23 2.23
1.98
1.97 1.60 1.82 2.07 2.07
1.82
1.87
ns
LVCMOS15_S16
0.59 0.62 0.73 0.88
0.62
0.86 1.62 1.81 2.02 2.02
1.81
1.85 1.45 1.65 1.86 1.86
1.65
1.74
ns
LVCMOS15_F2
0.59 0.62 0.73 0.88
0.62
0.86 3.38 3.69 4.18 4.18
3.69
2.74 3.21 3.53 4.02 4.02
3.53
2.64
ns
LVCMOS15_F4
0.59 0.62 0.73 0.88
0.62
0.86 2.04 2.21 2.44 2.44
2.21
1.72 1.87 2.06 2.27 2.27
2.06
1.62
ns
LVCMOS15_F6
0.59 0.62 0.73 0.88
0.62
0.86 1.47 1.74 2.09 2.09
1.74
1.49 1.30 1.58 1.93 1.93
1.58
1.39
ns
LVCMOS15_F8
0.59 0.62 0.73 0.88
0.62
0.86 1.31 1.46 1.61 1.61
1.46
1.47 1.14 1.30 1.45 1.45
1.30
1.37
ns
LVCMOS15_F12
0.59 0.62 0.73 0.88
0.62
0.86 1.21 1.34 1.45 1.45
1.34
1.44 1.04 1.18 1.29 1.29
1.18
1.34
ns
LVCMOS15_F16
0.59 0.62 0.73 0.88
0.62
0.86 1.18 1.31 1.41 1.68
1.31
1.41 1.01 1.15 1.25 1.52
1.15
1.31
ns
LVCMOS12_S2
0.64 0.67 0.78 1.04
0.67
0.95 3.38 3.80 4.48 4.48
3.80
3.27 3.21 3.64 4.31 4.31
3.64
3.17
ns
LVCMOS12_S4
0.64 0.67 0.78 1.04
0.67
0.95 2.62 2.94 3.43 3.43
2.94
2.76 2.45 2.78 3.27 3.27
2.78
2.65
ns
LVCMOS12_S6
0.64 0.67 0.78 1.04
0.67
0.95 2.05 2.33 2.72 2.72
2.33
2.24 1.88 2.17 2.56 2.56
2.17
2.14
ns
LVCMOS12_S8
0.64 0.67 0.78 1.04
0.67
0.95 1.94 2.18 2.51 2.51
2.18
2.16 1.77 2.02 2.34 2.34
2.02
2.06
ns
LVCMOS12_F2
0.64 0.67 0.78 1.04
0.67
0.95 2.84 3.15 3.62 3.62
3.15
2.47 2.67 2.99 3.46 3.46
2.99
2.37
ns
LVCMOS12_F4
0.64 0.67 0.78 1.04
0.67
0.95 1.97 2.18 2.44 2.44
2.18
1.69 1.80 2.02 2.28 2.28
2.02
1.59
ns
LVCMOS12_F6
0.64 0.67 0.78 1.04
0.67
0.95 1.33 1.51 1.70 1.70
1.51
1.43 1.16 1.35 1.54 1.54
1.35
1.32
ns
LVCMOS12_F8
0.64 0.67 0.78 1.04
0.67
0.95 1.27 1.42 1.55 1.55
1.42
1.41 1.10 1.26 1.39 1.39
1.26
1.31
ns
LVDCI_18
0.47 0.50 0.60 0.87
0.50
0.86 1.99 2.15 2.35 2.35
2.15
2.44 1.82 1.99 2.19 2.19
1.99
2.34
ns
LVDCI_15
0.59 0.62 0.73 0.92
0.62
0.87 1.98 2.23 2.58 2.58
2.23
2.40 1.81 2.07 2.41 2.41
2.07
2.29
ns
LVDCI_DV2_18
0.47 0.50 0.60 0.88
0.50
0.87 1.99 2.15 2.34 2.34
2.15
1.86 1.82 1.99 2.18 2.18
1.99
1.76
ns
LVDCI_DV2_15
0.59 0.62 0.73 0.88
0.62
0.87 1.98 2.23 2.58 2.58
2.23
1.83 1.81 2.07 2.41 2.41
2.07
1.73
ns
HSLVDCI_18
0.68 0.72 0.82 0.90
0.72
0.86 1.99 2.15 2.35 2.35
2.15
2.43 1.82 1.99 2.19 2.19
1.99
2.32
ns
HSLVDCI_15
0.68 0.72 0.82 0.93
0.72
0.84 1.98 2.23 2.58 2.58
2.23
2.27 1.81 2.07 2.41 2.41
2.07
2.17
ns
SSTL18_I_S
0.68 0.72 0.82 0.95
0.72
0.86 1.02 1.15 1.24 1.24
1.15
1.41 0.85 0.99 1.08 1.08
0.99
1.31
ns
SSTL18_II_S
0.68 0.72 0.82 1.01
0.72
0.87 1.17 1.29 1.37 1.38
1.29
1.55 1.00 1.13 1.21 1.22
1.13
1.45
ns
SSTL18_I_DCI_S 0.68 0.72 0.82 0.87
0.72
0.76 0.92 1.06 1.17 1.18
1.06
1.32 0.75 0.90 1.01 1.02
0.90
1.21
ns
SSTL18_II_DCI_S 0.68 0.72 0.82 0.82
0.72
0.78 0.88 0.98 1.08 1.12
0.98
1.26 0.71 0.83 0.92 0.96
0.83
1.15
ns
SSTL18_II_T_
DCI_S
0.68 0.72 0.82 0.98
0.72
0.78 0.92 1.06 1.17 1.18
1.06
1.32 0.75 0.90 1.01 1.02
0.90
1.21
ns
SSTL15_S
0.68 0.72 0.82 0.82
0.72
0.81 0.94 1.06 1.15 1.16
1.06
1.32 0.77 0.91 0.99 1.00
0.91
1.21
ns
SSTL15_DCI_S
0.68 0.72 0.82 0.90
0.72
0.78 0.94 1.06 1.15 1.16
1.06
1.30 0.77 0.90 0.99 1.00
0.90
1.20
ns
SSTL15_T_DCI_S 0.68 0.72 0.82 0.87
0.72
0.80 0.94 1.06 1.15 1.15
1.06
1.30 0.77 0.90 0.99 0.99
0.90
1.20
ns
SSTL135_S
0.69 0.72 0.82 0.93
0.72
0.89 0.97 1.10 1.19 1.20
1.10
1.35 0.80 0.94 1.03 1.03
0.94
1.24
ns
SSTL135_DCI_S
0.69 0.72 0.82 0.85
0.72
0.84 0.97 1.09 1.19 1.20
1.09
1.33 0.80 0.93 1.03 1.03
0.93
1.23
ns
SSTL135_T_
DCI_S
0.69 0.72 0.82 0.93
0.72
0.84 0.97 1.09 1.19 1.20
1.09
1.33 0.80 0.93 1.03 1.03
0.93
1.23
ns
SSTL12_S
0.69 0.72 0.82 1.02
0.72
0.95 0.96 1.09 1.18 1.18
1.09
1.33 0.79 0.93 1.02 1.02
0.93
1.23
ns
SSTL12_DCI_S
0.69 0.72 0.82 0.90
0.72
0.91 1.03 1.17 1.27 1.27
1.17
1.33 0.86 1.01 1.11 1.11
1.01
1.23
ns
DS182 (v2.18) June 28, 2019
Product Specification
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24
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
0.95V 0.9V
-1M/
-2/ -1 -1LM/
-2LI -2LE
-3 -2LE
-1Q
1.0V
-2/
-3 -2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI -2LE
-1Q
SSTL12_T_DCI_S 0.69 0.72 0.82 0.88
0.72
0.91 1.03 1.17 1.27 1.27
1.17
1.33 0.86 1.01 1.11 1.11
1.01
1.23
ns
DIFF_SSTL18_
I_S
0.75 0.79 0.92 0.99
0.79
0.89 1.02 1.15 1.24 1.29
1.15
1.43 0.85 0.99 1.08 1.13
0.99
1.32
ns
DIFF_SSTL18_
II_S
0.75 0.79 0.92 0.93
0.79
0.89 1.17 1.29 1.37 1.40
1.29
1.55 1.00 1.13 1.21 1.24
1.13
1.45
ns
DIFF_SSTL18_
I_DCI_S
0.75 0.79 0.92 0.92
0.79
0.76 0.92 1.06 1.17 1.24
1.06
1.40 0.75 0.90 1.01 1.08
0.90
1.29
ns
DIFF_SSTL18_
II_DCI_S
0.75 0.79 0.92 0.96
0.79
0.75 0.88 0.98 1.08 1.18
0.98
1.33 0.71 0.83 0.92 1.02
0.83
1.23
ns
DIFF_SSTL18_
II_T_DCI_S
0.75 0.79 0.92 0.92
0.79
0.76 0.92 1.06 1.17 1.24
1.06
1.40 0.75 0.90 1.01 1.08
0.90
1.29
ns
DIFF_SSTL15_S
0.68 0.72 0.82 0.99
0.72
0.89 0.94 1.06 1.15 1.16
1.06
1.32 0.77 0.91 0.99 1.00
0.91
1.21
ns
DIFF_SSTL15_
DCI_S
0.68 0.72 0.82 0.96
0.72
0.75 0.94 1.06 1.15 1.16
1.06
1.30 0.77 0.90 0.99 1.00
0.90
1.20
ns
DIFF_SSTL15_T_
0.68 0.72 0.82 0.88
DCI_S
0.72
0.76 0.94 1.06 1.15 1.23
1.06
1.38 0.77 0.90 0.99 1.07
0.90
1.28
ns
DIFF_SSTL135_S 0.69 0.72 0.82 1.09
0.72
0.91 0.97 1.10 1.19 1.20
1.10
1.35 0.80 0.94 1.03 1.03
0.94
1.24
ns
DIFF_SSTL135_D
0.69 0.72 0.82 0.90
CI_S
0.72
0.76 0.97 1.09 1.19 1.20
1.09
1.33 0.80 0.93 1.03 1.03
0.93
1.23
ns
DIFF_SSTL135_
T_DCI_S
0.69 0.72 0.82 0.84
0.72
0.76 0.97 1.09 1.19 1.27
1.09
1.43 0.80 0.93 1.03 1.11
0.93
1.32
ns
DIFF_SSTL12_S
0.69 0.72 0.82 0.96
0.72
0.91 0.96 1.09 1.18 1.18
1.09
1.33 0.79 0.93 1.02 1.02
0.93
1.23
ns
DIFF_SSTL12_
DCI_S
0.69 0.72 0.82 0.87
0.72
0.78 1.03 1.17 1.27 1.27
1.17
1.33 0.86 1.01 1.11 1.11
1.01
1.23
ns
DIFF_SSTL12_
T_DCI_S
0.69 0.72 0.82 0.96
0.72
0.80 1.03 1.17 1.27 1.27
1.17
1.41 0.86 1.01 1.11 1.11
1.01
1.31
ns
SSTL18_I_F
0.68 0.72 0.82 0.95
0.72
0.86 0.94 1.06 1.15 1.15
1.06
1.32 0.77 0.91 0.99 0.99
0.91
1.21
ns
SSTL18_II_F
0.68 0.72 0.82 1.01
0.72
0.87 0.97 1.09 1.16 1.21
1.09
1.36 0.80 0.93 1.00 1.05
0.93
1.26
ns
SSTL18_I_DCI_F 0.68 0.72 0.82 0.87
0.72
0.76 0.89 1.02 1.10 1.15
1.02
1.30 0.72 0.86 0.94 0.99
0.86
1.20
ns
SSTL18_II_DCI_F 0.68 0.72 0.82 0.82
0.72
0.78 0.89 1.02 1.10 1.10
1.02
1.24 0.72 0.86 0.94 0.94
0.86
1.14
ns
SSTL18_II_T_
DCI_F
0.68 0.72 0.82 0.98
0.72
0.78 0.89 1.02 1.10 1.15
1.02
1.27 0.72 0.86 0.94 0.99
0.86
1.17
ns
SSTL15_F
0.68 0.72 0.82 0.82
0.72
0.81 0.89 1.01 1.09 1.09
1.01
1.24 0.72 0.85 0.93 0.93
0.85
1.14
ns
SSTL15_DCI_F
0.68 0.72 0.82 0.90
0.72
0.78 0.89 1.01 1.09 1.12
1.01
1.27 0.72 0.85 0.93 0.96
0.85
1.17
ns
SSTL15_T_DCI_F 0.68 0.72 0.82 0.87
0.72
0.80 0.89 1.01 1.09 1.12
1.01
1.27 0.72 0.85 0.93 0.96
0.85
1.17
ns
SSTL135_F
0.69 0.72 0.82 0.93
0.72
0.89 0.88 1.00 1.08 1.12
1.00
1.27 0.71 0.85 0.92 0.96
0.85
1.17
ns
SSTL135_DCI_F
0.69 0.72 0.82 0.85
0.72
0.84 0.89 1.00 1.08 1.12
1.00
1.27 0.72 0.85 0.92 0.96
0.85
1.17
ns
SSTL135_T_
DCI_F
0.69 0.72 0.82 0.93
0.72
0.84 0.89 1.00 1.08 1.12
1.00
1.27 0.72 0.85 0.92 0.96
0.85
1.17
ns
SSTL12_F
0.69 0.72 0.82 1.02
0.72
0.95 0.88 1.00 1.08 1.12
1.00
1.26 0.71 0.84 0.92 0.96
0.84
1.15
ns
SSTL12_DCI_F
0.69 0.72 0.82 0.90
0.72
0.91 0.91 1.03 1.11 1.11
1.03
1.24 0.74 0.88 0.95 0.95
0.88
1.14
ns
SSTL12_T_DCI_F 0.69 0.72 0.82 0.88
0.72
0.91 0.91 1.03 1.11 1.12
1.03
1.26 0.74 0.88 0.95 0.96
0.88
1.15
ns
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Speed Grade
Speed Grade
Speed Grade
1.0V
0.95V 0.9V
-1M/
-2/ -1 -1LM/
-2LI -2LE
-3 -2LE
-1Q
1.0V
-2/
-3 -2LE
0.95V 0.9V
1.0V
-1M/
-1
-1LM/
-2LI -2LE
-1Q
-3
-2/
-2LE
0.95V 0.9V Units
-1M/
-1
-1LM/
-2LI -2LE
-1Q
DIFF_SSTL18_
I_F
0.75 0.79 0.92 0.99
0.79
0.89 0.94 1.06 1.15 1.23
1.06
1.38 0.77 0.91 0.99 1.07
0.91
1.28
ns
DIFF_SSTL18_
II_F
0.75 0.79 0.92 0.93
0.79
0.89 0.97 1.09 1.16 1.24
1.09
1.40 0.80 0.93 1.00 1.08
0.93
1.29
ns
DIFF_SSTL18_I_
DCI_F
0.75 0.79 0.92 0.92
0.79
0.76 0.89 1.02 1.10 1.23
1.02
1.36 0.72 0.86 0.94 1.07
0.86
1.26
ns
DIFF_SSTL18_II_
0.75 0.79 0.92 0.96
DCI_F
0.79
0.75 0.89 1.02 1.10 1.16
1.02
1.32 0.72 0.86 0.94 1.00
0.86
1.21
ns
DIFF_SSTL18_II_
0.75 0.79 0.92 0.92
T_DCI_F
0.79
0.76 0.89 1.02 1.10 1.24
1.02
1.38 0.72 0.86 0.94 1.08
0.86
1.28
ns
DIFF_SSTL15_F
0.68 0.72 0.82 0.99
0.72
0.89 0.89 1.01 1.09 1.09
1.01
1.24 0.72 0.85 0.93 0.93
0.85
1.14
ns
DIFF_SSTL15_D
CI_F
0.68 0.72 0.82 0.96
0.72
0.75 0.89 1.01 1.09 1.12
1.01
1.27 0.72 0.85 0.93 0.96
0.85
1.17
ns
DIFF_SSTL15_T_
0.68 0.72 0.82 0.88
DCI_F
0.72
0.76 0.89 1.01 1.09 1.20
1.01
1.35 0.72 0.85 0.93 1.03
0.85
1.24
ns
DIFF_SSTL135_F 0.69 0.72 0.82 1.09
0.72
0.91 0.88 1.00 1.08 1.12
1.00
1.27 0.71 0.85 0.92 0.96
0.85
1.17
ns
DIFF_SSTL135_
DCI_F
0.69 0.72 0.82 0.90
0.72
0.76 0.89 1.00 1.08 1.12
1.00
1.27 0.72 0.85 0.92 0.96
0.85
1.17
ns
DIFF_SSTL135_
T_DCI_F
0.69 0.72 0.82 0.84
0.72
0.76 0.89 1.00 1.08 1.20
1.00
1.35 0.72 0.85 0.92 1.03
0.85
1.24
ns
DIFF_SSTL12_F
0.69 0.72 0.82 0.96
0.72
0.91 0.88 1.00 1.08 1.12
1.00
1.26 0.71 0.84 0.92 0.96
0.84
1.15
ns
DIFF_SSTL12_
DCI_F
0.69 0.72 0.82 0.87
0.72
0.78 0.91 1.03 1.11 1.11
1.03
1.24 0.74 0.88 0.95 0.95
0.88
1.14
ns
DIFF_SSTL12_T_
0.69 0.72 0.82 0.96
DCI_F
0.72
0.80 0.91 1.03 1.11 1.18
1.03
1.33 0.74 0.88 0.95 1.02
0.88
1.23
ns
Table 22 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as
the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than
TIOTPHZ when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always
faster than TIOTPHZ when the INTERMDISABLE pin is used.
Table 22: IOB 3-state Output Switching Characteristics
Speed Grade
Symbol
Description
1.0V
0.95V
0.9V
Units
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
0.76
0.86
0.99
0.99
0.86
0.62
ns
TIOIBUFDISABLE_HR IBUF turn-on time from IBUFDISABLE to
O output for HR I/O banks
1.72
1.89
2.14
2.14
1.89
2.17
ns
TIOIBUFDISABLE_HP IBUF turn-on time from IBUFDISABLE to
O output for HP I/O banks
1.31
1.46
1.76
1.76
1.46
1.86
ns
TIOTPHZ
T input to pad high-impedance
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 23 shows the test setup parameters used for measuring input delay.
Table 23: Input Delay Measurement Methodology
Description
I/O Standard Attribute
VL (1)(2)
VH(1)(2)
VMEAS
VREF
(1)(4)(6)
(1)(3)(5)
LVCMOS, 1.2V
LVCMOS12
0.1
1.1
0.6
–
LVCMOS, 1.5V
LVCMOS15
0.1
1.4
0.75
–
LVCMOS, 1.8V
LVCMOS18
0.1
1.7
0.9
–
LVCMOS, 2.5V
LVCMOS25
0.1
2.4
1.25
–
LVCMOS, 3.3V
LVCMOS33
0.1
3.2
1.65
–
LVTTL, 3.3V
LVTTL
0.1
3.2
1.65
–
MOBILE_DDR, 1.8V
MOBILE_DDR
0.1
1.7
0.9
–
PCI33, 3.3V
PCI33_3
0.1
3.2
1.65
–
HSTL (High-Speed Transceiver Logic), Class I, 1.2V
HSTL_I_12
VREF – 0.5
VREF + 0.5
VREF
0.60
HSTL, Class I & II, 1.5V
HSTL_I, HSTL_II
VREF – 0.65
VREF + 0.65
VREF
0.75
HSTL, Class I & II, 1.8V
HSTL_I_18, HSTL_II_18
VREF – 0.8
VREF + 0.8
VREF
0.90
HSUL (High-Speed Unterminated Logic), 1.2V
HSUL_12
VREF – 0.5
VREF + 0.5
VREF
0.60
SSTL (Stub Terminated Transceiver Logic), 1.2V
SSTL12
VREF – 0.5
VREF + 0.5
VREF
0.60
SSTL, 1.35V
SSTL135, SSTL135_R
VREF – 0.575
VREF + 0.575
VREF
0.675
SSTL, 1.5V
SSTL15, SSTL15_R
VREF – 0.65
VREF + 0.65
VREF
0.75
SSTL, Class I & II, 1.8V
SSTL18_I, SSTL18_II
VREF – 0.8
VREF + 0.8
VREF
0.90
0.9 + 0.125
0(6)
–
0.6 + 0.125
0(6)
–
–
DIFF_MOBILE_DDR, 1.8V
DIFF_HSTL, Class I, 1.2V
DIFF_MOBILE_DDR
DIFF_HSTL_I_12
0.9 – 0.125
0.6 – 0.125
DIFF_HSTL, Class I & II,1.5V
DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125
0.75 + 0.125
0(6)
DIFF_HSTL, Class I & II, 1.8V
DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125
0.9 + 0.125
0(6)
–
DIFF_HSUL, 1.2V
DIFF_HSUL_12
0.6 – 0.125
0.6 + 0.125
0(6)
–
0.6 + 0.125
0(6)
–
–
DIFF_SSTL, 1.2V
DIFF_SSTL12
0.6 – 0.125
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V
DIFF_SSTL135,
DIFF_SSTL135_R
0.675 – 0.125 0.675 + 0.125
0(6)
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V
DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125
0.75 + 0.125
0(6)
–
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V
DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125
0.9 + 0.125
0(6)
–
LVDS (Low-Voltage Differential Signaling), 1.8V
LVDS
0.9 – 0.125
0.9 + 0.125
0(6)
–
1.2 + 0.125
0(6)
–
1.25 + 0.125
0(6)
–
1.25 + 0.125
0(6)
–
1.25 + 0.125
0(6)
–
1.25 + 0.125
0(6)
–
LVDS_25, 2.5V
BLVDS_25, 2.5V
MINI_LVDS_25, 2.5V
PPDS_25
RSDS_25
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BLVDS_25
MINI_LVDS_25
PPDS_25
RSDS_25
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1.2 – 0.125
1.25 – 0.125
1.25 – 0.125
1.25 – 0.125
1.25 – 0.125
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 23: Input Delay Measurement Methodology (Cont’d)
Description
TMDS_33
VL (1)(2)
VH(1)(2)
3 – 0.125
3 + 0.125
I/O Standard Attribute
TMDS_33
VMEAS
VREF
(1)(4)(6)
(1)(3)(5)
0(6)
–
Notes:
1.
2.
3.
4.
5.
6.
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
Input waveform switches between VLand VH.
Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
Input voltage level from which measurement starts.
This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 1.
The value given is the differential input voltage.
Output Delay Measurements
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay
of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure 1 and Figure 2.
X-Ref Target - Figure 1
VREF
RREF
FPGA Output
VMEAS
(Voltage Level When Taking
Delay Measurement)
CREF
(Probe Capacitance)
DS182_04_081114
Figure 1: Single-Ended Test Setup
X-Ref Target - Figure 2
FPGA Output
+
CREF
RREF VMEAS
–
DS182_05_080814
Figure 2: Differential Test Setup
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction
of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1.
Simulate the output driver of choice into the generalized test setup using values from Table 24.
2.
Record the time to VMEAS.
3.
Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance
value to represent the load.
4.
Record the time to VMEAS.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
5.
Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the
PCB trace.
Table 24: Output Delay Measurement Methodology
Description
I/O Standard Attribute
RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVCMOS, 1.2V
LVCMOS12
1M
0
0.6
0
LVCMOS/LVDCI/HSLVDCI, 1.5V
LVCMOS15, LVDCI_15, HSLVDCI_15
1M
0
0.75
0
LVCMOS/LVDCI/HSLVDCI, 1.8V
LVCMOS18, LVDCI_15, HSLVDCI_18
1M
0
0.9
0
LVCMOS, 2.5V
LVCMOS25
1M
0
1.25
0
LVCMOS, 3.3V
LVCMOS33
1M
0
1.65
0
LVTTL, 3.3V
LVTTL
1M
0
1.65
0
PCI33, 3.3V
PCI33_3
25
10
1.65
0
HSTL (High-Speed Transceiver Logic), Class I, 1.2V
HSTL_I_12
50
0
VREF
0.6
HSTL, Class I, 1.5V
HSTL_I
50
0
VREF
0.75
HSTL, Class II, 1.5V
HSTL_II
25
0
VREF
0.75
HSTL, Class I, 1.8V
HSTL_I_18
50
0
VREF
0.9
HSTL, Class II, 1.8V
HSTL_II_18
25
0
VREF
0.9
HSUL (High-Speed Unterminated Logic), 1.2V
HSUL_12
50
0
VREF
0.6
SSTL12, 1.2V
SSTL12
50
0
VREF
0.6
SSTL135/SSTL135_R, 1.35V
SSTL135, SSTL135_R
50
0
VREF
0.675
SSTL15/SSTL15_R, 1.5V
SSTL15, SSTL15_R
50
0
VREF
0.75
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
SSTL18_I, SSTL18_II
50
0
VREF
0.9
DIFF_MOBILE_DDR, 1.8V
DIFF_MOBILE_DDR
50
0
VREF
0.9
DIFF_HSTL, Class I, 1.2V
DIFF_HSTL_I_12
50
0
VREF
0.6
DIFF_HSTL, Class I & II, 1.5V
DIFF_HSTL_I, DIFF_HSTL_II
50
0
VREF
0.75
DIFF_HSTL, Class I & II, 1.8V
DIFF_HSTL_I_18, DIFF_HSTL_II_18
50
0
VREF
0.9
DIFF_HSUL_12, 1.2V
DIFF_HSUL_12
50
0
VREF
0.6
DIFF_SSTL12, 1.2V
DIFF_SSTL12
50
0
VREF
0.6
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V
DIFF_SSTL135, DIFF_SSTL135_R
50
0
VREF
0.675
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V
DIFF_SSTL15, DIFF_SSTL15_R
50
0
VREF
0.75
DIFF_SSTL18, Class I & II, 1.8V
DIFF_SSTL18_I, DIFF_SSTL18_II
50
0
VREF
0.9
0
0(2)
0
0
0(2)
0
0
0(2)
0
0
0(2)
0
0
0(2)
0
0
0(2)
0
0
0(2)
3.3
LVDS (Low-Voltage Differential Signaling), 1.8V
LVDS, 2.5V
BLVDS (Bus LVDS), 2.5V
Mini LVDS, 2.5V
PPDS_25
RSDS_25
TMDS_33
LVDS
LVDS_25
BLVDS_25
MINI_LVDS_25
PPDS_25
RSDS_25
TMDS_33
100
100
100
100
100
100
50
Notes:
1.
2.
CREF is the capacitance of the probe, nominally 0 pF.
The value given is the differential output voltage.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input/Output Logic Switching Characteristics
Table 25: ILOGIC Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
Setup/Hold
TICE1CK/
TICKCE1
CE1 pin Setup/Hold with respect to
CLK
0.42/0.00 0.48/0.00 0.67/0.00
0.67/0.00
0.48/0.00 0.56/–0.16
ns
TISRCK/TICKSR
SR pin Setup/Hold with respect to
CLK
0.53/0.01 0.61/0.01 0.99/0.01
0.99/0.01
0.61/0.01 0.88/–0.30
ns
TIDOCKE2/
TIOCKDE2
D pin Setup/Hold with respect to CLK
without Delay (HP I/O banks only)
0.01/0.27 0.01/0.29 0.01/0.34
0.01/0.34
0.01/0.29 0.01/0.41
ns
TIDOCKDE2/
TIOCKDDE2
DDLY pin Setup/Hold with respect to
CLK (using IDELAY) (HP I/O banks
only)
0.01/0.27 0.02/0.29 0.02/0.34
0.02/0.34
0.02/0.29 0.01/0.41
ns
TIDOCKE3/
TIOCKDE3
D pin Setup/Hold with respect to CLK
without Delay (HR I/O banks only)
0.01/0.27 0.01/0.29 0.01/0.34
0.01/0.34
0.01/0.29 0.01/0.41
ns
TIDOCKDE3/
TIOCKDDE3
DDLY pin Setup/Hold with respect to
CLK (using IDELAY) (HR I/O banks
only)
0.01/0.27 0.02/0.29 0.02/0.34
0.02/0.34
0.02/0.29 0.01/0.41
ns
Combinatorial
TIDIE2
D pin to O pin propagation delay, no
Delay (HP I/O banks only)
0.09
0.10
0.12
0.12
0.10
0.14
ns
TIDIDE2
DDLY pin to O pin propagation delay
(using IDELAY) (HP I/O banks only)
0.10
0.11
0.13
0.13
0.11
0.15
ns
TIDIE3
D pin to O pin propagation delay, no
Delay (HR I/O banks only)
0.09
0.10
0.12
0.12
0.10
0.14
ns
TIDIDE3
DDLY pin to O pin propagation delay
(using IDELAY) (HR I/O banks only)
0.10
0.11
0.13
0.13
0.11
0.15
ns
Sequential Delays
TIDLOE2
D pin to Q1 pin using flip-flop as a
latch without Delay (HP I/O banks
only)
0.36
0.39
0.45
0.45
0.39
0.54
ns
TIDLODE2
DDLY pin to Q1 pin using flip-flop as a
latch (using IDELAY) (HP I/O banks
only)
0.36
0.39
0.45
0.45
0.39
0.55
ns
TIDLOE3
D pin to Q1 pin using flip-flop as a latch
without Delay (HR I/O banks only)
0.36
0.39
0.45
0.45
0.39
0.54
ns
TIDLODE3
DDLY pin to Q1 pin using flip-flop as a
latch (using IDELAY) (HR I/O banks
only)
0.36
0.39
0.45
0.45
0.39
0.55
ns
TICKQ
CLK to Q outputs
0.47
0.50
0.58
0.58
0.50
0.71
ns
TRQ_ILOGICE2
SR pin to OQ/TQ out (HP I/O banks
only)
0.84
0.94
1.16
1.16
0.94
1.32
ns
TGSRQ_ILOGICE2 Global Set/Reset to Q outputs
(HP I/O banks only)
7.60
7.60
10.51
10.51
7.60
11.39
ns
TRQ_ILOGICE3
0.84
0.94
1.16
1.16
0.94
1.32
ns
7.60
7.60
10.51
10.51
7.60
11.39
ns
SR pin to OQ/TQ out
(HR I/O banks only)
TGSRQ_ILOGICE3 Global Set/Reset to Q outputs
(HR I/O banks only)
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 25: ILOGIC Switching Characteristics (Cont’d)
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
Set/Reset
TRPW_ILOGICE2
Minimum Pulse Width, SR inputs (HP
I/O banks only)
0.54
0.63
0.63
0.63
0.63
0.68
ns,
Min
TRPW_ILOGICE3
Minimum Pulse Width, SR inputs (HR
I/O banks only)
0.54
0.63
0.63
0.63
0.63
0.68
ns,
Min
Table 26: OLOGIC Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
Setup/Hold
TODCK/TOCKD
D1/D2 pins Setup/Hold with
respect to CLK
0.45/–0.13 0.50/–0.13 0.58/–0.13 0.58/–0.13 0.50/–0.13 0.79/–0.18
ns
TOOCECK/
TOCKOCE
OCE pin Setup/Hold with
respect to CLK
0.28/0.03
0.29/0.03
0.45/0.03
0.45/0.03
0.29/0.03
0.35/–0.10
ns
TOSRCK/TOCKSR
SR pin Setup/Hold with respect
to CLK
0.32/0.18
0.38/0.18
0.70/0.18
0.70/0.18
0.38/0.18
0.62/–0.04
ns
TOTCK/TOCKT
T1/T2 pins Setup/Hold with
respect to CLK
0.49/–0.16 0.56/–0.16 0.68/–0.16 0.68/–0.13 0.56/–0.16 0.67/–0.18
ns
TOTCECK/
TOCKTCE
TCE pin Setup/Hold with
respect to CLK
0.28/0.01
0.30/0.01
0.45/0.01
0.45/0.06
0.30/0.01
0.31/–0.10
ns
0.73
0.81
0.97
0.97
0.81
1.18
ns
Combinatorial
TODQ
D1 to OQ out or T1 to TQ out
Sequential Delays
TOCKQ
CLK to OQ/TQ out
0.41
0.43
0.49
0.49
0.43
0.63
ns
TRQ_OLOGICE2
SR pin to OQ/TQ out (HP I/O
banks only)
0.63
0.70
0.83
0.83
0.70
1.12
ns
TGSRQ_OLOGICE2 Global Set/Reset to Q outputs
(HP I/O banks only)
7.60
7.60
10.51
10.51
7.60
11.39
ns
TRQ_OLOGICE3
0.63
0.70
0.83
0.83
0.70
1.12
ns
7.60
7.60
10.51
10.51
7.60
11.39
ns
SR pin to OQ/TQ out (HR I/O
banks only)
TGSRQ_OLOGICE3 Global Set/Reset to Q outputs
(HR I/O banks only)
Set/Reset
TRPW_OLOGICE2
Minimum Pulse Width, SR
inputs (HP I/O banks only)
0.54
0.54
0.63
0.63
0.54
0.68
ns,
Min
TRPW_OLOGICE3
Minimum Pulse Width, SR
inputs (HR I/O banks only)
0.54
0.54
0.63
0.63
0.54
0.68
ns,
Min
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 27: ISERDES Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.02/0.13
0.02/0.15
0.02/0.15
0.95V
0.9V
-2LI
-2LE
0.02/0.13
Units
Setup/Hold for Control Lines
TISCCK_BITSLIP/
TISCKC_BITSLIP
BITSLIP pin Setup/Hold with
respect to CLKDIV
0.01/0.12
0.02/0.21
ns
TISCCK_CE/
TISCKC_CE(2)
CE pin Setup/Hold with respect
to CLK (for CE1)
0.39/–0.02 0.44/–0.02 0.63/–0.02 0.63/–0.02 0.44/–0.02 0.51/–0.22
ns
TISCCK_CE2/
TISCKC_CE2(2)
CE pin Setup/Hold with respect
to CLKDIV (for CE2)
–0.12/0.29 –0.12/0.31 –0.12/0.35 –0.12/0.35 –0.12/0.31 –0.17/0.40
ns
Setup/Hold for Data Lines
TISDCK_D/
TISCKD_D
D pin Setup/Hold with respect
to CLK
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.04/0.19
ns
TISDCK_DDLY/
TISCKD_DDLY
DDLY pin Setup/Hold with
respect to CLK (using
IDELAY)(1)
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.03/0.19
ns
TISDCK_D_DDR/
TISCKD_D_DDR
D pin Setup/Hold with respect
to CLK at DDR mode
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.04/0.19
ns
0.11/0.11
0.12/0.12
0.15/0.15
0.15/0.15
0.12/0.12
0.19/0.19
ns
0.46
0.47
0.58
0.58
0.47
0.67
ns
0.09
0.10
0.12
0.12
0.10
0.14
ns
TISDCK_DDLY_DDR/ D pin Setup/Hold with respect
TISCKD_DDLY_DDR to CLK at DDR mode (using
IDELAY)(1)
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
Propagation Delays
TISDO_DO
D input to DO output pin
Notes:
1.
2.
Recorded at 0 tap value.
TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 28: OSERDES Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.40/0.02
0.55/0.02
0.55/0.02
0.95V
0.9V
-2LI
-2LE
0.40/0.02
Units
Setup/Hold
TOSDCK_D/
TOSCKD_D
D input Setup/Hold with respect
to CLKDIV
0.37/0.02
0.44/–0.24
ns
TOSDCK_T/
TOSCKD_T(1)
T input Setup/Hold with respect
to CLK
0.49/–0.15 0.56/–0.15 0.68/–0.15 0.68/–0.15 0.56/–0.15 0.67/–0.25
ns
TOSDCK_T2/
TOSCKD_T2(1)
T input Setup/Hold with respect
to CLKDIV
0.27/–0.15 0.30/–0.15 0.34/–0.15 0.34/–0.15 0.30/–0.15 0.46/–0.25
ns
TOSCCK_OCE/
TOSCKC_OCE
OCE input Setup/Hold with
respect to CLK
0.28/0.03
0.29/0.03
0.45/0.03
0.45/0.03
0.29/0.03
0.35/–0.15
ns
TOSCCK_S
SR (Reset) input Setup with
respect to CLKDIV
0.41
0.46
0.75
0.75
0.46
0.70
ns
TOSCCK_TCE/
TOSCKC_TCE
TCE input Setup/Hold with
respect to CLK
0.28/0.01
0.30/0.01
0.45/0.01
0.45/0.01
0.30/0.01
0.31/–0.15
ns
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
0.35
0.37
0.42
0.42
0.37
0.54
ns
TOSCKO_TQ
Clock to out from CLK to TQ
0.41
0.43
0.49
0.49
0.43
0.63
ns
T input to TQ Out
0.73
0.81
0.97
0.97
0.81
1.18
ns
Combinatorial
TOSDO_TTQ
Notes:
1.
TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input/Output Delay Switching Characteristics
Table 29: Input/Output Delay Switching Characteristics
Speed Grade
Symbol
1.0V
Description
0.95V
0.9V
-2LI
-2LE
Units
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
3.22
3.22
3.22
3.22
3.22
3.22
µs
IDELAYCTRL
TDLYCCO_RDY
Reset to Ready for IDELAYCTRL
FIDELAYCTRL_REF
Attribute
REFCLK frequency = 200.00(1)
200.00
200.00
200.00
200.00
200.00
200.00
MHz
Attribute
REFCLK frequency = 300.00(1)
300.00
300.00
N/A
N/A
300.00
N/A
MHz
Attribute
REFCLK frequency = 400.00(1)
400.00
400.00
N/A
N/A
400.00
N/A
MHz
±10
±10
±10
±10
±10
±10
MHz
52.00
52.00
52.00
52.00
52.00
52.00
ns
IDELAYCTRL_REF REFCLK precision
_PRECISION
TIDELAYCTRL_RPW
Minimum Reset pulse width
IDELAY/ODELAY
TIDELAYRESOLUTION IDELAY/ODELAY chain delay
resolution
1/(32 x 2 x FREF)
µs
Pattern dependent period jitter in
delay chain for clock pattern.(2)
0
0
0
0
0
0
ps
per tap
Pattern dependent period jitter in
delay chain for random data pattern
(PRBS 23)(3)
±5
±5
±5
±5
±5
±5
ps
per tap
Pattern dependent period jitter in
delay chain for random data pattern
(PRBS 23)(4)
±9
±9
±9
±9
±9
±9
ps
per tap
TIDELAY_CLK_MAX/
TODELAY_CLK_MAX
Maximum frequency of CLK input to
IDELAY/ODELAY
800.00
800.00
710.00
710.00
800.00
710.00
MHz
TIDCCK_CE /
TIDCKC_CE
CE pin Setup/Hold with respect to C
for IDELAY
0.11/0.10
0.14/0.12
0.18/0.14
0.18/0.14
0.14/0.12
0.14/0.16
ns
TODCCK_CE /
TODCKC_CE
CE pin Setup/Hold with respect to C
for ODELAY
0.14/0.03
0.16/0.04
0.19/0.05
0.19/0.05
0.16/0.04
0.28/0.06
ns
TIDCCK_INC/
TIDCKC_INC
INC pin Setup/Hold with respect to
C for IDELAY
0.10/0.14
0.12/0.16
0.14/0.20
0.14/0.20
0.12/0.16
0.10/0.23
ns
TODCCK_INC/
TODCKC_INC
INC pin Setup/Hold with respect to
C for ODELAY
0.10/0.07
0.12/0.08
0.13/0.09
0.13/0.09
0.12/0.08
0.19/0.16
ns
TIDCCK_RST/
TIDCKC_RST
RST pin Setup/Hold with respect to
C for IDELAY
0.13/0.08
0.14/0.10
0.16/0.12
0.16/0.12
0.14/0.10
0.22/0.19
ns
TODCCK_RST/
TODCKC_RST
RST pin Setup/Hold with respect to
C for ODELAY
0.16/0.04
0.19/0.06
0.24/0.08
0.24/0.08
0.19/0.06
0.32/0.11
ns
TIDDO_IDATAIN
Propagation delay through IDELAY
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
ps
TODDO_ODATAIN
Propagation delay through
ODELAY
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
ps
TIDELAYPAT_JIT and
TODELAYPAT_JIT
Notes:
1.
2.
3.
4.
5.
Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
When HIGH_PERFORMANCE mode is set to TRUE.
When HIGH_PERFORMANCE mode is set to FALSE.
Delay depends on IDELAY/ODELAY tap setting. See the timing report for actual values.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 30: IO_FIFO Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
IO_FIFO Clock to Out Delays
TOFFCKO_DO
RDCLK to Q outputs
0.51
0.56
0.63
0.63
0.56
0.81
ns
TCKO_FLAGS
Clock to IO_FIFO Flags
0.59
0.62
0.81
0.81
0.62
0.77
ns
Setup/Hold
TCCK_D/
TCKC_D
D inputs to WRCLK
0.43/–0.01 0.47/–0.01 0.53/–0.01
0.53/0.09
0.47/–0.01 0.76/–0.05
ns
TIFFCCK_WREN /
TIFFCKC_WREN
WREN to WRCLK
0.39/–0.01 0.43/–0.01 0.50/–0.01 0.50/–0.01 0.43/–0.01 0.70/–0.05
ns
TOFFCCK_RDEN/
TOFFCKC_RDEN
RDEN to RDCLK
0.49/0.01
0.53/0.02
0.61/0.02
0.61/0.02
0.53/0.02
0.79/–0.02
ns
Minimum Pulse Width
TPWH_IO_FIFO
RESET, RDCLK, WRCLK
0.81
0.92
1.08
1.08
0.92
1.29
ns
TPWL_IO_FIFO
RESET, RDCLK, WRCLK
0.81
0.92
1.08
1.08
0.92
1.29
ns
533.05
470.37
400.00
400.00
470.37
333.33
MHz
Maximum Frequency
FMAX
RDCLK and WRCLK
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
CLB Switching Characteristics
Table 31: CLB Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
Combinatorial Delays
TILO
An – Dn LUT address to A
0.05
0.05
0.06
0.06
0.05
0.07
ns, Max
TILO_2
An – Dn LUT address to AMUX/CMUX
0.15
0.16
0.19
0.19
0.16
0.22
ns, Max
TILO_3
An – Dn LUT address to BMUX_A
0.24
0.25
0.30
0.30
0.25
0.37
ns, Max
TITO
An – Dn inputs to A – D Q outputs
0.58
0.61
0.74
0.74
0.61
0.91
ns, Max
TAXA
AX inputs to AMUX output
0.38
0.40
0.49
0.49
0.40
0.62
ns, Max
TAXB
AX inputs to BMUX output
0.40
0.42
0.52
0.52
0.42
0.66
ns, Max
TAXC
AX inputs to CMUX output
0.39
0.41
0.50
0.50
0.41
0.62
ns, Max
TAXD
AX inputs to DMUX output
0.43
0.44
0.52
0.52
0.44
0.67
ns, Max
TBXB
BX inputs to BMUX output
0.31
0.33
0.40
0.40
0.33
0.51
ns, Max
TBXD
BX inputs to DMUX output
0.38
0.39
0.47
0.47
0.39
0.62
ns, Max
TCXC
CX inputs to CMUX output
0.27
0.28
0.34
0.34
0.28
0.43
ns, Max
TCXD
CX inputs to DMUX output
0.33
0.34
0.41
0.41
0.34
0.54
ns, Max
TDXD
DX inputs to DMUX output
0.32
0.33
0.40
0.40
0.33
0.52
ns, Max
Sequential Delays
TCKO
Clock to AQ – DQ outputs
0.26
0.27
0.32
0.32
0.27
0.40
ns, Max
TSHCKO
Clock to AMUX – DMUX outputs
0.32
0.32
0.39
0.39
0.32
0.46
ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TAS/TAH
AN – DN input to CLK on
A – D flip-flops
0.01/0.12 0.02/0.13 0.03/0.18
0.03/0.24
0.02/0.13 0.02/0.18
ns, Min
TDICK/TCKDI
AX – DX input to CLK on
A – D flip-flops
0.04/0.14 0.04/0.14 0.05/0.20
0.05/0.26
0.04/0.14 0.05/0.21
ns, Min
AX – DX input through MUXs and/or
carry logic to CLK on A – D flip-flops
0.36/0.10 0.37/0.11 0.46/0.16
0.46/0.22
0.37/0.11 0.56/0.15
ns, Min
TCECK_CLB/
TCKCE_CLB
CE input to CLK on A – D flip-flops
0.19/0.05 0.20/0.05 0.25/0.05
0.25/0.11
0.20/0.05 0.24/0.04
ns, Min
TSRCK/TCKSR
SR input to CLK on A – D flip-flops
0.30/0.05 0.31/0.07 0.37/0.09
0.37/0.22
0.31/0.07 0.48/0.05
ns, Min
Set/Reset
TSRMIN
SR input minimum pulse width
0.52
0.78
1.04
1.04
0.78
0.95
ns, Min
TRQ
Delay from SR input to
AQ – DQ flip-flops
0.38
0.38
0.46
0.46
0.38
0.59
ns, Max
TCEO
Delay from CE input to
AQ – DQ flip-flops
0.34
0.35
0.43
0.43
0.35
0.54
ns, Max
FTOG
Toggle frequency (for export control)
1818
1818
1818
1818
1818
1286
MHz
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 32: CLB Distributed RAM Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
Sequential Delays
TSHCKO
Clock to A – B outputs
0.68
0.70
0.85
0.85
0.70
1.08
ns, Max
TSHCKO_1
Clock to AMUX – BMUX outputs
0.91
0.95
1.15
1.15
0.95
1.44
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS_LRAM/
TDH_LRAM
A – D inputs to CLK
0.45/0.23
0.45/0.24
0.54/0.27
0.54/0.28
0.45/0.24
0.69/0.33
ns, Min
TAS_LRAM/
TAH_LRAM
Address An inputs to clock
0.13/0.50
0.14/0.50
0.17/0.58
0.17/0.61
0.14/0.50
0.21/0.63
ns, Min
Address An inputs through MUXs
and/or carry logic to clock
0.40/0.16
0.42/0.17
0.52/0.23
0.52/0.29
0.42/0.17
0.63/0.23
ns, Min
TWS_LRAM/
TWH_LRAM
WE input to clock
0.29/0.09
0.30/0.09
0.36/0.09
0.36/0.11
0.30/0.09
0.46/0.10
ns, Min
TCECK_LRAM/
TCKCE_LRAM
CE input to CLK
0.29/0.09
0.30/0.09
0.37/0.09
0.37/0.11
0.30/0.09
0.47/0.10
ns, Min
Clock CLK
TMPW
Minimum pulse width
0.68
0.77
0.91
0.91
0.77
1.11
ns, Min
TMCP
Minimum clock period
1.35
1.54
1.82
1.82
1.54
2.22
ns, Min
0.95V
0.9V
-2LI
-2LE
Notes:
1.
TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 33: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
Units
Sequential Delays
TREG
Clock to A – D outputs
0.96
0.98
1.20
1.20
0.98
1.35
ns, Max
TREG_MUX
Clock to AMUX – DMUX output
1.19
1.23
1.50
1.50
1.23
1.72
ns, Max
TREG_M31
Clock to DMUX output via M31
output
0.89
0.91
1.10
1.10
0.91
1.25
ns, Max
Setup and Hold Times Before/After Clock CLK
TWS_SHFREG/
TWH_SHFREG
WE input
0.26/0.09 0.27/0.09 0.33/0.09
0.33/0.11
0.27/0.09 0.41/0.10
ns, Min
TCECK_SHFREG/
TCKCE_SHFREG
CE input to CLK
0.27/0.09 0.28/0.09 0.33/0.09
0.33/0.11
0.28/0.09 0.42/0.10
ns, Min
TDS_SHFREG/
TDH_SHFREG
A – D inputs to CLK
0.28/0.26 0.28/0.26 0.33/0.30
0.33/0.36
0.28/0.26 0.41/0.36
ns, Min
Clock CLK
TMPW_SHFREG
Minimum pulse width
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0.65
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0.78
0.78
0.65
0.91
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ns, Min
37
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 34: Block RAM and FIFO Switching Characteristics
Speed Grade
Symbol
1.0V
Description
0.95V
0.9V
-2LI
-2LE
Units
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
Clock CLK to DOUT output
(without output register)(2)(3)
1.57
1.80
2.08
2.08
1.80
2.44
ns, Max
Clock CLK to DOUT output (with
output register)(4)(5)
0.54
0.63
0.75
0.75
0.63
0.86
ns, Max
Clock CLK to DOUT output with
ECC (without output
register)(2)(3)
2.35
2.58
3.26
3.26
2.58
4.49
ns, Max
Clock CLK to DOUT output with
ECC (with output register)(4)(5)
0.62
0.69
0.80
0.80
0.69
0.94
ns, Max
TRCKO_DO_CASCOUT and Clock CLK to DOUT output with
TRCKO_DO_CASCOUT_REG Cascade (without output
register)(2)
2.21
2.45
2.80
2.80
2.45
3.19
ns, Max
Clock CLK to DOUT output with
Cascade (with output register)(4)
0.98
1.08
1.24
1.24
1.08
1.32
ns, Max
TRCKO_FLAGS
Clock CLK to FIFO flags
outputs(6)
0.65
0.74
0.89
0.89
0.74
0.97
ns, Max
TRCKO_POINTERS
Clock CLK to FIFO pointers
outputs(7)
0.79
0.87
0.98
0.98
0.87
1.10
ns, Max
TRCKO_PARITY_ECC
Clock CLK to ECCPARITY in
ECC encode only mode
0.66
0.72
0.80
0.80
0.72
0.93
ns, Max
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR (without
output register)
2.17
2.38
3.01
3.01
2.38
4.15
ns, Max
Clock CLK to BITERR (with
output register)
0.57
0.65
0.76
0.76
0.65
0.89
ns, Max
TRCKO_RDADDR_ECC and Clock CLK to RDADDR output
TRCKO_RDADDR_ECC_REG with ECC (without output
register)
0.64
0.74
0.90
0.90
0.74
0.98
ns, Max
Clock CLK to RDADDR output
with ECC (with output register)
0.71
0.79
0.92
0.92
0.79
1.10
ns, Max
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and
TRCKO_DO_REG(1)
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDRA/
TRCKC_ADDRA
ADDR inputs(8)
0.38/
0.27
0.42/
0.28
0.48/
0.31
0.48/
0.38
0.42/
0.28
0.65/
0.38
ns, Min
TRDCK_DI_WF_NC/
TRCKD_DI_WF_NC
Data input setup/hold time when
block RAM is configured in
WRITE_FIRST or NO_CHANGE
mode(9)
0.49/
0.51
0.55/
0.53
0.63/
0.57
0.63/
0.57
0.55/
0.53
0.78/
0.64
ns, Min
TRDCK_DI_RF/
TRCKD_DI_RF
Data input setup/hold time when
block RAM is configured in
READ_FIRST mode(9)
0.17/
0.25
0.19/
0.29
0.21/
0.35
0.21/
0.35
0.19/
0.29
0.25/
0.32
ns, Min
TRDCK_DI_ECC/
TRCKD_DI_ECC
DIN inputs with block RAM ECC
in standard mode(9)
0.42/
0.37
0.47/
0.39
0.53/
0.43
0.53/
0.58
0.47/
0.39
0.66/
0.46
ns, Min
TRDCK_DI_ECCW/
TRCKD_DI_ECCW
DIN inputs with block RAM ECC
encode only(9)
0.79/
0.37
0.87/
0.39
0.99/
0.43
0.99/
0.58
0.87/
0.39
1.17/
0.41
ns, Min
TRDCK_DI_ECC_FIFO/
TRCKD_DI_ECC_FIFO
DIN inputs with FIFO ECC in
standard mode(9)
0.89/
0.47
0.98/
0.50
1.12/
0.54
1.12/
0.69
0.98/
0.50
1.32/
0.65
ns, Min
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 34: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
TRCCK_INJECTBITERR/
TRCKC_INJECTBITERR
Inject single/double bit error in
ECC mode
0.49/
0.30
0.55/
0.31
0.63/
0.34
0.63/
0.43
0.55/
0.31
0.78/
0.41
ns, Min
TRCCK_EN/TRCKC_EN
Block RAM Enable (EN) input
0.30/
0.17
0.33/
0.18
0.38/
0.20
0.38/
0.32
0.33/
0.18
0.48/
0.22
ns, Min
TRCCK_REGCE/
TRCKC_REGCE
CE input of output register
0.21/
0.13
0.25/
0.13
0.31/
0.14
0.31/
0.19
0.25/
0.13
0.34/
0.16
ns, Min
TRCCK_RSTREG/
TRCKC_RSTREG
Synchronous RSTREG input
0.25/
0.06
0.27/
0.06
0.29/
0.06
0.29/
0.14
0.27/
0.06
0.35/
0.06
ns, Min
TRCCK_RSTRAM/
TRCKC_RSTRAM
Synchronous RSTRAM input
0.27/
0.35
0.29/
0.37
0.31/
0.39
0.31/
0.39
0.29/
0.37
0.34/
0.40
ns, Min
TRCCK_WEA/
TRCKC_WEA
Write Enable (WE) input (Block
RAM only)
0.38/
0.15
0.41/
0.16
0.46/
0.17
0.46/
0.29
0.41/
0.16
0.54/
0.19
ns, Min
TRCCK_WREN/
TRCKC_WREN
WREN FIFO inputs
0.39/
0.25
0.39/
0.30
0.40/
0.37
0.40/
0.49
0.39/
0.30
0.65/
0.37
ns, Min
TRCCK_RDEN/
TRCKC_RDEN
RDEN FIFO inputs
0.36/
0.26
0.36/
0.30
0.37/
0.37
0.37/
0.49
0.36/
0.30
0.60/
0.38
ns, Min
TRCO_FLAGS
Reset RST to FIFO
flags/pointers(10)
0.76
0.83
0.93
0.93
0.83
1.06
ns, Max
TRREC_RST/
TRREM_RST
FIFO reset recovery and removal
timing(11)
1.59/
–0.68
1.76/
–0.68
2.01/
–0.68
2.01/
–0.68
1.76/
–0.68
2.07/
–0.60
ns, Max
FMAX_BRAM_WF_NC
Block RAM
(Write first and No change
modes)
When not in SDP RF mode
601.32
543.77
458.09
458.09
543.77
372.44
MHz
FMAX_BRAM_RF
Block RAM
(Read first, Performance mode)
When in SDP RF mode but no
address overlap between port A
and port B
601.32
543.77
458.09
458.09
543.77
372.44
MHz
Block RAM
(Read first, Delayed_write mode)
When in SDP RF mode and
there is possibility of overlap
between port A and port B
addresses
528.26
477.33
400.80
400.80
477.33
317.36
MHz
FMAX_CAS_WF_NC
Block RAM Cascade
(Write first, No change mode)
When cascade but not in RF
mode
551.27
493.83
408.00
408.00
493.83
322.48
MHz
FMAX_CAS_RF
Block RAM Cascade
(Read first, Performance mode)
When in cascade with RF mode
and no possibility of address
overlap/one port is disabled
551.27
493.83
408.00
408.00
493.83
322.48
MHz
Reset Delays
Maximum Frequency
_PERFORMANCE
FMAX_BRAM_RF_
DELAYED_WRITE
_PERFORMANCE
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 34: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
When in cascade RF mode and
there is a possibility of address
overlap between port A and port
B
478.24
427.35
350.88
350.88
427.35
267.38
MHz
DELAYED_WRITE
FMAX_FIFO
FIFO in all modes without ECC
601.32
543.77
458.09
458.09
543.77
372.44
MHz
FMAX_ECC
Block RAM and FIFO in ECC
configuration
484.26
430.85
351.12
351.12
430.85
254.13
MHz
FMAX_CAS_RF_
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
The timing report shows all of these parameters as TRCKO_DO.
TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
These parameters also apply to synchronous FIFO with DO_REG = 0.
TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
These parameters include both A and B inputs as well as the parity inputs of A and B.
TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DSP48E1 Switching Characteristics
Table 35: DSP48E1 Switching Characteristics
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_A_AREG/
TDSPCKD_A_AREG
A input to A register CLK
0.24/
0.12
0.27/
0.14
0.31/
0.16
0.33/
0.18
0.27/
0.14
0.38/
0.12
ns
TDSPDCK_B_BREG/
TDSPCKD_B_BREG
B input to B register CLK
0.28/
0.13
0.32/
0.14
0.39/
0.15
0.41/
0.18
0.32/
0.14
0.51/
0.16
ns
TDSPDCK_C_CREG/
TDSPCKD_C_CREG
C input to C register CLK
0.15/
0.15
0.17/
0.17
0.20/
0.20
0.20/
0.22
0.17/
0.17
0.31/
0.21
ns
TDSPDCK_D_DREG/
TDSPCKD_D_DREG
D input to D register CLK
0.21/
0.19
0.27/
0.22
0.35/
0.26
0.35/
0.27
0.27/
0.22
0.46/
0.20
ns
TDSPDCK_ACIN_AREG/
TDSPCKD_ACIN_AREG
ACIN input to A register CLK
0.21/
0.12
0.24/
0.14
0.27/
0.16
0.30/
0.16
0.24/
0.14
0.31/
0.12
ns
TDSPDCK_BCIN_BREG/
TDSPCKD_BCIN_BREG
BCIN input to B register CLK
0.22/
0.13
0.25/
0.14
0.30/
0.15
0.32/
0.15
0.25/
0.14
0.34/
0.16
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, B}_MREG_MULT/
TDSPCKD_{A, B}_MREG_MULT
{A, B} input to M register CLK
using multiplier
2.04/
–0.01
2.34/
–0.01
2.79/
–0.01
2.79/
–0.01
2.34/
–0.01
3.66/
–0.06
ns
TDSPDCK_{A, D}_ADREG/
TDSPCKD_{A, D}_ADREG
{A, D} input to AD register CLK
1.09/
–0.02
1.25/
–0.02
1.49/
–0.02
1.49/
–0.02
1.25/
–0.02
1.94/
–0.23
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, B}_PREG_MULT/
TDSPCKD_{A, B} _PREG_MULT
{A, B,} input to P register CLK
using multiplier
3.41/
–0.24
3.90/
–0.24
4.64/
–0.24
4.64/
–0.24
3.90/
–0.24
5.89/
–0.41
ns
TDSPDCK_D_PREG_MULT/
TDSPCKD_D_PREG_MULT
D input to P register CLK
using multiplier
3.33/
–0.62
3.81/
–0.62
4.53/
–0.62
4.53/
–0.62
3.81/
–0.62
5.70/
–1.42
ns
TDSPDCK_{A, B} _PREG/
TDSPCKD_{A, B} _PREG
A or B input to P register CLK
not using multiplier
1.47/
–0.24
1.68/
–0.24
2.00/
–0.24
2.00/
–0.24
1.68/
–0.24
2.37/
–0.41
ns
TDSPDCK_C_PREG/
TDSPCKD_C_PREG
C input to P register CLK not
using multiplier
1.30/
–0.22
1.49/
–0.22
1.78/
–0.22
1.78/
–0.22
1.49/
–0.22
2.11/
–0.36
ns
TDSPDCK_PCIN_PREG/
TDSPCKD_PCIN_PREG
PCIN input to P register CLK
1.12/
–0.13
1.28/
–0.13
1.52/
–0.13
1.52/
–0.13
1.28/
–0.13
1.81/
–0.21
ns
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA;CEB}_{AREG;BREG}/
TDSPCKD_{CEA;CEB}_{AREG;BREG}
{CEA; CEB} input to {A; B}
register CLK
0.30/
0.05
0.36/
0.06
0.44/
0.09
0.44/
0.09
0.36/
0.06
0.55/
0.09
ns
TDSPDCK_CEC_CREG/
TDSPCKD_CEC_CREG
CEC input to C register CLK
0.24/
0.08
0.29/
0.09
0.36/
0.11
0.36/
0.11
0.29/
0.09
0.43/
0.11
ns
TDSPDCK_CED_DREG/
TDSPCKD_CED_DREG
CED input to D register CLK
0.31/
–0.02
0.36/
–0.02
0.44/
–0.02
0.44/
0.02
0.36/
–0.02
0.58/
0.12
ns
TDSPDCK_CEM_MREG/
TDSPCKD_CEM_MREG
CEM input to M register CLK
0.26/
0.15
0.29/
0.17
0.33/
0.20
0.33/
0.20
0.29/
0.17
0.39/
0.25
ns
TDSPDCK_CEP_PREG/
TDSPCKD_CEP_PREG
CEP input to P register CLK
0.31/
0.01
0.36/
0.01
0.45/
0.01
0.45/
0.01
0.36/
0.01
0.54/
0.00
ns
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 35: DSP48E1 Switching Characteristics (Cont’d)
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
Setup and Hold Times of the RST Pins
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/
TDSPCKD_{RSTA; RSTB}_{AREG; BREG}
{RSTA, RSTB} input to {A, B}
register CLK
0.34/
0.10
0.39/
0.11
0.47/
0.13
0.47/
0.14
0.39/
0.11
0.53/
0.34
ns
TDSPDCK_RSTC_CREG/
TDSPCKD_RSTC_CREG
RSTC input to C register CLK
0.06/
0.22
0.07/
0.24
0.08/
0.26
0.08/
0.26
0.07/
0.24
0.08/
0.31
ns
TDSPDCK_RSTD_DREG/
TDSPCKD_RSTD_DREG
RSTD input to D register CLK
0.37/
0.06
0.42/
0.06
0.50/
0.07
0.50/
0.07
0.42/
0.06
0.57/
0.07
ns
TDSPDCK_RSTM_MREG/
TDSPCKD_RSTM_MREG
RSTM input to M register CLK
0.18/
0.18
0.20/
0.21
0.23/
0.24
0.23/
0.24
0.20/
0.21
0.24/
0.29
ns
TDSPDCK_RSTP_PREG/
TDSPCKD_RSTP_PREG
RSTP input to P register CLK
0.24/
0.01
0.26/
0.01
0.30/
0.01
0.30/
0.11
0.26/
0.01
0.37/
0.00
ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT
A input to CARRYOUT output
using multiplier
3.21
3.69
4.39
4.39
3.69
5.60
ns
TDSPDO_D_P_MULT
D input to P output using
multiplier
3.15
3.61
4.30
4.30
3.61
5.44
ns
TDSPDO_A_P
A input to P output not using
multiplier
1.30
1.48
1.76
1.76
1.48
2.10
ns
TDSPDO_C_P
C input to P output
1.13
1.30
1.55
1.55
1.30
1.84
ns
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT,
BCOUT} output
0.47
0.53
0.63
0.63
0.53
0.75
ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT
{A, B} input to
CARRYCASCOUT output
using multiplier
3.44
3.94
4.69
4.69
3.94
5.96
ns
TDSPDO_D_CARRYCASCOUT_MULT
D input to CARRYCASCOUT
output using multiplier
3.36
3.85
4.58
4.58
3.85
5.77
ns
TDSPDO_{A, B}_CARRYCASCOUT
{A, B} input to
CARRYCASCOUT output not
using multiplier
1.50
1.72
2.04
2.04
1.72
2.44
ns
TDSPDO_C_CARRYCASCOUT
C input to CARRYCASCOUT
output
1.34
1.53
1.83
1.83
1.53
2.18
ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT
ACIN input to P output using
multiplier
3.09
3.55
4.24
4.24
3.55
5.42
ns
TDSPDO_ACIN_P
ACIN input to P output not
using multiplier
1.16
1.33
1.59
1.59
1.33
2.07
ns
TDSPDO_ACIN_ACOUT
ACIN input to ACOUT output
0.32
0.37
0.45
0.45
0.37
0.53
ns
TDSPDO_ACIN_CARRYCASCOUT_MULT
ACIN input to
CARRYCASCOUT output
using multiplier
3.30
3.79
4.52
4.52
3.79
5.76
ns
TDSPDO_ACIN_CARRYCASCOUT
ACIN input to
CARRYCASCOUT output not
using multiplier
1.37
1.57
1.87
1.87
1.57
2.40
ns
TDSPDO_PCIN_P
PCIN input to P output
0.94
1.08
1.29
1.29
1.08
1.54
ns
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 35: DSP48E1 Switching Characteristics (Cont’d)
Speed Grade
Symbol
TDSPDO_PCIN_CARRYCASCOUT
1.0V
Description
PCIN input to
CARRYCASCOUT output
0.95V
0.9V
-2LI
-2LE
Units
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
1.15
1.32
1.57
1.57
1.32
1.88
ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG
CLK PREG to P output
0.33
0.35
0.39
0.39
0.35
0.45
ns
TDSPCKO_CARRYCASCOUT_PREG
CLK PREG to
CARRYCASCOUT output
0.44
0.50
0.59
0.59
0.50
0.71
ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG
CLK MREG to P output
1.42
1.64
1.96
1.96
1.64
2.31
ns
TDSPCKO_CARRYCASCOUT_MREG
CLK MREG to
CARRYCASCOUT output
1.63
1.87
2.24
2.24
1.87
2.65
ns
TDSPCKO_P_ADREG_MULT
CLK ADREG to P output using
multiplier
2.30
2.63
3.13
3.13
2.63
3.90
ns
TDSPCKO_CARRYCASCOUT_
ADREG_MULT
CLK ADREG to
CARRYCASCOUT output
using multiplier
2.51
2.87
3.41
3.41
2.87
4.23
ns
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_P_AREG_MULT
CLK AREG to P output using
multiplier
3.34
3.83
4.55
4.55
3.83
5.80
ns
TDSPCKO_P_BREG
CLK BREG to P output not
using multiplier
1.39
1.59
1.88
1.88
1.59
2.24
ns
TDSPCKO_P_CREG
CLK CREG to P output not
using multiplier
1.43
1.64
1.95
1.95
1.64
2.32
ns
TDSPCKO_P_DREG_MULT
CLK DREG to P output using
multiplier
3.32
3.80
4.51
4.51
3.80
5.74
ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}
_{AREG; BREG}
CLK (ACOUT, BCOUT) to
{A,B} register output
0.55
0.62
0.74
0.74
0.62
0.87
ns
TDSPCKO_CARRYCASCOUT_
{AREG, BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output
using multiplier
3.55
4.06
4.84
4.84
4.06
6.13
ns
TDSPCKO_CARRYCASCOUT_ BREG
CLK BREG to
CARRYCASCOUT output not
using multiplier
1.60
1.82
2.16
2.16
1.82
2.58
ns
TDSPCKO_CARRYCASCOUT
_ DREG_MULT
CLK DREG to
CARRYCASCOUT output
using multiplier
3.52
4.03
4.79
4.79
4.03
6.07
ns
TDSPCKO_CARRYCASCOUT_ CREG
CLK CREG to
CARRYCASCOUT output
1.64
1.88
2.23
2.23
1.88
2.65
ns
Maximum Frequency
FMAX
With all registers used
741.84
650.20 547.95
547.95
650.20
429.37
MHz
FMAX_PATDET
With pattern detector
627.35
549.75 463.61
463.61
549.75
365.90
MHz
FMAX_MULT_NOMREG
Two register multiply without
MREG
412.20
360.75 303.77
303.77
360.75
248.32
MHz
FMAX_MULT_NOMREG_PATDET
Two register multiply without
MREG with pattern detect
374.25
327.65 276.01
276.01
327.65
225.73
MHz
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 35: DSP48E1 Switching Characteristics (Cont’d)
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
0.95V
0.9V
-1M/-1LM/
-1Q
-2LI
-2LE
Units
FMAX_PREADD_MULT_NOADREG
Without ADREG
468.82
408.66 342.70
342.70
408.66
263.44
MHz
FMAX_PREADD_MULT_
NOADREG_PATDET
Without ADREG with pattern
detect
468.82
408.66 342.70
342.70
408.66
263.44
MHz
FMAX_NOPIPELINEREG
Without pipeline registers
(MREG, ADREG)
306.84
267.81 225.02
225.02
267.81
177.15
MHz
FMAX_NOPIPELINEREG_PATDET
Without pipeline registers
(MREG, ADREG) with pattern
detect
285.23
249.13 209.38
209.38
249.13
165.32
MHz
Clock Buffers and Networks
Table 36: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
Symbol
Description
1.0V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
0.95V
0.9V
-2LI
-2LE
Units
TBCCCK_CE/
TBCCKC_CE(1)
CE pins Setup/Hold
0.12/0.30 0.14/0.38 0.26/0.38
0.26/0.92
0.14/0.38 0.23/0.40
ns
TBCCCK_S/
TBCCKC_S(1)
S pins Setup/Hold
0.12/0.30 0.14/0.38 0.26/0.38
0.26/0.92
0.14/0.38 0.23/0.40
ns
TBCCKO_O(2)
BUFGCTRL delay from I0/I1 to O
0.08
0.10
0.12
0.12
0.10
0.10
ns
741.00
710.00
625.00
625.00
710.00
560.00
MHz
Maximum Frequency
FMAX_BUFG
Global clock tree (BUFG)
Notes:
1.
2.
TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 37: Input/Output Clock Switching Characteristics (BUFIO)
Speed Grade
Symbol
TBIOCKO_O
Description
Clock to out delay from I to O
1.0V
0.95V
0.9V
Units
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
1.04
1.14
1.32
1.32
1.14
1.48
ns
800.00
800.00
710.00
710.00
800.00
710.00
MHz
Maximum Frequency
FMAX_BUFIO
I/O clock tree (BUFIO)
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 38: Regional Clock Buffer Switching Characteristics (BUFR)
Speed Grade
Symbol
Description
1.0V
0.95V
0.9V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
Units
TBRCKO_O
Clock to out delay from
I to O
0.60
0.65
0.77
0.77
0.65
1.06
ns
TBRCKO_O_BYP
Clock to out delay from I to O with
Divide Bypass attribute set
0.30
0.32
0.38
0.38
0.32
0.57
ns
TBRDO_O
Propagation delay from CLR to O
0.71
0.75
0.96
0.96
0.75
0.93
ns
600.00
540.00
450.00
450.00
540.00
450.00
MHz
Maximum Frequency
FMAX_BUFR(1)
Regional clock tree (BUFR)
Notes:
1.
The maximum input frequency to the BUFR and BUFMR is the BUFIO FMAX frequency except for the BUFMR in the -2LE at 0.9V, which has
a maximum input frequency of 667 MHz.
Table 39: Horizontal Clock Buffer Switching Characteristics (BUFH)
Speed Grade
Symbol
Description
TBHCKO_O
BUFH delay from I to O
TBHCCK_CE/
TBHCKC_CE
CE pin Setup and Hold
1.0V
0.95V
0.9V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
0.10
0.11
0.13
0.13
0.11
0.12
0.20/0.16 0.23/0.20 0.38/0.21
0.38/0.79
0.23/0.20 0.28/0.09
Units
ns
ns
Maximum Frequency
FMAX_BUFH
Horizontal clock buffer (BUFH)
741.00
710.00
625.00
625.00
710.00
560.00
MHz
0.95V
0.9V
Units
Table 40: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Symbol
Description
Device
1.0V
-3
-2/-2LE
-1
-1M/-1LM
-1Q
-2LI
-2LE
0.20
0.20
0.20
0.20
0.20
0.20
0.25
ns
0.29
0.40
0.40
N/A
N/A
N/A
0.47
ns
XC7K160T
0.42
0.53
0.57
N/A
N/A
0.53
0.59
ns
XC7K325T
0.59
0.74
0.79
N/A
N/A
0.74
0.91
ns
XC7K355T
0.45
0.57
0.59
N/A
N/A
0.57
0.69
ns
XC7K410T
0.60
0.74
0.79
N/A
N/A
0.74
0.91
ns
XC7K420T
0.60
0.74
0.79
N/A
N/A
0.74
0.91
ns
XC7K480T
0.60
0.74
0.79
N/A
N/A
0.74
0.91
ns
XA7K160T
N/A
N/A
N/A
N/A
0.57
N/A
N/A
ns
XQ7K325T
N/A
0.74
0.79
0.79
N/A
0.74
0.91
ns
XQ7K410T
N/A
0.74
0.79
0.79
N/A
0.74
0.91
ns
TDCD_CLK
Global Clock Tree Duty
Cycle Distortion(1)
All
TCKSKEW
Global Clock Tree Skew(2) XC7K70T
TDCD_BUFIO
I/O clock tree duty cycle
distortion
All
0.12
0.12
0.12
0.12
0.12
0.12
0.12
ns
TBUFIOSKEW
I/O clock tree skew across
one clock region
All
0.02
0.02
0.02
0.02
0.02
0.02
0.03
ns
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 40: Duty Cycle Distortion and Clock-Tree Skew (Cont’d)
Speed Grade
Symbol
TDCD_BUFR
Description
Device
Regional clock tree duty
cycle distortion
All
1.0V
0.95V
0.9V
-3
-2/-2LE
-1
-1M/-1LM
-1Q
-2LI
-2LE
0.15
0.15
0.15
0.15
0.15
0.15
0.15
Units
ns
Notes:
1.
2.
These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to
calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer
tools to evaluate clock skew specific to your application.
MMCM Switching Characteristics
Table 41: MMCM Specification
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
MMCM_FINMAX
Maximum Input Clock
Frequency
1066.00
933.00
800.00
800.00
933.00
800.00
MHz
MMCM_FINMIN
Minimum Input Clock
Frequency
10.00
10.00
10.00
10.00
10.00
10.00
MHz
MMCM_FINJITTER
Maximum Input Clock Period
Jitter
MMCM_FINDUTY
Allowable Input Duty Cycle:
10–49 MHz
25.00
25.00
25.00
25.00
25.00
25.00
%
Allowable Input Duty Cycle:
50–199 MHz
30.00
30.00
30.00
30.00
30.00
30.00
%
Allowable Input Duty Cycle:
200–399 MHz
35.00
35.00
35.00
35.00
35.00
35.00
%
Allowable Input Duty Cycle:
400–499 MHz
40.00
40.00
40.00
40.00
40.00
40.00
%
Allowable Input Duty Cycle:
>500 MHz
45.00
45.00
45.00
45.00
45.00
45.00
%
MMCM_FMIN_PSCLK
Minimum Dynamic Phase Shift
Clock Frequency
0.01
0.01
0.01
0.01
0.01
0.01
MHz
MMCM_FMAX_PSCLK
Maximum Dynamic Phase
Shift Clock Frequency
550.00
500.00
450.00
450.00
500.00
450.00
MHz
MMCM_FVCOMIN
Minimum MMCM VCO
Frequency
600.00
600.00
600.00
600.00
600.00
600.00
MHz
MMCM_FVCOMAX
Maximum MMCM VCO
Frequency
1600.00
1440.00
1200.00
1200.00
1440.00
1200.00
MHz
MMCM_FBANDWIDTH
Low MMCM Bandwidth at
Typical(1)
1.00
1.00
1.00
1.00
1.00
1.00
MHz
High MMCM Bandwidth at
Typical(1)
4.00
4.00
4.00
4.00
4.00
4.00
MHz
MMCM_TSTATPHAOFFSET Static Phase Offset of the
MMCM Outputs(2)
0.12
0.12
0.12
0.12
0.12
0.12
ns
MMCM_TOUTJITTER
< 20% of clock input period or 1 ns Max
MMCM Output Jitter
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 41: MMCM Specification (Cont’d)
Speed Grade
Symbol
1.0V
Description
0.95V
0.9V
-2LI
-2LE
Units
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.20
0.20
0.20
0.20
0.20
0.25
ns
MMCM_TOUTDUTY
MMCM Output Clock Duty
Cycle Precision(4)
MMCM_TLOCKMAX
MMCM Maximum Lock Time
100.00
100.00
100.00
100.00
100.00
100.00
µs
MMCM_FOUTMAX
MMCM Maximum Output
Frequency
1066.00
933.00
800.00
800.00
933.00
800.00
MHz
MMCM_FOUTMIN
MMCM Minimum Output
Frequency(5)(6)
4.69
4.69
4.69
4.69
4.69
4.69
MHz
MMCM_TEXTFDVAR
External Clock Feedback
Variation
MMCM_RSTMINPULSE
Minimum Reset Pulse Width
5.00
5.00
5.00
5.00
5.00
5.00
ns
MMCM_FPFDMAX
Maximum Frequency at the
Phase Frequency Detector
550.00
500.00
450.00
450.00
500.00
450.00
MHz
MMCM_FPFDMIN
Minimum Frequency at the
Phase Frequency Detector
10.00
10.00
10.00
10.00
10.00
10.00
MHz
MMCM_TFBDELAY
Maximum Delay in the
Feedback Path
< 20% of clock input period or 1 ns Max
3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold
TMMCMDCK_PSEN/
TMMCMCKD_PSEN
Setup and Hold of Phase Shift 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00
Enable
ns
TMMCMDCK_PSINCDEC/
TMMCMCKD_PSINCDEC
Setup and Hold of Phase Shift 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00
Increment/Decrement
ns
TMMCMCKO_PSDONE
Phase Shift Clock-to-Out of
PSDONE
ns
0.59
0.68
0.81
0.81
0.68
0.78
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
TMMCMDCK_DADDR/
TMMCMCKD_DADDR
DADDR Setup/Hold
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00
ns, Min
TMMCMDCK_DI/
TMMCMCKD_DI
DI Setup/Hold
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00
ns, Min
TMMCMDCK_DEN/
TMMCMCKD_DEN
DEN Setup/Hold
1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 1.97/0.00 2.40/0.00
ns, Min
TMMCMDCK_DWE/
TMMCMCKD_DWE
DWE Setup/Hold
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00
ns, Min
TMMCMCKO_DRDY
CLK to out of DRDY
FDCK
DCLK frequency
0.65
0.72
0.99
0.99
0.72
200.00
200.00
200.00
200.00
200.00
0.70
ns, Max
100.00 MHz, Max
Notes:
1.
2.
3.
4.
5.
6.
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any MMCM outputs with identical phase.
Values for this parameter are available in the Clocking Wizard.
See www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
Includes global clock buffer.
Calculated as FVCO/128 assuming output duty cycle is 50%.
When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
PLL Switching Characteristics
Table 42: PLL Specification
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
PLL_FINMAX
Maximum Input Clock Frequency
1066.00
933.00
800.00
800.00
933.00
800.00
MHz
PLL_FINMIN
Minimum Input Clock Frequency
19.00
19.00
19.00
19.00
19.00
19.00
MHz
PLL_FINJITTER
Maximum Input Clock Period
Jitter
PLL_FINDUTY
Allowable Input Duty Cycle:
19–49 MHz
25.00
25.00
25.00
25.00
25.00
25.00
%
Allowable Input Duty Cycle:
50–199 MHz
30.00
30.00
30.00
30.00
30.00
30.00
%
Allowable Input Duty Cycle:
200–399 MHz
35.00
35.00
35.00
35.00
35.00
35.00
%
Allowable Input Duty Cycle:
400–499 MHz
40.00
40.00
40.00
40.00
40.00
40.00
%
Allowable Input Duty Cycle:
>500 MHz
45.00
45.00
45.00
45.00
45.00
45.00
%
PLL_FVCOMIN
Minimum PLL VCO Frequency
800.00
800.00
800.00
800.00
800.00
800.00
MHz
PLL_FVCOMAX
Maximum PLL VCO Frequency
2133.00
1866.00
1600.00
1600.00
1866.00
1600.00
MHz
PLL_FBANDWIDTH
Low PLL Bandwidth at Typical(1)
1.00
1.00
1.00
1.00
1.00
1.00
MHz
High PLL Bandwidth at Typical(1)
4.00
4.00
4.00
4.00
4.00
4.00
MHz
0.12
0.12
0.12
0.12
0.12
0.12
ns
PLL_TSTATPHAOFFSET Static Phase Offset of the PLL
Outputs(2)
< 20% of clock input period or 1 ns Max
PLL_TOUTJITTER
PLL Output Jitter
Note 3
PLL_TOUTDUTY
PLL Output Clock Duty Cycle
Precision(4)
0.20
0.20
0.20
0.20
0.20
0.25
ns
PLL_TLOCKMAX
PLL Maximum Lock Time
100
100
100
100
100
100
µs
PLL_FOUTMAX
PLL Maximum Output Frequency 1066.00
933.00
800.00
800.00
933.00
800.00
MHz
PLL_FOUTMIN
PLL Minimum Output
Frequency(5)
6.25
6.25
6.25
6.25
6.25
MHz
PLL_TEXTFDVAR
External Clock Feedback
Variation
PLL_RSTMINPULSE
Minimum Reset Pulse Width
5.00
5.00
5.00
5.00
5.00
5.00
ns
PLL_FPFDMAX
Maximum Frequency at the
Phase Frequency Detector
550.00
500.00
450.00
450.00
500.00
450.00
MHz
PLL_FPFDMIN
Minimum Frequency at the Phase
Frequency Detector
19.00
19.00
19.00
19.00
19.00
19.00
MHz
PLL_TFBDELAY
Maximum Delay in the Feedback
Path
6.25
< 20% of clock input period or 1 ns Max
3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
TPLLCCK_DADDR/
TPLLCKC_DADDR
Setup and hold of D address
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00
ns, Min
TPLLCCK_DI/
TPLLCKC_DI
Setup and hold of D input
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00
ns, Min
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 42: PLL Specification (Cont’d)
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1
-1M/-1LM/
-1Q
0.95V
0.9V
-2LI
-2LE
Units
TPLLCCK_DEN/
TPLLCKC_DEN
Setup and hold of D enable
1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 1.97/0.00 2.40/0.00
ns, Min
TPLLCCK_DWE/
TPLLCKC_DWE
Setup and hold of D write enable 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00
ns, Min
TPLLCKO_DRDY
CLK to out of DRDY
FDCK
DCLK frequency
0.65
0.72
0.99
0.99
0.72
0.70
ns, Max
200.00
200.00
200.00
200.00
200.00
100.00
MHz, Max
Notes:
1.
2.
3.
4.
5.
The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any PLL outputs with identical phase.
Values for this parameter are available in the Clocking Wizard.
See www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
Includes global clock buffer.
Calculated as FVCO/128 assuming output duty cycle is 50%.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Output Parameter Guidelines
Table 43: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Speed Grade
Symbol
Description
Device
1.0V
-3
-2/-2LE
-1
-1M/-1LM
-1Q
0.95V
0.9V
-2LI
-2LE
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOF
Clock-capable clock input and XC7K70T
OUTFF at pins/banks closest to
the BUFGs without MMCM/PLL XC7K160T
(near clock region)
XC7K325T
4.98
5.49
6.17
N/A
N/A
N/A
7.04
ns
5.23
5.77
6.48
N/A
N/A
5.77
7.38
ns
5.72
6.31
7.09
N/A
N/A
6.31
8.07
ns
XC7K355T
5.34
5.87
6.57
N/A
N/A
5.87
7.51
ns
XC7K410T
5.84
6.44
7.22
N/A
N/A
6.44
8.21
ns
XC7K420T
5.50
6.04
6.77
N/A
N/A
6.04
7.73
ns
XC7K480T
5.50
6.04
6.77
N/A
N/A
6.04
7.73
ns
XA7K160T
N/A
N/A
N/A
N/A
6.48
N/A
N/A
ns
XQ7K325T
N/A
6.31
7.09
7.09
N/A
6.31
8.07
ns
XQ7K410T
N/A
6.44
7.22
7.22
N/A
6.44
8.21
ns
Notes:
1.
2.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475).
Table 44: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Speed Grade
Symbol
Description
Device
1.0V
-3
-2/-2LE
-1
-1M/-1LM
-1Q
0.95V
0.9V
-2LI
-2LE
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOFFAR
Clock-capable clock input
and OUTFF at pins/banks
farthest from the BUFGs
without MMCM/PLL (far
clock region)
XC7K70T
5.29
5.83
6.55
N/A
N/A
N/A
7.47
ns
XC7K160T
5.84
6.45
7.24
N/A
N/A
6.45
8.24
ns
XC7K325T
6.33
6.99
7.84
N/A
N/A
6.99
8.92
ns
XC7K355T
5.95
6.55
7.32
N/A
N/A
6.55
8.36
ns
XC7K410T
6.45
7.12
7.97
N/A
N/A
7.12
9.07
ns
XC7K420T
6.41
7.06
7.90
N/A
N/A
7.06
9.01
ns
XC7K480T
6.41
7.06
7.90
N/A
N/A
7.06
9.01
ns
XA7K160T
N/A
N/A
N/A
N/A
7.24
N/A
N/A
ns
XQ7K325T
N/A
6.99
7.84
7.84
N/A
6.99
8.92
ns
XQ7K410T
N/A
7.12
7.97
7.97
N/A
7.12
9.07
ns
Notes:
1.
2.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475).
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 45: Clock-Capable Clock Input to Output Delay With MMCM
Speed Grade
Symbol
Description
Device
1.0V
-3
-2/-2LE
-1
-1M/-1LM
-1Q
0.95V
0.9V
-2LI
-2LE
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
TICKOFMMCMCC
Clock-capable clock input
and OUTFF with MMCM
XC7K70T
0.95
0.95
0.95
N/A
N/A
N/A
1.74
ns
XC7K160T
0.96
0.96
0.96
N/A
N/A
0.96
1.78
ns
XC7K325T
1.00
1.00
1.00
N/A
N/A
1.00
1.82
ns
XC7K355T
1.00
1.00
1.00
N/A
N/A
1.00
1.78
ns
XC7K410T
1.00
1.00
1.00
N/A
N/A
1.00
1.82
ns
XC7K420T
1.07
1.07
1.07
N/A
N/A
1.07
1.82
ns
XC7K480T
1.07
1.07
1.07
N/A
N/A
1.07
1.82
ns
XA7K160T
N/A
N/A
N/A
N/A
0.96
N/A
N/A
ns
XQ7K325T
N/A
1.00
1.00
1.00
N/A
1.00
1.82
ns
XQ7K410T
N/A
1.00
1.00
1.00
N/A
1.00
1.82
ns
Notes:
1.
2.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
MMCM output jitter is already included in the timing calculation.
Table 46: Clock-Capable Clock Input to Output Delay With PLL
Speed Grade
Symbol
Description
Device
1.0V
-3
-2/-2LE
-1
-1M/-1LM
0.95V
0.9V
-1Q
-2LI
-2LE
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
TICKOFPLLCC
Clock-capable clock input
and OUTFF with PLL
XC7K70T
0.84
0.84
0.84
N/A
N/A
N/A
1.45
ns
XC7K160T
0.89
0.89
0.89
N/A
N/A
0.89
1.54
ns
XC7K325T
0.89
0.89
0.89
N/A
N/A
0.89
1.54
ns
XC7K355T
0.89
0.89
0.89
N/A
N/A
0.89
1.50
ns
XC7K410T
0.89
0.89
0.89
N/A
N/A
0.89
1.54
ns
XC7K420T
0.96
0.96
0.96
N/A
N/A
0.96
1.54
ns
XC7K480T
0.96
0.96
0.96
N/A
N/A
0.96
1.54
ns
XA7K160T
N/A
N/A
N/A
N/A
0.89
N/A
N/A
ns
XQ7K325T
N/A
0.89
0.89
0.89
N/A
0.89
1.54
ns
XQ7K410T
N/A
0.89
0.89
0.89
N/A
0.89
1.54
ns
Notes:
1.
2.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
PLL output jitter is already included in the timing calculation.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 47: Pin-to-Pin, Clock-to-Out using BUFIO
Speed Grade
Symbol
Description
1.0V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
0.95V
0.9V
-2LI
-2LE
Units
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.
TICKOFCS
Clock-to-Out of I/O clock for HR I/O banks
4.93
5.52
6.20
6.20
5.52
6.97
ns
Clock-to-Out of I/O clock for HP I/O banks
4.85
5.44
6.11
6.11
5.44
6.90
ns
Device Pin-to-Pin Input Parameter Guidelines
Table 48: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Speed Grade
Symbol
Description
Device
1.0V
-3
-2/-2LE
-1
-1M/-1LM
0.95V
0.9V
-1Q
-2LI
-2LE
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
XC7K70T
TPSFD/TPHFD Full Delay (Legacy
Delay or Default Delay)
Global Clock Input and
XC7K160T
IFF(2) without
MMCM/PLL with
ZHOLD_DELAY on HR XC7K325T
I/O Banks
2.83/
–0.29
2.95/
–0.29
3.15/
–0.29
N/A
N/A
N/A
4.96/
–0.33
ns
3.17/
–0.35
3.29/
–0.35
3.55/
–0.35
N/A
N/A
3.29/
–0.35
5.54/
–0.49
ns
2.83/
–0.06
2.94/
–0.06
3.15/
–0.06
N/A
N/A
2.94/
–0.06
5.18/
–0.14
ns
XC7K355T
3.26/
–0.32
3.41/
–0.32
3.67/
–0.32
N/A
N/A
3.41/
–0.32
5.84/
–0.49
ns
XC7K410T
3.43/
–0.34
3.59/
–0.34
3.88/
–0.34
N/A
N/A
3.59/
–0.34
6.21/
–0.54
ns
XC7K420T
3.37/
–0.27
3.48/
–0.27
3.76/
–0.27
N/A
N/A
3.48/
–0.27
6.00/
–0.52
ns
XC7K480T
3.37/
–0.27
3.48/
–0.27
3.76/
–0.27
N/A
N/A
3.48/
–0.27
6.00/
–0.52
ns
XA7K160T
N/A
N/A
N/A
N/A
3.55/
–0.35
N/A
N/A
ns
XQ7K325T
N/A
2.94/
–0.06
3.15/
–0.06
3.15/
–0.06
N/A
2.94/
–0.06
5.18/
–0.14
ns
XQ7K410T
N/A
3.59/
–0.34
3.88/
–0.34
3.88/
–0.34
N/A
3.59/
–0.34
6.21/
–0.54
ns
Notes:
1.
2.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 49: Clock-Capable Clock Input Setup and Hold With MMCM
Speed Grade
Symbol
Description
Device
1.0V
-3
-2/-2LE
-1
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15
TPSMMCMCC/ No Delay clockXC7K70T
TPHMMCMCC capable clock input and
IFF(2) with MMCM
XC7K160T
-1M/-1LM
0.95V
0.9V
-1Q
-2LI
-2LE
Units
Standard.(1)
2.39/
–0.22
2.65/
–0.22
2.94/
–0.22
N/A
N/A
N/A
2.21/
–0.44
ns
2.49/
–0.20
2.77/
–0.20
3.07/
–0.20
N/A
N/A
2.77/
–0.20
2.38/
–0.47
ns
XC7K325T
2.55/
–0.16
2.85/
–0.16
3.14/
–0.16
N/A
N/A
2.85/
–0.16
2.60/
–0.47
ns
XC7K355T
2.43/
–0.16
2.73/
–0.16
3.00/
–0.16
N/A
N/A
2.73/
–0.16
2.47/
–0.43
ns
XC7K410T
2.55/
–0.16
2.84/
–0.16
3.14/
–0.16
N/A
N/A
2.84/
–0.16
2.58/
–0.47
ns
XC7K420T
2.47/
–0.09
2.73/
–0.09
3.02/
–0.09
N/A
N/A
2.73/
–0.09
2.40/
–0.41
ns
XC7K480T
2.47/
–0.09
2.73/
–0.09
3.02/
–0.09
N/A
N/A
2.73/
–0.09
2.40/
–0.41
ns
XA7K160T
N/A
N/A
N/A
N/A
3.07/
–0.20
N/A
N/A
ns
XQ7K325T
N/A
2.85/
–0.16
3.14/
–0.16
3.14/
–0.16
N/A
2.85/
–0.16
2.60/
–0.47
ns
XQ7K410T
N/A
2.84/
–0.16
3.14/
–0.16
3.14/
–0.16
N/A
2.84/
–0.16
2.58/
–0.47
ns
Notes:
1.
2.
3.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 50: Clock-Capable Clock Input Setup and Hold With PLL
Speed Grade
Symbol
Description
Device
1.0V
-3
-2/-2LE
-1
-1M/-1LM
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15
TPSPLLCC/
TPHPLLCC
0.95V
0.9V
-1Q
-2LI
-2LE
Units
Standard.(1)
No Delay clock-capable XC7K70T
clock input and IFF(2)
with PLL
XC7K160T
2.75/
–0.32
3.04/
–0.32
3.33/
–0.32
N/A
N/A
N/A
2.42/
–0.54
ns
2.85/
–0.31
3.16/
–0.31
3.46/
–0.31
N/A
N/A
3.16/
–0.31
2.59/
–0.56
ns
XC7K325T
2.91/
–0.27
3.24/
–0.27
3.54/
–0.27
N/A
N/A
3.24/
–0.27
2.80/
–0.56
ns
XC7K355T
2.79/
–0.27
3.12/
–0.27
3.40/
–0.27
N/A
N/A
3.12/
–0.27
2.67/
–0.52
ns
XC7K410T
2.91/
–0.27
3.24/
–0.27
3.53/
–0.27
N/A
N/A
3.24/
–0.27
2.78/
–0.56
ns
XC7K420T
2.83/
–0.20
3.12/
–0.20
3.41/
–0.20
N/A
N/A
3.12/
–0.20
2.61/
–0.50
ns
XC7K480T
2.83/
–0.20
3.12/
–0.20
3.41/
–0.20
N/A
N/A
3.12/
–0.20
2.61/
–0.50
ns
XA7K160T
N/A
N/A
N/A
N/A
3.46/
–0.31
N/A
N/A
ns
XQ7K325T
N/A
3.24/
–0.27
3.54/
–0.27
3.54/
–0.27
N/A
3.24/
–0.27
2.80/
–0.56
ns
XQ7K410T
N/A
3.24/
–0.27
3.53/
–0.27
3.53/
–0.27
N/A
3.24/
–0.27
2.78/
–0.56
ns
Notes:
1.
2.
3.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 51: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Speed Grade
Symbol
Description
1.0V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
0.95V
0.9V
-2LI
-2LE
Units
Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.
TPSCS/TPHCS
Setup/Hold of I/O clock for
HR I/O banks
–0.36/1.36 –0.36/1.50 –0.36/1.70
–0.36/1.70
–0.36/1.50
–0.44/1.87
ns
Setup/Hold of I/O clock for
HP I/O banks
–0.34/1.39 –0.34/1.53 –0.34/1.73
–0.34/1.73
–0.34/1.53
–0.44/1.87
ns
0.95V
0.9V
Units
Table 52: Sample Window
Speed Grade
Symbol
TSAMP
Description
Sampling Error at Receiver Pins(1)
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1.0V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
0.51
0.56
0.61
0.61
0.56
0.56
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54
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 52: Sample Window (Cont’d)
Speed Grade
Symbol
TSAMP_BUFIO
Description
Sampling Error at Receiver Pins using
BUFIO(2)
1.0V
0.95V
0.9V
-3
-2/-2LE
-1
-1M/-1LM/-1Q
-2LI
-2LE
0.30
0.35
0.40
0.40
0.35
0.35
Units
ns
Notes:
1.
2.
This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Additional Package Parameter Guidelines
The parameters in this section provide the necessary values for calculating timing budgets for Kintex-7 FPGA clock
transmitter and receiver data-valid windows.
Table 53: Package Skew
Symbol
TPKGSKEW
Description
Package
Skew(1)
Device
XC7K70T
XC7K160T
XC7K325T
Package
Value
Units
FBG484
108
ps
FBG676
135
ps
FBG484
118
ps
FBG676
136
ps
FFG676
161
ps
FBG676
146
ps
FFG676
154
ps
FBG900
163
ps
FFG900
161
ps
XC7K355T
FFG901
149
ps
XC7K410T
FBG676
165
ps
XC7K420T
XC7K480T
FFG676
168
ps
FBG900
151
ps
FFG900
146
ps
FFG901
149
ps
FFG1156
145
ps
FFG901
149
ps
FFG1156
145
ps
XA7K160T
FFG676
161
ps
XQ7K325T
RF676
154
ps
RF900
161
ps
RF676
168
ps
RF900
146
ps
XQ7K410T
Notes:
1.
2.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die
pad to ball.
Package delay information is available for these device/package combinations. This information can be used to deskew the package.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
GTX Transceiver Specifications
GTX Transceiver DC Input and Output Levels
Table 54 summarizes the DC output specifications of the GTX transceivers in Kintex-7 FPGAs. Consult the 7 Series FPGAs
GTX/GTH Transceivers User Guide (UG476) for further details.
Table 54: GTX Transceiver DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
1000
–
–
mV
DVPPOUT
Differential peak-to-peak output Transmitter output swing is set to
voltage (1)
maximum setting
VCMOUTDC
DC common mode output
voltage.
ROUT
Differential output resistance
–
100
–
Ω
TOSKEW
Transmitter output pair (TXP and TXN) intra-pair skew
–
2
12
ps
>10.3125 Gb/s
150
–
1250
mV
6.6 Gb/s to 10.3125 Gb/s
150
–
1250
mV
Differential peak-to-peak input
voltage (external AC coupled)
DVPPIN
Equation based
VMGTAVTT – DVPPOUT/4
mV
≤ 6.6 Gb/s
150
–
2000
mV
VIN
Single-ended input
voltage(2)
DC coupled VMGTAVTT = 1.2V
–200
–
VMGTAVTT
mV
VCMIN
Common mode input voltage
DC coupled VMGTAVTT = 1.2V
–
2/3 VMGTAVTT
–
mV
RIN
Differential input resistance
–
100
–
Ω
–
100
–
nF
CEXT
Recommended external AC coupling
capacitor(3)
Notes:
1.
2.
3.
The output swing and preemphasis levels are programmable using the attributes discussed in the 7 Series FPGAs GTX/GTH Transceivers
User Guide (UG476) and can result in values lower than reported in this table.
Voltage measured at the pin referenced to ground.
Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 3
+V
P
Single-Ended
Peak-to-Peak
Voltage
N
0
DS182_01_071014
Figure 3: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 4
+V
Differential
Peak-to-Peak
Voltage
0
–V
P–N
DS182_02_071014
Figure 4: Differential Peak-to-Peak Voltage
Note: In Figure 4, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 55 summarizes the DC specifications of the clock input of the GTX transceiver. Consult the 7 Series FPGAs GTX/GTH
Transceivers User Guide (UG476) for further details.
Table 55: GTX Transceiver Clock DC Input Level Specification
Symbol
DC Parameter
Min
Typ
Max
Units
250
–
2000
mV
VIDIFF
Differential peak-to-peak input voltage
RIN
Differential input resistance
–
100
–
Ω
CEXT
Required external AC coupling capacitor
–
100
–
nF
GTX Transceiver Switching Characteristics
Consult the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) for further information.
Table 56: GTX Transceiver Performance
Speed Grade(1)
-2 (1.0V)
-2LE (1.0V)
-2LI (0.95V)
-3 (1.0V)
Symbol
Description
Output
Divider
Package Type
FF
FBG676
FBG484 FBG676
RF
FBG900 FBG484 FBG900
FF
FGTXMAX(4)
Maximum GTX transceiver
data rate
12.5(5) 10.3125(6)
FGTXMIN(4)
Minimum GTX transceiver
data rate
0.500
FGTXCRANGE
CPLL line rate range
QPLL line rate
range 1
0.500
FF
RF
FB
FF
RF
FB
6.6
6.6
10.3125(6)
6.6
8.0
6.6
6.6
0.500
0.500
0.500
0.500
0.500
0.500
Gb/s
0.500 Gb/s
1
3.2–6.6
Gb/s
2
1.6–3.3
Gb/s
4
0.8–1.65
Gb/s
8
0.5–0.825
Gb/s
16
N/A
Gb/s
1
FGTXQRANGE1
-1 (1.0V)(2)
-1M (1.0V)(2) -2LE (0.9V)(3)
-1LM (1.0V)(2)
-1Q (1.0V)(2)
Units
5.93–
8.0
5.93–
8.0
5.93–
6.6
5.93–
8.0
5.93–
6.6
5.93–
8.0
5.93–
6.6
5.93–6.6
Gb/s
2
2.965–4.0
2.965–4.0
2.965–4.0
2.965–3.3
Gb/s
4
1.4825–2.0
1.4825–2.0
1.4825–2.0
1.4825–1.65
Gb/s
8
0.74125–1.0
0.74125–1.0
0.74125–1.0 0.74125–0.825 Gb/s
16
N/A
N/A
1
9.8–
12.5
9.8–
10.3125
N/A
9.8–
10.3125
N/A
N/A
N/A
Gb/s
N/A
N/A
Gb/s
2
4.9–6.25
4.9–5.15625
N/A
N/A
Gb/s
4
2.45–3.125
2.45–2.578125
N/A
N/A
Gb/s
8
1.225–1.5625
1.225–1.2890625
N/A
N/A
Gb/s
0.6125–0.78125
0.6125–
0.64453125
N/A
N/A
Gb/s
GTX transceiver CPLL
frequency range
1.6–3.3
1.6–3.3
1.6–3.3
1.6–3.3
GHz
FGQPLLRANGE1 GTX transceiver QPLL
frequency range 1
5.93–8.0
5.93–8.0
5.93–8.0
5.93–6.6
GHz
FGTXQRANGE2
QPLL line rate
range 2(7)
16
FGCPLLRANGE
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 56: GTX Transceiver Performance (Cont’d)
Speed Grade(1)
-3 (1.0V)
Symbol
Output
Divider
Description
-1 (1.0V)(2)
-1M (1.0V)(2) -2LE (0.9V)(3)
-1LM (1.0V)(2)
-1Q (1.0V)(2)
Units
-2 (1.0V)
-2LE (1.0V)
-2LI (0.95V)
Package Type
FF
FGQPLLRANGE2 GTX transceiver QPLL
frequency range 2
FF
FBG676
FBG484 FBG676
RF
FBG900 FBG484 FBG900
9.8–12.5
FF
RF
9.8–10.3125
FB
FF
RF
N/A
FB
N/A
GHz
Notes:
1.
2.
3.
4.
5.
6.
7.
Voltages specified for speed grades are VCCINT.
The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s.
The -2LE (0.9V) speed grade requires a 4-byte internal data width for operation above 3.8 Gb/s.
Data rates between 8.0 Gb/s and 9.8 Gb/s are not available.
For line rates greater than 10.3125 Gb/s, VMGTAVCC is 1.05V nominal (see Table 2).
The FBG484 package supports data rates greater than 6.6 Gb/s in the -2 and -3 speed grades (requires Vivado Design Suite 2017.1 or
later).
For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125 Gb/s.
Table 57: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Speed Grade
Symbol
FGTXDRPCLK
Description
GTXDRPCLK maximum frequency
1.0V
0.95V
0.9V
-3
-2/-2LE
-1/-1M/-1LM/-1Q
-2LI
-2LE
175.01
175.01
156.25
175.01
125.00
Units
MHz
Table 58: GTX Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
All Speed Grades
Units
Min
Typ
Max
-3 speed grade
60
–
700
MHz
All other speed grades
60
–
670
MHz
FGCLK
Reference clock frequency range
TRCLK
Reference clock rise time
20% – 80%
–
200
–
ps
TFCLK
Reference clock fall time
80% – 20%
–
200
–
ps
TDCREF
Reference clock duty cycle
Transceiver PLL only
40
50
60
%
X-Ref Target - Figure 5
TRCLK
80%
20%
TFCLK
ds182_03_042712
Figure 5: Reference Clock Timing Parameters
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 59: GTX Transceiver PLL /Lock Time Adaptation
Symbol
TLOCK
Description
All Speed Grades
Conditions
Initial PLL lock
Clock recovery phase acquisition and
adaptation time for decision feedback
equalizer (DFE).
TDLOCK
Clock recovery phase acquisition and
adaptation time for low-power mode
(LPM) when the DFE is disabled.
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data
present at the input.
Units
Min
Typ
Max
–
–
1
ms
x106
UI
UI
–
50,000
37
–
50,000
2.3 x106
Table 60: GTX Transceiver User Clock Switching Characteristics(1)(2)
Speed Grade
Symbol
Description
Conditions
0.95V
0.9V
-3(3)
-2/-2LE(3)
1.0V
-1/-1M/-1LM/-1Q(4)
-2LI
-2LE(5)
Units
FTXOUT
TXOUTCLK maximum frequency
412.500
412.500
312.500
412.500
237.500
MHz
FRXOUT
RXOUTCLK maximum frequency
412.500
412.500
312.500
412.500
237.500
MHz
FTXIN
TXUSRCLK maximum
frequency
16-bit data path
412.500
412.500
312.500
412.500
237.500
MHz
32-bit data path
390.625
322.266
250.000
322.266
206.250
MHz
FRXIN
RXUSRCLK maximum
frequency
16-bit data path
412.500
412.500
312.500
412.500
237.500
MHz
32-bit data path
390.625
322.266
250.000
322.266
206.250
MHz
16-bit data path
412.500
412.500
312.500
412.500
237.500
MHz
FTXIN2
TXUSRCLK2 maximum
frequency
32-bit data path
390.625
322.266
250.000
322.266
206.250
MHz
64-bit data path
195.313
161.133
125.000
161.133
103.125
MHz
16-bit data path
412.500
412.500
312.500
412.500
237.500
MHz
32-bit data path
390.625
322.266
250.000
322.266
206.250
MHz
64-bit data path
195.313
161.133
125.000
161.133
103.125
MHz
RXUSRCLK2 maximum
frequency
FRXIN2
Notes:
1.
2.
3.
4.
5.
Clocking must be implemented as described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
These frequencies are not supported for all possible transceiver configurations.
For speed grades -3, -2, -2LE (1.0V), -2LI (0.95V), a 16-bit data path can only be used for speeds less than 6.6 Gb/s.
For speed grade -1, a 16-bit data path can only be used for speeds less than 5.0 Gb/s.
For speed grade -2LE (0.9V), a 16-bit data path can only be used for speeds less than 3.8 Gb/s.
Table 61: GTX Transceiver Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max
Units
0.500
–
FGTXMAX
Gb/s
–
40
–
ps
FGTXTX
Serial data rate range
TRTX
TX Rise time
20%–80%
TFTX
TX Fall time
80%–20%
–
40
–
ps
TLLSKEW
TX lane-to-lane skew(1)
–
–
500
ps
VTXOOBVDPP
Electrical idle amplitude
–
–
15
mV
TTXOOBTRANSITION
Electrical idle transition time
–
–
140
ns
–
–
0.28
UI
–
–
0.17
UI
–
–
0.28
UI
–
–
0.17
UI
Jitter(2)(4)
TJ12.5
Total
DJ12.5
Deterministic Jitter(2)(4)
TJ11.18
Total Jitter(2)(4)
DJ11.18
Deterministic
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12.5 Gb/s
11.18 Gb/s
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 61: GTX Transceiver Transmitter Switching Characteristics (Cont’d)
Symbol
TJ10.3125
Description
Total
Jitter(2)(4)
Jitter(2)(4)
DJ10.3125
Deterministic
TJ9.953
Total Jitter(2)(4)
DJ9.953
TJ9.8
Deterministic
Total
Jitter(2)(4)
Jitter(2)(4)
Jitter(2)(4)
DJ9.8
Deterministic
TJ8.0
Total Jitter(2)(4)
DJ8.0
Deterministic Jitter(2)(4)
TJ6.6_QPLL
Total
Jitter(2)(4)
Jitter(2)(4)
DJ6.6_QPLL
Deterministic
TJ6.6_CPLL
Total Jitter(3)(4)
DJ6.6_CPLL
Deterministic Jitter(3)(4)
TJ5.0
Total
Jitter(3)(4)
Jitter(3)(4)
DJ5.0
Deterministic
TJ4.25
Total Jitter(3)(4)
DJ4.25
Deterministic Jitter(3)(4)
TJ3.75
Total
Jitter(3)(4)
Jitter(3)(4)
DJ3.75
Deterministic
TJ3.2
Total Jitter(3)(4)
DJ3.2
Deterministic Jitter(3)(4)
TJ3.2L
Total
Jitter(3)(4)
Jitter(3)(4)
DJ3.2L
Deterministic
TJ2.5
Total Jitter(3)(4)
DJ2.5
Deterministic Jitter(3)(4)
TJ1.25
Total
Jitter(3)(4)
Jitter(3)(4)
DJ1.25
Deterministic
TJ500
Total Jitter(3)(4)
DJ500
Deterministic Jitter(3)(4)
Condition
10.3125 Gb/s
9.953 Gb/s
9.8 Gb/s
8.0 Gb/s
6.6 Gb/s
6.6 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.20 Gb/s(5)
3.20 Gb/s(6)
2.5 Gb/s(7)
1.25 Gb/s(8)
500 Mb/s
Min
Typ
Max
Units
–
–
0.28
UI
–
–
0.17
UI
–
–
0.28
UI
–
–
0.17
UI
–
–
0.28
UI
–
–
0.17
UI
–
–
0.30
UI
–
–
0.15
UI
–
–
0.28
UI
–
–
0.17
UI
–
–
0.30
UI
–
–
0.15
UI
–
–
0.30
UI
–
–
0.15
UI
–
–
0.30
UI
–
–
0.15
UI
–
–
0.30
UI
–
–
0.15
UI
–
–
0.2
UI
–
–
0.1
UI
–
–
0.32
UI
–
–
0.16
UI
–
–
0.20
UI
–
–
0.08
UI
–
–
0.15
UI
–
–
0.06
UI
–
–
0.1
UI
–
–
0.03
UI
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).
Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
All jitter values are based on a bit-error ratio of 1e-12.
CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
CPLL frequency at 1.6 GHz and TXOUT_DIV = 1.
CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 62: GTX Transceiver Receiver Switching Characteristics
Symbol
Description
Min
Typ
Max
Units
0.500
–
FGTXMAX
Gb/s
FGTXRX
Serial data rate
TRXELECIDLE
Time for RXELECIDLE to respond to loss or restoration of data
–
10
–
ns
RXOOBVDPP
OOB detect threshold peak-to-peak
60
–
150
mV
RXSST
Receiver spread-spectrum
tracking(1)
–5000
–
0
ppm
RXRL
Run length (CID)
–
–
512
UI
Bit rates ≤ 6.6 Gb/s
–1250
–
1250
ppm
Bit rates > 6.6 Gb/s and
≤ 8.0 Gb/s
–700
–
700
ppm
Bit rates > 8.0 Gb/s
–200
–
200
ppm
Data/REFCLK PPM offset
tolerance
RXPPMTOL
SJ Jitter
Modulated @ 33 KHz
Tolerance(2)
JT_SJ12.5
JT_SJ11.18
JT_SJ10.32
JT_SJ9.95
JT_SJ9.8
JT_SJ8.0
JT_SJ6.6_QPLL
JT_SJ6.6_CPLL
JT_SJ5.0
JT_SJ4.25
JT_SJ3.75
JT_SJ3.2
JT_SJ3.2L
JT_SJ2.5
JT_SJ1.25
JT_SJ500
Sinusoidal Jitter (QPLL)(3)
12.5 Gb/s
0.3
–
–
UI
Sinusoidal Jitter
(QPLL)(3)
11.18 Gb/s
0.3
–
–
UI
Sinusoidal Jitter
(QPLL)(3)
10.32 Gb/s
0.3
–
–
UI
Sinusoidal Jitter
(QPLL)(3)
9.95 Gb/s
0.3
–
–
UI
Sinusoidal Jitter
(QPLL)(3)
9.8 Gb/s
0.3
–
–
UI
Sinusoidal Jitter
(QPLL)(3)
8.0 Gb/s
0.44
–
–
UI
Sinusoidal Jitter
(QPLL)(3)
6.6 Gb/s
0.48
–
–
UI
Sinusoidal Jitter
(CPLL)(3)
6.6 Gb/s
0.44
–
–
UI
Sinusoidal Jitter
(CPLL)(3)
5.0 Gb/s
0.44
–
–
UI
Sinusoidal Jitter
(CPLL)(3)
4.25 Gb/s
0.44
–
–
UI
Sinusoidal Jitter
(CPLL)(3)
3.75 Gb/s
Sinusoidal Jitter
(CPLL)(3)
Sinusoidal Jitter
(CPLL)(3)
Sinusoidal Jitter
(CPLL)(3)
Sinusoidal Jitter
(CPLL)(3)
1.25
Sinusoidal Jitter
(CPLL)(3)
SJ Jitter Tolerance with Stressed
JT_TJSE3.2
JT_TJSE6.6
JT_SJSE3.2
JT_SJSE6.6
0.44
–
–
UI
3.2
Gb/s(4)
0.45
–
–
UI
3.2
Gb/s(5)
0.45
–
–
UI
2.5
Gb/s(6)
0.5
–
–
UI
0.5
–
–
UI
500 Mb/s
0.4
–
–
UI
3.2 Gb/s
0.70
–
–
UI
6.6 Gb/s
0.70
–
–
UI
3.2 Gb/s
0.1
–
–
UI
6.6 Gb/s
0.1
–
–
UI
Gb/s(7)
Eye(2)
Total Jitter with Stressed Eye(8)
Sinusoidal Jitter with Stressed
Eye(8)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Using RXOUT_DIV = 1, 2, and 4.
All jitter values are based on a bit error ratio of 1e–12.
The frequency of the injected sinusoidal jitter is 10 MHz.
CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
CPLL frequency at 1.6 GHz and RXOUT_DIV = 1.
CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
Composite jitter with RX in LPM or DFE mode.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
GTX Transceiver Protocol Jitter Characteristics
For Table 63 through Table 68, the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) contains recommended settings
for optimal usage of protocol specific characteristics.
Table 63: Gigabit Ethernet Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
1250
–
0.24
UI
1250
0.749
–
UI
Line Rate (Mb/s)
Min
Max
Units
3125
–
0.35
UI
3125
0.65
–
UI
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
Table 64: XAUI Protocol Characteristics
Description
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
Table 65: PCI Express Protocol Characteristics(1)
Standard
Description
Line Rate (Mb/s)
Min
Max
Units
PCI Express Transmitter Jitter Generation
PCI Express Gen 1
Total transmitter jitter
2500
–
0.25
UI
PCI Express Gen 2
Total transmitter jitter
5000
–
0.25
UI
–
31.25
ps
–
12
ps
0.65
–
UI
0.40
–
UI
0.30
–
UI
1.00
–
UI
Note 3
–
UI
0.10
–
UI
PCI Express Gen 3
Total transmitter jitter uncorrelated
Deterministic transmitter jitter uncorrelated
8000
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1
PCI Express Gen 2(2)
Total receiver jitter tolerance
Receiver inherent timing error
Receiver inherent deterministic timing error
2500
5000
0.03 MHz–1.0 MHz
PCI Express Gen 3
Receiver sinusoidal jitter
tolerance
1.0 MHz–10 MHz
8000
10 MHz–100 MHz
Notes:
1.
2.
3.
Tested per card electromechanical (CEM) methodology.
Using common REFCLK.
Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 66: CEI-6G and CEI-11G Protocol Characteristics
Description
Line Rate (Mb/s)
Interface
Min
Max
Units
CEI-6G-SR
–
0.3
UI
CEI-6G-LR
–
0.3
UI
CEI-6G-SR
0.6
–
UI
CEI-6G-LR
0.95
–
UI
CEI-11G-SR
–
0.3
UI
CEI-11G-LR/MR
–
0.3
UI
CEI-11G-SR
0.65
–
UI
CEI-11G-MR
0.65
–
UI
CEI-11G-LR
0.825
–
UI
CEI-6G Transmitter Jitter Generation
Total transmitter jitter(1)
4976–6375
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance(1)
4976–6375
CEI-11G Transmitter Jitter Generation
Total transmitter jitter(2)
9950–11100
CEI-11G Receiver High Frequency Jitter Tolerance
Total receiver jitter
tolerance(2)
9950–11100
Notes:
1.
2.
Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock.
Table 67: SFP+ Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
–
0.28
UI
0.7
–
UI
SFP+ Transmitter Jitter Generation
9830.40(1)
9953.00
Total transmitter jitter
10312.50
10518.75
11100.00
SFP+ Receiver Frequency Jitter Tolerance
9830.40(1)
9953.00
Total receiver jitter tolerance
10312.50
10518.75
11100.00
Notes:
1.
Line rated used for CPRI over SFP+ applications.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 68: CPRI Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
614.4
–
0.35
UI
1228.8
–
0.35
UI
2457.6
–
0.35
UI
3072.0
–
0.35
UI
4915.2
–
0.3
UI
6144.0
–
0.3
UI
9830.4
–
Note 1
UI
614.4
0.65
–
UI
1228.8
0.65
–
UI
2457.6
0.65
–
UI
3072.0
0.65
–
UI
4915.2
0.95
–
UI
6144.0
0.95
–
UI
9830.4
Note 1
–
UI
CPRI Transmitter Jitter Generation
Total transmitter jitter
CPRI Receiver Frequency Jitter Tolerance
Total receiver jitter tolerance
Notes:
1.
Tested per SFP+ specification, see Table 67.
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
www.xilinx.com/products/technology/pci-express.html
Table 69: Maximum Performance for PCI Express Designs(1)
Speed Grade
Symbol
Description
1.0V
0.95V
0.9V
Units
-3
-2/-2LE
-1/-1M/-1LM/-1Q
-2LI
-2LE
Pipe clock maximum frequency
250.00
250.00
250.00
250.00
250.00
MHz
FUSERCLK
User clock maximum frequency
500.00(1)
500.00(1)
250.00
500.00(1)
250.00
MHz
FUSERCLK2
User clock 2 maximum frequency
250.00
250.00
250.00
250.00
250.00
MHz
FDRPCLK
DRP clock maximum frequency
250.00
250.00
250.00
250.00
250.00
MHz
FPIPECLK
Notes:
1.
Refer to the 7 Series FPGAs Integrated Block for PCI Express Product Guide (PG054) for specific supported core configurations.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
XADC Specifications
Table 70: XADC Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V ± 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, Tj = –40°C to 100°C, Typical values at Tj=+40°C
ADC Accuracy(1)
Resolution
12
–
–
Bits
–
–
±3
LSBs
No missing codes, guaranteed monotonic
–
–
±1
LSBs
Offset Error
Offset calibration enabled
–
–
±6
LSBs
Gain Error
Gain calibration disabled
–
–
±0.5
%
Offset Matching
Offset calibration enabled
–
–
4
LSBs
Gain Matching
Gain calibration disabled
–
–
0.3
%
–
–
1
MS/s
FSAMPLE = 500KS/s, FIN = 20KHz
60
–
–
dB
External 1.25V reference
–
–
2
LSBs
On-chip reference
–
3
–
LSBs
FSAMPLE = 500KS/s, FIN = 20KHz
–
70
–
dB
Tj = –55°C to 125°C
10
–
–
Bits
INL
Tj = –55°C to 125°C
–
–
±1
DNL
No missing codes, guaranteed monotonic,
Tj = –55°C to 125°C
–
–
±1
LSB
(at 10 bits)
Unipolar operation
0
–
1
V
Bipolar operation
–0.5
–
+0.5
V
Unipolar common mode range (FS input)
0
–
+0.5
V
Bipolar common mode range (FS input)
+0.5
–
+0.6
V
Adjacent channels set within these ranges
should not corrupt measurements on adjacent
channels
–0.1
–
VCCADC
V
250
–
–
KHz
Tj = –40°C to 100°C
–
–
±4
°C
Tj = –55°C to +125°C
–
–
±6
°C
Integral
Nonlinearity(2)
Differential Nonlinearity
INL
DNL
Sample Rate
Signal to Noise
Ratio(2)
SNR
RMS Code Noise
Total Harmonic
Distortion(2)
THD
ADC Accuracy at Extended Temperatures
Resolution
Integral
Nonlinearity(2)
Differential Nonlinearity
Analog Inputs(3)
ADC Input Ranges
Maximum External Channel Input Ranges
Auxiliary Channel Full
Resolution Bandwidth
FRBW
On-Chip Sensors
Temperature Sensor Error
Tj = –40°C to +125°C
Supply Sensor Error
°C
Measurement range of VCCAUX 1.8V ±5%
Tj = –40°C to +100°C
–
–
±1
%
Measurement range of VCCAUX 1.8V ±5%
Tj = –55°C to +125°C
–
–
±2
%
Conversion Rate(4)
Conversion Time - Continuous
tCONV
Number of ADCCLK cycles
26
–
32
Cycles
Conversion Time - Event
tCONV
Number of CLK cycles
–
–
21
Cycles
DRP Clock Frequency
DCLK
DRP clock frequency
8
–
250
MHz
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 70: XADC Specifications (Cont’d)
Parameter
Symbol
ADC Clock Frequency
ADCCLK
Comments/Conditions
Min
Typ
Max
Units
1
–
26
MHz
40
–
60
%
1.20
1.25
1.30
V
1.2375
1.25
1.2625
V
Derived from DCLK
DCLK Duty Cycle
XADC Reference(5)
External Reference
VREFP
Externally supplied reference voltage
Ground VREFP pin to AGND,
Tj = –40°C to 100°C
On-Chip Reference
Notes:
1.
2.
3.
4.
5.
Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature
is enabled.
Only specified for bitstream option XADCEnhancedLinearity = ON.
For a detailed description, see the ADC chapter in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter User Guide (UG480).
For a detailed description, see the Timing chapter in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital
Converter User Guide (UG480).
Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by ±4% is permitted. On-chip reference variation is ±1%.
Configuration Switching Characteristics
Table 71: Configuration Switching Characteristics
Speed Grade
Symbol
1.0V
Description
0.95V
0.9V
-2LI
-2LE
Units
-3
-2/-2LE
-1/-1M/
-1LM/-1Q
5
5
5
5
5
ms, Max
Power-up Timing Characteristics
TPL(1)
Program latency
TPOR(1)
Power-on reset (50 ms ramp rate time)
10/50
10/50
10/50
10/50
10/50
ms, Min/Max
Power-on reset (1 ms ramp rate time)
10/35
10/35
10/35
10/35
10/35
ms, Min/Max
250
250
250
250
250
ns, Min
150
150
150
150
150
ns, Min
TPROGRAM
Program pulse width
CCLK Output (Master Mode)
TICCK
Master CCLK output delay
TMCCKL
Master CCLK clock Low time duty cycle
40/60
40/60
40/60
40/60
40/60
%, Min/Max
TMCCKH
Master CCLK clock High time duty cycle
40/60
40/60
40/60
40/60
40/60
%, Min/Max
FMCCK
Master CCLK frequency
100.00
100.00
100.00
100.00
70.00
MHz, Max
Master CCLK frequency for AES encrypted
x16
50.00
50.00
50.00
50.00
35.00
MHz, Max
FMCCK_START Master CCLK frequency at start of
configuration
3.00
3.00
3.00
3.00
3.00
MHz, Typ
FMCCKTOL
±50
±50
±50
±50
±50
%, Max
Frequency tolerance, master mode with
respect to nominal CCLK
CCLK Input (Slave Modes)
TSCCKL
Slave CCLK clock minimum Low time
2.50
2.50
2.50
2.50
2.50
ns, Min
TSCCKH
Slave CCLK clock minimum High time
2.50
2.50
2.50
2.50
2.50
ns, Min
FSCCK
Slave CCLK frequency
100.00
100.00
100.00
100.00
70.00
MHz, Max
2.50
2.50
2.50
2.50
2.50
ns, Min
EMCCLK Input (Master Mode)
TEMCCKL
External master CCLK Low time
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 71: Configuration Switching Characteristics (Cont’d)
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1/-1M/
-1LM/-1Q
0.95V
0.9V
-2LI
-2LE
Units
TEMCCKH
External master CCLK High time
2.50
2.50
2.50
2.50
2.50
ns, Min
FEMCCK
External master CCLK frequency
100.00
100.00
100.00
100.00
70.00
MHz, Max
100.00
100.00
100.00
100.00
70.00
MHz, Max
Internal Configuration Access Port
FICAPCK
Internal configuration access port (ICAPE2)
Master/Slave Serial Mode Programming Switching
TDCCK/
TCCKD
DIN Setup/Hold
TCCO
DOUT clock to out
4.00/0.00 4.00/0.00
8.00
8.00
4.00/0.00
8.00
4.00/0.00 5.00/0.00
8.00
9.00
ns, Min
ns, Max
SelectMAP Mode Programming Switching
TSMDCCK/
TSMCCKD
D[31:00] Setup/Hold
4.00/0.00 4.00/0.00
4.00/0.00
4.00/0.00 4.50/0.00
ns, Min
TSMCSCCK/
TSMCCKCS
CSI_B Setup/Hold
4.00/0.00 4.00/0.00
4.00/0.00
4.00/0.00 5.00/0.00
ns, Min
TSMWCCK/
TSMCCKW
RDWR_B Setup/Hold
10.00/0.00 10.00/0.00
10.00/0.00
10.00/0.00 12.00/0.00
ns, Min
TSMCKCSO
CSO_B clock to out (330Ω pull-up resistor
required)
7.00
7.00
7.00
7.00
8.00
ns, Max
TSMCO
D[31:00] clock to out in readback
8.00
8.00
8.00
8.00
10.00
ns, Max
FRBCCK
Readback frequency
100.00
100.00
100.00
100.00
70.00
MHz, Max
Boundary-Scan Port Timing Specifications
TTAPTCK/
TTCKTAP
TMS and TDI Setup/Hold
3.00/2.00 3.00/2.00
3.00/2.00
3.00/2.00 3.00/2.00
ns, Min
TTCKTDO
TCK falling edge to TDO output
7.00
7.00
7.00
7.00
8.50
ns, Max
FTCK
TCK frequency
66.00
66.00
66.00
66.00
50.00
MHz, Max
8.50
8.50
8.50
8.50
10.00
ns, Max
BPI Flash Master Mode Programming Switching
TBPICCO(2)
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,
ADV_B clock to out
TBPIDCC/
TBPICCD
D[15:00] Setup/Hold
4.00/0.00 4.00/0.00
4.00/0.00
4.00/0.00 4.50/0.00
ns, Min
3.00/0.00 3.00/0.00
3.00/0.00
3.00/0.00 3.00/0.00
ns, Min
SPI Flash Master Mode Programming Switching
TSPIDCC/
TSPICCD
D[03:00] Setup/Hold
TSPICCM
MOSI clock to out
8.00
8.00
8.00
8.00
9.00
ns, Max
TSPICCFC
FCS_B clock to out
8.00
8.00
8.00
8.00
9.00
ns, Max
STARTUPE2 Ports
TUSRCCLKO
STARTUPE2 USRCCLKO input to CCLK
output
FCFGMCLK
STARTUPE2 CFGMCLK output frequency
FCFGMCLKTOL STARTUPE2 CFGMCLK output frequency
tolerance
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0.50/7.50
0.50/6.70 0.50/7.50 ns, Min/Max
65.00
65.00
65.00
65.00
65.00
MHz, Typ
±50
±50
±50
±50
±50
%, Max
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 71: Configuration Switching Characteristics (Cont’d)
Speed Grade
Symbol
1.0V
Description
-3
-2/-2LE
-1/-1M/
-1LM/-1Q
100.00
100.00
100.00
0.95V
0.9V
-2LI
-2LE
100.00
70.00
Units
Device DNA Access Port
FDNACK
DNA access port (DNA_PORT)
MHz, Max
Notes:
1.
2.
To support longer delays in configuration, use the design solutions described in the 7 Series FPGA Configuration User Guide (UG470).
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
eFUSE Programming Conditions
Table 72 lists the programming conditions specifically for eFUSE. For more information, see the 7 Series FPGA Configuration
User Guide (UG470).
Table 72: eFUSE Programming Conditions(1)
Symbol
Description
Min
Typ
Max
Units
IFS
VCCAUX supply current
–
–
115
mA
tj
Temperature range
15
–
125
°C
Notes:
1.
The FPGA must not be configured during eFUSE programming.
Revision History
The following table shows the revision history for this document:
Date
Version
03/01/2011
1.0
Initial Xilinx release.
04/01/2011
1.1
Added the XC7K355T, XC7K420T, and XC7K480T devices throughout data sheet. Added the
extended temperature range discussion to page 1. Updated VCCAUX_IO in Table 2. Edits to clarify
Power-On/Off Power Supply Sequencing power sequencing discussion. Added ICCAUX_IO and ICCBRAM
to Table 6 and Table 7. Updated MMCM_FINDUTY and added FINJITTER, TOUTJITTER, TEXTFDVAR, and
Note 3 to Table 41. Removed the SBG324 package from Table 53. Updated the Notice of Disclaimer.
10/04/2011
1.2
Replaced -1L with -2L throughout this data sheet. Updated Min/Max values and removed Note 5 from
Table 2. Clarified Power-On/Off Power Supply Sequencing power sequencing discussion including
adding TVCCO2VCCAUX to Table 8. Updated VICM in Table 12 and Table 13. Added Note 1 to table 12.
Updated Table 72 including adding Note 1. Added Absolute Maximum Ratings for GTX Transceivers.
Revised the reference clock maximum frequency (FGCLK) in Table 58. Added Table 60. Added LVTTL
and removed SSTL135_II and SSTL15_II specifications from Table 20. Removed HSTL_III from
Table 21. Removed the I/O Standard Adjustment Measurement Methodology section. Use IBIS for
more accurate information and measurements. Updated TIDELAYPAT_JIT in Table 29. Added TAS/TAH to
Table 31. Added TRDCK_DI_WF_NC/TRCKD_DI_WF_NC and TRDCK_DI_RF/TRCKD_DI_RF to Table 34.
Completely updated Table 71. Updated the AC Switching Characteristics in Table 20, Table 21,
Table 22, Table 25, Table 26, Table 27, Table 29 through Table 41, Table 43 though Table 40, and Table
67.
11/03/2011
1.3
Revised the VOCM specification in Table 12. Updated the AC Switching Characteristics based upon the
ISE 13.3 v1.02 speed specification throughout document including Table 20 and Table 21. Added
MMCM_TFBDELAY while adding MMCM_ to the symbol names of a few specifications in Table 41 and
PLL to the symbol names in Table 42. In Table 43 through Table 50, updated the pin-to-pin descriptions
with the SSTL15 standard. Updated units in Table 52.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Date
Version
Description
02/13/2012
1.4
Updated summary description on page 1. In Table 2, revised VCCO for the 3.3V HR I/O banks and
updated Tj. Added typical values to Table 3. Updated the notes in Table 6. Added MGTAVCC,
MGTAVTT, and MGTVCCAUX power supply ramp times to Table 8. Rearranged Table 9, added
Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12, SSTL135_R, SSTL15_R, and SSTL12 and
removed DIFF_SSTL135, DIFF_SSTL18_I, DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II.
Added Table 10 and Table 11. Revised the specifications in Table 12 and Table 13. Updated the
eFUSE Programming Conditions section and removed the endurance table. Added the IO_FIFO
Switching Characteristics table. Revised ICCADC and updated Note 1 in Table 70. Revised DDR LVDS
transmitter data width in Table 17. Updated the AC Switching Characteristics based upon the ISE 13.4
v1.03 speed specification throughout document. Removed notes from Table 31 as they are no longer
applicable. Updated specifications in Table 71. Updated Note 1 in Table 40.
In the GTX Transceiver DC Input and Output Levels section: Revised VIN, and added IDCIN and IDCOUT
to Table 54. Added Note 7 to Table 56. In Table 58, revised FGCLK, removed TPHASE, and added
TDLOCK. Revised specifications and added Note 2 to Table 60. Added Table 61 and Table 62 along with
GTX Transceiver Protocol Jitter Characteristics in Table 63 through Table 68.
05/23/2012
1.5
Reorganized entire data sheet including adding Table 47 and Table 51.
Updated TSOL in Table 1. Updated IBATT and added RIN_TERM to Table 3. Added values to Table 6 and
Table 7. Updated Power-On/Off Power Supply Sequencing, page 7 with regards to GTX transceivers.
Updated many parameters in Table 9 including SSTL135 and SSTL135_R. Removed VOX column and
added DIFF_HSUL_12 to Table 11. Updated VOL in Table 12. Updated Table 17 and removed notes 2
and 3. Updated Table 18.
Updated the AC Switching Characteristics based upon the ISE 14.1 v1.04 for the -3, -2, -2L (1.0V), -1,
and -2L (0.9V) speed specifications throughout the document.
In Table 34, updated Reset Delays section including Note 10 and Note 11. Added data for TLOCK and
TDLOCK in Table 58. Updated many of the XADC specifications in Table 70 and added Note 2. Updated
and moved Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK section from
Table 71 to Table 41 and Table 42.
07/25/2012
1.6
Updated the descriptions, changed VIN and Note 2 and added Note 4 in Table 1. In Table 2, changed
descriptions and notes, removed Note 7, changed GTX transceiver parameters and values and added
Note 12. Updated parameters in Table 3. Added Table 4 and Table 5.
Changed the typical values for many of the devices in Table 7. Updated LVCMOS12 and the SSTLs in
Table 9. Updated many of the specifications in Table 10 and Table 11.
Updated speed specification to v1.06 (-3, -2, -2L(1.0V), -1) and v1.05 (-2L(0.9V)) with appropriate
changes to Table 15 and Table 16 including production release of the XC7K325T and the XC7K410T
in the -2, -2L(1.0V), and -1 speed designations.
Added notes and specifications to Table 18 and Table 19.
Updated the IOB Pad Input/Output/3-State discussion and changed Table 22 by adding
TIOIBUFDISABLE.
Removed many of the combinatorial delay specifications and TCINCK/TCKCIN from Table 31.
Rearranged Table 54 including moving some parameters to Table 1. Added Table 59. Updated
Table 60. In Table 62, updated SJ Jitter Tolerance with Stressed Eye section, page 62 and Note 8.
Added Note 1, Note 2, and Note 2 to Table 65. Added Note 1 and Note 2 to Table 66, and line rate
ranges. Updated Table 67 including adding Note 1. Updated Table 68 including adding Note 1.
In Table 70 updated Note 1 and added Note 4. In Table 71, updated TPOR and FEMCCK.
09/04/2012
1.7
Updated Table 15 and Table 16 for production release of the XC7K160T in the -2, -2L(1.0V), and -1
speed designations.
09/26/2012
1.8
In Table 2, revised VCCINT and VCCBRAM and added Note 3. Updated Table 15 and Table 16 for
production release of the XC7K480T in the -2, -2L(1.0V), and -1 speed designations and the
XC7K325T and XC7K410T in the -3 speed designation.
10/10/2012
1.9
Updated the ICCINTMIN value for the XC7K355T in Table 7. Updated Table 15 and Table 16 for
production release of the XC7K420T in the -2, -2L(1.0V), and -1 speed designations.
10/25/2012
2.0
Updated the AC Switching Characteristics based upon ISE 14.3 v1.07 for the -3, -2, -2L (1.0V), -1
speed specifications, and ISE 14.3 v1.06 for the -2L (0.9V) speed specifications throughout the
document.
Updated Table 15 and Table 16 for production release of the XC7K355T in the -2, -2L(1.0V), and -1
speed designations. Also updated Table 15 and Table 16 for production release of the XC7K325T and
XC7K410T in the -2L (0.9V).
Added values for Table 17 -2L (0.9V). Added package skew values to Table 53. In Table 56, increased
-1 speed grade (FF package) FGTXMAX value from 6.6 Gb/s to 8.0 Gb/s.
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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Date
Version
10/31/2012
2.1
Updated Table 15 and Table 16 for production release of the XC7K70T in the -2, -2L(1.0V), and -1
speed designations.
11/26/2012
2.2
Updated Table 15 and Table 16 for production release of -3 speed designation for XC7K70T,
XC7K160T, XC7K355T, XC7K420T, and XC7K480T. Removed Note 4 from Table 70.
12/05/2012
2.3
Updated Table 15 and Table 16 for production release of the -2L (0.9V) speed designation for
XC7K160T, XC7K420T, and XC7K480T. Updated Note 1 in Table 53.
12/12/2012
2.4
Updated Table 15 and Table 16 for production release of the -2L (0.9V) speed designation for
XC7K70T and XC7K355T. Added Internal Configuration Access Port section to Table 71.
10/04/2013
2.5
In Table 1, revised VIN (I/O input voltage) to match values in Table 4 and Table 5, and combined Note 4
with old Note 5 and then added new Note 5. Also in Table 1, updated IDCIN and IDCOUT sections.
Revised VIN description and added Note 3 and Note 8 in Table 2. Updated first 3 rows in Table 4 and
Table 5. Replaced XPower with Xilinx Power Estimator (XPE) in sentence before Table 7. Updated VIL
minimum for PCI33_3 in Table 9. Added Note 1 to Table 12. Added Note 1 to Table 13. Added Vivado
Design Suite to AC Switching Characteristics. Updated titles of Table 18 and Table 19, and removed
the following note: RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated
with memory IP. Updated TIOOP and TIOTP values in Table 20. Replaced “TRACE report” with “timing
report” in notes for Table 28, Table 29, Table 30, Table 32, and Table 34. Removed this note: A Zero “0”
Hold Time listing indicates no hold time or a negative hold time from Table 32, Table 33, and Table 48.
Updated Note 1 in Table 38. Updated Table 60 to more accurately show transceiver user clocks for
supported line rates. Updated Note 8 and description of FGTXRX in Table 62. Updated Note 2, Note 3,
and Note 4 in Table 70. Added TUSRCCLKO to Table 71.
11/27/2013
2.6
Added Kintex-7Q defense-grade devices throughout. Added -1M speed grade throughout. Added
reference to 7 Series FPGAs Overview and Defense-Grade 7 Series FPGAs Overview in Introduction.
In Table 2, added junction temperature operating range for military (M) devices. In Table 3, removed
commercial (C), industrial (I), and extended (E) from descriptions of RIN_TERM. Updated temperature
ranges in Table 4 and Table 5. Removed Note 1 and Note 2 from Table 7. Added TJ = 125°C to
Conditions column for TVCCO2VCCAUX in Table 8. Added Table 14. Updated description of
MMCM_FPFDMAX in Table 41. Updated description of PLL_FPFDMAX in Table 42. Added RF package
type to Table 56. Added FDNACK to Table 71.
02/07/2014
2.7
Updated the AC Switching Characteristics based upon ISE 14.7 and Vivado 2013.4. Updated Note 5
and added Note 6 to Table 2. Added Note 2 to Table 4. Added Note 2 and updated Note 3 in Table 5.
Added HSUL_12_F, DIFF_HSUL_12_F, MOBILE_DDR_S, MOBILE_DDR_F, DIFF_MOBILE_DDR_S,
and DIFF_MOBILE_DDR_F standards to and updated values in Table 20. Added HSUL_12_F,
DIFF_HSUL_12_F, DIFF_HSUL_12_DCI_S, and DIFF_HSUL_12_DCI_F standards to and updated
values in Table 21. In Table 35, corrected FMAX_CAS_RF_DELAYED_WRITE from 478.27 to 478.24 MHz to
match software behavior. Removed introductory paragraph of Device Pin-to-Pin Output Parameter
Guidelines and Device Pin-to-Pin Input Parameter Guidelines. Updated display format of “ADC
Accuracy at Extended Temperatures” section in Table 70.
03/04/2014
2.8
Updated Note 2 in Table 4 and Note 2 in Table 5. For XQ7K325T and XQ7K410T in Table 15, changed
-2 and -1 speed grades to -2I and -1I, respectively, and moved all XQ7K325T speed grades from
Preliminary to Production. In Table 16, added production software for XQ7K325T -2/2L, -1, -1M, and
(0.9V) -2L speed grades. Removed “and FB” from title of Table 19. Removed notes from Table 20 and
Table 21. Added Note 1 to Table 69.
06/20/2014
2.9
In Table 4 and Table 5, updated Note 2 per the customer notice XCN14014: 7 Series FPGA and
Zynq-7000 AP SoC I/O Undershoot Voltage Data Sheet Update. In Table 15, moved all XQ7K410T
speed grades from Preliminary to Production. In Table 16, added production software for XQ7K410T
-2/-2L, -1, -1M, and (0.9V) -2L speed grades and removed Note 2. Added Note 3 to Table 18. In
Table 29, added attribute REFCLK frequency of 400 MHz to FIDELAYCTRL_REF and average tap delay
at 400 MHz to Note 1. In Table 69, updated Note 1 to Gen 2 and added reference to 7 Series FPGAs
Integrated Block for PCI Express Product Guide (PG054). In Table 71, replaced USRCCLK Output with
STARTUPE2 Ports and added FCFGMCLK and FCFGMCLKTOL.
09/08/2014
2.10
Updated Note 3 in Table 6. In Power-On/Off Power Supply Sequencing, added sentence about there
being no recommended sequence for supplies not shown. Added I/O Standard Adjustment
Measurement Methodology. In Table 43, updated description of TICKOF and added Note 2. In Table 44,
updated description of TICKOFFAR and added Note 2. In Table 54, moved DVPPOUT value of 1000 mV
from Max to Min column, updated VIN DC parameter description, and added Note 2. Added “peak-topeak” to labels in Figure 3 and Figure 4.
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Date
Version
Description
10/06/2014
2.11
Added -2LI (0.95V) speed grade throughout. Removed 3.3V as a descriptor of HR I/O banks and 1.8V
as a descriptor of HP I/O banks throughout. Updated Introduction. Added -2LI (0.95V) to description
of VCCINT and VCCBRAM in Table 2. Added Note 1 and updated Note 2 in Table 16. Updated Note 3 in
Table 18.
11/19/2014
2.12
Replaced -2L speed grade with -2LE throughout. Updated descriptions of VCCINT and VCCBRAM in
Table 2. Updated the AC Switching Characteristics based upon Vivado 2014.4. In Table 14, updated
Vivado software version to 1.12 and added a row for VCCINT = 0.95V. In Table 15, moved -2LI (0.95V)
speed grade from Advance to Production. In Table 16, added Vivado 2014.4 software version to -2LI
(0.95V) speed grade column and removed notes. Added Selecting the Correct Speed Grade and
Voltage in the Vivado Tools. Updated speed grade heading row in Table 56. Added -2LI (0.95V)
speed grade to Note 3 in Table 60. Removed sentence about PCI Express x8 Gen 2 operation from
Note 1 in Table 69.
02/23/2015
2.13
In Table 12, changed maximum VICM value from 1.425V to 1.500V. Removed minimum sample rate
specification from Table 70.
09/24/2015
2.14
Updated first two paragraphs in Introduction. Added -1LM speed grade to VCCINT and VCCBRAM
descriptions in Table 2. In Table 6, added -1LM (1.0V) speed grade and assigned quiescent supply
currents to -2LI speed grade Kintex-7Q devices. In Table 16, changed -2LI speed grade Kintex-7Q
device cells from N/A to blank, added -1LM speed grade, and added Note 1. Added -1M and -1LM
speed grades to Table 17. Added introductory paragraph before Table 18. Removed Pb-free G suffix
from Table 18 and Table 19 titles and Note 3. Updated Note 3 in Table 18. Added -1LM speed grade in
Table 18 to Table 52, Table 57, Table 60, Table 69, and Table 71. Changed -2LI speed grade Kintex-7Q
device cells from N/A to blank in Table 40, Table 43 to Table 46, and Table 48 to Table 50. Added
FBV484, FBV676, FFV676, FBV900, FFV900, FFV901, and FFV1156 packages to Table 53. Added
-1LM (1.0V) speed grade to Table 56. Removed note about PCI-SIG 3.0 certification and compliance
test boards from Table 65.
11/24/2015
2.15
Updated the AC Switching Characteristics based upon Vivado 2015.4. In Table 15, added -2LI (0.95V)
and -1LM speed grades to Production column for XQ7K325T and XQ7K410T. In Table 16, removed
table note and added Vivado 2015.4 software version to -1LM and -2LI (0.95V) speed grades for
XQ7K325T and -2LI (0.95V) speed grade for XQ7K410T. In Table 40, added TCKSKEW for XQ7K325T
and XQ7K410T at -2LI (0.95V) speed grade. Updated device pin-to-pin output parameter tables
(Table 43 to Table 46) and input parameter tables (Table 48 to Table 50) for XQ7K325T and XQ7K410T
at -2LI (0.95V) speed grade.
05/08/2017
2.16
Updated Note 5 in Table 2. Added Note 1 to Table 14. Updated VMEAS for LVCMOS33, LVTTL, and
PCI33_3 I/O standard attributes in Table 23. In Table 29, changed TIDELAYRESOLUTION units from ps to
µs. Updated Note 1 in Table 38. Removed FBV484, FBV676, FFV676, FBV900, FFV900, FFV901, and
FFV1156 packages from Table 53 per the customer notice XCN16022: Cross-ship of Lead-free Bump
and Substrates in Lead-free (FFG/FBG/SBG) Packages. In Table 56, improved GTX performance for
FBG484 package in -2 and -3 speed grades (requires Vivado tools 2017.1), and added Note 1, Note 5,
and Note 6.
08/07/2018
2.16.1
05/15/2019
2.17
Added expanded temperature range and XA Kintex-7 FPGA Data Sheet: Overview (DS175) to
Introduction. Added -1Q speed grade and XA7K160T throughout. In Table 2, added -1Q to descriptions
of VCCINT and VCCBRAM, and added junction temperature operating range for expanded (Q)
temperature devices to Tj. Added XA Kintex-7 to second paragraph in Selecting the Correct Speed
Grade and Voltage in the Vivado Tools. In Table 40, updated TDCD_CLK for -2LI speed grade to 0.20 ns.
06/28/2019
2.18
Updated Table 14 with Vivado 2019.1.1 speed specification versions. In Table 15, moved -1Q speed
grade for XA7K160T from Advance to Production. In Table 16, added Vivado 2019.1.1 software version
to -1Q speed grade column for XA7K160T.
Editorial updates only. No technical content updates.
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