XC7S15-2CSGA225C

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.9) March 13, 2019 Product Specification Introduction Spartan®-7 FPGAs are available in -2, -1, and -1L speed grades, with -2 having the highest performance. The Spartan-7 FPGAs predominantly operate at a 1.0V core voltage. The -1L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 devices. The -1L devices operate only at VCCINT = VCCBRAM = 0.95V and have the same speed specifications as the -1 speed grade. Spartan-7 FPGA DC and AC characteristics are specified in commercial (C), industrial (I), and expanded (Q) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1Q expanded speed grade device are the same as for a -1C commercial speed grade device). However, only selected speed grades and/or devices are available in each temperature range. For example, the -1L speed grade is only available in the industrial (I) temperature range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Available device and package combinations can be found in: • 7 Series FPGAs Overview (DS180) [Ref 1] • XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2] This Spartan-7 FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/documentation. DC Characteristics Table 1: Absolute Maximum Ratings(1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage. –0.5 1.1 V VCCAUX Auxiliary supply voltage. –0.5 2.0 V VCCBRAM Supply voltage for the block RAM memories. –0.5 1.1 V VCCO Output drivers supply voltage for HR I/O banks. –0.5 3.6 V VREF Input reference voltage. –0.5 2.0 V DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 1 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units I/O input voltage. –0.4 VCCO + 0.55 V VIN(2)(3)(4) I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33.(5) –0.4 2.625 V VCCBATT Key memory battery backup supply. –0.5 2.0 V VCCADC XADC supply relative to GNDADC. –0.5 2.0 V VREFP XADC reference input relative to GNDADC. –0.5 2.0 V Storage temperature (ambient). –65 150 °C – +220 °C – +260 °C – +125 °C XADC Temperature TSTG TSOL Tj Maximum soldering temperature for Pb/Sn component bodies.(6) Maximum soldering temperature for Pb-free component Maximum junction temperature.(6) bodies.(6) Notes: 1. 2. 3. 4. 5. 6. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. The lower absolute voltage specification always applies. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3]. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4. See Table 9 for TMDS_33 specifications. For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4]. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 2 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 2: Recommended Operating Conditions(1)(2) Symbol Description Min Typ Max Units For -2 and -1 (1.0V) devices: internal supply voltage. 0.95 1.00 1.05 V For -1L (0.95V) devices: internal supply voltage. 0.92 0.95 0.98 V Auxiliary supply voltage. 1.71 1.80 1.89 V For -2 and -1 (1.0V) devices: block RAM supply voltage. 0.95 1.00 1.05 V For -1L (0.95V) devices: block RAM supply voltage. 0.92 0.95 0.98 V Supply voltage for HR I/O banks. 1.14 – 3.465 V I/O input voltage. –0.20 – VCCO + 0.20 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33.(7) –0.20 – 2.625 V – – 10 mA 1.0 – 1.89 V FPGA Logic VCCINT(3) VCCAUX VCCBRAM(3) VCCO(4)(5) VIN(6) IIN(8) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. VCCBATT(9) Battery voltage. XADC VCCADC XADC supply relative to GNDADC. 1.71 1.80 1.89 V VREFP Externally supplied reference voltage. 1.20 1.25 1.30 V 0 – 85 °C –40 – 100 °C –40 – 125 °C Temperature Junction temperature operating range for commercial (C) temperature devices. Junction temperature operating range for industrial (I) temperature devices. Tj Junction temperature operating range for expanded (Q) temperature devices. Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. All voltages are relative to ground. For the design of the power distribution system consult the 7 Series FPGAs PCB Design Guide (UG483) [Ref 5]. If VCCINT and VCCBRAM are operating at the same voltage, VCCINT and VCCBRAM should be connected to the same supply. Configuration data is retained even if VCCO drops to 0V. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%. The lower absolute voltage specification always applies. See Table 9 for TMDS_33 specifications. A total of 200 mA per bank should not be exceeded. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 3 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost). 0.75 – – V VDRI Data retention VCCAUX voltage (below which configuration data might be lost). 1.5 – – V IREF VREF leakage current per pin. – – 15 µA IL Input or output leakage current per pin (sample-tested). – – 15 µA CIN(2) Die input capacitance at the pad. – – 8 pF Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V. 90 – 330 µA Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V. 68 – 250 µA Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V. 34 – 220 µA Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V. 23 – 150 µA Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V. 12 – 120 µA IRPD Pad pull-down (when selected) at VIN = 3.3V. 68 – 330 µA ICCADC Analog supply current, analog circuits in powered up state. – – 25 mA IBATT(3) Battery supply current. – – 150 nA Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40). 28 40 55 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50). 35 50 65 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60). 44 60 83 Ω IRPU RIN_TERM(4) n Temperature diode ideality factor. – 1.010 – – r Temperature diode series resistance. – 2 – Ω Notes: 1. 2. 3. 4. Typical values are specified at nominal voltage, 25°C. This measurement represents the die capacitance at the pad, not including the package. Maximum value specified for worst case process at 25°C. Termination resistance to a VCCO/2 level. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 4 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) AC Voltage Overshoot % of UI at –40°C to 125°C VCCO + 0.55 AC Voltage Undershoot % of UI at –40°C to 125°C –0.40 100 –0.45 61.7 –0.50 25.8 –0.55 11.0 100 VCCO + 0.60 46.6 –0.60 4.77 VCCO + 0.65 21.2 –0.65 2.10 VCCO + 0.70 9.75 –0.70 0.94 VCCO + 0.75 4.55 –0.75 0.43 VCCO + 0.80 2.15 –0.80 0.20 VCCO + 0.85 1.02 –0.85 0.09 VCCO + 0.90 0.49 –0.90 0.04 VCCO + 0.95 0.24 –0.95 0.02 Notes: 1. 2. A total of 200 mA per bank should not be exceeded. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. Table 5: Typical Quiescent Supply Current(1)(2)(3) Speed Grade Symbol ICCINTQ Description Quiescent VCCINT supply current. DS189 (v1.9) March 13, 2019 Product Specification Device 1.0V 0.95V Units -2C -2I -1C -1I -1Q -1LI XC7S6 36 36 36 36 36 32 mA XC7S15 36 36 36 36 36 32 mA XC7S25 48 48 48 48 48 43 mA XC7S50 95 95 95 95 95 59 mA XC7S75 148 148 148 148 148 134 mA XC7S100 148 148 148 148 148 134 mA XA7S6 N/A 36 N/A 36 36 N/A mA XA7S15 N/A 36 N/A 36 36 N/A mA XA7S25 N/A 48 N/A 48 48 N/A mA XA7S50 N/A 95 N/A 95 95 N/A mA XA7S75 N/A 148 N/A 148 148 N/A mA XA7S100 N/A 148 N/A 148 148 N/A mA www.xilinx.com Send Feedback 5 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current(1)(2)(3) (Cont’d) Speed Grade Symbol ICCOQ ICCAUXQ Description Quiescent VCCO supply current. Quiescent VCCAUX supply current. DS189 (v1.9) March 13, 2019 Product Specification Device 1.0V 0.95V Units -2C -2I -1C -1I -1Q -1LI XC7S6 1 1 1 1 1 1 mA XC7S15 1 1 1 1 1 1 mA XC7S25 1 1 1 1 1 1 mA XC7S50 1 1 1 1 1 1 mA XC7S75 4 4 4 4 4 4 mA XC7S100 4 4 4 4 4 4 mA XA7S6 N/A 1 N/A 1 1 N/A mA XA7S15 N/A 1 N/A 1 1 N/A mA XA7S25 N/A 1 N/A 1 1 N/A mA XA7S50 N/A 1 N/A 1 1 N/A mA XA7S75 N/A 4 N/A 4 4 N/A mA XA7S100 N/A 4 N/A 4 4 N/A mA XC7S6 10 10 10 10 10 10 mA XC7S15 10 10 10 10 10 10 mA XC7S25 13 13 13 13 13 13 mA XC7S50 22 22 22 22 22 20 mA XC7S75 43 43 43 43 43 43 mA XC7S100 43 43 43 43 43 43 mA XA7S6 N/A 10 N/A 10 10 N/A mA XA7S15 N/A 10 N/A 10 10 N/A mA XA7S25 N/A 13 N/A 13 13 N/A mA XA7S50 N/A 22 N/A 22 22 N/A mA XA7S75 N/A 43 N/A 43 43 N/A mA XA7S100 N/A 43 N/A 43 43 N/A mA www.xilinx.com Send Feedback 6 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 5: Typical Quiescent Supply Current(1)(2)(3) (Cont’d) Speed Grade Symbol ICCBRAMQ Description Quiescent VCCBRAM supply current. Device 1.0V 0.95V Units -2C -2I -1C -1I -1Q -1LI XC7S6 1 1 1 1 1 1 mA XC7S15 1 1 1 1 1 1 mA XC7S25 1 1 1 1 1 1 mA XC7S50 2 2 2 2 2 1 mA XC7S75 9 9 9 9 9 8 mA XC7S100 9 9 9 9 9 8 mA XA7S6 N/A 1 N/A 1 1 N/A mA XA7S15 N/A 1 N/A 1 1 N/A mA XA7S25 N/A 1 N/A 1 1 N/A mA XA7S50 N/A 2 N/A 2 2 N/A mA XA7S75 N/A 9 N/A 9 9 N/A mA XA7S100 N/A 9 N/A 9 9 N/A mA Notes: 1. 2. 3. Typical values are specified at nominal voltage, 85°C junction temperature (Tj) with single-ended SelectIO™ resources. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. Use the Xilinx Power Estimator spreadsheet tool [Ref 6] to estimate static power consumption for conditions other than those specified. Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, V CCBRAM, VCCAUX, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If V CCAUX and VCCO have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. For V CCO voltages of 3.3V in HR I/O banks and configuration bank 0 the following conditions apply. • The voltage difference between VCCO and V CCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. • The T VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps. There is no recommended sequence for supplies not discussed in this section. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 7 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 6 shows the minimum current, in addition to I CCQ maximum, that is required by Spartan-7 devices for proper power-on and configuration. If the current minimums shown in Table 6 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator spreadsheet tool [Ref 6] to estimate current drain on these supplies. Table 6: Power-On Current ICCINTMIN ICCAUXMIN ICCOMIN ICCBRAMMIN Units XC7S6 ICCINTQ + 120 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XC7S15 ICCINTQ + 120 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XC7S25 ICCINTQ + 120 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XC7S50 ICCINTQ + 120 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XC7S75 ICCINTQ + 300 ICCAUXQ + 140 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XC7S100 ICCINTQ + 300 ICCAUXQ + 140 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XA7S6 ICCINTQ + 120 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XA7S15 ICCINTQ + 120 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XA7S25 ICCINTQ + 120 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XA7S50 ICCINTQ + 120 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XA7S75 ICCINTQ + 300 ICCAUXQ + 140 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA XA7S100 ICCINTQ + 300 ICCAUXQ + 140 ICCOQ + 40 mA per bank ICCBRAMQ + 60 mA Device Table 7: Power Supply Ramp Time Symbol Description Conditions Min Max Units TVCCINT Ramp time from GND to 90% of VCCINT. 0.2 50 ms TVCCO Ramp time from GND to 90% of VCCO. 0.2 50 ms TVCCAUX Ramp time from GND to 90% of VCCAUX. 0.2 50 ms TVCCBRAM Ramp time from GND to 90% of VCCBRAM. TVCCO2VCCAUX 0.2 50 ms TJ = 125°C(1) – 300 ms Allowed time per power cycle for VCCO – VCCAUX > 2.625V. TJ = 100°C(1) – 500 ms 85°C(1) – 800 ms TJ = Notes: 1. Based on 240,000 power cycles with a nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 8 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and V OH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V CCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 8: SelectIO DC Input and Output Levels(1)(2)(3) I/O Standard VIL V, Min VIH V, Max V, Min V, Max VOL VOH V, Max V, Min IOL IOH mA, Max mA, Min HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.00 –8.00 HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.00 –8.00 HSTL_II –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16.00 –16.00 HSTL_II_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16.00 –16.00 HSUL_12 –0.300 VREF – 0.130 VREF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.10 –0.10 LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 4 Note 4 LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 25% VCCO 75% VCCO Note 5 Note 5 LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 6 Note 6 LVCMOS25 –0.300 0.7 1.700 VCCO + 0.300 0.400 VCCO – 0.400 Note 5 Note 5 LVCMOS33 –0.300 0.8 2.000 3.450 0.400 VCCO – 0.400 Note 5 Note 5 LVTTL –0.300 0.8 2.000 3.450 0.400 2.400 Note 6 Note 6 MOBILE_DDR –0.300 20% VCCO 80% VCCO VCCO + 0.300 10% VCCO 90% VCCO 0.10 –0.10 PCI33_3 –0.400 30% VCCO 50% VCCO VCCO + 0.500 10% VCCO 90% VCCO 1.50 –0.50 SSTL135 –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 13.00 –13.00 SSTL135_R –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.90 –8.90 SSTL15 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 13.00 –13.00 SSTL15_R –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 8.90 –8.90 SSTL18_I –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470 8.00 –8.00 SSTL18_II –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.600 VCCO/2 + 0.600 13.40 –13.40 Notes: 1. 2. 3. 4. 5. 6. Tested according to relevant specifications. 3.3V and 2.5V standards are only supported in HR I/O banks. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3]. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 9 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 9: Differential SelectIO DC Input and Output Levels VICM(1) I/O Standard V, Typ V, Max V, Min VOCM(3) VOD(4) V, Typ V, Max V, Min V, Typ V, Max – – – 1.250 – Note 5 MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600 PPDS_25 0.200 0.900 VCCAUX 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600 TMDS_33 2.700 2.965 3.230 0.150 0.675 1.200 VCCO – 0.405 VCCO – 0.300 VCCO – 0.190 0.400 0.600 0.800 BLVDS_25 V, Min VID(2) 0.300 1.200 1.425 0.100 V, Min V, Typ V, Max Notes: 1. 2. 3. 4. 5. VICM is the input common mode voltage. VID is the input differential voltage (Q – Q). VOCM is the output common mode voltage. VOD is the output differential voltage (Q – Q). VOD for BLVDS will vary significantly depending on topology and loading. Table 10: Complementary Differential SelectIO DC Input and Output Levels VOL(3) VOH(4) V, Min V, Typ V, Max V, Min V, Max V, Max V, Min DIFF_HSTL_I 0.300 0.750 1.125 0.100 – 0.400 VCCO – 0.400 8.00 –8.00 DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 – 0.400 VCCO – 0.400 8.00 –8.00 DIFF_HSTL_II 0.300 0.750 1.125 0.100 – 0.400 VCCO – 0.400 16.00 –16.00 DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 – 0.400 VCCO – 0.400 16.00 –16.00 DIFF_HSUL_12 0.300 0.600 0.850 0.100 – 20% VCCO 80% VCCO 0.100 –0.100 DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 – 10% VCCO 90% VCCO 0.100 –0.100 DIFF_SSTL135 0.300 0.675 1.000 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 13.0 –13.0 DIFF_SSTL135_R 0.300 0.675 1.000 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.9 –8.9 DIFF_SSTL15 0.300 0.750 1.125 0.100 – (VCCO/2) – 0.175 (VCCO/2) + 0.175 13.0 –13.0 DIFF_SSTL15_R 0.300 0.750 1.125 0.100 – (VCCO/2) – 0.175 (VCCO/2) + 0.175 8.9 –8.9 DIFF_SSTL18_I 0.300 0.900 1.425 0.100 – (VCCO/2) – 0.470 (VCCO/2) + 0.470 8.00 –8.00 DIFF_SSTL18_II 0.300 0.900 1.425 0.100 – (VCCO/2) – 0.600 (VCCO/2) + 0.600 13.4 –13.4 I/O Standard VICM(1) VID(2) IOL IOH mA, Max mA, Min Notes: 1. 2. 3. 4. VICM is the input common mode voltage. VID is the input differential voltage (Q – Q). VOL is the single-ended low-output voltage. VOH is the single-ended high-output voltage. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 10 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics LVDS DC Specifications (LVDS_25) Table 11: LVDS_25 DC Specifications(1) Symbol DC Parameter Conditions Min Typ Max Units 2.375 2.500 2.625 V VCCO Supply voltage. VOH Output High voltage for Q and Q. RT = 100Ω across Q and Q signals. – – 1.675 V VOL Output Low voltage for Q and Q. RT = 100Ω across Q and Q signals. 0.700 – – V RT = 100Ω across Q and Q signals. 247 350 600 mV RT = 100Ω across Q and Q signals. 1.000 1.250 1.425 V 100 350 600 mV 0.300 1.200 1.500 V Differential output voltage: VODIFF (Q – Q), Q = High (Q – Q), Q = High VOCM Output common-mode voltage. Differential input voltage: VIDIFF (Q – Q), Q = High (Q – Q), Q = High VICM Input common-mode voltage. Notes: 1. Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3] for more information. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 11 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics AC Switching Characteristics All values represented in this data sheet are based on the speed specifications from the Vivado® Design Suite as outlined in Table 12. Table 12: Speed Specification Version By Device 2018.2.1 Device 1.23 XC7S6, XC7S15, XC7S25, XC7S50, XC7S75, XC7S100 1.16 XA7S6, XA7S15, XA7S25, XA7S50, XA7S75, XA7S100 Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows. Advance Product Specification These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary Product Specification These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production Product Specification These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Testing of AC Switching Characteristics Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Spartan-7 FPGAs. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 12 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Speed Grade Designations Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Spartan-7 device on a per speed grade basis. Table 13: Spartan-7 Device Speed Grade Designations Device Speed Grade, Temperature Range, and VCCINT Operating Voltage Advance Preliminary Production XC7S6 -2C (1.0V), -2I (1.0V), -1C (1.0V), -1I (1.0V), -1Q (1.0V), and -1LI (0.95V)(1) XC7S15 -2C (1.0V), -2I (1.0V), -1C (1.0V), -1I (1.0V), -1Q (1.0V), and -1LI (0.95V)(1) XC7S25 -2C (1.0V), -2I (1.0V), -1C (1.0V), -1I (1.0V), -1Q (1.0V), and -1LI (0.95V)(1) XC7S50 -2C (1.0V), -2I (1.0V), -1C (1.0V), -1I (1.0V), -1Q (1.0V), and -1LI (0.95V)(1) XC7S75 -2C (1.0V), -2I (1.0V), -1C (1.0V), -1I (1.0V), -1Q (1.0V), and -1LI (0.95V)(1) XC7S100 -2C (1.0V), -2I (1.0V), -1C (1.0V), -1I (1.0V), -1Q (1.0V), and -1LI (0.95V)(1) XA7S6 -2I (1.0V), -1I (1.0V), -1Q (1.0V) XA7S15 -2I (1.0V), -1I (1.0V), -1Q (1.0V) XA7S25 -2I (1.0V), -1I (1.0V), -1Q (1.0V) XA7S50 -2I (1.0V), -1I (1.0V), -1Q (1.0V) XA7S75 -2I (1.0V), -1I (1.0V), -1Q (1.0V) XA7S100 -2I (1.0V), -1I (1.0V), -1Q (1.0V) Notes: 1. The lowest power -1LI devices, where VCCINT = 0.95V, are listed in the Vivado Design Suite as -1IL. Production Silicon and Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 14 lists the production released Spartan-7 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 13 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 14: Spartan-7 Device Production Software and Speed Specification Release VCCINT Operating Voltage, Speed Grade, and Temperature Range 1.0V Device -2C -2I 0.95V -1C -1I -1Q -1LI XC7S6 Vivado tools 2018.2 v1.22 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.2 v1.22 XC7S15 Vivado tools 2018.2 v1.22 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.2 v1.22 XC7S25 Vivado tools 2017.4 v1.20 Vivado tools 2018.1 v1.21 Vivado tools 2017.4 v1.20 XC7S50 Vivado tools 2017.2 v1.17 Vivado tools 2017.3 v1.19 Vivado tools 2017.2 v1.17 XC7S75 Vivado tools 2018.1 v1.21 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.1 v1.21 XC7S100 Vivado tools 2018.1 v1.21 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.1 v1.21 XA7S6 N/A Vivado tools 2018.2.1 v1.16 N/A Vivado tools 2018.2.1 v1.16 N/A XA7S15 N/A Vivado tools 2018.2.1 v1.16 N/A Vivado tools 2018.2.1 v1.16 N/A XA7S25 N/A Vivado tools 2018.1 v1.15 N/A Vivado tools 2018.1 v1.15 N/A XA7S50 N/A Vivado tools 2017.3 v1.12 N/A Vivado tools 2017.3 v1.12 N/A XA7S75 N/A Vivado tools 2018.2.1 v1.16 N/A Vivado tools 2018.2.1 v1.16 N/A XA7S100 N/A Vivado tools 2018.2.1 v1.16 N/A Vivado tools 2018.2.1 v1.16 N/A Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Spartan-7 FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics, page 12. Table 15: Networking Applications Interface Performances VCCINT Operating Voltage, Speed Grade, and Temperature Range Description 1.0V SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) SDR LVDS receiver(1) DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com 0.95V Units -2C/-2I -1C/-1I/-1Q -1LI 680 600 600 Mb/s 1250 950 950 Mb/s 680 600 600 Mb/s Send Feedback 14 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 15: Networking Applications Interface Performances (Cont’d) VCCINT Operating Voltage, Speed Grade, and Temperature Range Description 1.0V DDR LVDS receiver(1) 0.95V -2C/-2I -1C/-1I/-1Q -1LI 1250 950 950 Units Mb/s Notes: 1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance. Table 16: Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface Generator(1) VCCINT Operating Voltage, Speed Grade, and Temperature Range Memory Standard 1.0V 0.95V Units -2C/-2I -1C/-1I/-1Q -1LI DDR3 800(2) 667 667 Mb/s DDR3L 800(2) 667 667 Mb/s DDR2 800(2) 667 667 Mb/s DDR3 800(2) 667 667 Mb/s DDR3L 800(2) 667 667 Mb/s DDR2 800(2) 667 667 Mb/s 667 533 533 Mb/s 4:1 Memory Controllers 2:1 Memory Controllers LPDDR2 Notes: 1. 2. VREF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586) [Ref 7]. The maximum PHY rate is 667 Mb/s in the FTGB196 package. IOB Pad Input/Output/3-State Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. • TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. • TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. • TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 15 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics TIOOP TIOPI TIOTP VCCINT Operating Voltage and Speed Grade I/O Standard 1.0V 0.95V 1.0V 0.95V 1.0V 0.95V Units -2 -1 -1L -2 -1 -1L -2 -1 -1L LVTTL_S4 1.34 1.41 1.41 3.93 4.18 4.18 3.96 4.20 4.20 ns LVTTL_S8 1.34 1.41 1.41 3.66 3.92 3.92 3.69 3.93 3.93 ns LVTTL_S12 1.34 1.41 1.41 3.65 3.90 3.90 3.68 3.91 3.91 ns LVTTL_S16 1.34 1.41 1.41 3.19 3.45 3.45 3.22 3.46 3.46 ns LVTTL_S24 1.34 1.41 1.41 3.41 3.67 3.67 3.44 3.68 3.68 ns LVTTL_F4 1.34 1.41 1.41 3.38 3.64 3.64 3.41 3.65 3.65 ns LVTTL_F8 1.34 1.41 1.41 2.87 3.12 3.12 2.90 3.13 3.13 ns LVTTL_F12 1.34 1.41 1.41 2.85 3.10 3.10 2.88 3.12 3.12 ns LVTTL_F16 1.34 1.41 1.41 2.68 2.93 2.93 2.71 2.95 2.95 ns LVTTL_F24 1.34 1.41 1.41 2.65 2.90 2.90 2.68 2.91 2.91 ns LVDS_25 0.81 0.88 0.88 1.41 1.67 1.67 1.44 1.68 1.68 ns MINI_LVDS_25 0.81 0.88 0.88 1.40 1.65 1.65 1.43 1.66 1.66 ns BLVDS_25 0.81 0.88 0.88 1.96 2.21 2.21 1.99 2.23 2.23 ns RSDS_25 (point to point) 0.81 0.88 0.88 1.40 1.65 1.65 1.43 1.66 1.66 ns PPDS_25 0.81 0.88 0.88 1.41 1.67 1.67 1.44 1.68 1.68 ns TMDS_33 0.81 0.88 0.88 1.54 1.79 1.79 1.57 1.80 1.80 ns PCI33_3 1.32 1.39 1.39 3.22 3.48 3.48 3.25 3.49 3.49 ns HSUL_12_S 0.75 0.82 0.82 1.93 2.18 2.18 1.96 2.20 2.20 ns HSUL_12_F 0.75 0.82 0.82 1.41 1.67 1.67 1.44 1.68 1.68 ns DIFF_HSUL_12_S 0.76 0.83 0.83 1.93 2.18 2.18 1.96 2.20 2.20 ns DIFF_HSUL_12_F 0.76 0.83 0.83 1.41 1.67 1.67 1.44 1.68 1.68 ns MOBILE_DDR_S 0.84 0.91 0.91 1.80 2.06 2.06 1.83 2.07 2.07 ns MOBILE_DDR_F 0.84 0.91 0.91 1.51 1.76 1.76 1.54 1.77 1.77 ns DIFF_MOBILE_DDR_S 0.78 0.85 0.85 1.82 2.07 2.07 1.85 2.09 2.09 ns DIFF_MOBILE_DDR_F 0.78 0.85 0.85 1.57 1.82 1.82 1.60 1.84 1.84 ns HSTL_I_S 0.75 0.82 0.82 1.74 1.99 1.99 1.77 2.01 2.01 ns HSTL_II_S 0.73 0.80 0.80 1.54 1.79 1.79 1.57 1.80 1.80 ns HSTL_I_18_S 0.75 0.82 0.82 1.41 1.67 1.67 1.44 1.68 1.68 ns HSTL_II_18_S 0.75 0.81 0.81 1.54 1.79 1.79 1.57 1.80 1.80 ns DIFF_HSTL_I_S 0.76 0.83 0.83 1.71 1.96 1.96 1.74 1.98 1.98 ns DIFF_HSTL_II_S 0.76 0.83 0.83 1.63 1.88 1.88 1.66 1.90 1.90 ns DIFF_HSTL_I_18_S 0.79 0.86 0.86 1.51 1.76 1.76 1.54 1.77 1.77 ns DIFF_HSTL_II_18_S 0.78 0.85 0.85 1.58 1.84 1.84 1.61 1.85 1.85 ns HSTL_I_F 0.75 0.82 0.82 1.22 1.48 1.48 1.25 1.49 1.49 ns HSTL_II_F 0.73 0.80 0.80 1.24 1.49 1.49 1.27 1.51 1.51 ns HSTL_I_18_F 0.75 0.82 0.82 1.26 1.51 1.51 1.29 1.52 1.52 ns DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 16 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) TIOPI TIOOP TIOTP VCCINT Operating Voltage and Speed Grade I/O Standard 1.0V 0.95V 1.0V 0.95V 1.0V 0.95V Units -2 -1 -1L -2 -1 -1L -2 -1 -1L HSTL_II_18_F 0.75 0.81 0.81 1.24 1.49 1.49 1.27 1.51 1.51 ns DIFF_HSTL_I_F 0.76 0.83 0.83 1.30 1.56 1.56 1.33 1.57 1.57 ns DIFF_HSTL_II_F 0.76 0.83 0.83 1.33 1.59 1.59 1.36 1.60 1.60 ns DIFF_HSTL_I_18_F 0.79 0.86 0.86 1.33 1.59 1.59 1.36 1.60 1.60 ns DIFF_HSTL_II_18_F 0.78 0.85 0.85 1.33 1.59 1.59 1.36 1.60 1.60 ns LVCMOS33_S4 1.34 1.41 1.41 3.93 4.18 4.18 3.96 4.20 4.20 ns LVCMOS33_S8 1.34 1.41 1.41 3.65 3.90 3.90 3.68 3.91 3.91 ns LVCMOS33_S12 1.34 1.41 1.41 3.21 3.46 3.46 3.24 3.48 3.48 ns LVCMOS33_S16 1.34 1.41 1.41 3.52 3.77 3.77 3.55 3.79 3.79 ns LVCMOS33_F4 1.34 1.41 1.41 3.38 3.64 3.64 3.41 3.65 3.65 ns LVCMOS33_F8 1.34 1.41 1.41 2.87 3.12 3.12 2.90 3.13 3.13 ns LVCMOS33_F12 1.34 1.41 1.41 2.68 2.93 2.93 2.71 2.95 2.95 ns LVCMOS33_F16 1.34 1.41 1.41 2.68 2.93 2.93 2.71 2.95 2.95 ns LVCMOS25_S4 1.20 1.27 1.27 3.26 3.51 3.51 3.29 3.52 3.52 ns LVCMOS25_S8 1.20 1.27 1.27 3.01 3.26 3.26 3.04 3.27 3.27 ns LVCMOS25_S12 1.20 1.27 1.27 2.60 2.85 2.85 2.63 2.87 2.87 ns LVCMOS25_S16 1.20 1.27 1.27 2.94 3.20 3.20 2.97 3.21 3.21 ns LVCMOS25_F4 1.20 1.27 1.27 2.87 3.12 3.12 2.90 3.13 3.13 ns LVCMOS25_F8 1.20 1.27 1.27 2.30 2.56 2.56 2.33 2.57 2.57 ns LVCMOS25_F12 1.20 1.27 1.27 2.29 2.54 2.54 2.32 2.55 2.55 ns LVCMOS25_F16 1.20 1.27 1.27 2.13 2.39 2.39 2.16 2.40 2.40 ns LVCMOS18_S4 0.83 0.89 0.89 1.74 1.99 1.99 1.77 2.01 2.01 ns LVCMOS18_S8 0.83 0.89 0.89 2.30 2.56 2.56 2.33 2.57 2.57 ns LVCMOS18_S12 0.83 0.89 0.89 2.30 2.56 2.56 2.33 2.57 2.57 ns LVCMOS18_S16 0.83 0.89 0.89 1.65 1.90 1.90 1.68 1.91 1.91 ns LVCMOS18_S24 0.83 0.89 0.89 1.72 1.98 1.98 1.75 1.99 1.99 ns LVCMOS18_F4 0.83 0.89 0.89 1.57 1.82 1.82 1.60 1.84 1.84 ns LVCMOS18_F8 0.83 0.89 0.89 1.80 2.06 2.06 1.83 2.07 2.07 ns LVCMOS18_F12 0.83 0.89 0.89 1.80 2.06 2.06 1.83 2.07 2.07 ns LVCMOS18_F16 0.83 0.89 0.89 1.52 1.77 1.77 1.55 1.79 1.79 ns LVCMOS18_F24 0.83 0.89 0.89 1.46 1.71 1.71 1.49 1.73 1.73 ns LVCMOS15_S4 0.86 0.93 0.93 2.18 2.43 2.43 2.21 2.45 2.45 ns LVCMOS15_S8 0.86 0.93 0.93 2.21 2.46 2.46 2.24 2.48 2.48 ns LVCMOS15_S12 0.86 0.93 0.93 1.71 1.96 1.96 1.74 1.98 1.98 ns LVCMOS15_S16 0.86 0.93 0.93 1.71 1.96 1.96 1.74 1.98 1.98 ns LVCMOS15_F4 0.86 0.93 0.93 1.97 2.23 2.23 2.00 2.24 2.24 ns DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 17 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) TIOPI TIOOP TIOTP VCCINT Operating Voltage and Speed Grade I/O Standard 1.0V 0.95V 1.0V 0.95V 1.0V 0.95V Units -2 -1 -1L -2 -1 -1L -2 -1 -1L LVCMOS15_F8 0.86 0.93 0.93 1.72 1.98 1.98 1.75 1.99 1.99 ns LVCMOS15_F12 0.86 0.93 0.93 1.47 1.73 1.73 1.50 1.74 1.74 ns LVCMOS15_F16 0.86 0.93 0.93 1.46 1.71 1.71 1.49 1.73 1.73 ns LVCMOS12_S4 0.95 1.02 1.02 2.69 2.95 2.95 2.72 2.96 2.96 ns LVCMOS12_S8 0.95 1.02 1.02 2.21 2.46 2.46 2.24 2.48 2.48 ns LVCMOS12_S12 0.95 1.02 1.02 1.91 2.17 2.17 1.94 2.18 2.18 ns LVCMOS12_F4 0.95 1.02 1.02 2.10 2.35 2.35 2.13 2.37 2.37 ns LVCMOS12_F8 0.95 1.02 1.02 1.66 1.92 1.92 1.69 1.93 1.93 ns LVCMOS12_F12 0.95 1.02 1.02 1.51 1.76 1.76 1.54 1.77 1.77 ns SSTL135_S 0.75 0.82 0.82 1.47 1.73 1.73 1.50 1.74 1.74 ns SSTL15_S 0.68 0.75 0.75 1.43 1.68 1.68 1.46 1.69 1.69 ns SSTL18_I_S 0.75 0.82 0.82 1.79 2.04 2.04 1.82 2.06 2.06 ns SSTL18_II_S 0.75 0.82 0.82 1.43 1.68 1.68 1.46 1.70 1.70 ns DIFF_SSTL135_S 0.76 0.83 0.83 1.47 1.73 1.73 1.50 1.74 1.74 ns DIFF_SSTL15_S 0.76 0.83 0.83 1.43 1.68 1.68 1.46 1.69 1.69 ns DIFF_SSTL18_I_S 0.79 0.86 0.86 1.80 2.06 2.06 1.83 2.07 2.07 ns DIFF_SSTL18_II_S 0.79 0.86 0.86 1.51 1.76 1.76 1.54 1.77 1.77 ns SSTL135_F 0.75 0.82 0.82 1.24 1.49 1.49 1.27 1.51 1.51 ns SSTL15_F 0.68 0.75 0.75 1.19 1.45 1.45 1.22 1.46 1.46 ns SSTL18_I_F 0.75 0.82 0.82 1.24 1.49 1.49 1.27 1.51 1.51 ns SSTL18_II_F 0.75 0.82 0.82 1.24 1.49 1.49 1.27 1.51 1.51 ns DIFF_SSTL135_F 0.76 0.83 0.83 1.24 1.49 1.49 1.27 1.51 1.51 ns DIFF_SSTL15_F 0.76 0.83 0.83 1.19 1.45 1.45 1.22 1.46 1.46 ns DIFF_SSTL18_I_F 0.79 0.86 0.86 1.35 1.60 1.60 1.38 1.62 1.62 ns DIFF_SSTL18_II_F 0.79 0.86 0.86 1.33 1.59 1.59 1.36 1.60 1.60 ns Table 18 specifies the values of T IOTPHZ and TIOIBUFDISABLE . TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 18 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 18: IOB 3-state Output Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units TIOTPHZ T input to pad high-impedance. 2.19 2.37 2.37 ns TIOIBUFDISABLE IBUF turn-on time from IBUFDISABLE to O output. 2.30 2.60 2.60 ns DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 19 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 19 shows the test setup parameters used for measuring input delay. Table 19: Input Delay Measurement Methodology Description I/O Standard Attribute VL(1) VH(1) VMEAS(3)(5) VREF(2)(4) LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 – LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 – LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 – LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 – LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 – LVTTL, 3.3V LVTTL 0.1 3.2 1.65 – MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9 – PCI33, 3.3V PCI33_3 0.1 3.2 1.65 – VREF – 0.5 VREF + 0.5 VREF 0.60 VREF – 0.65 VREF + 0.65 VREF 0.75 HSTL (high-speed transceiver HSTL_I_12 logic), Class I, 1.2V HSTL, Class I & II, 1.5V HSTL_I, HSTL_II HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF – 0.8 VREF + 0.8 VREF 0.90 HSUL (high-speed unterminated logic), 1.2V HSUL_12 VREF – 0.5 VREF + 0.5 VREF 0.60 SSTL (stub-terminated transceiver logic), 1.2V SSTL12 VREF – 0.5 VREF + 0.5 VREF 0.60 SSTL, 1.35V SSTL135, SSTL135_R VREF – 0.575 VREF + 0.575 VREF 0.675 SSTL, 1.5V SSTL15, SSTL15_R VREF – 0.65 VREF + 0.65 VREF 0.75 SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF – 0.8 VREF + 0.8 VREF 0.90 DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9 – 0.125 0.9 + 0.125 0(5) – DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.125 0.6 + 0.125 0(5) – DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I, DIFF_HSTL_II 0.75 – 0.125 0.75 + 0.125 0(5) – DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 0.9 – 0.125 0.9 + 0.125 0(5) – DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.125 0.6 + 0.125 0(5) – DIFF_SSTL135/ DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 0(5) – DIFF_SSTL15/ DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 0.75 – 0.125 0.75 + 0.125 0(5) – DIFF_SSTL18_I/ DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 0.9 – 0.125 0.9 + 0.125 0(5) – LVDS_25, 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0(5) – BLVDS_25, 2.5V BLVDS_25 1.25 – 0.125 1.25 + 0.125 0(5) – MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25 – 0.125 1.25 + 0.125 0(5) – DS189 (v1.9) March 13, 2019 Product Specification 0.675 – 0.125 0.675 + 0.125 www.xilinx.com Send Feedback 20 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 19: Input Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute VL(1) VH(1) VMEAS(3)(5) VREF(2)(4) PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0(5) – RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0(5) – TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0(5) – Notes: 1. 2. 3. 4. 5. Input waveform switches between VL and VH. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. Input voltage level from which measurement starts. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 1. The value given is the differential input voltage. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 21 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Output Delay Measurements Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2. X-Ref Target - Figure 1 VREF RREF Output VMEAS (voltage level when taking delay measurement) CREF (probe capacitance) X16654-092616 Figure 1: Single-ended Test Setup X-Ref Target - Figure 2 Output + CREF RREF VMEAS – X16640-092616 Figure 2: Differential Test Setup Parameters V REF, R REF, C REF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method: 1. Simulate the output driver of choice into the generalized test setup using values from Table 20. 2. Record the time to V MEAS. 3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to V MEAS. 5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 22 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 20: Output Delay Measurement Methodology Description I/O Standard Attribute RREF (Ω) CREF(1) VMEAS (pF) (V) VREF (V) LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0 LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0 LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0 LVTTL, 3.3V LVTTL 1M 0 1.65 0 PCI33, 3.3V PCI33_3 25 10 1.65 0 HSTL (high-speed transceiver logic), Class I, 1.2V HSTL_I_12 50 0 VREF 0.6 HSTL, Class I, 1.5V HSTL_I 50 0 VREF 0.75 HSTL, Class II, 1.5V HSTL_II 25 0 VREF 0.75 HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9 HSUL (high-speed unterminated logic), 1.2V HSUL_12 50 0 VREF 0.6 SSTL12, 1.2V SSTL12 50 0 VREF 0.6 SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 VREF 0.675 SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 VREF 0.75 SSTL (stub-series terminated logic), Class I & Class II, 1.8V SSTL18_I, SSTL18_II 50 0 VREF 0.9 DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 VREF 0.9 DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6 DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 VREF 0.75 DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 VREF 0.9 DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 VREF 0.6 DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 VREF 0.675 DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 VREF 0.75 DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 VREF 0.9 LVDS, 2.5V LVDS_25 100 0 0(2) 0 BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(2) 0 Mini LVDS, 2.5V MINI_LVDS_25 100 0 0(2) 0 0 0(2) 0 0 0(2) 0 0 0(2) 3.3 PPDS_25 RSDS_25 TMDS_33 PPDS_25 RSDS_25 TMDS_33 100 100 50 Notes: 1. 2. CREF is the capacitance of the probe, nominally 0 pF. The value given is the differential output voltage. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 23 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input/Output Logic Switching Characteristics Table 21: ILOGIC Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L Setup/Hold TICE1CK/TICKCE1 CE1 pin setup/hold with respect to CLK. 0.54/0.02 0.76/0.02 0.76/0.02 ns TISRCK/TICKSR SR pin setup/hold with respect to CLK. 0.70/0.01 1.13/0.01 1.13/0.01 ns TIDOCK/TIOCKD D pin setup/hold with respect to CLK without delay. 0.01/0.29 0.01/0.33 0.01/0.33 ns TIDOCKD/TIOCKDD DDLY pin setup/hold with respect to CLK (using IDELAY). 0.02/0.29 0.02/0.33 0.02/0.33 ns Combinatorial TIDI D pin to O pin propagation delay, no delay. 0.11 0.13 0.13 ns TIDID DDLY pin to O pin propagation delay (using IDELAY). 0.12 0.14 0.14 ns TIDLO D pin to Q1 pin using flip-flop as a latch without delay. 0.44 0.51 0.51 ns TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY). 0.44 0.51 0.51 ns TICKQ CLK to Q outputs. 0.57 0.66 0.66 ns TRQ_ILOGIC SR pin to OQ/TQ out. 1.08 1.32 1.32 ns TGSRQ_ILOGIC Global set/reset to Q outputs. 7.60 10.51 10.51 ns Minimum pulse width, SR inputs. 0.72 0.72 0.72 ns, Min Sequential Delays Set/Reset TRPW_ILOGIC DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 24 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 22: OLOGIC Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L Setup/Hold TODCK/TOCKD D1/D2 pins setup/hold with respect to CLK. 0.71/–0.11 0.84/–0.11 0.84/–0.11 ns TOOCECK/TOCKOCE OCE pin setup/hold with respect to CLK. 0.34/0.58 0.51/0.58 0.51/0.58 ns TOSRCK/TOCKSR SR pin setup/hold with respect to CLK. 0.44/0.21 0.80/0.21 0.80/0.21 ns TOTCK/TOCKT T1/T2 pins setup/hold with respect to CLK. TOTCECK/TOCKTCE TCE pin setup/hold with respect to CLK. 0.73/–0.14 0.89/–0.14 0.89/–0.14 ns 0.34/0.01 0.51/0.01 0.51/0.01 ns D1 to OQ out or T1 to TQ out. 0.96 1.16 1.16 ns TOCKQ CLK to OQ/TQ out. 0.49 0.56 0.56 ns TRQ_OLOGIC SR pin to OQ/TQ out. 0.80 0.95 0.95 ns TGSRQ_OLOGIC Global set/reset to Q outputs. 7.60 10.51 10.51 ns Minimum pulse width, SR inputs. 0.74 0.74 0.74 ns, Min Combinatorial TODQ Sequential Delays Set/Reset TRPW_OLOGIC DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 25 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 23: ISERDES Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L 0.02/0.15 0.02/0.17 0.02/0.17 Units Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin setup/hold with respect to CLKDIV. TISCCK_CE/ TISCKC_CE CE pin setup/hold with respect to CLK (for CE1). 0.50/–0.01 0.72/–0.01 0.72/–0.01 ns TISCCK_CE2/ TISCKC_CE2 CE pin setup/hold with respect to CLKDIV (for CE2). –0.10/0.36 –0.10/0.40 –0.10/0.40 ns ns Setup/Hold for Data Lines TISDCK_D/ TISCKD_D D pin setup/hold with respect to CLK. –0.02/0.14 –0.02/0.17 –0.02/0.17 ns TISDCK_DDLY/ TISCKD_DDLY DDLY pin setup/hold with respect to CLK (using IDELAY).(1) –0.02/0.14 –0.02/0.17 –0.02/0.17 ns TISDCK_D_DDR/ TISCKD_D_DDR D pin setup/hold with respect to CLK at DDR mode. –0.02/0.14 –0.02/0.17 –0.02/0.17 ns TISDCK_DDLY_DDR/ D pin setup/hold with respect to CLK at TISCKD_DDLY_DDR DDR mode (using IDELAY).(1) 0.14/0.14 0.17/0.17 0.17/0.17 ns CLKDIV to out at Q pin. 0.54 0.66 0.66 ns D input to DO output pin. 0.11 0.13 0.13 ns Sequential Delays TISCKO_Q Propagation Delays TISDO_DO Notes: 1. Recorded at 0 tap value. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 26 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Output Serializer/Deserializer Switching Characteristics Table 24: OSERDES Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L 0.45/0.03 0.63/0.03 0.63/0.03 Units Setup/Hold TOSDCK_D/ TOSCKD_D D input setup/hold with respect to CLKDIV. TOSDCK_T/ TOSCKD_T T input setup/hold with respect to CLK. 0.73/–0.13 0.88/–0.13 0.88/–0.13 ns TOSDCK_T2/ TOSCKD_T2 T input setup/hold with respect to CLKDIV. 0.34/–0.13 0.39/–0.13 0.39/–0.13 ns TOSCCK_OCE/ OCE input setup/hold with respect to CLK. TOSCKC_OCE TOSCCK_S SR (reset) input setup with respect to CLKDIV. TOSCCK_TCE/ TOSCKC_TCE TCE input setup/hold with respect to CLK. ns 0.34/0.58 0.51/0.58 0.51/0.58 ns 0.52 0.85 0.85 ns 0.34/0.01 0.51/0.01 0.51/0.01 ns Sequential Delays TOSCKO_OQ Clock to out from CLK to OQ. 0.42 0.48 0.48 ns TOSCKO_TQ Clock to out from CLK to TQ. 0.49 0.56 0.56 ns T input to TQ out. 0.92 1.11 1.11 ns Combinatorial TOSDO_TTQ DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 27 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Input/Output Delay Switching Characteristics Table 25: Input/Output Delay Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units IDELAYCTRL TDLYCCO_RDY FIDELAYCTRL_REF Reset to ready for IDELAYCTRL. 3.67 3.67 3.67 µs Attribute REFCLK frequency = 200.00.(1) 200.00 200.00 200.00 MHz Attribute REFCLK frequency = 300.00.(1) 300.00 300.00 300.00 MHz Attribute REFCLK frequency = 400.00.(1) 400.00 N/A N/A MHz ±10 ±10 ±10 MHz 59.28 59.28 59.28 ns IDELAYCTRL_REF_ REFCLK precision PRECISION TIDELAYCTRL_RPW Minimum reset pulse width. IDELAY TIDELAYRESOLUTION TIDELAYPAT_JIT IDELAY chain delay resolution. 1/(32 x 2 x FREF) µs Pattern dependent period jitter in delay chain for clock pattern.(2) 0 0 0 ps per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23).(3) ±5 ±5 ±5 ps per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23).(4) ±9 ±9 ±9 ps per tap 680.00 600.00 600.00 MHz TIDELAY_CLK_MAX Maximum frequency of CLK input to IDELAY. TIDCCK_CE / TIDCKC_CE CE pin setup/hold with respect to C for IDELAY. 0.16/0.13 0.21/0.16 0.21/0.16 ns TIDCCK_INC/ TIDCKC_INC INC pin setup/hold with respect to C for IDELAY. 0.14/0.18 0.16/0.22 0.16/0.22 ns TIDCCK_RST/ TIDCKC_RST RST pin setup/hold with respect to C for IDELAY. 0.16/0.11 0.18/0.14 0.18/0.14 ns TIDDO_IDATAIN Propagation delay through IDELAY. ps Note 5 Note 5 Note 5 Notes: 1. 2. 3. 4. 5. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. When HIGH_PERFORMANCE mode is set to TRUE. When HIGH_PERFORMANCE mode is set to FALSE. Delay depends on IDELAY tap setting. See the timing report for actual values. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 28 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 26: IO_FIFO Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units IO_FIFO Clock to Out Delays TOFFCKO_DO RDCLK to Q outputs. 0.60 0.68 0.68 ns TCKO_FLAGS Clock to IO_FIFO flags. 0.61 0.77 0.77 ns 0.51/0.02 0.58/0.02 0.58/0.02 ns Setup/Hold TCCK_D/TCKC_D D inputs to WRCLK. TIFFCCK_WREN/ TIFFCKC_WREN WREN to WRCLK. TOFFCCK_RDEN/ TOFFCKC_RDEN RDEN to RDCLK. 0.47/–0.01 0.53/–0.01 0.53/–0.01 ns 0.58/0.02 0.66/0.02 0.66/0.02 ns Minimum Pulse Width TPWH_IO_FIFO RESET, RDCLK, WRCLK. 2.15 2.15 2.15 ns TPWL_IO_FIFO RESET, RDCLK, WRCLK. 2.15 2.15 2.15 ns 200.00 200.00 200.00 MHz Maximum Frequency FMAX RDCLK and WRCLK. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 29 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics CLB Switching Characteristics Table 27: CLB Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units Combinatorial Delays TILO An – Dn LUT address to A. 0.11 0.13 0.13 ns, Max TILO_2 An – Dn LUT address to AMUX/CMUX. 0.30 0.36 0.36 ns, Max TILO_3 An – Dn LUT address to BMUX_A. 0.46 0.55 0.55 ns, Max TITO An – Dn inputs to A – D Q outputs. 1.05 1.27 1.27 ns, Max TAXA AX inputs to AMUX output. 0.69 0.84 0.84 ns, Max TAXB AX inputs to BMUX output. 0.66 0.83 0.83 ns, Max TAXC AX inputs to CMUX output. 0.68 0.82 0.82 ns, Max TAXD AX inputs to DMUX output. 0.75 0.90 0.90 ns, Max TBXB BX inputs to BMUX output. 0.57 0.69 0.69 ns, Max TBXD BX inputs to DMUX output. 0.69 0.82 0.82 ns, Max TCXC CX inputs to CMUX output. 0.48 0.58 0.58 ns, Max TCXD CX inputs to DMUX output. 0.59 0.71 0.71 ns, Max TDXD DX inputs to DMUX output. 0.58 0.70 0.70 ns, Max Sequential Delays TCKO Clock to AQ – DQ outputs. 0.44 0.53 0.53 ns, Max TSHCKO Clock to AMUX – DMUX outputs. 0.53 0.66 0.66 ns, Max AN – DN input to CLK on A – D flip-flops. 0.09/0.14 0.11/0.18 0.11/0.18 ns, Min AX – DX input to CLK on A – D flip-flops. 0.07/0.21 0.09/0.26 0.09/0.26 ns, Min AX – DX input through MUXs and/or carry logic to CLK on A – D flip-flops. 0.66/0.09 0.81/0.11 0.81/0.11 ns, Min TCECK_CLB/ TCKCE_CLB CE input to CLK on A – D flip-flops. 0.17/0.00 0.21/0.01 0.21/0.01 ns, Min TSRCK/TCKSR SR input to CLK on A – D flip-flops. 0.43/0.04 0.53/0.05 0.53/0.05 ns, Min Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TAS/TAH TDICK/TCKDI Set/Reset TSRMIN SR input minimum pulse width. 0.78 1.04 1.04 ns, Min TRQ Delay from SR input to AQ – DQ flip-flops. 0.59 0.71 0.71 ns, Max TCEO Delay from CE input to AQ – DQ flip-flops. 0.58 0.70 0.70 ns, Max FTOG Toggle frequency (for export control). 1286 1098 1098 MHz DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 30 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 28: CLB Distributed RAM Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units Sequential Delays TSHCKO Clock to A – B outputs. 1.09 1.32 1.32 ns, Max TSHCKO_1 Clock to AMUX – BMUX outputs. 1.53 1.86 1.86 ns, Max Setup and Hold Times Before/After Clock CLK TDS_LRAM/TDH_LRAM A – D inputs to CLK. 0.60/0.30 0.72/0.35 0.72/0.35 ns, Min Address An inputs to clock. 0.30/0.60 0.37/0.70 0.37/0.70 ns, Min TAS_LRAM/TAH_LRAM Address An inputs through MUXs and/or carry logic to clock. 0.77/0.21 0.94/0.26 0.94/0.26 ns, Min TWS_LRAM/TWH_LRAM WE input to clock. 0.43/0.12 0.53/0.17 0.53/0.17 ns, Min TCECK_LRAM/TCKCE_LRAM CE input to CLK. 0.44/0.11 0.53/0.17 0.53/0.17 ns, Min Clock CLK TMPW_LRAM Minimum pulse width. 1.13 1.25 1.25 ns, Min TMCP Minimum clock period. 2.26 2.50 2.50 ns, Min Notes: 1. TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path. CLB Shift Register Switching Characteristics (SLICEM Only) Table 29: CLB Shift Register Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units Sequential Delays TREG Clock to A – D outputs. 1.33 1.61 1.61 ns, Max TREG_MUX Clock to AMUX – DMUX output. 1.77 2.15 2.15 ns, Max TREG_M31 Clock to DMUX output via M31 output. 1.23 1.46 1.46 ns, Max Setup and Hold Times Before/After Clock CLK TWS_SHFREG/ TWH_SHFREG WE input. 0.41/0.12 0.51/0.17 0.51/0.17 ns, Min TCECK_SHFREG/ TCKCE_SHFREG CE input to CLK. 0.42/0.11 0.52/0.17 0.52/0.17 ns, Min TDS_SHFREG/ TDH_SHFREG A – D inputs to CLK. 0.37/0.37 0.44/0.43 0.44/0.43 ns, Min Clock CLK TMPW_SHFREG DS189 (v1.9) March 13, 2019 Product Specification Minimum pulse width. www.xilinx.com 0.86 0.98 0.98 Send Feedback ns, Min 31 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Block RAM and FIFO Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V Units -2 -1 -1L Clock CLK to DOUT output (without output register).(1)(2) 2.13 2.46 2.46 ns, Max Clock CLK to DOUT output (with output register).(3)(4) 0.74 0.89 0.89 ns, Max Clock CLK to DOUT output with ECC (without output register).(1)(2) 3.04 3.84 3.84 ns, Max Clock CLK to DOUT output with ECC (with output register).(3)(4) 0.81 0.94 0.94 ns, Max 2.88 3.30 3.30 ns, Max 1.28 1.46 1.46 ns, Max Block RAM and FIFO Clock-to-Out Delays TRCKO_DO and TRCKO_DO_REG TRCKO_DO_ECC and TRCKO_DO_ECC_REG Clock CLK to DOUT output with cascade (1) and (without output register). TRCKO_DO_CASCOUT TRCKO_DO_CASCOUT_REG Clock CLK to DOUT output with cascade (with output register).(3) TRCKO_FLAGS Clock CLK to FIFO flags outputs.(5) 0.87 1.05 1.05 ns, Max TRCKO_POINTERS Clock CLK to FIFO pointers outputs.(6) 1.02 1.15 1.15 ns, Max TRCKO_PARITY_ECC Clock CLK to ECCPARITY in ECC encode only mode. 0.85 0.94 0.94 ns, Max Clock CLK to BITERR (without output register). 2.81 3.55 3.55 ns, Max Clock CLK to BITERR (with output register). 0.76 0.89 0.89 ns, Max 0.88 1.07 1.07 ns, Max 0.93 1.08 1.08 ns, Max TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG Clock CLK to RDADDR output with ECC TRCKO_RDADDR_ECC and (without output register). TRCKO_RDADDR_ECC_REG Clock CLK to RDADDR output with ECC (with output register). Setup and Hold Times Before/After Clock CLK TRCCK_ADDRA/ TRCKC_ADDRA ADDR inputs.(7) 0.49/0.33 0.57/0.36 0.57/0.36 ns, Min TRDCK_DI_WF_NC/ TRCKD_DI_WF_NC Data input setup/hold time when block RAM is configured in WRITE_FIRST or NO_CHANGE mode.(8) 0.65/0.63 0.74/0.67 0.74/0.67 ns, Min TRDCK_DI_RF/ TRCKD_DI_RF Data input setup/hold time when block RAM is configured in READ_FIRST mode.(8) 0.22/0.34 0.25/0.41 0.25/0.41 ns, Min TRDCK_DI_ECC/ TRCKD_DI_ECC DIN inputs with block RAM ECC in standard mode.(8) 0.55/0.46 0.63/0.50 0.63/0.50 ns, Min TRDCK_DI_ECCW/ TRCKD_DI_ECCW DIN inputs with block RAM ECC encode only.(8) 1.02/0.46 1.17/0.50 1.17/0.50 ns, Min DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 32 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units TRDCK_DI_ECC_FIFO/ TRCKD_DI_ECC_FIFO DIN inputs with FIFO ECC in standard mode.(8) 1.15/0.59 1.32/0.64 1.32/0.64 ns, Min TRCCK_INJECTBITERR/ TRCKC_INJECTBITERR Inject single/double bit error in ECC mode. 0.64/0.37 0.74/0.40 0.74/0.40 ns, Min TRCCK_EN/TRCKC_EN Block RAM enable (EN) input. 0.39/0.21 0.45/0.23 0.45/0.23 ns, Min TRCCK_REGCE/ TRCKC_REGCE CE input of output register. 0.29/0.15 0.36/0.16 0.36/0.16 ns, Min TRCCK_RSTREG/ TRCKC_RSTREG Synchronous RSTREG input. 0.32/0.07 0.35/0.07 0.35/0.07 ns, Min TRCCK_RSTRAM/ TRCKC_RSTRAM Synchronous RSTRAM input. 0.34/0.43 0.36/0.46 0.36/0.46 ns, Min TRCCK_WEA/TRCKC_WEA Write enable (WE) input (block RAM only). 0.48/0.19 0.54/0.20 0.54/0.20 ns, Min TRCCK_WREN/ TRCKC_WREN WREN FIFO inputs. 0.46/0.35 0.47/0.43 0.47/0.43 ns, Min TRCCK_RDEN/ TRCKC_RDEN RDEN FIFO inputs. 0.43/0.35 0.43/0.43 0.43/0.43 ns, Min 0.98 1.10 1.10 ns, Max Reset Delays TRCO_FLAGS Reset RST to FIFO flags/pointers.(9) TRREC_RST/TRREM_RST FIFO reset recovery and removal timing.(10) 2.07/–0.81 2.37/–0.81 2.37/–0.81 ns, Max Maximum Frequency FMAX_BRAM_WF_NC FMAX_BRAM_RF_ PERFORMANCE FMAX_BRAM_RF_ DELAYED_WRITE FMAX_CAS_WF_NC FMAX_CAS_RF_ PERFORMANCE Block RAM (write first and no change modes) when not in SDP RF mode. 460.83 388.20 388.20 MHz Block RAM (read first, performance mode) when in SDP RF mode but no address overlap between port A and port B. 460.83 388.20 388.20 MHz Block RAM (read first, delayed write mode) when in SDP RF mode and there is possibility of overlap between port A and port B addresses. 404.53 339.67 339.67 MHz Block RAM cascade (write first, no change mode) when cascade but not in RF mode. 418.59 345.78 345.78 MHz Block RAM cascade (read first, performance mode) when in cascade with RF mode and no possibility of address overlap/one port is disabled. 418.59 345.78 345.78 MHz DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 33 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V Units -2 -1 -1L When in cascade RF mode and there is a possibility of address overlap between port A and port B. 362.19 297.35 297.35 MHz FMAX_FIFO FIFO in all modes without ECC. 460.83 388.20 388.20 MHz FMAX_ECC Block RAM and FIFO in ECC configuration. 365.10 297.53 297.53 MHz FMAX_CAS_RF_ DELAYED_WRITE Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. These parameters also apply to synchronous FIFO with DO_REG = 0. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. These parameters also apply to multi-rate (asynchronous) and synchronous FIFO with DO_REG = 1. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. These parameters include both A and B inputs as well as the parity inputs of A and B. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK). DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 34 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DSP48E1 Switching Characteristics Table 31: DSP48E1 Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade 1.0V Units 0.95V -2 -1 -1L Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK. 0.30/ 0.13 0.37/ 0.14 0.37/ 0.14 ns TDSPDCK_B_BREG/ TDSPCKD_B_BREG B input to B register CLK. 0.38/ 0.16 0.45/ 0.18 0.45/ 0.18 ns TDSPDCK_C_CREG/ TDSPCKD_C_CREG C input to C register CLK. 0.20/ 0.19 0.24/ 0.21 0.24/ 0.21 ns TDSPDCK_D_DREG/ TDSPCKD_D_DREG D input to D register CLK. 0.32/ 0.27 0.42/ 0.27 0.42/ 0.27 ns TDSPDCK_ACIN_AREG/ TDSPCKD_ACIN_AREG ACIN input to A register CLK. 0.27/ 0.13 0.32/ 0.14 0.32/ 0.14 ns TDSPDCK_BCIN_BREG/ TDSPCKD_BCIN_BREG BCIN input to B register CLK. 0.29/ 0.16 0.36/ 0.18 0.36/ 0.18 ns Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{A, B}_MREG_MULT/ TDSPCKD_{A, B}_MREG_MULT {A, B} input to M register CLK using multiplier. 2.76/ –0.01 3.29/ –0.01 3.29/ –0.01 ns TDSPDCK_{A, D}_ADREG/ TDSPCKD_{A, D}_ADREG {A, D} input to AD register CLK. 1.48/ –0.02 1.76/ –0.02 1.76/ –0.02 ns Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{A, B}_PREG_MULT/ TDSPCKD_{A, B} _PREG_MULT {A, B} input to P register CLK using multiplier. 4.60/ –0.28 5.48/ –0.28 5.48/ –0.28 ns TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT D input to P register CLK using multiplier. 4.50/ –0.73 5.35/ –0.73 5.35/ –0.73 ns TDSPDCK_{A, B} _PREG/ TDSPCKD_{A, B} _PREG A or B input to P register CLK not using multiplier. 1.98/ –0.28 2.35/ –0.28 2.35/ –0.28 ns TDSPDCK_C_PREG/ TDSPCKD_C_PREG C input to P register CLK not using multiplier. 1.76/ –0.26 2.10/ –0.26 2.10/ –0.26 ns TDSPDCK_PCIN_PREG/ TDSPCKD_PCIN_PREG PCIN input to P register CLK. 1.51/ –0.15 1.80/ –0.15 1.80/ –0.15 ns TDSPDCK_{CEA;CEB}_{AREG;BREG}/ TDSPCKD_{CEA;CEB}_{AREG;BREG} {CEA; CEB} input to {A; B} register CLK. 0.42/ 0.08 0.52/ 0.11 0.52/ 0.11 ns TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG CEC input to C register CLK. 0.34/ 0.11 0.42/ 0.13 0.42/ 0.13 ns TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG CED input to D register CLK. 0.43/ –0.03 0.52/ –0.03 0.52/ –0.03 ns Setup and Hold Times of the CE Pins DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 35 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade 1.0V Units 0.95V -2 -1 -1L TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG CEM input to M register CLK. 0.21/ 0.20 0.27/ 0.23 0.27/ 0.23 ns TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG CEP input to P register CLK. 0.43/ 0.01 0.53/ 0.01 0.53/ 0.01 ns TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ {RSTA, RSTB} input to {A, B} register CLK. TDSPCKD_{RSTA; RSTB}_{AREG; BREG} 0.46/ 0.13 0.55/ 0.15 0.55/ 0.15 ns TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG RSTC input to C register CLK. 0.08/ 0.11 0.09/ 0.12 0.09/ 0.12 ns TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG RSTD input to D register CLK 0.50/ 0.08 0.59/ 0.09 0.59/ 0.09 ns TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG RSTM input to M register CLK 0.23/ 0.24 0.27/ 0.28 0.27/ 0.28 ns TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG RSTP input to P register CLK 0.30/ 0.01 0.35/ 0.01 0.35/ 0.01 ns Setup and Hold Times of the RST Pins Combinatorial Delays from Input Pins to Output Pins TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output using multiplier. 4.35 5.18 5.18 ns TDSPDO_D_P_MULT D input to P output using multiplier. 4.26 5.07 5.07 ns TDSPDO_B_P B input to P output not using multiplier. 1.75 2.08 2.08 ns TDSPDO_C_P C input to P output. 1.53 1.82 1.82 ns Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT, BCOUT} output. 0.63 0.74 0.74 ns TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to CARRYCASCOUT output using multiplier. 4.65 5.54 5.54 ns TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT output using multiplier. 4.54 5.40 5.40 ns TDSPDO_{A, B}_CARRYCASCOUT {A, B} input to CARRYCASCOUT output not using multiplier. 2.03 2.41 2.41 ns TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT output. 1.81 2.15 2.15 ns Combinatorial Delays from Cascading Input Pins to All Output Pins TDSPDO_ACIN_P_MULT ACIN input to P output using multiplier. 4.19 5.00 5.00 ns TDSPDO_ACIN_P ACIN input to P output not using multiplier. 1.57 1.88 1.88 ns TDSPDO_ACIN_ACOUT ACIN input to ACOUT output. 0.44 0.53 0.53 ns TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to CARRYCASCOUT output using multiplier. 4.47 5.33 5.33 ns TDSPDO_ACIN_CARRYCASCOUT ACIN input to CARRYCASCOUT output not using multiplier. 1.85 2.21 2.21 ns TDSPDO_PCIN_P PCIN input to P output. 1.28 1.52 1.52 ns DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 36 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade 1.0V TDSPDO_PCIN_CARRYCASCOUT PCIN input to CARRYCASCOUT output. Units 0.95V -2 -1 -1L 1.56 1.85 1.85 ns Clock to Outs from Output Register Clock to Output Pins TDSPCKO_P_PREG CLK PREG to P output. 0.37 0.44 0.44 ns TDSPCKO_CARRYCASCOUT_PREG CLK PREG to CARRYCASCOUT output. 0.59 0.69 0.69 ns Clock to Outs from Pipeline Register Clock to Output Pins TDSPCKO_P_MREG CLK MREG to P output. 1.93 2.31 2.31 ns TDSPCKO_CARRYCASCOUT_MREG CLK MREG to CARRYCASCOUT output. 2.21 2.64 2.64 ns TDSPCKO_P_ADREG_MULT CLK ADREG to P output using multiplier. 3.10 3.69 3.69 ns TDSPCKO_CARRYCASCOUT_ADREG_MULT CLK ADREG to CARRYCASCOUT output using multiplier. 3.38 4.02 4.02 ns Clock to Outs from Input Register Clock to Output Pins TDSPCKO_P_AREG_MULT CLK AREG to P output using multiplier. 4.51 5.37 5.37 ns TDSPCKO_P_BREG CLK BREG to P output not using multiplier. 1.87 2.22 2.22 ns TDSPCKO_P_CREG CLK CREG to P output not using multiplier. 1.93 2.30 2.30 ns TDSPCKO_P_DREG_MULT CLK DREG to P output using multiplier. 4.48 5.32 5.32 ns CLK (ACOUT, BCOUT) to {A,B} register output. 0.73 0.87 0.87 ns CLK (AREG, BREG) to CARRYCASCOUT output using multiplier. 4.79 5.70 5.70 ns TDSPCKO_CARRYCASCOUT_ BREG CLK BREG to CARRYCASCOUT output not using multiplier. 2.15 2.55 2.55 ns TDSPCKO_CARRYCASCOUT_ DREG_MULT CLK DREG to CARRYCASCOUT output using multiplier. 4.76 5.65 5.65 ns TDSPCKO_CARRYCASCOUT_ CREG CLK CREG to CARRYCASCOUT output. 2.21 2.63 2.63 ns Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUT; BCOUT}_ {AREG; BREG} TDSPCKO_CARRYCASCOUT_ {AREG, BREG}_MULT Maximum Frequency FMAX With all registers used. 550.66 464.25 464.25 MHz FMAX_PATDET With pattern detector. 465.77 392.93 392.93 MHz FMAX_MULT_NOMREG Two register multiply without MREG. 305.62 257.47 257.47 MHz FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect. 277.62 233.92 233.92 MHz FMAX_PREADD_MULT_NOADREG Without ADREG. 346.26 290.44 290.44 MHz FMAX_PREADD_MULT_NOADREG_PATDET Without ADREG with pattern detect. 346.26 290.44 290.44 MHz FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG). 227.01 190.69 190.69 MHz FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect. 211.15 177.43 177.43 MHz DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 37 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Clock Buffers and Networks Table 32: Global Clock Switching Characteristics (Including BUFGCTRL) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L TBCCCK_CE/TBCCKC_CE(1) CE pins setup/hold. 0.13/0.40 0.16/0.41 0.16/0.41 ns TBCCCK_S/ TBCCKC_S(1) 0.13/0.40 0.16/0.41 0.16/0.41 ns TBCCKO_O (2) S pins setup/hold. BUFGCTRL delay from I0/I1 to O. 0.09 0.10 0.10 ns 628.00 464.00 464.00 MHz Maximum Frequency FMAX_BUFG Global clock tree (BUFG). Notes: 1. 2. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. Table 33: Input/Output Clock Switching Characteristics (BUFIO) VCCINT Operating Voltage and Speed Grade Symbol TBIOCKO_O Description Clock to out delay from I to O. 1.0V 0.95V Units -2 -1 -1L 1.26 1.54 1.54 ns 680.00 600.00 600.00 MHz Maximum Frequency FMAX_BUFIO I/O clock tree (BUFIO). Table 34: Regional Clock Buffer Switching Characteristics (BUFR) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units TBRCKO_O Clock to out delay from I to O. 0.76 0.99 0.99 ns TBRCKO_O_BYP Clock to out delay from I to O with Divide Bypass attribute set. 0.39 0.52 0.52 ns TBRDO_O Propagation delay from CLR to O. 0.85 1.09 1.09 ns 375.00 315.00 315.00 MHz Maximum Frequency FMAX_BUFR(1) Regional clock tree (BUFR). Notes: 1. The maximum input frequency to the BUFR is the BUFIO FMAX frequency. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 38 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 35: Horizontal Clock Buffer Switching Characteristics (BUFH) VCCINT Operating Voltage and Speed Grade Symbol TBHCKO_O Description 1.0V Units -2 -1 -1L 0.11 0.13 0.13 ns 0.22/0.15 0.28/0.21 0.28/0.21 ns 628.00 464.00 464.00 MHz BUFH delay from I to O. TBHCCK_CE/ TBHCKC_CE CE pin setup and hold. 0.95V Maximum Frequency FMAX_BUFH Horizontal clock buffer (BUFH). Table 36: Duty Cycle Distortion and Clock-Tree Skew VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V 0.95V Units -2 -1 -1L All 0.20 0.20 0.20 ns XC7S6 0.05 0.06 0.06 ns XC7S15 0.05 0.06 0.06 ns XC7S25 0.26 0.26 0.26 ns XC7S50 0.26 0.26 0.26 ns XC7S75 0.33 0.36 0.36 ns XC7S100 0.33 0.36 0.36 ns XA7S6 0.05 0.06 N/A ns XA7S15 0.05 0.06 N/A ns XA7S25 0.26 0.26 N/A ns XA7S50 0.26 0.26 N/A ns XA7S75 0.33 0.36 N/A ns XA7S100 0.33 0.36 N/A ns TDCD_BUFIO I/O clock tree duty cycle distortion. All 0.14 0.14 0.14 ns TBUFIOSKEW I/O clock tree skew across one clock region. All 0.03 0.03 0.03 ns TDCD_BUFR All 0.18 0.18 0.18 ns TDCD_CLK TCKSKEW Global clock tree duty-cycle distortion.(1) Global clock tree skew.(2) Regional clock tree duty cycle distortion. Notes: 1. 2. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx timing analysis tools to evaluate clock skew specific to your application. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 39 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics MMCM Switching Characteristics Table 37: MMCM Specification VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units MMCM_FINMAX Maximum input clock frequency. 800.00 800.00 800.00 MHz MMCM_FINMIN Minimum input clock frequency. 10.00 10.00 10.00 MHz MMCM_FINJITTER Maximum input clock period jitter. < 20% of clock input period or 1 ns Max MMCM_FINDUTY Allowable input duty cycle: 10—49 MHz. 25 25 25 % Allowable input duty cycle: 50—199 MHz. 30 30 30 % Allowable input duty cycle: 200—399 MHz. 35 35 35 % Allowable input duty cycle: 400—499 MHz. 40 40 40 % Allowable input duty cycle: > 500 MHz. 45 45 45 % MMCM_FMIN_PSCLK Minimum dynamic phase-shift clock frequency. 0.01 0.01 0.01 MHz MMCM_FMAX_PSCLK Maximum dynamic phase-shift clock frequency. 500.00 450.00 450.00 MHz MMCM_FVCOMIN Minimum MMCM VCO frequency. 600.00 600.00 600.00 MHz MMCM_FVCOMAX Maximum MMCM VCO frequency. 1440.00 1200.00 1200.00 MHz Low MMCM bandwidth at typical.(1) 1.00 1.00 1.00 MHz typical.(1) 4.00 4.00 4.00 MHz 0.12 0.12 0.12 ns MMCM_FBANDWIDTH High MMCM bandwidth at MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs.(2) MMCM_TOUTJITTER MMCM output jitter. MMCM_TOUTDUTY MMCM output clock duty-cycle precision.(4) MMCM_TLOCKMAX MMCM_FOUTMAX Note 3 0.20 0.20 0.20 ns MMCM maximum lock time. 100.00 100.00 100.00 µs MMCM maximum output frequency. 800.00 800.00 800.00 MHz 4.69 4.69 4.69 MHz frequency.(5)(6) MMCM_FOUTMIN MMCM minimum output MMCM_TEXTFDVAR External clock feedback variation. < 20% of clock input period or 1 ns Max MMCM_RSTMINPULSE Minimum reset pulse width. 5.00 5.00 5.00 ns MMCM_FPFDMAX Maximum frequency at the phase frequency detector. 500.00 450.00 450.00 MHz MMCM_FPFDMIN Minimum frequency at the phase frequency detector. 10.00 10.00 10.00 MHz MMCM_TFBDELAY Maximum delay in the feedback path. 3 ns Max or one CLKIN cycle MMCM Switching Characteristics Setup and Hold TMMCMDCK_PSEN/ TMMCMCKD_PSEN Setup and hold of phase-shift enable. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com 1.04/0.00 1.04/0.00 1.04/0.00 Send Feedback ns 40 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 37: MMCM Specification (Cont’d) VCCINT Operating Voltage and Speed Grade Symbol Description TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC Setup and hold of phase-shift increment/decrement. TMMCMCKO_PSDONE Phase shift clock-to-out of PSDONE. 1.0V 0.95V Units -2 -1 -1L 1.04/0.00 1.04/0.00 1.04/0.00 ns 0.68 0.81 0.81 ns Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK TMMCMDCK_DADDR/ TMMCMCKD_DADDR DADDR setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min TMMCMDCK_DI/ TMMCMCKD_DI DI setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min TMMCMDCK_DEN/ TMMCMCKD_DEN DEN setup/hold. 1.97/0.00 2.29/0.00 2.29/0.00 ns, Min TMMCMDCK_DWE/ TMMCMCKD_DWE DWE setup/hold. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min TMMCMCKO_DRDY CLK to out of DRDY. 0.72 0.99 0.99 ns, Max FDCK DCLK frequency. 200.00 200.00 200.00 MHz, Max Notes: 1. 2. 3. 4. 5. 6. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any MMCM outputs with identical phase. Values for this parameter are available in the Clocking Wizard [Ref 8]. Includes global clock buffer. Calculated as FVCO/128 assuming output duty cycle is 50%. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz. PLL Switching Characteristics Table 38: PLL Specification VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V -2 -1 -1L Units PLL_FINMAX Maximum input clock frequency. 800.00 800.00 800.00 MHz PLL_FINMIN Minimum input clock frequency. 19.00 19.00 19.00 MHz PLL_FINJITTER Maximum input clock period jitter. < 20% of clock input period or 1 ns Max PLL_FINDUTY Allowable input duty cycle: 19—49 MHz. 25 25 25 % Allowable input duty cycle: 50—199 MHz. 30 30 30 % Allowable input duty cycle: 200—399 MHz. 35 35 35 % Allowable input duty cycle: 400—499 MHz. 40 40 40 % Allowable input duty cycle: >500 MHz. 45 45 45 % PLL_FVCOMIN Minimum PLL VCO frequency. 800.00 800.00 800.00 MHz PLL_FVCOMAX Maximum PLL VCO frequency. 1866.00 1600.00 1600.00 MHz DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 41 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 38: PLL Specification VCCINT Operating Voltage and Speed Grade Symbol PLL_FBANDWIDTH Description 1.0V -2 -1 -1L Low PLL bandwidth at typical. 1.00 1.00 1.00 MHz High PLL bandwidth at typical.(1) 4.00 4.00 4.00 MHz 0.12 0.12 0.12 ns PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs.(2) PLL_TOUTJITTER Units 0.95V PLL output jitter. Note 3 PLL_TOUTDUTY PLL output clock duty-cycle PLL_TLOCKMAX PLL_FOUTMAX precision.(4) 0.20 0.20 0.20 ns PLL maximum lock time. 100.00 100.00 100.00 µs PLL maximum output frequency. 800.00 800.00 800.00 MHz 6.25 6.25 6.25 MHz frequency.(5) PLL_FOUTMIN PLL minimum output PLL_TEXTFDVAR External clock feedback variation. < 20% of clock input period or 1 ns Max PLL_RSTMINPULSE Minimum reset pulse width. 5.00 5.00 5.00 ns PLL_FPFDMAX Maximum frequency at the phase frequency detector. 500.00 450.00 450.00 MHz PLL_FPFDMIN Minimum frequency at the phase frequency detector. 19.00 19.00 19.00 MHz PLL_TFBDELAY Maximum delay in the feedback path. 3 ns Max or one CLKIN cycle Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK TPLLDCK_DADDR/ TPLLCKD_DADDR Setup and hold of D address. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min TPLLDCK_DI/ TPLLCKD_DI Setup and hold of D input. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min TPLLDCK_DEN/ TPLLCKD_DEN Setup and hold of D enable. 1.97/0.00 2.29/0.00 2.29/0.00 ns, Min TPLLDCK_DWE/ TPLLCKD_DWE Setup and hold of D write enable. 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min TPLLCKO_DRDY CLK to out of DRDY. 0.72 0.99 0.99 ns, Max FDCK DCLK frequency. 200.00 200.00 200.00 MHz, Max Notes: 1. 2. 3. 4. 5. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any PLL outputs with identical phase. Values for this parameter are available in the Clocking Wizard [Ref 8]. Includes global clock buffer. Calculated as FVCO/128 assuming output duty cycle is 50%. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 42 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Device Pin-to-Pin Output Parameter Guidelines Table 39: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1) VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOF Clock-capable clock input and OUTFF at pins/banks closest to the BUFGs without MMCM/PLL (near clock region).(2) XC7S6 5.55 6.50 6.50 ns XC7S15 5.55 6.50 6.50 ns XC7S25 5.55 6.44 6.44 ns XC7S50 5.71 6.62 6.62 ns XC7S75 5.73 6.71 6.71 ns XC7S100 5.73 6.71 6.71 ns XA7S6 5.55 6.50 N/A ns XA7S15 5.55 6.50 N/A ns XA7S25 5.55 6.44 N/A ns XA7S50 5.71 6.62 N/A ns XA7S75 5.73 6.71 N/A ns XA7S100 5.73 6.71 N/A ns Notes: 1. 2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4]. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 43 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1) VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOFFAR Clock-capable clock input and OUTFF at pins/banks farthest from the BUFGs without MMCM/PLL (far clock region).(2) XC7S6 5.55 6.50 6.50 ns XC7S15 5.55 6.50 6.50 ns XC7S25 5.55 6.44 6.44 ns XC7S50 5.71 6.62 6.62 ns XC7S75 6.01 7.02 7.02 ns XC7S100 6.01 7.02 7.02 ns XA7S6 5.55 6.50 N/A ns XA7S15 5.55 6.50 N/A ns XA7S25 5.55 6.44 N/A ns XA7S50 5.71 6.62 N/A ns XA7S75 6.01 7.02 N/A ns XA7S100 6.01 7.02 N/A ns Notes: 1. 2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4]. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 44 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 41: Clock-Capable Clock Input to Output Delay With MMCM(1) VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM.(2) XC7S6 1.03 1.03 1.03 ns XC7S15 1.03 1.03 1.03 ns XC7S25 1.00 1.00 1.00 ns XC7S50 1.00 1.00 1.00 ns XC7S75 1.00 1.00 1.00 ns XC7S100 1.00 1.00 1.00 ns XA7S6 1.03 1.03 N/A ns XA7S15 1.03 1.03 N/A ns XA7S25 1.00 1.00 N/A ns XA7S50 1.00 1.00 N/A ns XA7S75 1.00 1.00 N/A ns XA7S100 1.00 1.00 N/A ns Notes: 1. 2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 45 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 42: Clock-Capable Clock Input to Output Delay With PLL(1) VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. TICKOFPLLCC Clock-capable clock input and OUTFF with PLL.(2) XC7S6 0.85 0.85 0.85 ns XC7S15 0.85 0.85 0.85 ns XC7S25 0.83 0.83 0.83 ns XC7S50 0.83 0.83 0.83 ns XC7S75 0.83 0.83 0.83 ns XC7S100 0.83 0.83 0.83 ns XA7S6 0.85 0.85 N/A ns XA7S15 0.85 0.85 N/A ns XA7S25 0.83 0.83 N/A ns XA7S50 0.83 0.83 N/A ns XA7S75 0.83 0.83 N/A ns XA7S100 0.83 0.83 N/A ns Notes: 1. 2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. PLL output jitter is already included in the timing calculation. Table 43: Pin-to-Pin, Clock-to-Out using BUFIO VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO. TICKOFCS Clock to out of I/O clock. DS189 (v1.9) March 13, 2019 Product Specification 5.61 www.xilinx.com 6.64 6.64 Send Feedback ns 46 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted. Table 44: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 -1L Units Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) TPSFD/ TPHFD Full delay (legacy delay or default XC7S6 (2) delay) global clock input and IFF XC7S15 without MMCM/PLL with ZHOLD_DELAY XC7S25 on HR I/O banks. XC7S50 2.76/–0.40 3.17/–0.40 3.17/–0.40 ns 2.76/–0.40 3.17/–0.40 3.17/–0.40 ns 2.67/–0.37 3.12/–0.37 3.12/–0.37 ns 2.66/–0.28 3.11/–0.28 3.11/–0.28 ns XC7S75 2.91/–0.33 3.36/–0.33 3.36/–0.33 ns XC7S100 2.91/–0.33 3.36/–0.33 3.36/–0.33 ns XA7S6 2.76/–0.40 3.17/–0.40 N/A ns XA7S15 2.76/–0.40 3.17/–0.40 N/A ns XA7S25 2.67/–0.37 3.12/–0.37 N/A ns XA7S50 2.66/–0.28 3.11/–0.28 N/A ns XA7S75 2.91/–0.33 3.36/–0.33 N/A ns XA7S100 2.91/–0.33 3.36/–0.33 N/A ns Notes: 1. 2. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input flip-flop or latch. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 47 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 45: Clock-Capable Clock Input Setup and Hold With MMCM VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)(2) TPSMMCMCC/ No delay clock-capable clock input and TPHMMCMCC IFF(3) with MMCM. XC7S6 2.73/–0.59 3.27/–0.59 3.27/–0.59 ns XC7S15 2.73/–0.59 3.27/–0.59 3.27/–0.59 ns XC7S25 2.69/–0.61 3.21/–0.61 3.21/–0.61 ns XC7S50 2.81/–0.62 3.35/–0.62 3.35/–0.62 ns XC7S75 2.81/–0.62 3.36/–0.62 3.36/–0.62 ns XC7S100 2.81/–0.62 3.36/–0.62 3.36/–0.62 ns XA7S6 2.73/–0.59 3.27/–0.59 N/A ns XA7S15 2.73/–0.59 3.27/–0.59 N/A ns XA7S25 2.69/–0.61 3.21/–0.61 N/A ns XA7S50 2.81/–0.62 3.35/–0.62 N/A ns XA7S75 2.81/–0.62 3.36/–0.62 N/A ns XA7S100 2.81/–0.62 3.36/–0.62 N/A ns Notes: 1. 2. 3. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. Use IBIS to determine any duty-cycle distortion incurred using various standards. IFF = Input flip-flop or latch. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 48 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 46: Clock-Capable Clock Input Setup and Hold With PLL VCCINT Operating Voltage and Speed Grade Symbol Description Device 1.0V -2 0.95V -1 Units -1L Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)(2) TPSPLLCC/ TPHPLLCC No delay clock-capable clock input and IFF(3) with PLL. XC7S6 3.07/–0.17 3.69/–0.17 3.69/–0.17 ns XC7S15 3.07/–0.17 3.69/–0.17 3.69/–0.17 ns XC7S25 3.04/–0.19 3.64/–0.19 3.64/–0.19 ns XC7S50 3.15/–0.19 3.77/–0.19 3.77/–0.19 ns XC7S75 3.15/–0.19 3.78/–0.19 3.78/–0.19 ns XC7S100 3.15/–0.19 3.78/–0.19 3.78/–0.19 ns XA7S6 3.07/–0.17 3.69/–0.17 N/A ns XA7S15 3.07/–0.17 3.69/–0.17 N/A ns XA7S25 3.04/–0.19 3.64/–0.19 N/A ns XA7S50 3.15/–0.19 3.77/–0.19 N/A ns XA7S75 3.15/–0.19 3.78/–0.19 N/A ns XA7S100 3.15/–0.19 3.78/–0.19 N/A ns Notes: 1. 2. 3. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. Use IBIS to determine any duty-cycle distortion incurred using various standards. IFF = Input flip-flop or latch. Table 47: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard. TPSCS/TPHCS Setup and hold of I/O clock. DS189 (v1.9) March 13, 2019 Product Specification –0.38/1.46 www.xilinx.com –0.38/1.73 –0.38/1.76 Send Feedback ns 49 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 48: Sample Window VCCINT Operating Voltage and Speed Grade Symbol TSAMP Description 1.0V Sampling error at receiver pins.(1) TSAMP_BUFIO Sampling error at receiver pins using BUFIO.(2) 0.95V Units -2 -1 -1L 0.64 0.70 0.70 ns 0.40 0.46 0.46 ns Notes: 1. 2. This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 50 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Additional Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for Spartan-7 FPGA clock transmitter and receiver data-valid windows. Table 49: Package Skew(1) Symbol Description Device XC7S6 XC7S15 XC7S25 XC7S50 XC7S75 TPKGSKEW Package skew.(2) XC7S100 XA7S6 XA7S15 XA7S25 XA7S50 XA7S75 XC7S100 Package Value Units CPGA196 44 ps CSGA225 83 ps FTGB196 65 ps CPGA196 44 ps CSGA225 83 ps FTGB196 65 ps CSGA225 93 ps CSGA324 62 ps FTGB196 83 ps CSGA324 80 ps FGGA484 110 ps FTGB196 103 ps FGGA484 117 ps FGGA676 110 ps FGGA484 117 ps FGGA676 110 ps CPGA196 44 ps CSGA225 83 ps CPGA196 44 ps CSGA225 83 ps CSGA225 93 ps CSGA324 62 ps CSGA324 80 ps FGGA484 110 ps FGGA484 117 ps FGGA676 110 ps FGGA484 117 ps FGGA676 110 ps Notes: 1. 2. Package delay information is available for these device/package combinations. This information can be used to deskew the package. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 51 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics XADC Specifications The 7 Series FPGAs Overview (DS180) [Ref 1] and XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2] list the devices that contain a 7 series XADC dual 12-Bit 1 MSPS analog-to-digital converter. Table 50: XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units 12 – – Bits –40°C ≤ Tj ≤ 100°C – – ±2 LSBs –55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C – – ±3 LSBs No missing codes, guaranteed monotonic. – – ±1 LSBs –40°C ≤ Tj ≤ 100°C – – ±8 LSBs –55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C – – ±12 LSBs –55°C ≤ Tj ≤ 125°C – – ±4 LSBs Gain error – – ±0.5 % Offset matching – – 4 LSBs Gain matching – – 0.3 % – – 1 MS/s 60 – – dB External 1.25V reference. – – 2 LSBs On-chip reference. – 3 – LSBs 70 – – dB 0 – 1 V –0.5 – +0.5 V 0 – +0.5 V Bipolar common mode range (FS input). +0.5 – +0.6 V Maximum external channel input ranges Adjacent analog channels set within these ranges should not corrupt measurements on adjacent channels. –0.1 – VCCADC V Full-resolution bandwidth Auxiliary channel full resolution bandwidth. 250 – – kHz –40°C ≤ Tj ≤ 100°C – – ±4 °C –55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C – – ±6 °C –40°C ≤ Tj ≤ 100°C – – ±1 % –55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C – – ±2 % VCCADC = 1.8V ± 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, –55°C ≤ Tj ≤ 125°C. Typical values at Tj = +40°C. ADC Accuracy(1) Resolution Integral nonlinearity(2) INL Differential nonlinearity DNL Unipolar Offset error Bipolar Sample rate ratio(2) Signal to noise SNR RMS code noise Total harmonic distortion(2) THD FSAMPLE = 500 KS/s, FIN = 20 kHz FSAMPLE = 500 KS/s, FIN = 20 kHz Analog Inputs(3) Unipolar operation. Bipolar operation. ADC input ranges Unipolar common mode range (FS input). FRBW On-chip Sensors Temperature sensor error Supply sensor error DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 52 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 50: XADC Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units 26 – 32 Cycles Conversion Rate(4) Conversion time: continuous tCONV Number of ADCCLK cycles. Conversion time: event tCONV Number of CLK cycles. – – 21 Cycles DRP clock frequency DCLK DRP clock frequency. 8 – 250 MHz ADC clock frequency ADCCLK Derived from DCLK. 1 – 26 MHz 40 – 60 % 1.20 1.25 1.30 V 1.2375 1.25 1.2625 V 1.225 1.25 1.275 V DCLK duty cycle XADC Reference(5) External reference On-chip reference VREFP Externally supplied reference voltage. Ground VREFP pin to AGND, –40°C ≤ Tj ≤ 100°C Ground VREFP pin to AGND, –55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C Notes: 1. 2. 3. 4. 5. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled. Only specified for bitstream option XADCEnhancedLinearity = ON. For a detailed description, see the ADC chapter in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 9]. For a detailed description, see the Timing chapter in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 9]. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 53 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Configuration Switching Characteristics Table 51: Configuration Switching Characteristics VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V 0.95V Units -2 -1 -1L 5.00 5.00 5.00 ms, Max Power-on reset (50 ms ramp rate time). 10/50 10/50 10/50 ms, Min/Max Power-on reset (1 ms ramp rate time). 10/35 10/35 10/35 ms, Min/Max Program pulse width. 250.00 250.00 250.00 ns, Min Power-up Timing Characteristics TPL(1) TPOR(2) TPROGRAM Program latency. CCLK Output (Master Mode) TICCK Master CCLK output delay. 150.00 150.00 150.00 ns, Min TMCCKL Master CCLK clock Low time duty cycle. 40/60 40/60 40/60 %, Min/Max TMCCKH Master CCLK clock High time duty cycle. 40/60 40/60 40/60 %, Min/Max Master CCLK frequency. 100.00 100.00 100.00 MHz, Max 50.00 50.00 50.00 MHz, Max 3.00 3.00 3.00 MHz, Typ ±50 ±50 ±50 %, Max FMCCK Master CCLK frequency for AES encrypted x16.(2) FMCCK_START Master CCLK frequency at start of configuration. FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK. CCLK Input (Slave Modes) TSCCKL Slave CCLK clock minimum Low time. 2.50 2.50 2.50 ns, Min TSCCKH Slave CCLK clock minimum High time. 2.50 2.50 2.50 ns, Min FSCCK Slave CCLK frequency. 100.00 100.00 100.00 MHz, Max EMCCLK Input (Master Mode) TEMCCKL External master CCLK Low time. 2.50 2.50 2.50 ns, Min TEMCCKH External master CCLK High time. 2.50 2.50 2.50 ns, Min FEMCCK External master CCLK frequency. 100.00 100.00 100.00 MHz, Max 100.00 100.00 100.00 MHz, Max Internal Configuration Access Port FICAPCK Internal configuration access port (ICAPE2) clock frequency. Master/Slave Serial Mode Programming Switching TDCCK/ TCCKD DIN setup/hold. TCCO DOUT clock to out. 4.00/0.00 4.00/0.00 4.00/0.00 8.00 8.00 8.00 ns, Min ns, Max SelectMAP Mode Programming Switching TSMDCCK/ TSMCCKD D[31:00] setup/hold. DS189 (v1.9) March 13, 2019 Product Specification 4.00/0.00 4.00/0.00 4.00/0.00 www.xilinx.com Send Feedback ns, Min 54 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Table 51: Configuration Switching Characteristics (Cont’d) VCCINT Operating Voltage and Speed Grade Symbol Description 1.0V -2 0.95V -1 Units -1L TSMCSCCK/ TSMCCKCS CSI_B setup/hold. TSMWCCK/ TSMCCKW RDWR_B setup/hold. TSMCKCSO CSO_B clock to out (330 Ω pull-up resistor required). 7.00 7.00 7.00 ns, Max TSMCO D[31:00] clock to out in readback. 8.00 8.00 8.00 ns, Max FRBCCK Readback frequency. 100.00 100.00 100.00 MHz, Max 4.00/0.00 4.00/0.00 4.00/0.00 ns, Min 10.00/0.00 10.00/0.00 10.00/0.00 ns, Min Boundary-Scan Port Timing Specifications TTAPTCK/ TTCKTAP TMS and TDI setup/hold. TTCKTDO TCK falling edge to TDO output. FTCK TCK frequency. 3.00/2.00 3.00/2.00 3.00/2.00 ns, Min 7.00 7.00 7.00 ns, Max 66.00 66.00 66.00 MHz, Max SPI Flash Master Mode Programming Switching TSPIDCC/ TSPICCD D[03:00] setup/hold. TSPICCM MOSI clock to out. 8.00 8.00 8.00 ns, Max TSPICCFC FCS_B clock to out. 8.00 8.00 8.00 ns, Max 3.00/0.00 3.00/0.00 3.00/0.00 ns, Min STARTUPE2 Ports TUSRCCLKO STARTUPE2 USRCCLKO input to CCLK output. FCFGMCLK STARTUPE2 CFGMCLK output frequency. FCFGMCLKTOL STARTUPE2 CFGMCLK output frequency tolerance. 0.50/6.70 0.50/7.50 0.50/7.50 ns, Min/Max 65.00 65.00 65.00 MHz, Typ ±50 ±50 ±50 %, Max 100.00 100.00 100.00 MHz, Max Device DNA Access Port FDNACK DNA access port (DNA_PORT). Notes: 1. 2. To support longer delays in configuration, use the design solutions described in the 7 Series FPGA Configuration User Guide (UG470) [Ref 10]. See the 7 Series FPGAs Overview (DS180) [Ref 1] and XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2] for a list of devices that support bitstream encryption. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 55 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics eFUSE Programming Conditions Table 52 lists the programming conditions specifically for eFUSE. For more information, see the 7 Series FPGA Configuration User Guide (UG470) [Ref 10]. Table 52: eFUSE Programming Conditions(1) Symbol Description IFS VCCAUX supply current Tj Temperature range Min Typ Max Units – – 115 mA 15 – 125 °C Notes: 1. The FPGA must not be configured during eFUSE programming. References 1. 7 Series FPGAs Overview (DS180) 2. XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) 3. 7 Series FPGAs SelectIO Resources User Guide (UG471) 4. 7 Series FPGA Packaging and Pinout Specification (UG475) 5. 7 Series FPGAs PCB Design Guide (UG483) 6. Xilinx Power Estimator spreadsheet tool (XPE) 7. Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586) 8. See the Clocking Wizard in Vivado software. 9. 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) 10. 7 Series FPGA Configuration User Guide (UG470) DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 56 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Revision History The following table shows the revision history for this document: Date Version Description of Revisions 03/13/2019 1.9 Removed FTGB196 package from XA7S6, XA7S15, XA7S25, and XA7S50 devices in Table 49. 09/28/2018 1.8 Removed description of -1Q speed grade only being available in XA Spartan-7 FPGAs from second paragraph of Introduction. 07/31/2018 1.7 In Table 12, updated Vivado tools version to 2018.2.1. In Table 13, moved all speed grades for all devices to Production. In Table 14, added Vivado tools version for XC7S6, XC7S15, XC7S75, XC7S100, XA7S6, XA7S15, XA7S75, and XA7S100. 06/18/2018 1.6 In Table 12, updated Vivado tools version to 2018.2. In Table 13, moved all speed grades except -1Q (1.0V) for XC7S6 and XC7S15 to Production. In Table 14, added Vivado tools version for XC7S6 and XC7S15. 04/04/2018 1.5 Added XA7S6, XA7S15, XA7S25, XA7S75, and XA7S100 devices throughout. In Table 5, updated typical quiescent supply current values for XC7S25 and XC7S50 devices, and added values for XC7S6, XC7S15, XC7S75, and XC7S100 devices. In Table 6, updated table title and ICCINTMIN and ICCAUXMIN for XC7S75 and XC7S100 devices. In Table 13, moved all speed grades for XC7S6 and XC7S15 to Preliminary, moved -1LI (0.95V) speed grade for XC7S25 to Production, and moved all speed grades except -1Q (1.0V) for XC7S75 and XC7S100 from Preliminary to Production. In Table 14, added Vivado tools version for XC7S25, XC7S75, and XC7S100. In Table 36, Table 39, Table 40, Table 41, Table 42, Table 44, Table 45, and Table 46, changed parameter value for XA7S50 to N/A. In Table 49, added package skew values for XC7S6 and XC7S15 devices. 12/22/2017 1.4 In Table 12, updated Vivado tools version to 2017.4. In Table 13, moved all speed grades for XC7S75 and XC7S100 from Advance to Preliminary and all speed grades except -1LI (0.95V) for XC7S25 from Advance to Production. In Table 14, added Vivado tools version for XC7S25. Added Note 2 to Table 16. In Table 49, added package skew values for XC7S25 device in CSGA324 package and XC7S75 and XC7S100 devices in FGGA676 package. 11/20/2017 1.3 Added XA7S50 device throughout. Updated description of offered temperature ranges in second paragraph of Introduction. Added row for junction temperature (Tj) at expanded (Q) temperature to Table 2. Added -1Q (1.0V) speed grade to Table 5, and Table 13 to Table 16. In Table 12, updated Vivado tools version to 2017.3. In Table 49, added package skew values for XC7S25, XC7S50, XC7S75, and XC7S100 devices in CSGA225, FTGB196, and FGGA484 packages. Added XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) to References. 06/20/2017 1.2 Updated paragraph before Table 6. In Table 12, updated Vivado tools version to 2017.2. In Table 13, moved all speed grades for XC7S50 from Preliminary to Production and updated Note 1. In Table 14, added Vivado tools version for XC7S50. In Table 49, added package skew value for XC7S50 device in FGGA484 package. DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 57 Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics Date Version Description of Revisions 04/07/2017 1.1 Added 1.35V to Note 5 in Table 2. In Table 12, updated Vivado tools version to 2016.4. In Table 13, moved all speed grades for XC7S50 from Advance to Preliminary. Removed SFI-4.1 and SPI-4.2 from descriptions of SDR LVDS receiver and DDR LVDS receiver, respectively, in Table 15. In Table 25, changed TIDELAYRESOLUTION units from ps to µs. Removed BUFMR from Note 1 in Table 34. In Table 49, replaced TQGA144 with FTGB196 for XC7S6, XC7S15, and XC7S25 devices, added FTGB196 package for XC7S50 device, and added package skew value for XC7S50 device in CSGA324 package. 09/27/2016 1.0 Initial Xilinx release. Please Read: Important Legal Notices The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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DS189 (v1.9) March 13, 2019 Product Specification www.xilinx.com Send Feedback 58