Device Package
User Guide
UG112 (v3.7) September 5, 2012
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Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or
consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are
subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be
subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be failsafe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical
Applications: http://www.xilinx.com/warranty.htm#critapps.
© 2004–2012 Xilinx, Inc. Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands
included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective
owners.
Device Package User Guide
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UG112 (v3.7) September 5, 2012
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
01/31/04
1.0
Initial release
02/04/05
1.1
Added Pb-free packaging information.
05/31/06
2.0
Extensive updates and new material added.
05/18/07
3.0
Updated “Material Data Declaration Sheet (MDDS)” in Chapter 1; revised link to “Xilinx
Packaging Material Content Data for Standard and PB-Free Packages”.
Revised “Part Marking” in Chapter 1; added “Ordering Information”, “Marking
Template”, Table 1-1: “Example Part Numbers (FPGA, CPLD, and PROM)”, and
Table 1-2: “Xilinx Device Marking Definition—Example”.
Updated “Flip-Chip BGA Packages” in Chapter 1; added content to “Package
Construction” to clarify Type I and Type II lid usage.
Updated “Thermal Management & Thermal Characterization Methods & Conditions” in
Chapter 3; removed “Junction-to-Board Measurement - ΨJB”, added link to new “Data
Acquisition and Package Thermal Database”, added Figure 3-11, page 53, “Package
Thermal Data Query for Device-Specific Data” (query tool replaces Table 3-1: “Summary
of Thermal Resistance for Packages”, which was removed).
Updated “Recommended PCB Design Rules for BGA, CSP, and CCGA Packages,”
page 87; added missing (D) values for CP56 and CP132 packages and corrected SF363
package specification (D) value in Table 5-3, page 88. Added CS48 to Table 5-4, page 88.
Updated Table 6-2, page 108 to include MSL ratings for Pb-free packages.
Updated “Package Peak Reflow Temperature” in Chapter 7; correction to peak reflow
temperature. Added post-wash bake details to “Post Reflow Washing” section.
12/18/08
3.1
Added link to Package Thermal Data Query Tool on xilinx.com. Updated remaining
external links.
Added Spartan®-3A DSP information to Table 1-1, page 13.
Added these packages to Table 2-3, page 36: FG484 and FGG484.
Added these packages to Table 5-3, page 88: SFG363, FF676, FGG484, FFG676, FT64 and
FTG64.
Removed these packages from Table 5-3, page 88: FF896, FFG896, FF1704, FFG1704,
FF1696 and FFG1696.
Added these packages to Table 5-4, page 88: CS484 and CSG484.
UG112 (v3.7) September 5, 2012
www.xilinx.com
Device Package User Guide
Date
Version
Revision
03/17/09
3.2
Revised “Small Form Factor Packages,” page 15 to include description of third template
used for marking small form factor packages.
Revised “Package Construction,” page 20 to describe flip-chip package vent hole
locations.
Added missing Pb-free packages to Table 1-3, page 27.
Revised mass of FG676 and FGG676 packages in Table 1-3, page 27.
Added CS484 and CSG484 information to Table 1-3, page 27 and Table 2-3, page 36.
Added FF1136 and FFG1136 tray and box information to Table 2-3, page 36.
Changed link from DS529 to UG331 in third paragraph of “Data Acquisition and
Package Thermal Database,” page 52.
Added CS484 electrical data to Table 4-1, page 75.
Added note to Table 5-3, page 88, referring to UG195.
Revised humidity value in third paragraph of “Dry Bake Recommendation and Dry Bag
Policy,” page 107.
Revised humidity value in first and fourth paragraph of “Expiration Date,” page 107.
Updated links in Table A-1, page 121.
04/23/09
3.3
Added FG400, FGG400, FF323, FFG323, FF324, FFG324, FF665, FFG665, FF676, FFG676,
FF1153, FFG1153, FF1156, FFG1156, FF1738, FFG1738, FF1760, and FFG1760 to Table 2-3,
page 36.
Revised the via land diameters for CF1140, CF1144, and CF1509 packages in Table 5-5,
page 89.
06/10/09
3.4
Revised third paragraph of “Package Construction,” page 20 about EF flip-chip package
epoxy protection.
Revised second paragraph of “Post Reflow Washing,” page 117 excepting EF packages
from cleaning solution/solvent recommendation.
11/06/09
3.5
Added link to MDDS documents under “Material Data Declaration Sheet (MDDS),”
page 10. Added FF896, EF1152, EF1704, FF1704, EF668, and EF672 to Table 5-3, page 88.
Added EF957 to Table 5-4, page 88.
09/22/10
3.6
Added CS225/CSG225 and CS324/CSG324 in Table 2-3, page 36. Added CF1752 to
heading in CF1509 column, and changed “Solder (ball) land pitch” to “Solder (column)
land pitch” in Table 5-5, page 89. Added VO48/VOG48 in Table 6-2, page 108.
09/05/12
3.7
Updated “Thermal Management,” page 39. Updated “Characterization Methods,”
page 47 and added “Calibration of System Monitor,” page 47. Removed Tt and Tl from
and added TS to “Definition of Terms,” page 48. Updated “Junction-to-Case
Measurement — qJC,” page 49, with JEDEC Standard JESD51-14. Updated document
references in “Data Acquisition and Package Thermal Database,” page 52. Removed
“Junction-to-Top Measurement — ΨJT” and “Support for Compact Thermal Models
(CTM).” Updated note for TA in “Thermal Data Usage Examples,” page 54. Updated
“Additional Power Management Options,” page 57.
Device Package User Guide
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UG112 (v3.7) September 5, 2012
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 1: Package Information
Package Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Introduction to Xilinx Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Packaging Technology at Xilinx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Material Data Declaration Sheet (MDDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Specifications and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Inches vs. Millimeters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pressure Handling Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clockwise or Counterclockwise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cavity-Up or Cavity-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
12
Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Marking Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package Technology Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pb-Free Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cavity-Up Plastic BGA Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cavity-Down Thermally Enhanced BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip-Chip BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembling Flip-Chip BGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Scale Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quad Flat No-Lead (QFN) Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ceramic Column Grid Array (CCGA) Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermally Enhanced Lead Frame Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
17
18
19
21
22
23
24
25
Package Mass Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 2: Pack and Ship
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cover Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bar Code Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shipping Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Bar Code Label Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
32
32
32
32
34
Tubes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Trays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Chapter 3: Thermal Management & Thermal Characterization Methods
& Conditions
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Xilinx Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Heatsinks, Heatsink Interface Materials, and Heatsink Attachments . . . . . . . . . . . . .
Power Estimation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compact Thermal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Design: Layer, Board, and Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature, Enclosures, and Airflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Altitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Data Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
40
40
41
42
43
43
44
44
Package Thermal Characterization Methods and Conditions . . . . . . . . . . . . . . . . . 47
Characterization Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration of Isolated Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calibration of System Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction-to-Reference General Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction-to-Case Measurement — qJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction-to-Ambient Measurement — qJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance: Junction-to-Board — qJB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Acquisition and Package Thermal Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
47
47
47
48
48
49
49
51
52
52
Application of Thermal Resistance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Thermal Data Usage Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Heatsink Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Additional Power Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
System Simulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 4: Package Electrical Characteristics
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Terminology - Definitions and Reviews . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Resistance (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductance (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitance (C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conductance (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Impedance (Z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time Delay (Td) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Integrity and Package Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
65
67
69
69
69
70
71
71
Electrical Data Generation and Measurement Methods . . . . . . . . . . . . . . . . . . . . . . 72
Review of Practical Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package Sample and Fixture Preparation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6
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Software-Based Simulations and Extractions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Electrical Data Delivery Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Models at Xilinx - Electrical Data Delivery via Models . . . . . . . . . . . . . . . . . . . . . . . . .
Further Explanations on Model Data and Terminology . . . . . . . . . . . . . . . . . . . . . . . .
73
74
75
79
81
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 5: Recommended PCB Design Rules
Recommended PCB Design Rules for QFP Packages . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended PCB Design Rules for TSOP/TSSOP Packages . . . . . . . . . . . . . . .
Recommended PCB Design Rules for BGA, CSP, and CCGA Packages . . . . . . .
Board Routability Guidelines with Xilinx Fine-Pitch BGA Packages . . . . . . . . .
85
86
87
89
Board Level Routing Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Board Routing Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Board Routing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Recommended PCB Design Rules for QFN Packages . . . . . . . . . . . . . . . . . . . . . . . . 98
PCB Pad Pattern Design and Surface-Mount Considerations
for QFN Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
PCB Pad Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Thermal Pad and Via Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Solder Masking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Stencil Design for Perimeter Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Stencil Design for Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Via Types and Solder Voiding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Stencil Thickness and Solder Paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Chapter 6: Moisture Sensitivity of PSMCs
Moisture-Induced Cracking During Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . .
Factory Floor Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dry Bake Recommendation and Dry Bag Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Handling Parts in Sealed Bags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expiration Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
106
107
107
107
107
107
108
Assigned Package MSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Chapter 7: Reflow Soldering Process Guidelines
Solder Reflow Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Package Peak Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Soldering Problems Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Typical Conditions for IR Reflow Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Implementing and Optimizing Solder Reflow Process
for BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Reflow Ovens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Reflow Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Methods of Measuring Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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Reflow Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Post Reflow Washing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reworking Flip-Chip BGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BGA Reballing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conformal Coating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Post Assembly Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Heat Sink Removal Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Pressure Handling Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
117
117
119
119
119
119
119
120
QFN Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Appendix A: Additional Information
Table of Socket Manufacturers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Web Sites for Heatsink Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Web Sites for Interface Material Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Xilinx Web Sites and Links to Xilinx Packaging Application Notes .
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Chapter 1
Package Information
Package Overview
Introduction to Xilinx Packaging
Electronic packages are interconnectable housings for semiconductor devices. The major
functions of the electronic packages are to provide electrical interconnections between the
IC and the board and to efficiently remove heat generated by the device.
Feature sizes are constantly shrinking, resulting in increased number of transistors being
packed into the device. Today's submicron technology is also enabling large-scale
functional integration and system-on-a-chip solutions. In order to keep pace with these
new advancements in silicon technologies, semiconductor packages have also evolved to
provide improved device functionality and performance.
Feature size at the device level is driving package feature sizes down to the design rules of
the early transistors. To meet these demands, electronic packages must be flexible to
address high pin counts, reduced pitch and form factor requirements. At the same time,
packages must be reliable and cost effective.
Packaging Technology at Xilinx
Xilinx provides a wide range of leaded and array packaging solutions for our advanced
silicon products. Xilinx® advanced packaging solutions include overmolded plastic ball
grid arrays (PBGA), small form factor Chip Scale Packages, “Cavity-Down” BGAs,
flip-chip BGAs, flip-chip ceramic column grid arrays (CCGA), as well as the newer lead
frame packages such as Quad Flat No-Lead (QFN) packages to meet various pin counts
and density requirements. Packages from Xilinx are designed, optimized, and
characterized to support the long-term mechanical reliability requirements as well as to
support the cutting-edge electrical and thermal performance requirements for our highspeed advanced FPGA products.
Pb-free Packaging Solutions from Xilinx
Xilinx also develops packaging solutions that are safer for the environment. Today,
standard packages from Xilinx do not contain substances that are identified as harmful to
the environment including cadmium, hexavalent chromium, mercury, PBB, and PBDE. Pbfree solutions take that one step further and also do not contain lead (Pb). This makes Pbfree solutions from Xilinx RoHS (Reduction of Hazardous Substances) compliant. Pb-free
packages from Xilinx are also JEDEC J-STD-020 compliant, meaning that the packages are
made to be more robust so they are capable of withstanding higher reflow temperatures.
Xilinx is now ready to support the industry requirements for Pb-free packaging solutions.
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Chapter 1: Package Information
Package Drawings
Package drawings are mechanical specifications that include exact dimensions for the
placement of pins, height of the package, and related information.
Package drawings are available online at
http://www.xilinx.com/support/documentation/package_specifications.htm.
Material Data Declaration Sheet (MDDS)
The MDDS template used by Xilinx is based on the Electronic Industries Alliance (EIA)
September 19, Material Composition Declaration Guide dated September 19, 2003 for
Level A and Level B materials of interest.
As per EIA, “Level A” List is composed of materials and substances subject to currently
enacted legislation that:
a.
Prohibits their use and/or marketing
b.
Restricts their use and/or marketing
c.
Requires reporting or results in other regulatory effect.
As per EIA, “Level B” List is composed of materials and substances that the industry has
determined relevant for disclosure because they meet one or more of the following criteria:
a.
Precious materials/substances that provide economic value for end-of-life
management purposes
b.
Materials/substances that are of significant environmental, health, or safety
interest
c.
Materials/substances that would trigger hazardous waste management
requirements
d. Materials/substances that could have a negative impact on end-of-life
management.
See the EIA standard for more specific information.
MDDS documents are available online at
http://www.xilinx.com/support/documentation/package_specifications.htm.
Information about Pb-Free and RoHS-compliant products is available at
http://www.xilinx.com/system_resources/lead_free.
Package Samples
Xilinx offers two types of non-product-specific package samples that can help develop
custom processes and perform board-level tests. These samples can be ordered with
ordering codes as detailed below.
Mechanical Samples XCMECH-XXXXX (where XXXXX is the package code of interest)
This part type is used for mechanical evaluations, process setup, etc. Most packages are
based on the JEDEC outline, and these parts are at times referred to as "dummy" parts since
mechanical samples do not contain a die.
Example:
To order a FG676 package as a mechanical sample (without the die), the part number
would be XCMECH-FG676.
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Specifications and Definitions
Daisy Chain Samples XCDAISY-XXXXX (where XXXXX is the package code of interest)
Use this part type to perform board-based evaluations (such as vibrations and temperature
cycles) to see how well the solder balls withstand these mechanical conditions. For Xilinx
daisy chain parts (XCDAISY-XXXXX), a specific ball assignment chain is available. If you
do not have a board already made, you can use our default chain. You can purchase these
parts from Xilinx through standard sales outlets. Xilinx does not support unique chains
because these parts do not have the volume to justify the development effort.
Example:
To order a FG676 package in a daisy-chained configuration, the part number would be
XCDAISY-FG676.
Specifications and Definitions
Inches vs. Millimeters
The JEDEC standards for PLCC, CQFP, and PGA packages define package dimensions in
inches. The lead spacing is specified as 25 mils, 50 mils, or 100 mils (0.025 in., 0.050 in. or
0.100 in.).
The JEDEC standards for PQFP, HQFP, TQFP, VQFP, CSP, and BGA packages define
package dimensions in millimeters. The lead frame packages have lead spacings of
0.5 mm, 0.65 mm, or 0.8 mm. The CSP and BGA packages have ball pitches of 0.5 mm,
0.8 mm, 1.00 mm, or 1.27 mm.
Because of the potential for measurement discrepancies, this Data Book provides
measurements in the controlling standard only, either inches or millimeters.
Pressure Handling Capacity
For mounted BGA packages, including flip chips, a direct compressive (non-varying) force
applied normally to the lid or top of package with a tool head that coincides with the lid (or
is slightly bigger) will not induce mechanical damage to the device including external
balls, provided the force is not over 5.0 grams per external ball, and the device and board
are supported to prevent any flexing or bowing.
These components are tested in sockets with loads in the 5 to 10 gm/ball range for short
durations. Analysis using a 10g/ball (e.g., 10 kg for FF1148) showed little impact on shortterm but some creep over time. 20 gm/ball and 45 gm/ball loads at 85°C over a six week
period has shown the beginning of bridging of some outer balls; these were static load
tests. The component can survive forces greater than the 5 gm limit while in short-term
situations. However, sustained higher loads should be avoided (particularly if they are
overlaid with thermal or power cycle loads). Within the recommended limits, circuit board
needs to be properly supported to prevent any flexing resulting from force application.
Any flexing or bowing resulting from such a force can likely damage the package-to-board
connections. Besides the damage that can occur from bending, the only major concern is
long-term creep and bulging of the solder balls in compression to cause bridging. For the
life of a part, staying below the recommended limit will ensure against that remote
possibility.
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Chapter 1: Package Information
Clockwise or Counterclockwise
The orientation of the die in the package and the orientation of the package on the PC
board affect the PC board layout. PLCC and PQFP packages specify pins in a
counterclockwise direction, when viewed from the top of the package (the surface with the
Xilinx logo). PLCCs have pin 1 in the center of the beveled edge while all other packages
have pin 1 in one corner, with one exception: The 100-pin and 165-pin CQFPs (CB100 and
CB164) for the XC3000 devices have pin 1 in the center of one edge.
CQFP packages specify pins in a clockwise direction, when viewed from the top of the
package. The user can make the pins run counterclockwise by forming the leads such that
the logo mounts against the PC board. However, heat flow to the surrounding air is
impaired if the logo is mounted down.
Cavity-Up or Cavity-Down
Most Xilinx devices attach the die against the inside bottom of the package (the side that
does not carry the Xilinx logo). Called “Cavity-Up,” this has been the standard IC
assembly method for over 25 years. This method does not provide the best thermal
characteristics. Pin Grid Arrays (greater than 130 pins), copper based BGA packages, and
Ceramic Quad Flat Packs are assembled “Cavity-Down,” with the die attached to the
inside top of the package, for optimal heat transfer to the ambient air. More information on
“Cavity-Up” packages and “Cavity-Down” packages can be found in the “Package
Technology Descriptions” section.
For most packages this information does not affect how the package is used because the
user has no choice in how the package is mounted on a board. For Ceramic Quad Flat Pack
(CQFP) packages however, the leads can be formed to either side. Therefore, for best heat
transfer to the surrounding air, CQFP packages should be mounted with the logo up,
facing away from the PC board.
Part Marking
Ordering Information
An example of an ordering code for a Xilinx FPGA is XC4VLX60-10FFG668CS2. The
ordering code stands for:
XC4VLX – Family (Virtex®-4 LX)
60 – Number of system gates or logic cells (60,000 logic cells)
-10 – Speed grade (-10 speed)
FFG – Package type (Pb-free flip-chip BGA)
668 – number of pins (668 pins)
C – Temperature grade (Commercial)
S2 – Step 2
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Part Marking
Other examples are shown in Table 1-1.
Table 1-1:
Example Part Numbers (FPGA, CPLD, and PROM)
Family
Part Number
Sample Ordering Code
Virtex-5 LX
XC5VLX##
XC5VLX110 -1 FFG676C
Virtex-5 LXT
XC5VLX##T
XC5VLX330T-1FF1738I
Virtex-5 SXT
XC5VSX##T
XC5VSX35T-2FF665C
Virtex-4 LX
XC4VLX##
XC4VLX25 -10 FF668C
Virtex-4 SX
XC4VSX##
XC4VSX55 -11 FF1148C
Virtex-II Pro
XC2VP##
XC2VP7 -7 FG456C
Virtex-II
XC2V##
XC2V1000 -5 FG456C
Virtex-E
XCV##E
XCV300E -6 PQ240C
Virtex
XCV##
XCV300 -6 PQ240C
Spartan®-3
XC3S##
XC3S1000 -4 FG676C
Spartan-3A
XC3S##A
XC3S50A -4 FTG256C
Spartan-3E
XC3S##E
XC3S250E -4 FT256C
Spartan-II
XC2S##
XC2S50 -6 PQ208C
Spartan-IIE
XC2S##E
XC2S50E -6 PQ208C
Spartan-3AN
XC3Sx###AN
XC3S400AN-4FG400I
Spartan-3A DSP
XC3SD####A
XC3SD1800A-4CS484LI
Spartan
XCS##
XCS20 -4 PQ208C
Spartan-XL
XCS##XL
XCS20XL -4 PQ208C
4000E
XC4##E
XC4013E -3 HQ240C
4000XL
XC4##XL
XC4013XL -3 PQ208C
CoolRunner™-II
XC2C##
XC2C256 -7 PQ208C
CoolRunner (XPLA3)
XCR##XL
XCR3512XL -7 PQ208C
9500XV
XC95##XV
XC9536XV -7 VQ44I
9500XL
XC95##XL
XC9572XL -7 TQ100C
9500
XC95##
XC95216 -10 HQ208C
Notes:
1. Automotive parts use “XA” instead of “XC”.
2. QML-certified parts use “XQ” instead of “XC”.
3. Aerospace parts have an “R” after “XQ” instead of “XC”.
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Chapter 1: Package Information
Examples
CPLD Ordering Information
An example of an ordering number for a Xilinx CPLD is XC2C256-7PQ108I, and is defined
as follows:
XC2C – Family (CoolRunner-II)
256 – Number of macrocells (256 macrocells)
-7 – Speed grade (-7 speed)
PQ – Package type (Plastic Quad Flat Pack)
208 – Number of pins (208 pins)
I – Temperature grade (Industrial)
PROM Ordering Information
An example of an ordering number for a Xilinx PROM is XC18V04VQ44C, and is defined
as follows:
XC18V – Family - 1800 (ISP) PROM
04 – PROM size (18V00, 17V00, 1700E/L) or equivalent Spartan-II or Spartan-IIE
device (17S00A/XL/L), 4 Mb of storage capacity
VQ – Package type (Plastic Quad Flat Pack)
44 – Number of pins (44 pins)
C – Temperature grade (commercial)
To determine the valid ordering combinations for a given device, consult the device data
sheet. Data sheets are available at
http://www.xilinx.com/support/documentation/index.htm
Marking Template
Large Form Factor Packages
On December 26, 1995, Product Change Notice (PCN) 95013 was issued to acknowledge a
change to the Xilinx standard for package marking. You can view this notice at
http://www.xilinx.com/support/documentation/customer_notices/pcn95013.pdf
Xilinx part marking follows generalized marking templates that are different for small and
large packages. Within each group, some minor variations exist due to device family
branding.
The large package template (Figure 1-1) consists of the Xilinx Logo, the family brand logo,
and 4 lines of information.
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Part Marking
X-Ref Target - Figure 1-1
R
R
Device Type
Package
Speed Grade
XC5VLX50T TM
FFG1136xxxXXXX
DxxxxxxxA
1C - ES
Date Code
Lot Code
Engineering Sample
Operating Range
UG112_C1_01_040709
Figure 1-1:
Table 1-2:
Top Marking (for Large Device Packages)
Xilinx Device Marking Definition—Example
Item
Description
Corporate Logo
Xilinx logo, Xilinx name with trademark, and trademark-registered status.
Family Brand Logo
Product family name with trademark and trademark-registered status. This line is optional and
could appear blank.
1st Line
Device type.
Package type and pin count, circuit design revision, the location code for the wafer fab, the
geometry code, and date code.
2nd Line
3rd Line
A G in the third letter of a package type indicates a Pb-free RoHS compliant package. For more
details on Xilinx Pb-Free and RoHS Compliant Products, see:
http://www.xilinx.com/system_resources/lead_free/index.htm.
Ten alphanumeric characters for assembly, lot, and step information. The last digit is usually an
A or an M if a stepping version does not exist.
Device speed grade and temperature range. If a grade is not marked on the package, the
product is considered commercial grade.
Other variations for the 4th line:
4th Line
1C-xxxx
The xxxx indicates the SCD for the device. An SCD is a special ordering code
that is not always marked in the device top mark.
1C-ES
The ES indicates an Engineering Sample.
Small Form Factor Packages
A second template is used on smaller packages that do not have enough room for six lines
of marking. This marking is used mainly for PROMs, and can be found on some mediumsize packages as well.
Line 1
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Chapter 1: Package Information
Product name code, eight characters. Five or six characters (for example, 1765D)
designate the product name representation (usually the name without the “XC”). The
name is followed by the PROM package designator (usually a single character). The
last letter represents the temperature range (for example, M, I, C).
Line 2
Six numeric characters preceded by the “X” of the Xilinx logo. The first numeric
character after the “X” designates the last digit of the year in which the product was
assembled. This digit will be the same every 10 years. The next two numeric characters
identify the assembly work week. The last three characters are the final three digits of
the Assembly number for the lot.
Line 3
This line is usually left blank for customer PROM designator marking.
A third template is used for CPLD and Spartan FPGA small form factor packages.
Information is provided on four lines.
Line 1
Product name code (without XC). For example, 9536XL or 3S250E preceded by the "X"
of the Xilinx logo.
Line 2
Consists of 11 alphanumeric characters. The first character is a letter that represents the
manufacturing location. The next five numeric characters are the lot number. The last
four numeric characters are the four digit date code in YYWW format.
Line 3
Indicates the country of origin.
Line 4
Consists of about seven alphanumeric characters. The first two characters are the
CPLD or Spartan FPGA package designator and are followed by a three letter mask
code. The last two characters are the speed and temperature range.
Package Technology Descriptions
Pb-Free Packaging
Recent legislative directives and corporate driven initiatives around the world have called
for the elimination of Pb and other hazardous substances in electronics used in many
sectors of the electronics industry. The Pb-free program at Xilinx was established in 1999 as
a proactive effort to develop and qualify suitable material sets and processes for Pb-free
applications. Xilinx has taken the leadership position by quickly forming partnerships
with our customers, suppliers, and participating in industry consortiums to provide
technical solutions that are aligned with industry requirements.
Pb-free Material Set
Xilinx has researched alternatives for Pb compounds and has selected matte Sn lead finish
for lead-frame packages and SnAgCu solder balls for BGA packages. In addition, suitable
material sets are chosen and qualified for higher reflow temperatures (245oC – 260oC) that
are required by Pb-free soldering processes. Pb-free products from Xilinx are designated
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Package Technology Descriptions
with an additional “G” in the package designator portion of the part number. For example,
FGG1152 is the Pb-free version of FG1152.
Features
•
RoHS compliant
•
Compliant to JEDEC-J-STD-020 standard for peak reflow temperature (245oC – 260oC)
•
Packages marked with Pb-free identifier
Backward Compatibility
Backward compatibility, as described in this chapter, refers only to the soldering process.
Pb-free devices from Xilinx have the same form, fit and function as standard Pb-based
products. No changes are required for board design when using Pb-free products from
Xilinx. However, finish materials for boards might need to be adjusted.
Lead frame packages (PQG, TQG, VQG, PCG, QFG, etc.) from Xilinx are backward
compatible, meaning that the component can be soldered with Sn/Pb solder using Sn/Pb
soldering process. Lead-frame packages from Xilinx use a matte Sn plating on the leads
which is compatible with both Pb-free soldering alloys and Sn/Pb soldering alloy.
BGA packages (CPG, FTG, FGG, BGG, etc.), however, are not recommended to be soldered
with SnPb solder using a Sn/Pb soldering process. The traditional Sn/Pb soldering
process usually has a peak reflow temperature of 205oC - 220oC. At this temperature range,
the SnAgCu BGA solder balls do not properly melt and wet to the soldering surfaces. As a
result, reliability and assembly yields might be compromised.
For more information on Xilinx Pb-free solutions, refer to
http://www.xilinx.com/system_resources/lead_free/index.htm, and for more
information on the Pb-free reflow process, refer to XAPP427.
Tin Whisker Mitigation
Following are some of the efforts Xilinx is making to mitigate tin whiskering in Pb-free
lead-frame packages (non-BGA):
a.
b.
c.
Tin whisker growth mitigation practices are:
-
Annealing matte tin for 1 hour @ 150°C within 8 hours after tin plating
-
Minimum thicker plating thickness 400 micro inches (10 micro meter)
Xilinx assembly subcontractors comply with JEDEC standards for tin whisker test
conditions outlined by:
-
JESD22A121.01 (May 2005)
-
JESD201 (March 2006)
The lead finish method for Xilinx Pb-Free lead-frame product is:
-
100% matte tin plating over a bare Cu lead frame
Cavity-Up Plastic BGA Packages
BGA is a plastic package technology that utilizes area array solder balls at the bottom of the
package to make electrical contact with the system circuit board. The area array format of
solder balls reduces package size considerably when compared to leaded products. It also
results in improved electrical performance as well as having higher manufacturing yields.
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Chapter 1: Package Information
The substrate is made of a mutilayer BT (bismaleimide triazene) epoxy-based material.
Power and ground pins are grouped together and the signal pins are assigned in the
perimeter format for ease of routing on to the board. The package is offered in a die up
format and contains a wirebonded device that is covered with a mold compound.
Package Construction
X-Ref Target - Figure 1-2
Plastic Mold
Plated Copper Conductor
Soldermask
Thermal Vias
BT (PCB Laminate)
Solder Ball
UG112_c1_02_111508
Figure 1-2:
Cavity-Up Ball Grid Array Package
As shown in the cross section of Figure 1-2, the BGA package contains a wire bonded die
on a single-core printed circuit board with an overmold. Beneath the die are the thermal
vias which can dissipate the heat through a portion of the solder ball array and ultimately
into the power and ground planes of the system circuit board. This thermal management
technique provides better thermal dissipation than a standard PQFP package. Metal planes
also distribute the heat across the entire package, enabling a 15–20% decrease in thermal
resistance to the case.
Key Features/Advantages of Xilinx Cavity-Up BGA Packages
•
High board assembly yield since board attachment process is self-centering
•
SMT compatible, resulting in minimum capital investment
•
Extendable to multichip modules
•
Low profile and small footprint
•
Improved electrical performance (short wire length)
•
Enhanced thermal performance
•
Excellent board level reliability
Cavity-Down Thermally Enhanced BGA Packages
Copper-based cavity-down BGAs are high-performance, low-profile packages that offer
superior electrical and thermal characteristics. This technology is especially applicable for
high-speed, high-power semiconductors such as the Virtex device family.
Package Construction
Figure 1-3 depicts the cross-section of the cavity-down BGA package. It should be noted
that this is a solid construction without any internal cavity. The backside die is attached
directly to the copper heat spreader and conducts heat out of the package through an
epoxy die attach adhesive. The larger the die size and the package body size, the better the
thermal performance. The incorporation of the copper heat spreader also results in thermal
resistance values that are lowest among the packages offered by Xilinx.
18
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Package Technology Descriptions
Attached to the heatspreader is a copper stiffener with cavity out to accommodate the die.
Along with the heatspreader, this stiffener provides the mechanical flexural strength and
warpage control for the package. On the exposed surface of the stiffener is a laminate or
build-up structure that contains the circuit traces, the power and ground planes if any, and
the sites for the connecting solder balls. The laminate is made of either a glass-reinforced
high-glass transition temperature (Tg) bismaleimide triazine (BT) or build-up structure.
Xilinx uses laminate with up to four layers, including PWR and GND planes.
Key Features/Advantages of Xilinx Cavity-Down BGAs
•
Lowest thermal resistance (θJA < 13°C/W)
•
Superior electrical performance
•
Low profile and light weight construction
•
Excellent board-level reliability
X-Ref Target - Figure 1-3
Cu Heatspreader
Die Attach Adhesive
Cu Ring
Substrate
Gold Wire
Solder Ball
Encapsulant
UG112_c1_03_111508
Figure 1-3:
Cavity-Down BGA Package
Flip-Chip BGA Packages
Flip chip is a packaging interconnect technology that replaces peripheral bond pads of
traditional wirebond interconnect technology with area array interconnect technology at
the die/substrate interface. The bond pads are either redistributed on the surface of the die
or in some very limited cases, they are directly dropped from the core of the die to the
surface. Because of this inherent distribution of bond pads on the surface of the device,
more bond pads and I/Os can be packed into the device.
X-Ref Target - Figure 1-4
UG112_c1_04_111508
Figure 1-4:
Device Package User Guide
UG112 (v3.7) September 5, 2012
www.xilinx.com
Eutectic Bumps
19
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Chapter 1: Package Information
The Xilinx flip-chip BGA package is offered for Xilinx high-performance FPGA products.
Unlike traditional packaging in which the die is attached to the substrate face up and the
connection is made by using wire, the solder bumped die in flip-chip BGA is flipped over
and placed face down, with the conductive bumps connecting directly to the matching
metal pads on the laminate substrate.
Unlike traditional packaging technology in which the interconnection between the die and
the substrate is made possible using wire, flip chip utilizes conductive bumps that are
placed directly on the area array pads of the die surface. The area array pads contain
wettable metallization for solders (either eutectic or high lead) where a controlled amount
of solder is deposited either by plating or screen-printing. These parts are then reflowed to
yield bumped dies with relatively uniform solder bumps over the surface of the device.
The device is then flipped over and reflowed on a ceramic or organic laminate substrate.
The solder material at molten stage is self-aligning and produces good joints even if the
chips are placed offset to the substrates. After the die is soldered to the substrate, the gap
(standoff) formed between the chip and the substrate is filled with an organic compound
called underfill. The underfill is a type of epoxy that helps distribute stresses from these
solder joints to the surface of the whole die and hence improve the reliability and fatigue
performance of these solder joints.
This interconnect technology has emerged in applications related to high performance
communications, networking and computer applications as well as in consumer
applications where miniaturization, high I/O count, and good thermal performance are
key attributes.
Package Construction
Flip-chip BGA packages for high-performance applications are built on high-density
multi-layer organic laminate substrates. Because the flip-chip bump pads are in area array
configuration, it requires very fine lines and geometry on the substrates to be able to
successfully route the signals from the die to the periphery of the substrates. Multilayer
build-up structures offer this layout flexibility on flip-chip packages.
Figure 1-5 and Figure 1-6 show cross-section views of the package constructions. Note that
two types of lids are used to assemble flip-chip BGA packages; type I lids (as shown in
with flat top) and type II lids (as shown in Figure 1-6 with hat-type top), depending on the
package type. Use the package drawing specification (to determine the lid type used on the
specific packages, see
http://www.xilinx.com/support/documentation/package_specifications.htm.
X-Ref Target - Figure 1-5
Underfill
Epoxy
Flip Chip
Solder Bump
Adhesive
Epoxy
Thermal Interface
Material
Copper
Heatspreader
Silicon Die
Solder Ball
Organic Build-up
Substrate
UG112_c1_05_052709
Figure 1-5:
20
Flip-Chip BGA Package with Type I Lid
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Device Package User Guide
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Package Technology Descriptions
X-Ref Target - Figure 1-6
Copper
Heatspreader
Flip Chip
Solder Bump
Adhesive
Epoxy
Thermal Interface Underfill
Material
Epoxy
Silicon Die
Solder Ball
Organic Build-up
Substrate
UG112_c1_06_111508
Figure 1-6:
Flip-Chip BGA Package with Type II Lid
Xilinx flip-chip packages are not hermetically sealed, and exposure to cleaning solvents or
excessive moisture during board assembly can pose serious package reliability concerns.
Small vents are placed by design between the heatspreader (lid) and the organic substrate
to allow for outgassing and moisture evaporation. These vent holes are located in the
middle of all four sides of FF flip-chip packages. Solvents or other corrosive chemicals can
seep through these vents and attack the organic materials and components inside the
package and are strongly discouraged during board assembly of Xilinx flip-chip BGA
packages. The only exception would be for EF flip-chip packages in which special epoxy
protection is applied to protect against solvents.
Key Features/Advantages of Flip-Chip BGA Packages
•
Easy access to core power/ground, resulting in better electrical performance
•
Excellent thermal performance (direct heatsinking to backside of the die)
•
Higher I/O density since bond pads are in area array format
•
Higher frequency switching with better noise control
Assembling Flip-Chip BGAs
The Xilinx flip-chip BGAs conform to JEDEC body sizes and footprint standards. These
packages follow the EIA moisture level classification for plastic surface mount components
(PSMC). Standard surface mount assembly process should be used with consideration for
the slightly higher thermal mass for these packages.
Like other SMT components, flip-chip BGA assembly involves the following process:
screen printing, solder reflow, post reflow washing. The following will serve as a guideline
on how to assemble flip-chip BGAs onto PCBs.
Screen Printing Machine Parameters
Below is an example of the parameters that were used for the screen printing process. Note
that these might not be optimized parameters. Optimized parameters will depend on
user's applications and setup.
•
Equipment: MPM Ultraprint 2000
•
Squeegee Type: Metal
•
Squeegee Angle: 45°
Device Package User Guide
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Chapter 1: Package Information
•
Squeegee Pressure: 24 lbs/sq. in.
•
Squeegee Speed: 0.7 in/second
•
Print Cycle: One pass
•
Stencil Snap Off: 0.10 inches
•
Stencil Lift Off Speed: Slow
Screen Printing Process Parameters
•
Solder paste: Alpha Metals WS609 (water soluble)
•
Stencil aperture: 0.0177 inches diameter
•
Stencil thickness: 0.006 inches
•
Aperture creation: Laser cut
It is highly recommended to use either a no-clean solder paste or a water soluble solder paste. If
cleaning is required, then a water soluble solder paste should be used.
Chip Scale Packages
Chip Scale Packages have emerged as a dominant packaging option for meeting the
demands of miniaturization while offering improved performance. Applications for Chip
Scale Packages are targeted to portable and consumer products where real estate is of
utmost importance, miniaturization is key, and power consumption/dissipation must be
low. A Chip Scale Package is defined as a package that fits the definition of being between
1 to 1.2 times the area of the die that the package contains while having a pitch of less than
1 mm.
By employing CSP packages, system designers can dramatically reduce board real estate
and increase the I/O counts.
Package Construction
Although there are currently more than 50 different types of CSPs available in the market,
Xilinx CSP packages fall into two categories, as shown in Figure 1-7: flex-based substrates
and rigid BT-based substrates. Although, both types meet the reliability requirement at the
component and board level, BT-based substrate was chosen for the newer devices because
of the large vendor base producing/supporting the BT-based substrates.
Key Features/Advantages of CSP Packages
22
•
An extremely small form factor which significantly reduces board real estate for such
applications as PCMCIA cards, portable and wireless designs, and PC add-in cards
•
Lower inductance and lower capacitance
•
The absence of thin, fragile leads found on other packages
•
A very thin, light-weight package
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Device Package User Guide
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Package Technology Descriptions
X-Ref Target - Figure 1-7
Die
Attach
Molding
Compond
Die
Attach
Molding
Compond
IC
BT Resin
Solder Ball
Solder
Mask
Plated
Via
Polyimide
Tape
Copper
Plating
UG112_c1_07_112508
Figure 1-7:
Rigid BT-Based Substrate Chip Scale Packages, Left; Flex-Based Tape
Substrate, Right
Quad Flat No-Lead (QFN) Packages
Quad Flat No-Lead (QFN) or MLF package is a robust and low-profile lead frame-based
plastic package that has several advantages over traditional lead frame packages. The
exposed die-attach paddle enables efficient thermal dissipation when directly soldered to
the PCB. Additionally, this near chip scale package offers improved electrical performance,
smaller package size, and an absence of external leads. Since the package has no external
leads, coplanarity and bent leads are no longer a concern.
Xilinx Quad Flat No-Lead packages are ideal for portable applications where size, weight,
and performance matter.
Package Construction
The QFN is a molded leadless package with land pads on the bottom of the package.
Electrical contact to the PCB is made by soldering the land pads to the PCB. The backside
of the die is attached to the exposed paddle through the die attach material which is
electrically conductive. The exposed pad therefore represents a weak ground and should
be left floating or connected to a ground net.
X-Ref Target - Figure 1-8
Gold
Wire
Mold
Compound
Die Attach
Epoxy
Silicon Die
Copper
Leadframe
Down
Bond
Exposed
Die Paddle
Ground
Bond
UG112_c1_08_112508
Figure 1-8:
Device Package User Guide
UG112 (v3.7) September 5, 2012
QFN Cross Section (Left) and Bottom View (Right)
www.xilinx.com
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Chapter 1: Package Information
Key Features/Advantages of QFN Packages
•
Small size and light weight
•
Excellent thermal and electrical performance
•
Compatible with conventional SMT processes
Ceramic Column Grid Array (CCGA) Packages
Ceramic Column Grid Array (CCGA) packages are surface-mount-compatible packages
that use high-temperature solder columns as interconnections to the board. Compared to
the solder spheres, the columns have lower stiffness and provide a higher stand-off. These
features significantly increase the reliability of the solder joints. When combined with a
high-density, multilayer ceramic substrate, this packaging technology offers a high density,
reliable packaging solution. Ceramic offers the following benefits:
Key Features/Advantages of CCGA Packages
•
High planarity and excellent thermal stability at high temperature
•
CTE matches well with the silicon die
•
Low moisture absorption
Xilinx offers 3 different formats of CCGA: “Cavity-Down” wire-bonded CCGA, “CavityUp” wire-bonded CCGA, and flip-chip CCGA.
Cavity-Down Wire-Bonded CCGA – CG560 Package Construction
CG560 is offered with the Xilinx XQV1000 and XQVR1000 devices. It is pin-compatible
with the plastic BG560 package. Below are additional attributes of CG560.
•
Interconnect: 90Pb/10Sn hard solder column interposer, attached with 63Sn/37Pb soft
solder.
•
Hermetically sealed with eutectic Sn/Au
-
X-Ref Target - Figure 1-9
Copper/Tungsten
Heatsink
Solder
Column
Kovar
(Plated with Au)
Lid
Ceramic
Substrate
UG112_c1_09_111608
Figure 1-9:
CG560 Package
Cavity-Up Wire-Bonded BGA – CG717 Package Construction
CG717 is offered with the Xilinx XQ2V3000 and XQR2V3000 devices. It is pin-compatible
with the plastic BG728 package. Below are additional attributes of CG717.
•
24
Interconnect: 80Pb/20Sn hard solder column, attached with 63Sn/37Pb soft solder.
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Device Package User Guide
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Package Technology Descriptions
•
Hermetically sealed with eutectic Sn/Au
X-Ref Target - Figure 1-10
Kovar
(Plated with Au)
Lid
Solder
Column
Ceramic
Substrate
UG112_c1_10_111608
Figure 1-10: CG717 Package
Flip-Chip CCGA – CF1144 Package Construction
Flip-Chip CCGA is targeted for applications that require high performance, density, and
high reliability. CF1144 is offered with the Xilinx XQ2V6000 and XQR2V6000 devices. The
CF1144 package is pin-compatible with the plastic flip-chip FF1152 package. Below are
additional attributes of CF1144:
•
95Pb/5Sn flip-chip solder bumps
•
90Pb/10Sn hard solder column
X-Ref Target - Figure 1-11
Underfill
Epoxy
Flip-chip
Solder Bump
Thermal
Adhesive
Aluminum
Heatspreader
Silicon Die
Solder
Column
Ceramic Multi-layer
Substrate
UG112_c1_11_120908
Figure 1-11:
CF1144 Package
Thermally Enhanced Lead Frame Packaging
Xilinx offers thermally enhanced quad flat pack packages on XC4000 Series devices and
some earlier Virtex devices. This section discusses the performance and usage of these
packages (designated HQ).
Key Features/Advantages of Thermally Enhanced Lead Frame Packages
•
The HQ-series and the regular PQ packages conform to the same JEDEC drawings.
•
The HQ and PQ packages use the same PCB land patterns.
Device Package User Guide
UG112 (v3.7) September 5, 2012
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Chapter 1: Package Information
•
The HQ packages have more mass
•
Thermal performance is better for the HQ packages
Applications of HQ Packages
•
HQ packages are offered as the thermally enhanced equivalents of PQ packages. They
are used for high gate count or high I/O count devices in packages, where heat
dissipation without the enhancement might be a handicap for device performance.
Such devices include XC4013E, XC4020E, XC4025E, and XC5215.
•
The HQ series at the 240-pin count level or below are offered with the heatsink at the
bottom of the package. This was done to ensure pin to pin compatibility with the
existing PQ packages.
At the 304-pin count level, the HQ is offered with the heatsink up. This arrangement
offers a better potential for further thermal enhancement by the designer.
X-Ref Target - Figure 1-12
A. Die Up / Heatsink Down
B. Die Down / Heatsink Up
A. Heatsink Down Orientation B. Heatsink Up Orientation
UG112_c1_12_040709
Figure 1-12:
•
Heatsink Orientation
In the die-up/heatsink-down configuration, the heatsink surface is insulated.
Package Mass Table
The numbers provided in Table 1-3 represent average values for typical devices used in the
package. Die size variation from device to device, slight changes in moisture content,
number of specific layers used in the specific substrate etc., will provide some variation. In
some cases the data accuracy can be up to ±10%. More precise numbers for specific devices
in a lot can be obtained from in situ weighing. If this is critical, specific lot information can
be requested.
26
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Package Mass Table
Table 1-3:
Package Mass (Weight) by Package Type
Package
Description
Mass (g)
BF957, BFG957
957 ball flip-chip BGA 40 x 40 body (1.27 mm
pitch)
18.5
BG225, BGG225
Molded BGA 27 mm Full Matrix
2.2
BG256, BGG256
Molded BGA 27 mm Peripheral
2.2
BG352, BGG352
SuperBGA 35 x 35 mm Peripheral
7.1
MPM BGA 35 x 35 mm (1.27 mm pitch)
4.6
BG432, BGG432
SuperBGA 40 x 40 mm Peripheral
9.1
BG492, BGG492
Molded BGA 35 mm (1.27 mm pitch)
4.6
BG560, BGG560
SuperBGA 42.5 x 42.5 mm SQ
12.3
BG575, BGG575
575 BGA 31 x 31 mm body (1.27 mm pitch)
4.4
BG728, BGG728
728 BGA 35 x 35 mm body (1.27 mm pitch)
6.2
CB100
NCTB Top Brazed XC3000/XC4000 VER
10.8
CB164
NCTB Top Brazed XC3000/XC4000 VER
11.5
CB196
NCTB Top Brazed XC4000 VER
15.3
CB228
NCTB Top Brazed XC4000 VER
17.6
CC20
Ceramic Leaded Chip Carrier
8.4
CC44
Ceramic Leaded Chip Carrier
2.9
CD48
Ceramic Side Brazed DIP
8.0
CD8
Ceramic Side Brazed DIP
0.9
CF1144
Ceramic Column flip chip, 35 x 35 mm,
1.0 mm pitch
44.0
CG560
Ceramic SPGA 42.5 x 42.5
44.0
CG717
Ceramic Column Grid Array, 35 x 35 mm,
1.27 mm pitch
13.3
CSP 56 BGA 6 mm (0.5 mm pitch)
0.1
CSP 132 BGA 8 x 8 mm, 0.5 mm ball pitch
0.1
CSP 48 BGA 7 mm (0.8 pitch)
0.2
CS144, CSG144
CSP 144 BGA 12 mm (0.8 pitch)
0.3
CS280, CSG280
CSP 280 BGA 16 mm (0.8 pitch)
0.5
CS484, CSG484
CSP 484 BGA 19 mm (0.8 pitch)
1.4
Cerdip Package (.300" Row Spacing)
1.1
FF665, FFG665
Flip-chip BGA 27 x 27 mm 1.0 mm pitch
4.4
FF668, FFG668
668 ball Ceramic Column flip-chip BGA,
27 x 27 mm, 1.0 mm ball pitch
4.4
BG388
CP56, CPG56
CP132, CPG132
CS48, CSG48
DD8
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Chapter 1: Package Information
Table 1-3:
Package Mass (Weight) by Package Type (Cont’d)
Package
Mass (g)
FF672, FFG672
672 ball flip-chip BGA, 27 x 27 mm, 1.0 mm
ball pitch
4.4
FF676, FFG676
676 ball flip-chip BGA, 27 x 27 mm, 1.0 mm
pitch Full
4.4
FF896, FFG896
896 ball flip-chip BGA 31 x 31 mm body
(1.0 mm pitch)
11.2
FF1136, FFG1136
Flip-chip BGA, 35 x 35 mm, 1.0 mm
14.0
FF1148, FFG1148
1148 ball flip-chip BGA 35 x 35 mm body
(1.0 mm pitch)
14.0
FF1152, FFG1152
1152 ball flip-chip BGA 35 x 35 mm body
(1.0 mm pitch)
14.0
FF1153, FFG1153
Flip-chip BGA 35 mm x 35 mm 1.0 mm
14.0
FF1513, FFG1513
1513 ball flip-chip BGA 40 x 40 mm body
(1.0 mm pitch)
17.0
FF1517, FFG1517
1517 ball flip-chip BGA 40 x 40 mm body
(1.0 mm pitch)
17.2
FF1696, FFG1696
1696 ball flip-chip BGA 42.5 x 42.5 mm body
(1.0 mm pitch)
20.5
FF1704, FFG1704
1704 ball flip-chip BGA 42.5 x 42.5 mm body
(1.0 mm pitch)
21.1
FF1738, FFG1738
Flip-chip BGA 42.5 x 42.5 mm 1.0 mm pitch
22.0
FF1760, FFG1760
Flip-chip BGA 42.5 x 42.5 mm 1.0 mm pitch
22.0
FG256, FGG256
Fine pitch BGA 17 x 17 mm, 1.0 mm ball pitch
0.8
FG320, FGG320
Fine pitch BGA 19 x 19 mm, 1.0 mm ball pitch
1.4
FG324, FGG324
Molded BGA 23 mm 1.0 mm pitch
2.2
FG456, FGG456
Fine pitch BGA 23 x 23 mm, 1.0 mm ball pitch
2.2
FG400, FGG400
Fine pitch BGA 21 x 21 mm, 1.0 mm ball pitch
2.2
FG484, FGG484
Molded BGA 23 mm 1.0 mm pitch
2.2
FG556, FGG556
Fine pitch BGA 31 x 31 mm, 1.0 mm ball pitch
3.9
SuperBGA 35 x 35 mm, 1.0 mm pitch
7.1
FG676, FGG676
Fine pitch BGA 27 x 27 mm, 1.0 mm ball pitch
3.06
FG680, FGG680
Fine pitch BGA 40 x 70 mm, 1.0 mm ball pitch
10.6
FG860, FGG860
Fine pitch BGA 42.5 x 42.57 mm, 1.0 mm ball
pitch
13.8
FG900, FGG900
Fine pitch BGA 31 x 31 mm, 1.0 mm ball pitch
4.2
FG1156, FGG1156
Fine pitch BGA 35 x 35 mm, 1.0 mm ball pitch
6.2
CSP 48BGA, 6 x 8 mm, 0.8 mm ball pitch
0.1
FG580
FS48, FSG48
28
Description
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Package Mass Table
Table 1-3:
Package Mass (Weight) by Package Type (Cont’d)
Package
Description
Mass (g)
256 Thin PBGA 17 x 17 mm body (1.0 mm
pitch)
0.9
HQ160, HQG160
Metric 28 x 28 0.65 mm 1.6H/S Die Up
10.8
HQ208, HQG208
Metric 28 x 28 H/S Die Up
10.8
HQ240, HQG240
Metric QFP 32 x 32 H/S Die Up
15.0
HQ304, HQG304
Metric QFP 40 x 40 H/S Die Down
26.2
HT144
Thin QFP 1.4 H/S (HQ) Die Up
2.6
HT176
Thin QFP 1.4 H/S (HQ) Die Up
3.5
PC20, PCG20
PLCC JEDEC MO-047
0.8
PC28, PCG28
PLCC JEDEC MO-047
1.1
PC44, PCG44
PLCC JEDEC MO-047
1.2
PC68, PCG68
PLCC JEDEC MO-047
4.8
PC84, PCG84
PLCC JEDEC MO-047
6.8
PD8, PDG8
DIP .300 Standard
0.5
PD48
DIP .600 Standard
7.9
PG68
Ceramic PGA “Cavity Up” 11 x 11
7.0
PG84
Ceramic PGA “Cavity Up” 11 x 11
7.2
PG84
Windowed CPGA “Cavity Up” 11 x 11
7.5
PG120
Ceramic PGA 13 x 13 Matrix
11.5
PG132
Ceramic PGA 14 x 14 Matrix
11.8
PG144
Ceramic PGA 15 X15 Cavity Up
16.9
PG156
Ceramic PGA 16 x 16 Matrix
17.1
PG175
Ceramic PGA 16 x 16 Standard Version
17.7
PG191
Ceramic PGA 18 x 18 Standard (All)
21.8
PG223
Ceramic PGA 18 x 18 Type
26.0
PG299
Ceramic PGA 20 x 20 Heatsink
37.5
PG299
Ceramic PGA 20 x 20 Matrix
29.8
PG411
Ceramic PGA 39 x 39 Stagger
36.7
PG475
Ceramic PGA 41 x 41 Stagger
39.5
PG559
Ceramic PGA 43 x 43
44.5
PQ44, PQG44
EIAJ 10 x 10 x 2.0 QFP
0.5
PQ100, PQG100
EIAJ 14 x 20 QFP - 1.60 (default)
1.6
PQ100, PQG100
EIAJ 14 x 20 QFP - 1.80 (not used)
1.6
FT256, FTG256
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Chapter 1: Package Information
Table 1-3:
Package Mass (Weight) by Package Type (Cont’d)
Package
Mass (g)
PQ100, PQG100
EIAJ 14 x 20 QFP - 1.95 (old version)
1.6
PQ160, PQG160
EIAJ 28 x 28 0.65 mm 1.60
5.8
PQ208, PQG208
EIAJ 28 x 28 0.5 mm 1.30
5.3
PQ240, PQG240
EIAJ 32 x 32 0.5 mm
7.1
Flip-chip BGA 17 x 17, 0.8 mm pitch
1.6
Version 1 0.150/50 mil
0.1
SO20, SOG20
300 mil SOIC
0.5
SO24
300 mil SOIC
0.6
TQ100, TQG100
Thin QFP 1.4 mm thick
0.7
TQ128, TQG128
Thin QFP 1.4 mm thick RECT
0.8
TQ144, TQG144
Thin QFP 1.4 mm thick
1.4
TQ176, TQG176
Thin QFP 1.4 mm thick
1.9
Thin SOIC - II
0.1
VO20, VOG20
Thin SSOP, 4.4 mm
0.1
VO48, VOG48
Thin SOP
0.5
VQ44, VQG44
Thin QFP 1.0 thick
0.4
VQ64, VQG64
THIN QFP 1.0 thick
0.5
VQ100, VQG100
Thin QFP 1.0 thick
0.6
SF363, SFG363
SO8, SOG8
VO8, VOG8
30
Description
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Chapter 2
Pack and Ship
Introduction
Xilinx offers several packing options for our through-hole and surface-mount products.
The devices are packed in either tubes, trays, or tape and reel.
Tape and Reel
Xilinx offers a tape and reel packing for PLCC, BGA, QFP, and SO packages. The packing
material is made of black conductive polystyrene and protects the packages from
mechanical and electrical damage. The reel material provides a suitable medium for pick
and place equipment.
The tape and reel packaging consists of a pocketed carrier tape, sealed with a protective
cover. The device sits on pedestals (for PLCC, QFP packages) to protect the leads from
mechanical damage. All devices loaded into the tape carriers are baked, lead scanned
before the cover tape is attached and sealed to the carrier. In-line mark inspection for mark
quality and package orientation is used to ensure shipping quality.
Benefits
•
Increased quantity of devices per reel versus tubes improves cycle time and reduces
the amount of time to index spent tubes.
•
Tape and reel packaging enables automated pick and place board assembly.
•
Reels are uniform in size enabling equipment flexibility.
•
Transparent cover tape allows device verification and orientation.
•
Antistatic reel materials provides ESD protection.
•
Carrier design include a pedestal to protect package leads during shipment.
•
Bar code labels on each reel facilitate automated inventory control and component
traceability.
•
All tape and reel shipments include desiccant pouches and humidity indicators to
ensure products are safe from moisture.
•
Compliant to Electronic Industries Association (EIA) 481. Material and Construction
Carrier Tape.
•
The pocketed carrier tape is made of conductive polystyrene material, or equivalent,
with a surface resistivity level of less than 106 ohms per square inch.
•
Devices are loaded “live bug” or leads down, into a device pocket.
•
Each carrier pocket has a hole in the center for automated sensing of whether a unit is
in the pocket or not.
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Chapter 2: Pack and Ship
•
Sprocket holes along the edge of the carrier tape enable direct feeding into automated
board assembly equipment.
Cover Tape
An anti-static, transparent, polyester cover tape, with heat activated adhesive coating,
sealed to the carrier edges to hold the devices in the carrier pockets.
Surface resistivity on both sides is less than 1011 ohms per square inch.
Reel
The reel is made of anti-static polystyrene material. The loaded carrier tape is wound onto
this conductive plastic reel.
A protective strip made of conductive polystyrene material is placed on the outer part of
the reel to protect the devices from external pressure in shipment.
Surface resistivity is less than 1011 ohms per square inch.
Device loading orientation is in compliance with EIA Standard 481.
Bar Code Label
The bar code label on each reel provides customer identification, device part number, date
code of the product and quantity in the reel.
Print quality are in accordance with ANSI X3.182-1990 Bar Code Print Quality Guidelines.
Presentation of Data on labels are EIA-556-A compliant.
The label is an alphanumeric, medium density Code 39 labels.
This machine-readable label enhances inventory management and data input accuracy.
Shipping Box
The shipping container for the reels are in a 13 in. x 13 in. x 3 in. C-flute, corrugated, #3
white “pizza box,” rated to 200 lb. test.
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Table 2-1:
Tape and Reel
Tape and Reel Packaging
Package Code
Qty. Per Reel
Reel Size (inches) Carrier Width (mm) Cover Width (mm)
Pitch (mm)
BG225(1), BGG225(1)
500
13
44
37.5
32
BG256(1), BGG256(1)
500
13
44
37.5
32
BG272(1), BGG272(1)
500
13
44
37.5
32
CP56(1), CPG56(1)
4000
13
12
9.2
8
CS48(1),
1500
13
16
13.3
12
CS144(1), CSG144(1)
2000
13
24
21.0
16
FG256(1), FGG256(1)
1000
13
24
21.0
20
FG456(1), FGG456(1)
500
13
44
37.5
32
FG676(1), FGG676(1)
500
13
44
37.5
32
FT256, FTG256
1000
13
24
21
20.0
PC20(1), PCG20(1)
750
13
16
13.3
12
PC44(1), PCG44(1)
500
12
32
25.5
14
PC68(1), PCG68(1)
250
13
44
37.5
32
PC84(1), PCG84(1)
250
13
44
37.5
36
PQ100, PQG100
250
13
44
37.5
32
PQ160, PQG160
200
13
44
37.5
40
BG352(1), BGG352(1)
200
13
56
49.5
40
BG432(1), BGG432(1)
200
13
56
49.5
48
BG560(1), BGG560(1)
200
13
56
49.5
48
SO8
750
7
12
9.2
8
SO20
1000
13
24
21.0
12
TQ100, TQG100
1000
13
24
21.0
32
TQ144, TQG144
750
13
44
37.5
24
VO8, VOG8
750
7
12
9.2
8
VO20, VOG20
2500
13
16
13.3
12.0
VQ44, VQG44
2000
13
24
21.0
16
VQ64, VQG64
2000
13
24
21.0
16
VQ100, VQG100
1000
13
24
21.0
32
CSG48(1)
Note:
1. In-house capability.
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Chapter 2: Pack and Ship
Standard Bar Code Label Locations
X-Ref Target - Figure 2-1
Antistatic Tape
Desiccant
Bag
Bar Code
Label
ESD
Label
Antistatic Tape
Desiccant
Bag
UG112_C2_01_111208
Figure 2-1:
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Tubes
X-Ref Target - Figure 2-2
Desiccant
Included
Label
Bar Code
Label
ESD
Label
Vacuum Sealed Bag
UG112_C2_02_111208
Figure 2-2:
Standard Bar Code Label Locations
Tubes
Tubes are used as unit carriers for most of Xilinx smaller packages. All of our tubes are
coated with an antistatic material to protect the product from ESD damage.
Table 2-2:
Standard Device Quantities per Tube
Full Tube Quantity
Max. Tube Qty. per ESD Bag
(8.5” x 27”)
Max. Tube Qty. per
ESD Bag (12” x 27”)
PC84, PCG84, WC84
15
24
40
PC68, PCG68, WC68
18
36
50
PC44, PCG44, CC44, WC44
26
40
50
PC28, PCG28
37
40
50
PC20, PCG20, CC20
46
50
60
CD48
7
24
30
PD48
7
24
30
CD8
37
10
15
PD8
50
50
60
DD8
50
50
60
SO24
31
40
50
Package
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Chapter 2: Pack and Ship
Table 2-2:
Standard Device Quantities per Tube
SO20
37
60
100
SO8
98
240
350
VO20, VOG20
74
240
350
VO24
62
240
350
VO8, VOG8
98
240
350
Trays
Trays are used to pack most of Xilinx surface-mount devices since they provide excellent
protection from mechanical damage. In addition, they are coated with antistatic material to
provide protection against ESD damage and can withstand operation temperature of up to
150o C.
Table 2-3:
Standard Device Counts per Tray and Box
Max Number of Devices
Per Tray
Max Number of Units In
One Internal Box
BF957/BFG957
21
105
BG225/BGG225
BG256/BGG256
40
200
BG352/BGG352
BG492/BGG492
BG728/BGG728
24
120
BG432/BGG432
21
105
BG560/BGG560
12
60
BG575/BGG575
27
135
CB100, CB164, CB196,
CB228
4
20
CP56/CPG56
360
1800
CP132/CPG132
360
1800
CS48/CSG48
416
2080
CS144/CSG144
198
990
CS225/CSG225
160
800
CS280/CSG280
119
595
CS324/CSG324
126
630
CS484, CSG484
84
420
FG256/FGG256
90
450
FG320/FGG320
84
420
FG324/FGG324
60
300
Package
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Trays
Table 2-3:
Standard Device Counts per Tray and Box (Cont’d)
Max Number of Devices
Per Tray
Max Number of Units In
One Internal Box
FG400/FGG400
FG456/FGG456,
FG484/FGG484
60
300
FG676/FGG676
40
200
FG860
12
60
FG900/FGG900
27
135
FG680/FGG680
21
105
FF323/FFG323
FF324/FFG324
84
420
FG1156/FGG1156
24
120
FF665/FFG665
FF668 / FFG668
40
200
FF672/FFG672
FF676/FFG676
40
200
FF896/FFG896
27
135
FF1136/FFG1136
FF1148/FFG1148
FF1152/FFG1152
FF1153/FFG1153
FF1156/FFG1156
24
120
FF1513/FFG1513
FF1517/FFG1517
21
105
FF1696/FFG1696
FF1704/FFG1704
FF1738/FFG1738
FF1760/FFG1760
12
60
FS48/FSG48
108
525
FT256/FTG256
90
450
HQ160/HQG160
HQ208/HQG208
24
120
HQ240/HQG240
24
120
HQ304
12
60
HT144
60
300
HT176
40
200
PG68, PG84
40
200
PG120
24
120
PG132/PP132
21
105
PG144
18
90
Package
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Chapter 2: Pack and Ship
Table 2-3:
Standard Device Counts per Tray and Box (Cont’d)
Max Number of Devices
Per Tray
Max Number of Units In
One Internal Box
PG156/PP156
PG175/PP175
14
70
PG191, PG223
12
60
PG299
10
50
PG411, PG475, PG559
10
50
PQ44/PQG44
96
480
PQ100/PQG100
66
330
PQ160/PQG160
PQ208/PQG208
24
120
PQ240/PQG240
24
120
QFG32
490
2450
QFG48
260
1300
SF363/SFG363
90
450
TQ144, TQG144
60
300
TQ160, TQ176
40
200
TQ100/TQG100
90
450
TQ128
72
360
VO48/VOG48
96
480
VQ44/VQG44
VQ64/VQG64
160
800
VQ100/VQG100
90
450
Package
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Chapter 3
Thermal Management & Thermal
Characterization Methods & Conditions
Introduction
This chapter addresses the need to manage the heat generated in CMOS logic devices, an
industry wide pursuit, and describes the measures Xilinx uses and recommends to its
customers to quantify and manage potential thermal problems in FPGAs.
Thermal Management
Modern high-speed logic devices consume an appreciable amount of electrical energy. This
energy invariably turns into heat. Higher device integration drives technologies to
produce smaller device geometry and interconnections. With chip sizes getting smaller
and circuit densities at their highest levels, the amount of heat generated on these fastswitching CMOS circuits can be very significant. As an example, Xilinx 7 series FPGAs
incorporate multiple processors, multiple-gigabit transceivers, digital-controlled
impedance I/Os, and I/Os capable of supporting various high current standards. Special
attention must be paid to addressing the heat removal needs for these devices.
The need to manage the heat generated in a modern CMOS logic device is not unique to
Xilinx. This is a general industry pursuit. However, unlike the power needs of a typical
industry application-specific integrated circuit (ASIC) gate array, the field-programmable
device’s power requirement is not determined in the factory. Customers' designs can vary
in power as well as physical needs. This is the challenge in predicting FPGA thermal
management needs.
Xilinx Packages
In assigning packages to devices, efforts have been made to tailor the packages to the
power needs of typical users. For each device, suitable packages are chosen to handle
typical designs and gate utilization for the device. Sometimes, the choice of a package as
the primary or internal heat removal casing works well without any external heat
management. Increasingly, with highly integrated devices, the need arises for customers to
utilize an FPGA device beyond typical design parameters. For these situations, the use of
the primary package without external enhancement might not be adequate to address the
heat removal needs of the device. In that case it becomes essential to manage the heat
removal through external means. Heat has to be removed from a device to ensure that the
device is maintained within its functional and maximum design temperature limits. If heat
buildup becomes excessive, the device temperature might exceed its limits. Consequently,
the device might fail to meet the speed-file performance specifications. In addition to
performance considerations, there is also the need to satisfy system reliability objectives by
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operating at a lower temperature. Failure mechanisms and the failure rate of devices have
an exponential dependence on the device’s operating temperatures. Thus, the control of
the package, and by extension device temperature, is essential to ensure product reliability.
Heatsinks, Heatsink Interface Materials, and Heatsink Attachments
The primary purpose of a heatsink is to help remove heat from a device more efficiently
than just the device’s package alone. Heatsinks accomplish this by decreasing the overall
thermal resistance between the case of a device and the surrounding air. They effectively
increase the surface area over which heat can be dissipated. Three factors should be
considered for a given heatsink design: the heatsink itself, the heatsink interface material,
and the attachment mechanism. With a heatsink attached to an integrated circuit (IC), heat
from the device flows from the junction of the device to the case, from the case to the
interface material, from the interface material to the heatsink, and finally from the heatsink
to ambient air. In situations where a heatsink is used with a heatsink compound, the
thermal resistance of the heatsink is referenced as θSA (sink-to-ambient) and that of the
attached material as θCS (case-to-heatsink). These thermal resistances can be added. For
example, θJAtop = θJCtop + θCS + θSA is an expression used in heatsink situations with
interface material resistance θCS.
Heatsinks come in a variety of materials, shapes, and sizes, but share the common goal of
maximizing the heat dissipation between the device that they attach to and the
surrounding air, which might be still air or air flowing via a forced convection system
(typically fans). The improved heat dissipation of a heatsink is accomplished by
maximizing surface area through the use of fins of varying dimensions and spacings, and
might also include components such as copper heat spreaders that can help distribute the
heat from smaller ICs more evenly over the surface area of the heatsink.
Heatsink interface materials, which are used between the heatsink and the device, can be
of many kinds, including greases, gels, adhesives, tapes, silicon rubber materials, and
special thermoplastic adhesives known as phase change materials. Each of these has
unique benefits and drawbacks that need to be considered for their ability to meet the
requirements and priorities of the particular design. When choosing a heatsink, the
manufacturer should provide recommendations for possible interface materials.
Heatsink attachments attach the heatsink either directly to the device package, or to the
PCB around the device. Possible heatsink attachments include thermal epoxies and tapes,
mechanical attachments such as clips that attach directly to the package, or pins and
screws that attach to the PCB. Each of these attachments has unique benefits and
drawbacks that need to be considered for their ability to meet the needs of the particular
design. When choosing a heatsink from a manufacturer, the attachment mechanism can be
part of the heatsink, or they might be options recommended by the manufacturer. For
additional information about heatsinks and other thermal management solutions, refer to
“Additional Power Management Options,” page 57.
Power Estimation Tools
Xilinx offers two software-based power-estimator tools to help the user predict power
consumption: XPower Estimator (XPE) and XPower Analyzer (XPA). These tools provide
the capability of performing detailed power estimation and analysis for designs running in
Xilinx FPGAs. With these tools, it is possible to perform “what if” scenarios to analyze the
power consumption of variations to a given design. θJA for still or forced air flow, θJB, and
even θSA for heatsinks are all provided as estimates within the XPE tool. These can also be
overridden if the values are extracted from higher accuracy simulations or methods. A key
output of these tools is the device junction temperature (TJ) based on the power estimates.
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Like most tools, however, the predicted output depends on the work put into the
predicting effort. For more information on power estimation and optimization in the Xilinx
design tools, see:
•
UG786, Power Methodology Guide
•
UG440, XPower Estimator User Guide
•
UG907, Vivado Design Suite User Guide: Power Analysis and Optimization
•
XPower Analyzer details
www.xilinx.com/products/design_tools/logic_design/verification/xpower_an.htm
•
UG733, Xilinx Power Tools Tutorial
Compact Thermal Models
While the XPE and XPA power-estimator tools can provide the traditional thermal
resistance data for all Xilinx packages in addition to the estimated power consumption of
a design, this resistance data is measured using a prescribed JEDEC standard that might
not necessarily reflect the actual user environment. The quoted θJA and θJC numbers are
environmentally dependent, and JEDEC has traditionally recommended that these be used
with that awareness. For more accurate junction temperature prediction, these might not
be enough, and a system-level thermal simulation might be required. To aid in this, Delphi
boundary condition independent compact thermal models (BCI-CTM) are available for
most Xilinx device/packages at the Xilinx support download center:
http://www.xilinx.com/support/download/index.htm.
These models are available to use with computational fluid dynamic (CFD) software to do
detailed thermal simulation and analysis of entire boards and systems, including the
printed circuit board design, other devices, heatsinks, enclosures, and airflows. Xilinx
provides these models in both the Mentor FloTHERM and ANSYS Icepack formats.
Figure 3-1 shows two forms of compact thermal model topologies, the DELPHI BCI-CTM,
and the two-resistor model. Xilinx provides models in the DELPHI BCI-CTM format.
X-Ref Target - Figure 3-1
DELPHI BCI-CTM Topology for FCBGA
TI
Two-Resistor Model
TO
R jc
Junction
Side
Junction
R jb
BI
BO
UG112_c3_06 _110711
Figure 3-1:
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Chapter 3: Thermal Management & Thermal Characterization Methods & Conditions
PCB Design: Layer, Board, and Layout Considerations
The majority of heat flow from an IC generally follows two paths:
•
Through the top of the case to the surrounding air (optionally through a heatsink)
•
Through the soldered interface to the PCB, and from the PCB to the surrounding air
Thus, a two-resistor compact model is commonly used to model the thermal behavior of a
package. The two-resistor compact model for a package consists of θJAtop in parallel with
θJAboard. A graphical representation of this can be found in the JEDEC standard JESD51-12,
as shown in Figure 3-2.
X-Ref Target - Figure 3-2
Case-to-Ambient
Resistance
Junction-to-Case
Resistance
Junction
JCtop
Case Node
CA
JB
Board Node
BA
Junction-to-Board
Resistance
Figure 3-2:
Board-to-Ambient
Resistance
Ambient
UG112_c3_15_110711
Equivalent Thermal Resistance Diagram of the Two-Resistor Model on
a PCB
While this is known as a two-resistor model, it is really more of a four-resistor model, with
θJAtop being the sum of θJCtop + θCA, and θJAboard being the sum of θJB + θBA. The overall
θJA value can be estimated by calculating the parallel thermal resistance of θJAtop in
parallel with θJAboard.
The θJB and θBA thermal resistances can vary significantly depending on the PCB design, in
particular due to the size of the board and the number and thickness of the copper layers.
The more the copper material and surface area, the better the heat dissipation and the
lesser the thermal resistance between the devices and the board (θJB), as well as between
the board and the surrounding air (θJA). Larger boards provide larger surface area and
usually provide more copper material. As layer counts and copper thickness increase, θJB
and θJA tend to decrease—in particular for power or ground plane layers, as those tend to
be solid copper layers. Table 3-2, page 45 illustrates the effect of both board size and layer
count on the overall θJA.
Other layout considerations that can affect θJB and θBA include the types of power and
ground plane layers that are used (hatching vs. solid), and the use of thermal reliefs,
particularly at the board vias that connect the device being analyzed to the ground and
VCC planes. Historically, hatched plane layers provided a number of benefits including
aiding in the manufacturing process and providing flexibility to meet transmission line
impedance goals. However, they had the drawback of not having a solid plane of copper to
aid with thermal heat dissipation. There are better alternatives to cross-hatching planes for
modern board design and fabrication, and consequently, this technique is seldom used
today. Because of the reduction in the thermal heat dissipation, it is strongly recommended
to completely avoid the use of hatched planes. Thermal reliefs at the through-hole pads
and vias serve the purpose of actually increasing the thermal impedance between the
board landing pads for a component and the copper planes and traces that it connects to.
This is used to improve the solderability of devices, particularly for devices with
through-hole packages that require wave solder or similar assembly techniques (vs. solder
oven installation). However, thermal reliefs work in direct conflict to the goal of improving
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the overall thermal heat dissipation for when the board is operating—the thermal reliefs
effectively increase θJB. Most Xilinx device packages are not of the through-hole type and
are primarily offered in QFP and BGA packages. For these package types, it is not
necessary to use thermal reliefs on the pad vias for assembly purposes, and it is advised to
avoid doing so to minimize θJB.
Ambient temperature, Enclosures, and Airflow
One of the most critical variables required to analyze the thermal management of ICs on a
PCB is the device’s junction temperature (TJ). All ICs have requirements or specifications
for minimum and maximum TJ for the device and can include absolute maximum ratings,
as well as recommended operating condition ratings (Xilinx devices have both). TJ is a
direct function of the power dissipated in the device, the thermal conductivity of the
device’s package, and the PCB it is mounted on, the ambient temperature (TA) inside the
enclosure the board is contained within, and the cooling systems that might include
natural airflow, forced airflow, heatsinks, or even more complex systems.
When designing boards and the enclosures that they are housed in, it is possible to select
the device placement to create air paths and take advantage of natural convection cooling,
and also to optimize the physical locations so that heat sensitive devices are not next to
heat generating devices. However, it is important to also consider challenges presented by
the specific manufacturing or application environment. For example, when dealing with
dirty industrial environments, the objective is to find a thermal management solution that
includes protection against dust, dirt, and oil that a sealed enclosure provides. To this end,
enclosure designs need to strike a balance between protecting components from the
detrimental influences of the outside environment, while also preventing excessive
build-up of heat and humidity inside the enclosure. It is also important to consider the
enclosure’s surface area because the physical size of the enclosure is a primary factor in
determining its ability to dissipate heat to the surrounding environment.
Airflow is a critical factor to consider when evaluating or optimizing the heat dissipation
for devices on a PCB. Airflow provides heat dissipation through convection. It is a key
component for determining the thermal resistance between a device and the surrounding
air (the overall θJA). Even still air in which the heat dissipation is dominated by radiation
typically has some small amounts of airflow created by the natural heat radiating from the
devices inside the PCBs. However, the direct use of forced air as a tool to improve heat
dissipation through convection can be a required component of a system design. In sealed
enclosures, it is possible to use circulating fans to reduce hot spots within the enclosure, as
well as fans mounted directly to heatsinks. For non-sealed enclosures, heat dissipation can
be maximized by using cabinet fans to force airflow through the enclosure in from and out
to the surrounding environment.
Humidity
Humidity is a thermal management component that is frequently overlooked. While the
humidity of the air inside an enclosure can somewhat affect the air’s ability to conduct
heat, this is generally considered an insignificant effect. A bigger challenge related to
humidity is to identify a thermal solution that can regulate both humidity and temperature
inside the enclosure. If left unchecked, excessive humidity can lead to condensation and
subsequent corrosion of both the enclosure and the internal components, as well as
increased heat from corroded connection points.
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Altitude
Because the density of air varies with altitude, so does the efficiency of a heatsink. As can
be seen from Table 3-1, the effects are not insignificant.
Table 3-1:
Altitude Derating Factors
Altitude (Metres)
Altitude (Feet)
Derating Factor
0 (sea level)
0
1.00
1,000
3,000
0.95
1,500
5,000
0.90
2,000
7,000
0.86
3,000
10,000
0.80
3,500
12,000
0.75
The altitude effect should be considered in all cases. While the air temperature of an indoor
environment is normally controlled and is not affected by altitude change, the indoor air
pressure does change with altitude. Because many electronic systems are installed at an
elevated altitude, it is necessary to derate the heatsink performance mainly due to the
lower air density caused by the lower air pressure at higher altitudes. Table 3-1 shows the
performance derating factors for typical heatsinks at high altitudes.
To determine the actual thermal performance of a heatsink at altitudes other than sea level,
the thermal resistance values read off from the performance graphs should be divided by
the derating factor before the values are compared with the required thermal resistance.
For example, a 1°C/W heatsink would become 1.16°C/W at an altitude of 2,000 meters, or
1.25°C/W at 3,000 meters.
Thermal Data Comparison
X-Ref Target - Figure 3-3
40.0
35.0
FG456
FG484
FG556
FT256
FG676
ΘJA (°C/W)
30.0
25.0
20.0
15.0
10.0
5.0
100
200
300
400
500
Die Size (mils)
UG112_c3_07 _040709
Figure 3-3: Effect of Die Size on the Thermal Resistance (θJA) of PBGA Packages
44
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Thermal Management
X-Ref Target - Figure 3-4
30
ΘJA (°C/W)
25
20
15
10
5
0
100
200
400
600
800
Air Flow (linear ft/min)
XC4010E-HQ208
XC4013E-HQ240
XC4010E-PQ208
XC4013E-PQ240
XC4025E-HQ304
UG112_c3_08 _040709
Figure 3-4:
Table 3-2:
Effect of Air Flow on the Thermal Resistance (θJA) of HQ/PQ Packages
Impact of Mounted Board Characteristics on θJA Flip-Chip FF1148
Xilinx 35 x 35 mm
Board Size
FF1148-4VLX100
Layer Count of
Mounted Board
4 in x 4 in Board
10 in x 10 in Board
20 in x 20 in Board
4
10.1 (100%)
9.2 (91%)
N/A
8
8.9 (88%)
6.1 (60%)
5.5 (54%)
12
8.3 (82%)
5.2 (51%)
4.9 (48%)
16
8.0 (79%)
5.0 (50%)
4.6 (46%)
24
N/A
4.7 (47%)
4.5 (44%)
1. JEDEC mount conditions.
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Chapter 3: Thermal Management & Thermal Characterization Methods & Conditions
X-Ref Target - Figure 3-5
20
ΘJA (°C/W)
15
10
5
0
A
B
C
D
E
F
PG299 - Various Enhancements
A Standard Pkg
B Pkg+Finned HS (Passive)
C Pkg+Active Fan (V=0)
D Pkg+Active Fan (V=12)
E Std Pkg +250LFM
F Pkg+Finned HS+ 250LFM
UG112_c3_09 _040709
Figure 3-5:
Effect of Active and Passive Heat Sinks on the Thermal Resistance
(θJA) of PG299 Packages
X-Ref Target - Figure 3-6
35.0
30.0
25.0
)W/C¡(
20.0
Θ
AJ
15.0
10.0
5.0
0.0
0
100
200
300
400
500
600
700
800
Air Flow (linear ft/min)
XC2S300E-FT256
XC3S1500-FG456
XCV1000E-FG680
XC2V6000-FF1152
XC2VP40-FG676
UG112_C3_10 _111208
Figure 3-6:
46
Effect of Air Flow on the Thermal Resistance (θJA) of BGA Packages
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Package Thermal Characterization Methods and Conditions
Package Thermal Characterization Methods and Conditions
Characterization Methods
Xilinx uses several methods to obtain thermal performance characteristics of integrated
circuit packages. The methods include thermal simulation using finite element software
tools, and an indirect electrical method utilizing an isolated diode on a special thermal test
die. This can even be done on a Xilinx FPGA housed in the package of interest or by using
System Monitor to measure die temperature. The majority of the data reported by Xilinx on
previous technologies is based on the indirect diode method, but on newer devices, System
Monitor has been the main characterization method. Simulation tools, calibrated with
actual measurement data, are used to supplement thermal collateral data generation. Most
published compact thermal model data is based on such an effort.
Calibration of Isolated Diode
In the direct electrical method, the forward-voltage drop of an isolated diode residing on a
special test die or the temperature diode of the Xilinx FGPA is calibrated by applying a
constant forcing current (from 0.100 mA to 0.500 mA) over a temperature range of
0°C – 125°C (degrees Celsius). The calibrated packaged device is then mounted on an
appropriate board and placed in the testing environment — e.g., still air or forced
convection. Power (PD) is applied to the device through diffused resistors on the same
thermal die. In the FPGA case, a known self-heating program is loaded and clocked to
generate the monitored power. Usually, between 0.5 watts to 4 watts can be applied.
Higher power (up to 10 watts) is possible, depending on the package. The resulting rise in
junction temperature is monitored with the forward-voltage drop of the precalibrated
diode.
Calibration of System Monitor
The System Monitor calibration is done through the internal settings of the device. A
voltage reference regulator that sets the accuracy level is connected to the System Monitor.
This voltage reference should be set to a level that is above the voltage limit of the System
Monitor, which is set to 3.0 V. Providing a voltage below this limit compromises the
accuracy of the System Monitor.
Simulation Methods
In the simulation effort, finite element (FEA) methodology is used to represent the
packages of interest. The package geometrical details (based on CAD data), as well as the
board stack-up details are captured. Published material properties are used as input to
derive the thermal characteristics based on JEDEC environment and boundary conditions.
Using sample test data, the FEA inputs and assumptions are optimized to minimize
variation between measurement and simulation.
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Chapter 3: Thermal Management & Thermal Characterization Methods & Conditions
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X-Ref Target - Figure 3-7
UG112_C3_01_111208
Figure 3-7: Simulation Tool Outputs:
a) Quarter Model of a Package, b) CTM in JEDEC Enclosure
Once the simulation inputs and assumptions are refined, the FEA method is used to obtain
the thermal characteristics including thermal models of devices in a family using the same
material set and construction details.
Measurement Standards
Previously, Xilinx Thermal lab used the SEMI thermal test methods (#G38-87) and
associated SEMI-based boards (#G42-87) to perform thermal characterization. Most of our
recent measurements and simulations are based on provision of the JEDEC and EIA
Standard — JESD51-n series specifications. It is our assessment that the latter standard
offers some options that are not available in the SEMI method. We will continue to quote
the SEMI-based data (designated by SEMI in the comment column) for older packages
measured in the earlier era, and when we quote new data, they will be designated as JESD
in the comment section.
It is also essential to note that these standard-based measurements give characterization
results that allow packages and conditions to be compared. Like miles per gallon (MPG)
figures quoted on new cars, the numbers should be used with caution. As specific user
environments will not be identical to the conditions used in the characterization, the
numbers quoted might not precisely predict the performance of the package in an
application-specific environment.
For better in-system TJ prediction, Xilinx provides compact thermal models for its devices.
Some of these are available in model libraries for download at the Download Center
http://www.xilinx.com/support/download/index.htm
Models for older products can be requested from ctm_team@xilinx.com.
Definition of Terms
TJ – Junction Temperature, defined as the maximum temperature on the die, expressed
in °C (degrees Celsius).
TA – Ambient Temperature, defined as the temperature of the surrounding
environment, expressed in °C (degrees Celsius).
TC – Temperature of the package taken at a defined location on the body. In most
situations, it is taken at the primary heat flow path on the package and will represent
the hottest part on the package, expressed in °C. See the next item for when TC is taken
at the top.
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Package Thermal Characterization Methods and Conditions
TB – This is the board temperature taken at a predefined location on the board near the
component under test, expressed in °C.
PD – The total device power dissipation, expressed in watts.
TS – This is the heatsink temperature, expressed in °C.
Junction-to-Reference General Setup
X-Ref Target - Figure 3-8
Environment
Const
Current
Source
D
Vf
R
DUT
If
Environment may be:
Still or Forced Air - Ja
Or Circulated FC-40 - Jc, Jl
D => Sensing Diode
R => Diffused Resistors
Resistor
Supply
Vr
Ir
Data Acquisition And
Control Computer
UG112_c3_02 _040709
Figure 3-8:
Thermal Measurement Setup (Schematic for Junction to Reference)
Junction-to-Case Measurement — θJC
Theta-JC (θJC) measures the heat flow resistance between the die surface and the surface of
the package (case). This data is relevant for packages used with external heatsinks. It
assumes that heat is flowing through the top to the exclusion of the others. In the ideal case,
all the heat is forced to escape the package at the path where TC is taken. The lateral heat
flow is not allowed or minimized so that the source of temperature differential will be
attributable to the total known heat input.
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X-Ref Target - Figure 3-9
UG112_C3_03_111208
Figure 3-9:
θJC Measurement Setup
A copper heatsink plate at the top of the package is used in θJC methods to achieve the
forced preferred directional flow.
Prior to 1999, the junction-to-case characterization on some heatsink packages was
accomplished in a 3M Flourinert (FC-40) isothermal circulating fluid stabilized at 25°C.
Current Xilinx data on θJC is simulated using the cold plate approach.
Prior to 2010, The JEDEC standard proposed to use thermocouples to measure TC. The new
JEDEC standard JESD51-14 does not include the measurement of case temperature.
Instead, it describes the transient dual interface (TDI) test method for the measurement of
the junction-to-case thermal resistance.
From the previous JEDEC standards, with applied power (PD) and under stabilized
conditions, case temperature (TC) is measured with a low gauge thermocouple (36-40
AWG) at the primary heat-flow path of the particular package. Junction temperature (TJ) is
calculated from the diode forward-voltage drop from the initial stable condition before
power is applied:
θJC = (TJ – TC)/PD
where the terms are as defined above. A poorly defined θJC condition usually leads to
lower numbers being reported. In such cases, the recorded temperature difference (TJ-TC)
is the result of having a fraction of the power going through the path. However, in the
calculation, the full power is used.
Because the necessary thermocouple measurement of the case temperature is prone to
errors, these results are often not sufficiently reproducible. Some of the errors that could
occur are:
50
•
A temperature distribution at the package case while the thermocouple measures the
temperature at its contact point to the case. This might not be the maximum case
temperature.
•
A potentially low case temperature reading because the thermocouple beads are often
not sufficiently insulated against the cold plate and could therefore be cooled from the
wire and cold plate side.
•
The application of considerable clamping pressure to press the semiconductor device
against the heatsink, which closes delaminations.
•
The drill hole for the thermocouple in the heatsink influencing the thermocouple
measurement. This influence increases with smaller devices.
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Package Thermal Characterization Methods and Conditions
The new JEDEC standard JESD51-14 specifies the TDI measurement method of the
junction-to-case thermal resistance without a case temperature measurement. The thermal
impedance or Zth-function ZθJC(t) of a semiconductor device that is heated with constant
power (PH) starting at time t = 0 while its case surface is connected to a heatsink is defined
as:
ZθJC(t) = (TJ(t) – TJ(t = 0))/PH
Thus, the thermal impedance equals the time-dependent change of the junction
temperature TJ(t) divided by the heating power. If the cooling condition at the package
case is changed, this should have no influence on the thermal impedance until the
temperature starts to increase at the package case where the contact to the heatsink is
located. However, a measurement with a different contact resistance changes the total
thermal resistance at steady state and therefore separates the impedance curves of different
measurements starting from the point where the external contact resistance begins, which
can be identified as the package case interface.
Two thermal impedance measurements are made with different contact resistances for
cooling the package case surface connected to the heatsink to identify this surface in
transient measurements. The cumulative thermal resistance at the separation point of these
two measurements is defined as RθJC (θJC).
Junction-to-Ambient Measurement — θJA
X-Ref Target - Figure 3-10
UG112_C3_04_111208
Figure 3-10:
θJA Measurement Setup
SEMI method: Some of the data reported are based on the SEMI standard methods and
associated board standards. θJA data reported as based on SEMI were measured on
FR4-based PC boards measuring 4.5 in x 6.0 in x .0625 in (114.3 mm x 152.4 mm x 1.6 mm)
with edge connectors. Several versions are available to handle various surface mount
(SMT) devices. They are, however, grouped into two main types. Type I board (the
equivalent of the JEDEC low-conductivity board) is single layer with two signal planes
(one on each surface) and no internal Power/GND planes. This is the 2L/0P or 2S/0P
board and the trace density on this board is less than 10% per side. The type II board (the
equivalent of the JEDEC 2S/2P board) has two internal copper planes — one power and
one ground. These planes are in addition to the two signal trace layers on both surfaces.
This is the 4L/2P (four-layer, also referred to as 2S/2P) board.
JEDEC measurements: Packages are measured in a one foot-cube enclosure based on
JEDS51-2. Test boards are fashioned per test board specification JESD51-3 and JESD51-7.
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The board sizes depend on the package and are typically 76.2 mm x 114.3 mm x 1.6 mm or
101.6 mm x 114.3 mm x 1.6 mm. These come in low-conductivity as well as highconductivity versions.
Thermal resistance data can be taken with the package mounted in a socket or with the
package mounted directly on traces on the board. Socket measurements typically use the
2S/0P or low-conductivity boards. SMT devices, on the other hand, can use either board.
Published data always reflect the board and mount conditions used (ref 2S/0P or 4L/2P).
The board with the device under test (DUT) is mounted in the test enclosure and data is
taken at the prevailing temperature and pressure conditions — between 20°C and 30°C
ambient (TA). Appropriate power is used, depending on the anticipated thermal resistance
of the package. Applied power, signal monitoring — including the enclosure (ambient)
temperatures are noted. The junction to ambient thermal resistance is calculated as follows:
θJA = (TJ – TA)/PD
In the case of airflow measurement, this is done in a special airflow enclosure section of a
suction-type low-velocity wind tunnel. Airflow velocities from 0–1000 linear feet per
minute (LFM), i.e., 0–5.08 m/s, are used with very low turbulence. The controlling
specification is JESD51-6. Airflow measurements use similar boards as θJA with air
conditions noted with hot wire anemometer.
Thermal Resistance: Junction-to-Board — θJB
This is defined as:
θJB = (TJ – TB)/PD
where TB is the board temperature at steady state measured at specified location on the
board. PD is the actual power in watts that produces the change in temperature.
TB is monitored on a board with a 40-gauge thermocouple at specific location in the
proximity of the package leads or balls. As an example, for BGA package, the
thermocouple is attached to a trace midway along the side of the package with the
attachment point within 1 mm of the package body.
Like θJC, θJB depends on constrained flow in a preferred direction. In actual measurement
or simulations the heat flow is forced to go preferably through the board by excluding
other paths with insulation. The measurement conditions are not likely to be reproduced in
a real application.
Data Acquisition and Package Thermal Database
Data for a package type is gathered for various die sizes, power levels, cooling modes (air
flow and sometimes heatsink effects) with a Data Acquisition and Control System (DAS).
The system controls and conditions the power supplies and other ancillary equipment for
hands-free data taking. A package is completely characterized with respect to the major
variables that influence the thermal resistance. A database is generated for the package.
From the database, thermal resistance data is interpolated as typical values for individual
Xilinx devices that are assembled in the characterized package.
Figure 3-11 is a screen shot of the Package Thermal Data Query for Xilinx components. This
tool is located on Xilinx.com at http://www.xilinx.com/cgi-bin/thermal/thermal.pl.
Device-specific data from the thermal database can be obtained from this web site. The
data from this query is specific to the devices of the individual packages.
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Application of Thermal Resistance Data
X-Ref Target - Figure 3-11
UG112_C3_05_111208
Figure 3-11:
Package Thermal Data Query for Device-Specific Data
Thermal data consistent with the above query results can also be found in product-specific
user guides for newer device families. Below are three examples:
•
UG365, Virtex-6 FPGA Packaging and Pinout Specifications
•
UG385, Spartan-6 FPGA Packaging and Pinouts Product Specification
•
UG475, 7 Series FPGAs Packaging and Pinout Advance Specification
The linked query provides thermal data for all released and active Xilinx products. The
supporting data table is updated periodically to include newer products and prune
inactive products. Data from the Query replaces the generic package based (summarized
by package type) thermal data that used to be tabulated in previous versions of this user
guide.
Application of Thermal Resistance Data
Thermal resistance data is used to gauge the IC package thermal performance. There are
several ways to express the thermal resistance between two points. The following are a few
of them:
•
θJA = Junction to ambient thermal resistance (°C/W).
•
θJC = Junction to case thermal resistance (°C/W)
•
θJB = Junction to board thermal resistance (°C/W)
•
θCA = Case to ambient thermal resistance (°C/W)
•
θCS = Case to heatsink thermal resistance (°C/W)
•
θSA = Heatsink to ambient thermal resistance (°C/W)
Other thermal parameters include
•
•
ΨJC = Junction to board thermal characteristic parameter (°C/W)
ΨJT = Junction to package thermal characteristic parameter (°C/W)
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Chapter 3: Thermal Management & Thermal Characterization Methods & Conditions
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θJC measures the internal package resistance to heat conduction from the die surface,
through the die mount material to the package exterior. θJC strongly depends on the
package material’s heat conductivity and geometrical considerations.
θJA measures the total package thermal resistance including θJC. θJA depends on the
package material properties and such external conditions as convective efficiency and
board mount conditions. For example, a package mounted on a socket can have a θJA value
20% higher than the same package mounted on a four-layer board with power and ground
planes.
In general, θMN expresses the thermal resistance between points M and N. In the above
expression, the source and end points are indicated.
In situations where a heatsink is used with a heatsink compound, thermal resistance of
heatsink is referenced as θSA (sink-to-ambient) and the attached material as θCS (case-toheatsink). These thermal resistances can be added. For example, θJA = θJC + θCS + θSA is an
expression used in heatsink situations with interface material resistance θCS.
Thermal Data Usage Examples
Note: Actual thermal resistance in a system can be impacted by several user conditions. In the
examples that follow, it should be noted that unique user conditions will impact predictions and
estimates. Such user conditions have not been taken into consideration in the examples. One of the
main influences on thermal resistance is board conditions. Table 3-2 shows a table that illustrates
how the thermal resistance of a flip-chip package (FF1148) is influenced by the board characteristics.
The package with a high-conductivity JEDEC board-based measured θJAof 10.1°C/watt can exhibit
almost a 50% reduction in θJA if a 10 in square board with 16 copper layers is used. Other user
boundary conditions can also affect the effective thermal resistance in a system. Figure 3-4 depicts
the impact when airflow is applied to packages. In general, as users work their way through these
examples, external influences have not been taken into account in the estimates.
The following are some data requirements for using thermal resistance in an application.
•
•
Xilinx-supplied data:
•
Thermal data for θJA and θJCis available at:
http://www.xilinx.com/cgi-bin/thermal/thermal.pl
•
Thermal data for is θSA is provided by heatsink supplier.
Items that the user might need to supply:
•
•
TJmax
-
This can go as high as the absolute maximum temperature for the package —
typically 125°C to 135°C for plastic
-
Note that components are tested to meet the speed file specifications at the
temperatures associated with them – 85°C for C grade, and higher I and M
grades. Running the parts at a higher TJ than specified might not meet the
specifications.
-
The user will have to pick a TJmax for reliability considerations, and plan the
thermal budget around that
TA: Ambient temperature in a system
-
•
54
This is also another variable that the user can control. Typically, this is set to
approximately 45°C to 55°C. It could also be as high as 75°C or 100°C, based
on the application.
Items usually estimated:
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Thermal Data Usage Examples
•
Power dissipation. The thermal equation can be used to determine a power range
that can satisfy some given conditions
•
Also, if power is known, TJmax can be calculated from the equations
•
If the temperature on the top of a bare part is well monitored in a system (not the
way θJC is measured), the thermal parameter ΨJT can be used to get junction
temperature
•
Similarly, a well monitored board temperature can be used to predict junction
with the ΨJC parameter
In non-heatsink situations, the following inequality formula should hold:
TJmax > θJA x PD + TA
The two examples below illustrate the use of the above inequality formula. Specific
packages are used in the examples, but any package—Quad, BGA, FGs, or even flip-chip
based BGs—are applicable.
Example 1
The manufacturer’s goal is to achieve TJmax < 85°C
A module is designed for a TA = 45°C max.
An XCV300 in a FG456 has a θJA = 16.5°C/watt. θJC = 2.0°C/watt.
Given an XCV300 with a logic design with a rated power PD of 2.0 watts.
With this information, the maximum die temperature can be calculated as:
TJ = 45 + (16.5 x 2.0) = 78°C.
The system manufacturer’s goal of TJ < 85°C is met in this case.
Example 2
A module has a TA = 55°C max.
The Xilinx FPGA XCV400E is in a PQ240 package.
A logic design in XCV400E is determined to be 2.70 watts. The module manufacturer’s
goal is to achieve TJ (max.) < 100°C.
Table 3-3 shows the package and thermal enhancement combinations required to meet the
goal of TJ < 100°C.
Table 3-3:
Thermal Resistance for XCV400E in PQ240 Package
Device
Name
Package
θJA
still air
θJA
(250 LFM)
θJA
(500 LFM)
θJA
(750 LFM)
θJC
Comments
XCV400E
PQ240
17.9
13.2
11.7
10.8
3.2
Cu, SMT 2L/0P
For all solutions, the junction temperature is calculated as: TJ = Power x θJA + TA. All
solutions meet the module requirement of less than 100°C, with the exception of the PQ240
package in still air. In general, depending on ambient and board temperatures conditions,
and most importantly the total power dissipation, thermal enhancements such as forced
air cooling, heat sinking, etc., might be necessary to meet the TJ (max) conditions set.
Possible solutions to meet the module requirements of 100°C:
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Chapter 3: Thermal Management & Thermal Characterization Methods & Conditions
1.
Using the standard PQ240: TJ = 55 + (17.9 x 2.70) = 103.33°C.
2.
Using standard PQ240 with 250 LFM forced air: TJ = 55 + (13.2 x 2.70) = 90.64°C.
Heatsink Calculation
Example illustrating the use of heatsink:
Device is XCV1000E-FG680
There is a need for external thermal enhancements.
Data supplied from Xilinx on XCV1000E-FG680 is shown in Table 3-4
Table 3-4:
Data Supplied from Xilinx on XCV1000E-FG680
Package Code
θJA
still air
θJC °C/W
θJA
(250 LFM)
θJA
(500 LFM)
θJA
(750 LFM)
FG680
10.6
0.9
7.5
6.1
5.6
•
•
•
•
Customer requirements
•
Ta = 50°C
•
Power = 8.0 watts (user’s estimate)
•
User does not want to exceed TJmax of 100°C
Determination with base Still Air data:
•
TJ = TA + (θJA) x P
•
TJ = 50 + 8 x 10.6 = 134.8°C
•
Unacceptable! θJA in still air will not work because the 134.8°C is beyond the
stated goal of 100°C or less.
Calculating acceptable thermal resistance:
•
Determine what θJA will be required to stay below 100°C with the 8 watts power?
•
Thermal budget = (TJ – TA) = 50°C.
•
θJA = (50)/8 = 6.25°C/watt.
•
The package and any enhancement to it need to have an effective thermal
resistance from the junction to ambient less than 6.25°C/watt. That becomes the
goal any thermal solution ought to meet.
Solution Options:
•
The bare package with 500 LFM (2.54 meters/s) of air will give θJA = 6.1°C/watt.
(from the data table above). That will be a workable option, if that much airflow
will be tolerable.
•
Heatsink calculation. With a heatsink, heat will now pass through the package
(θJC) then through an interface material (θCS), and from the heatsink to ambient
(θSA). This can be expressed as follows:
-
θJA ≥ θJC + θCS + θSA
-
6.25 ≥ 0.9+0.1+ θSA
where
56
-
6.25°C/watt is the condition to be met
-
0.9°C/watt — θJC from data
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Additional Power Management Options
-
0.1°C/watt — θCS from interface material data
•
From above, θSA ≤ 5.25°C/watt
•
The objective will be to look for a heatsink with θSA < 5.25°C/watt that meets the
physical constraints in the system
•
Passive heatsink with some air flow — 250 LFM (1.25 m/s) can be selected
•
Active heatsinks — it might be possible to use small low-profile heatsinks with
DC fans
Additional Power Management Options
The variety of applications that the FPGA devices are used in makes it a challenge to
anticipate the power requirements and thus the thermal management needs a particular
user might have. While Xilinx programmable devices might not be the dominating power
consumers in some systems, it is conceivable that high-gate-count FPGA devices will be
exercised sufficiently to generate considerable heat.
X-Ref Target - Figure 3-12
UG112_C3_11_111208
Figure 3-12:
Enhanced BGA with Low Profile Retainer Type Passive Heatsinks
In general, high-I/O and high-gate-count devices have the potential of being clocked to
produce high wattage. Being aware of this potential in power needs, the package offering
for these devices includes medium- and high-power-capable package options. This allows
a system designer to further enhance these high-end BGA packages to handle more power.
When the actual or estimated power dissipation appears to be more than the specification
of the bare package, some thermal management options can be considered. The
accompanying Thermal management chart illustrates the incremental nature of the
recommendations — ranging from simple airflow to schemes that can include passive
heatsinks and active heatsinks.
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X-Ref Target - Figure 3-13
Low end
1Ð6W
Bare package with
moderate airflow
8Ð12¡C/W.
Bare package
can be used with
moderate airflow within
a system.
Mid range
4Ð10W
Passive heat sink
with moderate
airflow 5Ð10¡C/W.
Package used with
various forms of
passive heat sinks and
heat spreader techniques.
High end
8Ð25W
Active heat sink
2Ð3¡C/W or better.
Package used with
active heat sinks
TEC and board level
heat spreader techniques.
UG112_C3_12 _111208
Figure 3-13:
Thermal Management — Incremental Options
The use of heat pipes, and even liquid-cooled heat plates, can be considered in the extreme
for some of these packages. Details on the engineering designs and analysis of some of
these suggested considerations might require the help of thermal management
consultants. The references listed at the end of this section can provide heatsink solutions
for industry-standard packages.
Some of the options available in thermal management can include the following:
58
•
Most high-gate-count Xilinx devices come in more than two package types. Explore
thermally enhanced package options available for devices. The quad packages and
some BGA packages have heat enhancement options. Typically, 25% to 40%
improvement in thermal performance can be expected from these heatsink-embedded
packages.
•
In a system design, natural convection can be enhanced with venting in the system
enclosure. This will effectively lower the Ta and increase available thermal budget for
moderate power dissipation.
•
The use of forced-air fans is the next step beyond natural convection, and it can be an
effective way to improve thermal performance. As seen on the graphs and the
calculations above, forced air (200-300 LFM) can reduce junction-to-ambient thermal
resistance by up to 30%.
•
For moderate power dissipation, the use of passive heatsinks and heat spreaders
attached with thermally conductive double-sided tapes or retainers can offer quick
solutions.
•
The use of lightweight finned external passive heatsinks can be effective for
dissipating up to 8 watts on some packages. If implemented with forced air as well,
the benefit can be a 40% to 50% reduction as illustrated in the XCV1000E-FG680
example. The more efficient external heatsinks tend to be tall and heavy. When using a
bulky heatsink, it is advisable to use spring-loaded pins or clips to reduce heatsinkinduced stress on the solder joints of the component as these pins or clips help
transfer the mounting stress to the circuit board. The diagonals of some of these
heatsinks can be designed with extensions to allow direct connection to the board (see
Figure 3-14).
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Additional Power Management Options
X-Ref Target - Figure 3-14
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Figure 3-14:
Heatsink with Clips
•
Exposed metal heatsink packages: All thermally enhanced BGAs with dies facing
down (including these package codes - BG352, BG432, BG560, FG680, FG860, and
flip-chip BGAs) are offered with an exposed metal heatsink at the top. These are
considered high-end thermal packages and they lend themselves to the application of
external heatsinks (passive or active) for further heat removal efficiency. Again,
precautions should be taken to prevent component damage when a bulky heatsink is
attached.
•
Active heatsinks can include a simple heatsink incorporating a mini fan or even
Peltier Thermoelectric Coolers (TECs) with a fan to carry away any heat generated.
Any consideration of applying TEC in heat management should include consultation
with experts in using the devices, as these devices can be reversed and this might
damage components. Also, condensation can be an issue.
•
Molded packages (FG456, FG676, FG1156, PQs, etc.) without exposed metal at the top
also can use these heatsinks at the top for further heat reduction. These BGA packages
are similar in construction to those used in graphic cards in PC applications, and
heatsinks used for those applications can easily be used for these packages as well. In
this case, the θJC resistance will be the limiting consideration.
X-Ref Target - Figure 3-15
UG112_C3_14_111208
Figure 3-15:
•
Example of Active Heatsink for BGA (Malico)
Outside the package itself, the board on which the package sits can have a significant
impact on thermal performance. Board designs can be implemented to take advantage
of a board’s ability to spread heat. Heat flows to the outside of a package and is sunk
into the board to be conducted away – through heatpipes or by normal convection.
The effect of the board will be dependent on the size and how it conducts heat. Board
size, the level of copper traces on it, and the number of buried copper planes all lower
the θJA thermal resistance for a package mounted on it. Some of the heatsink packages
– like HQ, with the exposed heatsink on the board side – can be glued to the board
with thermal compound to enhance heat removal into the board. BGA packages with
full matrix of balls can be cooled with this scheme. Users need to be aware that a
direct heat path to the board from a component also exposes the component to the
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Chapter 3: Thermal Management & Thermal Characterization Methods & Conditions
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effect of other heat sources, particularly if the board is not cooled effectively. An
otherwise cooler component can be heated by other heat-contributing components on
the board.
See “Web Sites for Heatsink Sources” for lists of Web sites that offer more information on
heat management and sources for interface material.
System Simulation Support
For more accurate in-system TJ prediction, Xilinx can provide Compact Thermal Models
(CTMs) to be used in system thermal simulations. The figure of merit thermal data Xilinx
provides can be used to select packages and perform comparative thermal analysis and
some preliminary TJ predictions. However, when the thermal margins are very tight, or the
component is integrated with other heat sources in a system, a full system thermal analysis
might be required. These CTMs are provided to reduce the computational complexity.
Our CTMs are based on the Delphi approach that JEDEC has proposed. Since the JEDEC
neutral (XML) format proposal has not been adopted yet, the Delphi approach is used to
generate these files and the data saved in the native and proprietary file formats of the
targeted CFD tools, rather than follow a neutral file. We are closely following JC15-1
developments and hope to offer the neutral file format when it is ready and adopted by the
CFD tool vendors.
In the meantime, these CTMs are based on the Delphi (dotcomp optimization) approach
for specific tools. These tools occupied the first two places in our pre-introduction
customer survey. The libraries are available in Flotherm (pdml) format; V5.1 and above
and Icepack (ver. 4.2 and above) format.
The Virtex-4 device, and newer products are supported. CTM data can be downloaded
from the Xilinx Support Download Center
http://www.xilinx.com/support/download/index.htm.
Models for older products can be requested from: ctm_team@xilinx.com.
The plan is to support models for other CFD tools through the neutral format approach.
Before the neutral file format is adopted, there might be limited support of Xilinx
formatted ASCII-based file defining nodes and listing the associated resistances between
notes for manual entry into various other tools that support CTM usage; requests of this
type should be directed to: ctm_team@xilinx.com.
References
These references provide additional information to support the material in this chapter:
http://www.jedec.org/standards-documents/results/jesd51
http://www.irf.com/technical-info/appnotes/an-1057.pdf
http://www.aavidthermalloy.com/technical/papers/pdfs/select.pdf
http://goliath.ecnext.com/coms2/gi_0199-832204/Approaches-to-thermalmanagement-enclosure.html
http://www2.emersonprocess.com/siteadmincenter/PM%20DeltaV%20Documents/W
hitepapers/WP_Heat_Airflow_Encl.pdf
http://www.midwestequipment.com/docs/enclosureratings.pdf
http://www.midwestequipment.com/docs/enclosurenemaratings.pdf
60
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References
http://www.midwestequipment.com/docs/heatdissipation.pdf
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Chapter 4
Package Electrical Characteristics
Introduction
As data rates increase and signal rise times become shorter, the effects of package parasitics
are becoming increasingly significant as the hardware engineers model their circuits.
Discontinuities that might have had minimal impact on circuit performance in past
generations of components are now of paramount importance as designers strive to
achieve higher performance in their systems.
The IC package forms an interconnect system just like traces on a printed circuit board
(PCB) or conductors in connectors. When a designer simulates the signaling performance
from a driver to a receiver, all the interconnect parasitics in the path, including the package,
must be considered in order to achieve simulation results that represent the entire system's
performance.
Current Xilinx packages are constructed with either wirebond or flip chip interconnect
technology. Some components use simpler leadframe-based packages, while others use
laminate-based packages with multilayer construction. The choice of package matches the
performance and marketing objectives sought for the device family. In multilayer
packages, innovative pin-out selections and creative design techniques are used in a codesign effort to optimize package performance and to prevent the package from being a
limiting factor for the device. For these high performance FPGA packages, Xilinx also
provides package models that allow the user to take package parasites into account to
accurately model the component's performance prior to committing to hardware.
This chapter focuses on defining certain critical concepts associated with electrical
characterization of packages. It is also intended to provide relevant theoretical review of
electrical issues and concepts as they relate to the characterization effort. The document
provides descriptions of the methods utilized to generate the parasitic data and derive
appropriate models for their use. Some data examples, ranging from simple tabulated RLC
to s-parameter models, are given to illustrate the range of electrical data that are available
for the packages.
Terminology - Definitions and Reviews
There are a number of key concepts that should be understood in order to appreciate how
packages affect the signals transiting through them, as well as how package parasitics are
modeled or measured in the lab.
Any conductor system is characterized by some basic electrical parameters which are
dependent of the physical design of the system, a package is no exception. The basic
electrical parameters associated with packages are resistance, inductance, conductance,
and capacitance. These are commonly referred to as RLGC parameters. The parameters
will be defined in the following subsections. The section also explains several other metrics
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Chapter 4: Package Electrical Characteristics
which are derived from RLGC parameter values. Finally, more advanced concepts such as
s-parameters, crosstalk, and SSN will be covered.
Resistance (R)
Resistance is one of the basic electrical parameters that commonly defines the series loss in
a conductor. Electrically, Ohm's law defines resistance as the ratio of voltage to current in a
conductor:
E
R = --I
Equation 4-1
Where:
R = electrical resistance (Ω)
E = voltage (V)
I = current (A)
Physically, resistance is defined as:
ρ l⋅
R = --------A
Equation 4-2
Where:
R = resistance (Ω)
ρ = resistivity of the conductor material
l = length of conductor
A = cross-sectional area of the conductor
The physical equation above is valid at DC where the current flows through the whole
cross sectional area of the conductor. At higher frequencies, where skin effect becomes
important, the cross sectional area is decreased and consequently the resistance increases
at higher frequencies. The amount that the cross sectional area is decreased is highly
geometry-dependent and is also a function of the proximity of the conductor to other
nearby current carrying conductors. Typically, the reported R component of the package
resistances are given at DC for nets intended to operate below about 1 GHz. Higher
frequency nets, such as those associated with transceivers (MGTs and GTPs), are
characterized with frequency-dependent losses. These frequency-dependent losses are
best determined with 2D or 3D extractor software.
The skin depth (which is the depth of electric and magnetic field penetration) of a
conductor is given by:
ρ
δ = 50μ --f
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Equation 4-3
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Terminology - Definitions and Reviews
Where:
δ = skin depth in microns (μ)
ρ = conductor resistivity (μΩ - cm)
ƒ = frequency (MHz)
As a point of reference, δ is about 20 microns at 10 MHz frequency if the conductor is
copper. Note that δ decreases with 1 (⁄ f ) , so at a frequency of 4ƒ, the skin depth would be
one half the value that it was at a frequency of ƒ.
Inductance (L)
Inductance is one of the fundamental properties of any electrical conductor. Any current
carrying conductor is surrounded by lines of magnetic flux. These lines are circular loops
which encircle the current carrying conductor. The number of loops in any instance is
concentrated near the conductor with the density of the lines decreasing as the distance
from the conductor increases. A basic relationship for inductance is:
N
L = ---I
Equation 4-4
Where:
L = inductance in (H)
N = number of magnetic lines encircling the conductor in (Wb)
I = current (A)
Inductance is geometry-dependent.
Whether a conductor has 1 Amp or 100 Amps flowing through it, the inductance is the
same since the ratio remains constant. The presence of dielectric material near the
conductor will not alter the inductance. The presence of ferro-magnetic material with
permeability greater than 1 will affect the inductance.
When we discuss inductance, the terms loop inductance, partial inductance, self inductance,
and mutual inductance are some of the items that come up. These are explained below:
•
Loop inductance is the inductance of a complete current carrying loop. It is a unique
value dependent on the loop geometry. The larger the area encompassed by the loop,
the larger the loop inductance will be.
•
A partial inductance is the inductance contributed by a portion of the loop. It is not a
unique value.
•
Self Inductance - When one refers to the inductance of a conductor the reference is
usually meant to imply the self inductance. This is the ratio of lines of magnetic flux to
current where the lines encircle their own conductor.
•
The concept of mutual inductance comes into play when one considers lines of
magnetic flux generated by a current carrying conductor that also encircle (or couple
to) another conductor. These lines of flux will cause a voltage to be generated into the
coupled conductor.
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Chapter 4: Package Electrical Characteristics
Some Inductance Expressions
Closed form analytical equations to calculate inductance do exist for simple geometries. In
a complex system like a package, such simplified closed form expressions are hard to come
by; approximations abound with varying degrees of accuracy. To accurately determine the
partial inductance of conductor geometry in a package, the use of a good 2D or 3D
electromagnetic extractor program is recommended. Below are some closed-form
formulas that are reasonably accurate for geometries commonly found in packages.
•
Partial self inductance of a round wire (with ground at infinity):
2 ⋅d
3
L wire = 5 ⋅d ⋅ ln ---------- – -- r 4
Equation 4-5
Where:
Lwire = inductance (nH)
d = wire length (inches)
r = wire radius (inches)
•
Partial self inductance of a round wire over a metal plane:
2 ⋅h
L wire = 5 ⋅d ⋅ ln -------- r
Equation 4-6
Where:
Lwire = inductance (nH)
d = wire length (inches)
h = height of wire above the plane (inches)
r = wire radius (inches)
•
Partial self inductance of a rectangular conductor (with ground at infinity):
2 ⋅d
1
L = 5 ⋅d ⋅ ln ----------------- + --(w + t)
2
Equation 4-7
Where:
L = inductance (nH)
d = conductor length (inches)
w = conductor width (inches)
t = thickness of conductor (inches)
•
Partial self inductance of a rectangular conductor - like a trace or perhaps a leadframe
lead over a metal plane:
8 h⋅
w+t
L = 5 ⋅d ⋅ ln ----------------- + -----------(w + t)
4 h⋅
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Equation 4-8
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Terminology - Definitions and Reviews
Where:
L = Inductance (nH)
d = conductor length (inches)
h = height of conductor above the plane (inches)
w = conductor width (inches)
t = thickness of conductor (inches)
These relationships are compiled from publications by several authors(1,2,3) including Eric
Bogatin, and Brian Young and Grover.
Capacitance (C)
The capacitance of a conductor is dependent on the area of the conductor, the distance the
conductor is placed from some reference conductor and the dielectric constant of the
dielectric material. An expression for simple parallel plate capacitance is commonly
expressed as:
ε o ⋅A
C = -------------t
Equation 4-9
Where:
C = capacitance
ε0 = permittivity of free space
A = conductor area
t = dielectric thickness
If the dielectric material between the conductors is some material other than air or vacuum
the equation is modified to include the relative dielectric constant εr as follows:
ε o ⋅ε r ⋅ A
C = ----------------------t
Equation 4-10
Where:
C = capacitance
ε0 = permittivity of free space
A = conductor area
t = dielectric thickness
εo is equal to 0.0885 pF/cm or equivalently 0.225 pF/inch. The capacitance of a conductor
increases if the size of the conductor increases, the thickness of the dielectric decreases, or
the dielectric constant of the dielectric material increases. While this expression is not
directly applicable to the geometries of package transmission lines and planes, it does
illustrate the basic relationships between capacitance and the dielectric constant,
conductor area and dielectric thickness.
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Chapter 4: Package Electrical Characteristics
Other ways of expressing capacitance:
•
Capacitance is also defined as the ratio of charge to voltage that can be stored between
a pair of conductors:
Q
C = ---V
Equation 4-11
Where:
C = capacitance (Farads)
Q = charge (Coulombs)
V = voltage (volts)
•
Transmission lines commonly have their capacitance specified as a per-unit-length
(PUL) value such thatC total = C PUL × length:
•
Self capacitance is the capacitance of a conductor to ground (C1 would be the
capacitance of conductor 1 to ground). Mutual capacitance is the capacitance between
two conductors (C12 would be the capacitance between conductor 1 and conductor 2).
Examples of closed form expressions for capacitance:
For complex structure a field solver is the preferred method of determining the capacitance
of a conductor, however for a couple simple structures the following equations can provide
answers accurate to within about 5%.
•
Wire over a ground:
1 ⋅ 4 ⋅ εeff
C = ---------------------2h
ln ------
r
(pF/inch)
Equation 4-12
ε r + 1 ε r – 1
1
ε e f f = ------------- + -------------- ---------------------------
2
2
10h
Equation 4-13
1 + ---------
r
Where:
εr = relative dielectric constant of the dielectric
h = distance from the ground plane to the center of the wire (inches)
r = is the radius of the wire (inches)
•
Capacitance between two parallel wires:
1 ⋅ 4 ⋅ εr
C = ------------------2
s
ln -----
ab
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(pF/inch)
Equation 4-14
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Terminology - Definitions and Reviews
where:
s = distance between wire centers
a = diameter of first wire
b = diameter of second wire
Conductance (G)
The conductance parameter (G) is related to the losses in the insulating substrate material.
This is a frequency dependent parameter that scales directly with frequency. Most all
substrate materials utilized in package construction have very low losses at low
frequencies (less than 1 GHz). As a result, the conductance (a parallel loss) is very low and
is usually ignored when modeling SelectIO™ lines. The dielectric loss does become
significant at the higher frequencies where high speed nets are utilized. These lines are
typically characterized by s-parameters as opposed to RLGC parameters.
Impedance (Z)
The impedance of a transmission line can be calculated readily if the line’s inductance and
capacitance are known. The relevant equation is:
L
Z = ---C
Equation 4-15
Where:
Z = impedance in (Ω)
L = the line’s per-unit-length inductance (H)
C = the line’s per-unit-length capacitance (F)
When circuit elements interface with each other (for example, package trace and PCB trace,
or PCB trace and termination), any mismatch in their impedances at their boundaries will
result in reflections. The higher the mismatched magnitude, the greater the associated
reflection, hence distortion in the signal traversing the mismatched interface. For this
reason, it makes sense to minimize the impedance mismatches in a system.
Time Delay (Td)
The time delay for transmission line (i.e., conductor) in a package is calculated by the
equation [ T d = L ⋅C ] where the delay is in seconds, the capacitance is in Farads and the
inductance is in Henrys. Knowledge of a line's delay contribution is needed in determining
timing closure. Time delay can also be determined if one knows the relative dielectric
constant εr of the substrate material associated with a transmission line. A transmission
line with air as a dielectric propagates signals at the speed of light (c = 3 x 1010 cm/second)
or about 5.9 inches/psec. In a material with a relative dielectric of εr the velocity of
propagation is given by the expression:
c
v = ----------
εr
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Equation 4-16
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Chapter 4: Package Electrical Characteristics
Where:
v = velocity in the material
c = speed of light
εr = relative dielectric constant of the dielectric material
For example, typical FR4 material has a dielectric constant of about 4, so the velocity of
propagation in a transmission line utilizing FR4 as the dielectric material will be c/2 (one
half the speed of light) or 2.95 inches/psec. The time delay of a transmission line is simply
the reciprocal of the velocity. In the case of FR4, the Td is about 169.5 inches/psec.
Additionally, the time of flight (Tof) in a transmission line is simply the line's length times
Td. This Tof number is what would be used in timing closure calculations.
For large size laminate and ceramic-based packages where Td is likely to be over 50 ps, the
delay data is provided. This Td is derived from the LC data if the per-pin data is available.
In some cases, Td is derived directly from the trace length data of the relevant package
design.
Crosstalk
Coupling (usually unwanted) from one conductor to another is termed “Crosstalk”. The
line generating the signal is called the “aggressor” and the line into which the signal is
coupled is termed the “victim.” Generally, this coupled signal is considered noise and is
undesired. There are two mechanisms involved in this unwanted coupling between
circuits; capacitive and inductive. Capacitive coupling occurs when the victim net is
affected by the electric-field lines generated by the aggressor. Inductive coupling is caused
by the magnetic-field lines generated by the aggressor inducing a voltage in the victim
circuit. Physically, the two items that affect coupling are the distance between the two
circuits and the length of the coupling regions. The most effective way to minimize
crosstalk is to increase the spacing between the aggressor and victim nets.
Crosstalk is broadly divided into “near-end” and “far-end” crosstalk. Near-end crosstalk is
always positive since the currents generated by the inductive and capacitive coupling
components add and sum at the near end. Far-end crosstalk can be either negative or
positive. If the magnitude of the inductively coupled component is larger than the
capacitive coupled component then the difference of the currents at the far end is positive,
however, if the capacitive component predominates then the far end effect will be a
negative voltage. Also note, that the magnitude of the near-end crosstalk is insensitive to
the coupled length of the aggressor and victim nets. However, the far-end crosstalk will
increase with increasing coupled length until a saturation point is reached.
The exact mathematical relationships for calculating crosstalk can be complex and vary in
detail depending on whether the nets are terminated or open circuited and whether
near-end or far-end crosstalk are considered.
The following expressions, taken from High Speed Digital System Design4, illustrate a couple
of cases where both the aggressor and victim nets are terminated at both the near and
far-end (quite often the case): The above reference reviews other terminated cases as well.
•
70
Far-end Crosstalk
C ij
ij
L
------ – ------------------
L i C i + C ij
-----------------------------------------4
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Equation 4-17
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•
Near-end Crosstalk
C ij
ij
L
------ + ------------------
L i C i + C ij
------------------------------------------2
Equation 4-18
Where:
Ci and Li are the self capacitance and inductances of the victim lines, respectively.
Cij and Lij are the mutual capacitances and inductances respectively between nets i and
j.
Ground Bounce
Ground bounce is the voltage difference between any two grounds (typically between an
IC and circuit board ground) induced by simultaneously switching current through bond
wire, lead, or other interconnect inductance. When IC outputs change state, large current
spikes result from charging or discharging the load capacitance. The larger the load
capacitance and faster the rise/fall times, the larger the current spikes are: I = C * dv/dt.
Current spikes through the IC pin and bondwire induce a voltage drop across the leads
and bondwires: V = L * di/dt. The result is a momentary voltage difference between the
internal IC ground and system ground, which show up as voltage spikes and unswitched
outputs.
Factors that affect ground bounce include:
•
rise and fall times
•
load capacitance
•
package inductance
•
number of output drivers sharing the same ground path
•
device type
Signal Integrity and Package Performance
Resistance, Capacitance and Inductance (defined in the “Terminology - Definitions and
Reviews” section) are the three major electrical parameters used in one format or another
to describe package electrical performance. These metrics are used to describe I/O, as well
as power networks of the packages. The parameters, also known as interconnect parasitics,
can be the source of many serious issues in digital systems. For example, a large resistance
can cause RC and RL off-chip delays, power dissipation, and edge-rate degradation. Large
capacitance in I/O nets can cause RC delays, crosstalk, edge-rate degradation, and signal
distortion. Lead inductance, perhaps the most damaging parasitic in digital circuitry, can
cause such problems as ground bounce (also known as simultaneous switching noise or
delta-I noise), RL delays, crosstalk, edge-rate degradation, and signal distortion.
In the design of Xilinx packages, the challenge is to seek the appropriate balance for these
parameters so that signal integrity issues are minimized. Package characterization is
geared to assist the package designers in a co-design effort to make the appropriate choices
backed by simulation and measurements in optimizing the package design and layout for
performance. A further goal of the effort is to gather the parasitics data and seek the
appropriate data representation of these parameters to help end-users deploy these
packages. To this end, Xilinx offers raw tabulated package parasitic data, summaries of
data, and various models as part of the deliverable. Representative samples will be shown
at appropriate sections.
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Chapter 4: Package Electrical Characteristics
The measurement and 3D extraction capability, as well as the models support, will be
described in the subsequent sections.
Electrical Data Generation and Measurement Methods
With regards to experimental measurements, Xilinx uses both the Time-Domain
Reflectometry (TDR) method for parasitic inductance and capacitance measurements, as
well as frequency domain measurements performed with a 4-port Vector Network
Analyzer (VNA). The practical measurement capability is augmented by a range of
analytical calculators, 2D and 3D full wave FEM tools that are utilized through simulations
to extract various signal integrity-based parameters about the packages.
Review of Practical Measurements
The main components of a TDR setup includes a digitizing sampling oscilloscope, a fast
rise-time step generator (5 mils
1.0 mm
5 mils
6 mils
(8.8 mils)
>5 mils
Signal
(L1)
Signal
(L2)
Signal Signal PWR
(L3)
(L4) Plane
GND
Plane
O0.30 mm (0.012)
O0.61 mm (0.024)
I/O
GND
PWR
VCCINT
O0.5 mm (0.020)
O0.4 mm (0.016)
1-Line/Channel
5 mils Line/ 5 mils Spacing
(Standard Technology)
1-Line/Channel
6 mils Line/ 6 mils Spacing
(Standard Technology)
Detail "A"
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Figure 5-5:
FG676 PC Board Layout/Land Pattern
Figure 5-5 describes a board-level layout strategy for a Xilinx 1.0 mm pitch FG676 package.
Detail A in Figure 5-5 describes the opening geometry for the land pad and the solder
mask. Routing with 5 mils lines/trace allows one signal per channel (between the balls).
For successful routing, eight row deep signal traces require six PCB layers. Figure 5-6
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Chapter 5: Recommended PCB Design Rules
shows the suggested schematic of layers for the six-layer routing scheme.
Using premium board technology such as Microvia Technology (allowing up to 4 mils
lines and spaces) efficient routing is possible with a reduced number of board layers. A
grouping scheme for power, ground, control and I/O pins, can also enable efficient
routing.
X-Ref Target - Figure 5-6
Signal
L-1
Power/Gnd
L-2
Signal
L-3
Signal
L-4
Power/Gnd
L-5
Signal
L-6
UG112_C5_06_111208
Figure 5-6:
Six-Layer Routing Scheme
Board Routing Examples
Figure 5-7 through Figure 5-11 offer examples of layer-by-layer board routing
implementation using the rules outlined above for the Virtex®-E family of 1.0 mm BGA
packages - FG256, FG456, FG676, FG900, and FG1156. The rule used assumes 5 mils lines
and spaces. This is just an illustration of how the strategies outlined above can be used; it
does not represent any specific implementation pin-out.
Similar board layout examples can be generated for other family (Virtex-II, Virtex-II Pro,
etc.) pin-outs with the rules and strategies discussed in this section. It should be noted that
the need to shield high-speed signals and meet Signal Integrity constraints might disrupt
the plane sequence.
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X-Ref Target - Figure 5-7
First Signal Layer
Second Signal Layer
Notes:
1) Solder Land Diameter 0.4 mm Nonsolder Mask Defined
2) Solder Mask Opening Diameter 0.5 mm
3) Via Diameter 0.3 mm on 0.61 mm Diameter Via Land
4) Trace Width 0.127 mm
UG112_c5_07 _040809
Figure 5-7:
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X-Ref Target - Figure 5-8
First Signal Layer
Second Signal Layer
Third Signal Layer
Notes:
1) Solder Land Diameter 0.4 mm Nonsolder Mask Defined
2) Solder Mask Opening 0.5 mm Diameter
3) Via Diameter 0.3 mm on 0.61 mm Diameter Via Land
4) All Layers Trace Width 0.127 mm
UG112_c5_08 _040809
Figure 5-8:
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X-Ref Target - Figure 5-9
Top Signal Layer
Second Signal Layer
Third Signal Layer
Fourth Signal Layer
Notes:
1) Solder Land Diameter 0.4 mm Nonsolder Mask Defined
2) Solder Mask Opening Diameter 0.5 mm
3) Via Diameter 0.3 mm on 0.61 mm Diameter Via Land
4) Trace Width 0.127 mm
UG112_c5_09 _040809
Figure 5-9:
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XCV800 - FG676 NSMD Land Pad
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X-Ref Target - Figure 5-10
Top Signal Layer
Second Signal Layer
Third Signal Layer
Fourth Signal Layer
Fifth Signal Layer
Sixth Signal Layer
Notes:
1) Solder Land Diameter 0.4 mm Nonsolder Mask Defined
2) Solder Mask Opening Diameter 0.5 mm
3) Via Diameter 0.3 mm on 0.61 mm Diameter Via Land
4) Trace Width 0.127 mm
UG112_C5_10 _111208
Figure 5-10:
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X-Ref Target - Figure 5-11
Top Signal Layer
Second Signal Layer
Third Signal Layer
Fourth Signal Layer
Fifth Signal Layer
Sixth Signal Layer
Notes:
1) Solder Land Diameter 0.4 mm Nonsolder Mask Defined
2) Solder Mask Opening Diameter 0.5 mm
3) Via Diameter 0.3 mm on 0.61 mm Diameter Via Land
4) All layers, Trace Width 0.127 mm
UG112_C5_11 _111208
Figure 5-11:
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Recommended PCB Design Rules for QFN Packages
X-Ref Target - Figure 5-12
Zmax
D2’
CLL
CPL
Gmin
Y
Amax
D2’
Zmax
X
Amax
Gmin
UG112_C5_12 _111208
Figure 5-12:
Table 5-6:
IPC Standard Board Layout of Soldered Pads for QFN Packages
Recommended PCB Land Pattern Dimensions (mm)
Package
PCB Land Pattern Dimensions
Package
Body
Size
Lead
Pitch
Xmax
Yref
Amax
Gmin
Zmax
D2max
CLL(1)
CPL(2)
QFG32
5x5
0.50
0.28
0.69
3.78
3.93
5.31
3.63
0.10
0.15
QFG48
7x7
0.50
0.28
0.69
5.78
5.93
7.31
5.63
0.10
0.15
1. CLL defines the minimum distance between land to land for the corner joints on adjacent sides.
2. CPL defines the minimum distance between the inner tip of the peripheral lands and the outer edge of the thermal pad.
PCB Pad Pattern Design and Surface-Mount Considerations
for QFN Packages
Xilinx Quad Flat No-Lead (QFN) package is a robust and low profile leadframe-based
plastic package that has several advantages over traditional leadframe packages.The
exposed die attach paddle enables efficient thermal dissipation when directly soldered to
the PCB. Additionally, this near chip scale package offers improved electrical performance,
smaller package size, and an absence of external leads. Since the package has no external
leads, coplanarity and bent leads are no longer a concern.
The exposed pads at the bottom of a QFN package can be used to enhance both electrical
and thermal performance of the QFN component. To implement this, note that the exposed
pad is a weak ground through its connection to the silicon. Under no circumstances should
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the pad be connected to a positive or negative voltage. The paddle should only be left
floating or connected to corresponding ground pad on the board. Ground pads
incorporating thermal vias in them will significantly improve thermal performance, as
shown in Figure 5-14.
The following factors have major effect on the quality and reliability of assembling QFN
packages: PCB pad pattern design, amount of solder paste in thermal pad region, stencil
design, type of solder paste, and reflow profile. This application note provides a good
guideline on PCB pad pattern design and assembling of QFN packages for optimal
reliability and quality. This is only a guideline and users are encouraged to perform actual
studies to optimize the process.
PCB Pad Patterns
Figure 5-13 shows the PCB pad pattern dimensions to be determined. The dimension X
and Y indicate the width and length of the pad. CLL and CPL define the clearances needed
to avoid solder bridging. CLL defines the minimum distance between land to land for the
corner joints on adjacent sides and CPL defines the minimum distance between the inner
tip of the peripheral lands and the outer edge of the thermal pad. CLL should be 0.1 mm
and CPL should be 0.15 mm.
X-Ref Target - Figure 5-13
Zmax
D2’
CLL
CPL
Gmin
Y
Amax
D2’
Zmax
X
Amax
Gmin
UG112_C5_12 _111208
Figure 5-13:
Device Package User Guide
UG112 (v3.7) September 5, 2012
PCB Land Pattern Dimensions
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Tolerance analysis should be performed on the package and the PCB dimensions in order
to design a proper pad pattern. The recommended PCB land pattern dimensions are
shown in Table 5-6.
Table 5-7:
Recommended PCB Land Pattern Dimensions (all dimensions in mm)
Package
Package
PCB Land Pattern Dimensions
Body Size
Lead Pitch
Xmax
Yref
Amax
Gmin
Zmax
D2max
QFG32
5x5
0.50
0.28
0.69
3.78
3.93
5.31
3.63
QFG48
7x7
0.50
0.28
0.69
5.78
5.93
7.31
5.63
Thermal Pad and Via Design
Typical deployment of a QFN package has a thermal resistance (θja) of 35 – 45o C/watt
(depending on package size). When needed, the base performance can be improved and a
lower overall θja is achieved by taking advantage of the exposed thermal pad feature. To
take advantage of the exposed thermal pad under the package, the PCB should incorporate
thermal pad and thermal vias. The thermal pad on the PCB acts as a solderable surface and
the thermal vias provide a thermal path to the inner and/or bottom layers of the PCB to
remove the heat. The number of thermal vias will depend on the following: application,
power dissipation and electrical requirements. The thermal performance gets better as
more thermal vias are added. However, there is a point of diminishing returns as shown in
Figure 5-14 where the effect of number of vias on θja is plotted for a 7 mm, 48-lead package.
A via diameter of 0.3 mm was used for this simulation.
X-Ref Target - Figure 5-14
30
ThetaJA (C/W)
29
28
27
26
25
24
4
2x2
2.4
9
3x3
1.8
16
4x4
1.2
36
6x6
0.9
# of Vias Matrix Pitch (mm)
UG112_C5_14 _111208
Figure 5-14:
θJA vs. Number of Vias Graph
Based on the above and similar thermal simulations, it is recommended to incorporate an
array of thermal vias that have pitch of 1.0 to 1.2 mm with via diameter of 0.3 to 0.33 mm.
Solder Masking Considerations
The PCB have pads that are either solder mask defined (SMD) or non solder mask defined
(NSMD). NSMD pads are preferred over SMD pads since the copper etching process has
tighter control than the solder masking process. Furthermore, NSMD pads with solder
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mask opening larger than the metal pad size improves the reliability of the solder joints as
solder is allowed to wrap around the sides of metal pads.
The solder mask opening should be larger than the pad size by 120 to 150 microns. This
results in a clearance of 60 – 75 microns between the copper pad and the solder mask.
The thermal pad area can be solder mask defined in order to avoid any solder bridging
between the thermal pad and the perimeter pads. The mask opening should be 100
microns smaller than the thermal land size on all four sides.
Stencil Design for Perimeter Pads
To achieve reliable solder joints, the solder joints on the perimeter pads should have about
50 to 75 microns standoff height and good side fillet on the outside. Good stand off can be
achieved by having a stencil aperture opening that allows for maximum paste release. This
is accomplished by having an area ratio that is greater than 0.66 and an aspect ratio that is
greater than 1.5. Area Ratio and Aspect Ratio is defined below:
Area Ratio = LW/2T(L+W)
Aspect Ratio = W/T
Where L and W are the aperture length and width, and T is the stencil thickness. The
stencil aperture should have a 1:1 ratio with the PCB pad sizes as both area and aspect ratio
targets can easily be achieved by this aperture. Also, the stencil should be laser cut and
electro-polished.
Stencil Design for Thermal Pad
To enhance thermal and electrical performance, the die paddle should be soldered to the
PCB thermal pad (see “PCB Pad Pattern Design and Surface-Mount Considerations for
QFN Packages,” page 98). Since outgassing occurs during reflow process and might cause
defects such as splatter and solder balling, care must be taken to avoid large solder paste
coverage. Thus, it is recommended to use smaller multiple openings in the stencil instead
of one big opening for printing solder paste on the thermal pad area. By doing this, 50 to
80% solder paste coverage can be achieved. Figure 5-15 below shows one way to achieve
these levels of solder paste coverage.
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Chapter 5: Recommended PCB Design Rules
X-Ref Target - Figure 5-15
1.35 x 1.35 mm Squares
@ 1.65 mm Pitch
Coverage: 68%
UG112_C5_15 _111208
Figure 5-15:
Thermal Pad Stencil Design
Via Types and Solder Voiding
Voids in the thermal pad region are not expected to degrade thermal and electrical
performance. However, large voids in the thermal pad area should be avoided. To control
these voids, solder masking might be required for thermal vias to prevent solder wicking
inside the via during reflow. Methods commonly used in the industry to control the voids
include “via tenting” (top or bottom side) using dry film solder mask, “via plugging” with
liquid photo-imageable (LPI) solder mask from the bottom side, or “via encroaching”.
Figure 5-16 shows these options. For via tenting, the solder mask diameter should be 100
microns larger than the diameter of the via.
X-Ref Target - Figure 5-16
(a)
(b)
(c)
(d)
UG112_C5_16_111208
Figure 5-16: Solder Mask Options for Thermal Vias: (a) Via Tenting from Top, (b) Via
Tenting from Bottom, (c) Via Plugging from Bottom, and (d) Via Encroached from
Bottom.
There are advantages/disadvantages to each of these options. Via tenting from the top side
might result in smaller voids, but the presence of the solder mask on the top side of the
board can hinder proper paste printing. Via tenting from the bottom and via plugging from
the bottom might result in larger voids because of outgassing. Finally, encroached vias
allow the solder to wick inside the vias and reduce the size of the voids. This option,
however, results in lower standoff of the package.
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Stencil Thickness and Solder Paste
For 0.5 mm pitch parts, a stencil thickness of 0.125 mm is recommended. Also, to improve
the paste release, a stainless steel stencil with electro-polished trapezoidal walls is
recommended.
For the paste, it is recommended to use “No Clean”, Type 3 paste. Since the pads on the
package are plated with 100% matte Sn, the package can be soldered using either Pb-free or
SnPb solder paste.
References
Application Notes for Surface Mount Assembly of Amkor’s MicroLeadFrame (MLF) Packages,
Amkor Technology, www.amkor.com
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Chapter 6
Moisture Sensitivity of PSMCs
Moisture-Induced Cracking During Solder Reflow
The surface mount reflow processing step subjects the Plastic Surface Mount Components
(PSMC) to high thermal exposure and chemicals from solder fluxes and cleaning fluids
during board mount assembly. The plastic mold compounds used for device encapsulation
are, universally, hygroscopic and absorb moisture at a level determined by storage
environment and other factors. Entrapped moisture can vaporize during rapid heating in
the solder reflow process generating internal hydrostatic pressure. Additional stress is
added due to thermal mismatch, and the Thermal Coefficient of Expansion (TCE) of
plastic, metal lead frame, and silicon die. The resultant pressure might be sufficient to
cause delamination within the package, or worse, an internal or external crack in the
plastic package. Cracks in the plastic package can allow high moisture penetration,
inducing transport of ionic contaminants to the die surface and increasing the potential for
early device failure. Cracks in the plastic package can also result in broken/lifted bond
wires.
How the effects of moisture in plastic packages and the critical moisture content result in
package damage or failure is a complex function of several variables. Among them are
package construction details—materials, design, geometry, die size, encapsulant thickness,
encapsulant properties, TCE, and the amount of moisture absorbed. The PSMC moisture
sensitivity has, in addition to package cracking, been identified as a contributor to
delamination-related package failure artifacts. These package failure artifacts include bond
lifting and breaking, wire neckdown, bond cratering, die attach separation, and die
passivation/metal breakage.
Because of the importance of the PSMC moisture sensitivity, both device suppliers and
device users have ownership and responsibility. The background for present conditions,
moisture sensitivity standardized test and handling procedures are published by two
national organizations. Users and suppliers are urged to obtain copies of both documents
(listed below) and use them rigorously. Xilinx adheres to both.
•
IPC/JEDEC J-STD-020C
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface
Mount Devices.” Available on www.jedec.org website.
•
IPC/JEDEC J-STD-033A
“Standard for Handling, Packing, Shipping, and Use of Moisture/Reflow Sensitive
Surface Mount Devices.” Available on www.jedec.org website.
None of the previously stated or following recommendations apply to parts in a
socketed application. For board mounted parts careful handling by the supplier and
the user is vital. Each of the above publications has addressed the sensitivity issue and
has established eight levels of sensitivity (based on the variables identified). A
replication of those listings, including the preconditioning and test requirements, and
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Chapter 6: Moisture Sensitivity of PSMCs
the factory floor life conditions for each level are outlined in Table 6-1. Xilinx devices
are characterized to their proper level as listed. This information is conveyed to the
user via special labeling on the Moisture Barrier Bag (MBB).
The moisture sensitivity level number, found in Table 6-1, is printed on the MBB prior to
shipment. This establishes the user's factory floor life conditions as listed in the time
column. The soak requirement is the test limit used by Xilinx to determine the level
number. This time includes manufacturer's exposure time or the time it will take for Xilinx
to bag the product after baking.
Table 6-1:
Package Moisture Sensitivity Levels
Soak Requirements(1)
Floor Life
Standard
Level
Time
Conditions
Time (hours)
Conditions
1
Unlimited
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