XCR3512XL-7PQ208C

0 XCR3512XL: 512 Macrocell CPLD R DS081 (v2.0) March 31, 2006 0 14 Product Specification Features Description • • • • • The CoolRunner™ XPLA3 XCR3512XL device is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide 12,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 135 MHz. • • • • • Programmable slew rate control per output • • Security bit prevents unauthorized access Refer to the CoolRunner™ XPLA3 family data sheet (DS012) for architecture description TotalCMOS Design Technique for Fast Zero Power CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution, both in process technology and design technique. This family employs a cascade of CMOS gates to implement its sum of products, instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3512XL TotalCMOS CPLD (data taken with 32 resetable up/down, 16-bit counters at 3.3V, 25°C). 300 270 240 Typical ICC (mA) • Low power 3.3V 512 macrocell CPLD 7.0 ns pin-to-pin logic delays System frequencies up to 135 MHz 512 macrocells with 12,000 usable gates Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (260 user I/O) Optimized for 3.3V systems - Ultra low power operation - Typical Standby Current of 18 μA at 25° C - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero Power™ (FZP) CMOS design technology - 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O) Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 clocks available per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for additional I/O 2.7V to 3.6V supply voltage at industrial grade voltage range 210 180 150 120 90 60 30 0 20 40 60 80 100 120 Frequency (MHz) Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C Frequency (MHz) 0 1 10 20 40 60 80 100 120 Typical ICC (mA) 0.018 2.57 25.5 50.8 100.3 147.9 193.5 237.8 281.6 © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS081 (v2.0) March 31, 2006 Product Specification www.xilinx.com 1 XCR3512XL: 512 Macrocell CPLD R DC Electrical Characteristics Over Recommended Operating Conditions(1) Symbol VOH (2) Parameter Output High voltage Test Conditions Typical Min. Max. Unit VCC = 3.0V to 3.6V, IOH = –8 mA - 2.4 - V VCC = 2.7V to 3.0V, IOH = –8 mA - 2.0 - V IOH = –500 μA - 90% VCC(3) - V VOL Output Low voltage IOL = 8 mA - - 0.4 V IIL Input leakage current VIN = GND or VCC to 5.5V - –10 10 μA IIH I/O High-Z leakage current VIN = GND or VCC to 5.5V - –10 10 μA ICCSB(7) Standby current VCC = 3.6V 32.5 - 100 μA f = 1 MHz - - 7 mA f = 50 MHz - - 175 mA ICC Dynamic current(4,5) CIN Input pin capacitance(6) f = 1 MHz - - 8 pF CCLK Clock input capacitance(6) f = 1 MHz - - 12 pF f = 1 MHz - - 10 pF CI/O I/O pin capacitance(6) Notes: 1. See CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions 2. See Figure 2 for output drive characteristics of the CoolRunner XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. See Table 1, Figure 1 for typical values. 5. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 6. Typical values, not tested. 7. Typical value at 70° C. 100 90 IOL (3.3V) 80 70 mA 60 50 IOH (3.3V) 40 30 IOH (2.7V) 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Volts DS012_10_041901 Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family, 25°C 2 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification XCR3512XL: 512 Macrocell CPLD R AC Electrical Characteristics Over Recommended Operating Conditions(1,2) -7 Symbol -12 Min. Max. Min. Max. Min. Max. Unit - 7.0 - 9.0 - 10.8 ns - 7.5 - 10.0 - 12.0 ns - 5.0 - 5.8 - 6.9 ns Setup time (fast input register) 4.0 - 5.0 - 5.0 - ns Setup time (single p-term) 3.8 - 5.5 - 6.7 - ns TSU2 Setup time (OR array) 4.3 - 6.5 - 7.9 - ns TH(4) Hold time 0 - 0 - 0 - ns TWLH(4) Global Clock pulse width (High or Low) 3.0 - 4.0 - 5.0 - ns P-term clock pulse width 4.5 - 6.0 - 7.5 - ns Asynchronous preset/reset pulse width (High or Low) 4.5 - 6.0 - 7.5 - ns Input rise time - 20 - 20 - 20 ns Input fall time - 20 - 20 - 20 ns TPD1 Parameter -10 Propagation delay time (single p-term) array)(3) TPD2 Propagation delay time (OR TCO Clock to output (global synchronous pin clock) TSUF TSU1 TPLH (4) (4) TAPRPW TR TL (4) (4) fSYSTEM (4) - 135 - 97 - 77 MHz time(5) - 200 - 200 - 200 μs TINIT(4) ISP initialization time - 200 - 200 - 200 μs TPOE(4) P-term OE to output enabled - 9.0 - 11.0 - 13.0 ns - 9.0 - 11.0 - 13.0 ns TCONFIG ) (4 Maximum system frequency Configuration TPOD (4) P-term OE to output TPCO (4) P-term clock to output - 8.5 - 10.3 - 12.4 ns (4) P-term set/reset to output valid - 9.0 - 11.0 - 13.0 ns TPAO disabled(6) Notes: 1. Specifications measured with one output switching. 2. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 17 mA at 3.6V. 6. Output CL = 5 pF. DS081 (v2.0) March 31, 2006 Product Specification www.xilinx.com 3 XCR3512XL: 512 Macrocell CPLD R Internal Timing Parameters(1,2) -7 Symbol Parameter -10 -12 Min. Max. Min. Max. Min. Max. Unit Buffer Delays TIN Input buffer delay - 2.5 - 3.3 - 4.0 ns TFIN Fast input buffer delay - 4.7 - 4.3 - 4.3 ns TGCK Global clock buffer delay - 1.5 - 1.3 - 1.5 ns TOUT Output buffer delay - 2.5 - 3.2 - 3.8 ns TEN Output buffer enable/disable delay - 4.5 - 5.2 - 6.0 ns - 1.3 - 1.6 - 2.0 ns Internal Register and Combinatorial Delays TLDI Latch transparent delay TSUI Register setup time 0.8 - 1.0 - 1.2 - ns THI Register hold time 0.3 - 0.5 - 0.7 - ns TECSU Register clock enable setup time 2.0 - 2.5 - 3.0 - ns TECHO Register clock enable hold time 3.0 - 4.5 - 5.5 - ns TCOI Register clock to output delay - 1.0 - 1.3 - 1.6 ns TAOI Register async. S/R to output delay - 2.0 - 2.0 - 2.2 ns TRAI Register async. recovery - 5.0 - 7.0 - 8.0 ns TPTCK Product term clock delay - 2.5 - 2.5 - 3.0 ns TLOGI1 Internal logic delay (single p-term) - 2.0 - 2.5 - 3.0 ns TLOGI2 Internal logic delay (PLA OR term) - 2.5 - 3.5 - 4.2 ns - 3.1 - 4.5 - 6.0 ns Feedback Delays TF ZIA delay Time Adders TLOGI3 Fold-back NAND delay - 2.0 - 2.5 - 3.0 ns TUDA Universal delay - 3.5 - 4.0 - 4.0 ns TSLEW Slew rate limited delay - 5.0 - 5.0 - 6.0 ns Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See the CoolRunner XPLA3 family data sheet (DS012) for timing model. 4 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification XCR3512XL: 512 Macrocell CPLD R Switching Characteristics VCC S1 Component R1 R2 C1 R1 Values 390Ω 390Ω 35 pF VIN VOUT R2 Measurement TPOE (High) TPOE (Low) TP C1 S1 Open Closed Closed S2 Closed Open Closed Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH – 300 mV. S2 DS023_03_102401 (ns) Figure 3: AC Load Circuit 7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 +3.0V 90% 10% 0V TR 1.5 ns 1 2 4 8 16 Number of Adjacent Outputs Switching TL 1.5 ns Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. DS017_05_042800 DS081_04_120902 Figure 5: Voltage Waveform Figure 4: Derating Curve for TPD2 DS081 (v2.0) March 31, 2006 Product Specification www.xilinx.com 5 XCR3512XL: 512 Macrocell CPLD R Pin Descriptions Table 3: XCR3512XL I/O Pins (Continued) Table 2: XCR3512XL User I/O Pins Total User I/O Pins Macrocell PQ208 FT256 FG324 PQ208 FT256 FG324 2 14 4 D14 F19 180 212 260 2 15 - - E21 2 16 6 D15 E22 3 1 203 A14 B19 3 2 - E11 A20 Table 3: XCR3512XL I/O Pins 6 Function Block Function Block Macrocell PQ208 FT256 FG324 3 3 202 - C18 1 1 208 C14 C21 3 4 201 A13 B18 1 2 - D13 C20 3 5 - - - 1 3 207 - B22 3 6 - - - 1 4 206 A15 B21 3 7 - - - 1 5 - - - 3 8 - - - 1 6 - - - 3 9 - - - 1 7 - - - 3 10 - - - 1 8 - - - 3 11 - - - 1 9 - - - 3 12 - - - 1 10 - - - 3 13 - D12 A19 1 11 - - - 3 14 - - D17 1 12 - - - 3 15 199 B13 A18 1 13 - - A22 3 16 198 C12 C17 1 14 205 B15 A21 4 1 7 E13 F20 1 15 - B14 B20 4 2 - - F21 1 16 204 C13 C19 4 3 8 C16 F22 2 1 1 E12 D20 4 4 9 F12 G19 2 2 - - C22 4 5 - - - 2 3 2 A16 D21 4 6 - - - 2 4 - C15 D22 4 7 - - - 2 5 - - - 4 8 - - - 2 6 - - - 4 9 - - - 2 7 - - - 4 10 - - - 2 8 - - - 4 11 - - - 2 9 - - - 4 12 - - - 2 10 - - - 4 13 - - G20 2 11 - - - 4 14 10 D16 G21 2 12 - - - 4 15 - E14 G22 2 13 3 B16 E20 4 16 11 E15 H20 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification XCR3512XL: 512 Macrocell CPLD R Table 3: XCR3512XL I/O Pins (Continued) Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 Function Block Macrocell PQ208 FT256 FG324 5 1 197 A12 B17 7 4 189(1) C10(1) B14(1) 5 2 - - A17 7 5 - - - 5 3 196 D11 D16 7 6 - - - 5 4 - - C16 7 7 - - - 5 5 - - - 7 8 - - - 5 6 - - - 7 9 - - - 5 7 - - - 7 10 - - - 5 8 - - - 7 11 - - - 5 9 - - - 7 12 - - - 5 10 - - - 7 13 188 - A14 5 11 - - - 7 14 - - D13 5 12 - - - 7 15 - A9 C13 5 13 195 A11 B16 7 16 187 D9 B13 5 14 - E10 A16 8 1 18 G13 K21 5 15 194 B12 C15 8 2 - - K22 5 16 193 C11 B15 8 3 19 F16 L19 6 1 12 F13 H21 8 4 - - L20 6 2 - - H22 8 5 - - - 6 3 13 E16 J19 8 6 - - - 6 4 - - J20 8 7 - - - 6 5 - - - 8 8 - - - 6 6 - - - 8 9 - - - 6 7 - - - 8 10 - - - 6 8 - - - 8 11 - - - 6 9 - - - 8 12 - - - 6 10 - - - 8 13 20 G14 L21 6 11 - - - 8 14 21 G16 L22 6 12 - - - 8 15 22 H13 M21 6 13 15 F15 J21 8 16 24 H12 M20 6 14 16 G12 J22 9 1 51 P16 AA21 6 15 - F14 K19 9 2 - N14 AB22 6 16 17 G15 K20 9 3 49 R16 AA22 7 1 192 B11 A15 9 4 - - Y20 7 2 - D10 D14 9 5 - - - 7 3 190 A10 C14 9 6 - - - DS081 (v2.0) March 31, 2006 Product Specification www.xilinx.com 7 XCR3512XL: 512 Macrocell CPLD R Table 3: XCR3512XL I/O Pins (Continued) 8 Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 Function Block Macrocell PQ208 FT256 FG324 9 7 - - - 11 10 - - - 9 8 - - - 11 11 - - - 9 9 - - - 11 12 - - - 9 10 - - - 11 13 - - V22 9 11 - - - 11 14 40 M15 U20 9 12 - - - 11 15 39 L16 U21 9 13 48 M13 Y21 11 16 38 K12 U22 9 14 47 P15 W20 12 1 58 R14 Y17 9 15 46 L12 W21 12 2 - N12 AA18 9 16 45 N16 Y22 12 3 59 T14 AB18 10 1 52 N13 AB21 12 4 - - AA17 10 2 53 R15 Y19 12 5 - - - 10 3 54 M12 AA20 12 6 - - - 10 4 - - AB20 12 7 - - - 10 5 - - - 12 8 - - - 10 6 - - - 12 9 - - - 10 7 - - - 12 10 - - - 10 8 - - - 12 11 - - - 10 9 - - - 12 12 - - - 10 10 - - - 12 13 60 M11 AB17 10 11 - - - 12 14 - R13 W16 10 12 - - - 12 15 61 P12 Y16 10 13 55 T16 Y18 12 16 62 T13 AA16 10 14 56 P14 AA19 13 1 37 L15 T19 10 15 - T15 AB19 13 2 - - T20 10 16 57 P13 W17 13 3 36 K13 T21 11 1 44 M14 W22 13 4 35 K16 T22 11 2 43 M16 V20 13 5 - - - 11 3 42 L13 V21 13 6 - - - 11 4 - N15 U19 13 7 - - - 11 5 - - - 13 8 - - - 11 6 - - - 13 9 - - - 11 7 - - - 13 10 - - - 11 8 - - - 13 11 - - - 11 9 - - - 13 12 - - - www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification XCR3512XL: 512 Macrocell CPLD R Table 3: XCR3512XL I/O Pins (Continued) Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 Function Block Macrocell PQ208 FT256 FG324 13 13 - K14 R20 15 16 25 H15 M19 13 14 34 K15 R21 16 1 70 T11 W13 13 15 33 L14 R22 16 2 71 R10 Y13 13 16 31 J16 P19 16 3 73 P10 AA13 14 1 64 N11 AB16 16 4 - T10 AB13 14 2 - R12 Y15 16 5 - - - 14 3 65 T12 AA15 16 6 - - - 14 4 66 R11 AB15 16 7 - - - 14 5 - - - 16 8 - - - 14 6 - - - 16 9 - - - 14 7 - - - 16 10 - - - 14 8 - - - 16 11 - - - 14 9 - - - 16 12 - - - 14 10 - - - 16 13 - - W12 14 11 - - - 16 14 76 N9 AA12 14 12 - - - 16 15 77 R9 AB12 14 13 67 M10 W14 16 16 78 P9 Y11 14 14 68 P11 Y14 17 1 157 B1 C3 14 15 - - AA14 17 2 - B2 A2 14 16 69 N10 AB14 17 3 158 C3 B3 15 1 30(1) J13(1) P20(1) 17 4 - - C4 15 2 29 J15 P21 17 5 - - - 15 3 28 J14 P22 17 6 - - - 15 4 - - N19 17 7 - - - 15 5 - - - 17 8 - - - 15 6 - - - 17 9 - - - 15 7 - - - 17 10 - - - 15 8 - - - 17 11 - - - 15 9 - - - 17 12 - - - 15 10 - - - 17 13 159 D4 B4 15 11 - - - 17 14 - A2 C5 15 12 - - - 17 15 160 A1 B5 15 13 27 H16 N21 17 16 161 B3 A3 15 14 - - N22 18 1 156 C1 D3 15 15 26 H14 M22 18 2 155 D3 B2 DS081 (v2.0) March 31, 2006 Product Specification www.xilinx.com 9 XCR3512XL: 512 Macrocell CPLD R Table 3: XCR3512XL I/O Pins (Continued) Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 Function Block Macrocell PQ208 FT256 FG324 18 3 154 C2 B1 20 6 - - - 18 4 153 F5 C2 20 7 - - - 18 5 - - - 20 8 - - - 18 6 - - - 20 9 - - - 18 7 - - - 20 10 - - - 18 8 - - - 20 11 - - - 18 9 - - - 20 12 - - - 18 10 - - - 20 13 - - F2 18 11 - - - 20 14 146 F4 F1 18 12 - - - 20 15 145 F1 G4 18 13 - - C1 20 16 144 G5 G3 18 14 151 D1 E3 21 1 168 B5 B7 18 15 - - D2 21 2 - D6 A7 18 16 150 E4 D1 21 3 169 A5 C8 19 1 162 C4 A4 21 4 - - B8 19 2 - - D6 21 5 - - - 19 3 163 A3 A5 21 6 - - - 19 4 - D5 C6 21 7 - - - 19 5 - - - 21 8 - - - 19 6 - - - 21 9 - - - 19 7 - - - 21 10 - - - 19 8 - - - 21 11 - - - 19 9 - - - 21 12 - - - 19 10 - - - 21 13 170 C6 A8 19 11 - - - 21 14 171 B6 D9 19 12 - - - 21 15 - E7 C9 19 13 164 B4 B6 21 16 172 A6 B9 19 14 - E6 A6 22 1 142 E2 G2 19 15 166 A4 D7 22 2 141 F3 G1 19 16 167 C5 C7 22 3 - - H3 20 1 149 D2 F4 22 4 140 F2 H2 20 2 148 E3 F3 22 5 - - - 20 3 - - E2 22 6 - - - 20 4 147 E1 E1 22 7 - - - 20 5 - - - 22 8 - - - 10 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification XCR3512XL: 512 Macrocell CPLD R Table 3: XCR3512XL I/O Pins (Continued) Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 Function Block Macrocell PQ208 FT256 FG324 22 9 - - - 24 12 - - - 22 10 - - - 24 13 133 J1 K1 22 11 - - - 24 14 - - L1 22 12 - - - 24 15 - - L4 22 13 - - H1 24 16 132 J3 L3 22 14 139 G4 J4 25 1 105 P2 AA1 22 15 - G1 J3 25 2 106 P3 Y3 22 16 138 G3 J2 25 3 - - Y2 23 1 173 D7 A9 25 4 108 T1 W3 23 2 - B7 D10 25 5 - - - 23 3 175 C7 C10 25 6 - - - 23 4 - C8 B10 25 7 - - - 23 5 - - - 25 8 - - - 23 6 - - - 25 9 - - - 23 7 - - - 25 10 - - - 23 8 - - - 25 11 - - - 23 9 - - - 25 12 - - - 23 10 - - - 25 13 - - Y1 23 11 - - - 25 14 109 N3 W2 23 12 - - - 25 15 110 R1 W1 23 13 - - A10 25 16 111 M4 V3 23 14 176(1) A7(1) D11(1) 26 1 104 M5 AB1 23 15 177 D8 C11 26 2 - N4 AA2 23 16 178 B8 B11 26 3 103 R2 AB2 24 1 137 H1 J1 26 4 - T2 AA3 24 2 136 H4 K4 26 5 - - - 24 3 135 G2 K3 26 6 - - - 24 4 - H3 K2 26 7 - - - 24 5 - - - 26 8 - - - 24 6 - - - 26 9 - - - 24 7 - - - 26 10 - - - 24 8 - - - 26 11 - - - 24 9 - - - 26 12 - - - 24 10 - - - 26 13 102 P4 Y4 24 11 - - - 26 14 - - AB3 DS081 (v2.0) March 31, 2006 Product Specification www.xilinx.com 11 XCR3512XL: 512 Macrocell CPLD R Table 3: XCR3512XL I/O Pins (Continued) Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 Function Block Macrocell PQ208 FT256 FG324 26 15 101 R3 AA4 29 2 - - R3 26 16 100 N5 Y5 29 3 120 M1 R2 27 1 112 P1 U4 29 4 121 K5 R1 27 2 - - V2 29 5 - - - 27 3 113 L5 V1 29 6 - - - 27 4 114 N2 U3 29 7 - - - 27 5 - - - 29 8 - - - 27 6 - - - 29 9 - - - 27 7 - - - 29 10 - - - 27 8 - - - 29 11 - - - 27 9 - - - 29 12 - - - 27 10 - - - 29 13 122 L3 P4 27 11 - - - 29 14 123 K4 P3 27 12 - - - 29 15 - - P2 27 13 - - U2 29 16 124 L1 P1 27 14 115 M3 U1 30 1 92 T6 Y7 27 15 117 L4 T3 30 2 - T5 AA7 27 16 118 M2 T2 30 3 91 M7 AB7 28 1 99 T3 AA5 30 4 - - Y8 28 2 98 M6 AB4 30 5 - - - 28 3 - R4 W6 30 6 - - - 28 4 97 P5 AB5 30 7 - - - 28 5 - - - 30 8 - - - 28 6 - - - 30 9 - - - 28 7 - - - 30 10 - - - 28 8 - - - 30 11 - - - 28 9 - - - 30 12 - - - 28 10 - - - 30 13 90 R6 AA8 28 11 - - - 30 14 89 N7 AB8 28 12 - - - 30 15 88 T7 W9 28 13 - - Y6 30 16 87 P6 Y9 28 14 96 T4 AA6 31 1 126 K2 N4 28 15 95 N6 AB6 31 2 - K3 N3 28 16 93 R5 W7 31 3 127(1) K1(1) N2(1) 29 1 119 L2 T1 31 4 128 J4 N1 12 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification XCR3512XL: 512 Macrocell CPLD R Table 3: XCR3512XL I/O Pins (Continued) Table 4: XCR3512XL Global, JTAG, Port Enable, Power, and No Connect Pins Function Block Macrocell PQ208 FT256 FG324 Pin Type PQ208 FT256 FG324 31 5 - - - IN0 / CLK0 181 B9 C12 31 6 - - - IN1 / CLK1 182 A8 B12 31 7 - - - IN2 / CLK2 183 C9 D12 31 8 - - - IN3 / CLK3 184 B10 A12 31 9 - - - TCK 30 J13 P20 31 10 - - - TDI 176 A7 D11 31 11 - - - TDO 189 C10 B14 31 12 - - - TMS 127 K1 N2 31 13 - - M4 116(1) N1(1) T4(1) 31 14 129 J2 M3 31 15 130 J5 M2 31 16 131 H2 L2 32 1 86 R7 AA9 32 2 - P7 AB9 32 3 84 T8 W10 32 4 - N8 Y10 32 5 - - - 32 6 - - - 32 7 - - - 32 8 - - - 32 9 - - - 32 10 - - - 32 11 - - - 32 12 - - - 32 13 - - AA10 32 14 81 R8 AB11 32 15 80 P8 W11 32 16 79 T9 AA11 Notes: 1. JTAG pins. PORT_EN Vcc A11, A13, 5, 23, 41, 63, E8, E9, F7, 74, 83, 85, F8, F9, F10, D8, D15, H4, H19, J10, G6, G11, H5, 107, 125, J11, J12, H6, H11, J6, 143, 165, J13, K9, J11, J12, K6, 179, 186, K14, L9, K11, L7, L8, 191 L9, L10, M8, L14, M1, M9, M14, N9, M9 N14, N20, P10, P11, P12, P13, R4, R19, W8, W15, Y12, AB10 GND 14, 32, 50, E5, F6, F11, D4, D5, D18, D19, E4, G7, G8, G9, 72, 75, 82, 94, 134, 152, G10, H7, H8, E19, J9, J14, K10, K11, H9, H10, J7, 174, 180, K12, K13, J8, J9, J10, 185, 200 L10, L11, K7, K8, K9, L12, L13, K10, L6, L11 M10, M11, M12, M13, N10, N11, N12, N13, P9, P14, V4, V19, W4, W5, W18, W19 No Connects - - A1 Notes: 1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full explanation. DS081 (v2.0) March 31, 2006 Product Specification www.xilinx.com 13 XCR3512XL: 512 Macrocell CPLD R Device Part Marking and Ordering Combination Information R XCRxxxxXL TQ144 Device Type Package This line not related to device part number 7C Speed Operating Range 1 Sample package with part marking. Speed (pin-to-pin delay) Pkg. Symbol No. of Pins XCR3512XL-7PQ208C 7.5 ns PQ208 208-pin Plastic Quad Flat Pack (PQFP) C XCR3512XL-7PQG208C 7.5 ns PQG208 208-pin Plastic Quad Flat Pack (PQFP); Pb-Free C XCR3512XL-7FT256C 7.5 ns FT256 256-ball Fine-Pitch BGA (FT) C XCR3512XL-7FG324C 7.5 ns FG324 324-ball Fineline BGA Package (FG) C XCR3512XL-10PQ208C 10 ns PQ208 208-pin Plastic Quad Flat Pack (PQFP) C XCR3512XL-10PQG208C 10 ns PQG208 208-pin Plastic Quad Flat Pack (PQFP); Pb-Free C XCR3512XL-10FT256C 10 ns FT256 256-ball Fine-Pitch BGA (FT) C XCR3512XL-10FG324C 10 ns FG324 324-ball Fineline BGA Package (FG) C XCR3512XL-10PQ208I 10 ns PQ208 208-pin Plastic Quad Flat Pack (PQFP) I XCR3512XL-10PQG208I 10 ns PQG208 208-pin Plastic Quad Flat Pack (PQFP); Pb-Free I XCR3512XL-10FT256I 10 ns FT256 256-ball Fine-Pitch BGA (FT) I XCR3512XL-10FG324I 10 ns FG324 324-ball Fineline BGA Package (FG) I XCR3512XL-12PQ208C 12 ns PQ208 208-pin Plastic Quad Flat Pack (PQFP) C XCR3512XL-12PQG208C 12 ns PQG208 208-pin Plastic Quad Flat Pack (PQFP); Pb-Free C XCR3512XL-12FT256C 12 ns FT256 256-ball Fine-Pitch BGA (FT) C XCR3512XL-12FG324C 12 ns FG324 324-ball Fineline BGA Package (FG) C XCR3512XL-12PQ208I 12 ns PQ208 208-pin Plastic Quad Flat Pack (PQFP) I XCR3512XL-12PQG208I 12 ns PQG208 208-pin Plastic Quad Flat Pack (PQFP); Pb-Free I XCR3512XL-12FT256I 12 ns FT256 256-ball Fine-Pitch BGA (FT) I XCR3512XL-12FG324I 12 ns FG324 324-ball Fineline BGA Package (FG) I Device Ordering and Part Marking Number Operating Range(1) Package Type Notes: 1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C 14 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification XCR3512XL: 512 Macrocell CPLD R Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Additional Information CoolRunner XPLA3 Data Sheets and Application Notes Device Package User Guide Device Packages Revision History The following table shows the revision history for this document Date Version 04/11/01 1.0 Initial Xilinx release. 04/19/01 1.1 Updated Typical I/V curve, Figure 2: added voltage levels. 09/04/01 1.2 Updated AC Electrical: added TINIT spec.; Internal Timing Parameters; added -12 industrial temperature. 01/08/02 1.3 Updated TINIT spec and TCONFIG spec. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated THI spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement. 01/06/03 1.4 Updated all AC and DC parameters based on product characterization. Released to Preliminary. Updated TPCO (added TPTCK). Updated Ordering Information format. 07/15/03 1.5 Updated test conditions for IIL and IIH. 09/23/03 1.6 Updated Package Device Marking Pin 1 orientation. Removed Preliminary. 02/13/04 1.7 Add solder temperature specification. Add links to data sheets, application notes, and packages. 01/05/05 1.8 Fixed broken links. 04/08/05 1.9 Added ICCSB Typical and TAPRPW specifications. Removed TSOL specification. 03/31/06 2.0 Added Warranty Disclaimer; Added Pb-Free package ordering information. DS081 (v2.0) March 31, 2006 Product Specification Revision www.xilinx.com 15