KESTX01IG

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ KESTX01 400MHz - 460MHz ASK Transmitter Preliminary Information Supersedes September 1996 version, DS4548 - 2.0 DS3969 - 3.8 August 1998 The KESTX01 is a single chip ASK (Amplitude Shift Key) transmitter IC. It is designed to operate in a variety of low power radio applications including keyless entry, general domestic and industrial remote control, RF tagging and local paging systems. The transmitter offers a high level of integration and performance, which enables the harmonic rejection and fundamental power requirements of the ESTI 300 220, and other governing bodies, to be met. The basic architecture utilises a crystal reference oscillator, an integrated frequency multiplying PLL and a power output stage. The design is centred around the popular 433.92MHz operating frequency and particular emphasis has been placed on low current drain, including a power–down feature which greatly increases battery life. XTAL1 VCOTST VEE1 LF LF1 TXEN VCC 1. 41 XTAL2 PWRC DATA OUTB OUT VCCPA KESTX01 8 7 KESTX01 VEE2 MP14 Figure.1 Pin connections - top view FEATURES s Low supply Current s Power down feature s Adjustable output power level s Low external part count s Fully integrated VCO, PLL and Power Amplifier ABSOLUTE MAXIMUM RATINGS Junction temperature -55 to +150°C Storage temperature -55 to +150°C Supply voltage VEE-0.5 to +8.0V Voltage on any pin VEE -0.5 to VCC+0.5V Notes: 1. The voltage on pin OUT and OUTB (open collector outputs) can support a higher voltage than this (+14V) ORDERING INFORMATION KESTX01/IG/MPAD (Tape and Reel) KESTX01/IG/MPAS (Tubes) VCC VCC TXEN PLL POWER SUPPLY VCCPA PWRC DATA 1 64 PHASE DETECTOR OUT OUT B VEE2 XTAL OSCILLATOR VCO VEE1 XTAL1 XTAL2 LF LF1 VCOTST Figure.2 block diagram KESTX01 ELECTRICAL CHARACTERISTICS Operating conditions T amb = –40°C to + 85°C, VCC = 3.5V to 6.5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Power supply voltage Ambient temperature Symbol Min VCC Ta 3.5 –40 Value Typ Units Max 6.5 +85 V °C Conditions Electro static discharge 2kV all pins – human body model ELECTRICAL CHARACTERISTICS D.C. T amb = –40°C to + 85°C, VCC = 3.5V to 6.5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Supply current stand by mode Supply current PLL enable/transmit space Supply current PLL enable/transmit mark Supply current PLL enable/transmit space Supply current PLL enable/transmit mark see note 1 TXEN – transmit enable TXEN – transmit disable/stand by Input bias current TXEN Bias voltage pin PWRC Data pin input logic high Data pin input logic low Data pin input current – logic low Data pin input current – logic high V ih Symbol Min I CC1 Value Typ Units Max 0.7 µA Condition V TXEN =0V; V DATA =0V;Ta=25°C VCC = 7V I mod =0 µA; VCC =V TXEN 3.5V V DATA =LOW; 434MHz I mod =150 µA; VCC =V TXEN =3.5V V DATA =HIGH; 434MHz I mod =0 µA; VCC =V TXEN =6.5V V DATA =LOW; 434MHz I mod =150µA; VCC =V TXEN =6.5V V DATA =HIGH; 434MHz I CC 2 I CC 3 I CC 4 I CC 5 1.6 2.8 4 mA 6.4 8.5 10.1 mA 1.6 3.17 5.0 mA 6.4 9.8 12.5 mA Ven V dis 3.5 VEE –0.2 VCC +0.2 0.5 V V I txen 150 1.0 0.7VCC V EE –0.5 –100 1.20 1.5 V CC +0.5 0.3VCC µA V V V µA µA TXEN = VCC transmit enable I mod =150 A V CC = 3.5V V il I inl VCC = 7V VDATA = 2.1V VCC = 7V VDATA = 4.9V I inh +100 Notes:– 1. The maximum supply current is directly related to Imod and hence the output power level. (Figure 4) 2 KESTX01 ELECTRICAL CHARACTERISTICS A.C. T amb = –40°C to + 85°C, V CC = 3.5V to 6.5V. These characteristics are guaranteed by either production test, characterisation or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Output current at fundamental, VCC=3.5V Output current at Fundamental, VCC = 3.5V Output current fundamental VCC = 6.5V Output level at 2 x fundamental see note 1 Output level at 3 x fundamental and all other spurii see note 1 Phase detector gain Extinction ratio see note 2 VCO gain TXEN settling time see note 3 Output sidebands due to reference frequency see note 4 30dB rise timeRF envelope of Data pulse 30dB fall timeRF envelope of Data pulse VCO operating frequency PDG ER 4.7 40 8 Symbol Min IF75 1.4 Value Typ 2.1 Units Max 2.8 pk–pk mA pk-pk mA pk–pk mA dBc I mod =75µA, F o =434MHz =150µA, Fo =434MHz Conditions IF150 2.4 3.8 4.9 I mod IF150(6V5) 3.0 4.6 5.6 I mod =150µA, F o =434MHz I mod =150µA, F o =434MHz (1) I mod =150µA, Fo=434MHz (1) –32 –11 dBc 9.5 µA/rad dB VCC = 3.5V G VCO Txe 110 5.0 MHz/V ms I mod =150µA, F o =434MHz (1, 4) SB –40 dBc T30R 380 ns T30F 430 ns 400 434 460 MHz VCC = 3.5 Notes: 1. The spurii are specified relative to the fundamental, measured in a 300KHz resolution bandwidth. 2. Extinction ratio is defined as the ratio of the output power SPACE to output power MARK measured at the output operating fequency. 3. Regulatory issues demand that transmission does not take place until the PLL has acquired lock and the VCO is operating at its final output frequency. This requirement demands that pin TXEN is set high at least Txe ms prior to the transmission of any data. This value is dependent on the PLL loop bandwidth and hence on the value of the external loop filter component values. The specification value above is for the loop filter components shown in the applications diagram (Figure. 6) 4. Sidebands on the output due to the PLL reference are a function of the PLL loop bandwidth and the application. Reducing the closed loop bandwidth of the PLL loop will aid in reducing the level of the PLL reference spurii. 3 KESTX01 PIN LISTING Signal XTAL1 XTAL2 DATA TXEN OUT OUTB LF Description Crystal oscillator Crystal oscillator Input data Transmit enable/stand by Power amplifier output/antenna interface Power amplifier output/antenna interface (complementary output) Phase detector output Signal LF1 PWRC VCCPA VEE2 VEE1 VCC VCOTST Description VCO control input Output power control Power amplifier positive supply Power amplifier ground PLL ground Positive supply VCO test control input FUNCTION When the IC is enabled (TXEN high) a phase locked loop locks the output of the VCO to a multiple of a crystal defined reference input. The output of the VCO operates at the final output frequency and is the input to a power amplifier stage. The power amplifier directly drives the antenna. Output stage (PA) The input signal at pin DATA produces amplitude shift key (ASK) modulation of the VCO output. This is achieved by on–off keying of the bias current in the output power amplifier stage. The output of the PA is a balanced output (pin OUT and OUTB) and is current source driven (open collector outputs). The outputs of which should be D.C. referenced to a positive supply voltage (anticipated to be VCC in most applications). The current source outputs can drive a PCB antenna directly (Figure 6) or if a higher output power is required on limited supply headroom via a simple impedance transforming network. A balanced output stage is used as it automatically suppresses the even order harmonics of the fundamental. In order to obtain the benefits of this output stage it is essential to use a balanced antenna. Phase locked loop Dividers A divide by 64 prescaler is present in the PLL feedback loop. The final output frequency is then Fo = 64xFref. Phase detector The phase detector used is a phase frequency detector (PFD) with a current (charge pump) output. This phase detector has a triangular characteristic for an input phase error in the range –2π