MT093AP

ISO-CMOS MT093 8 x 12 Analog Switch Array F eatures • • • • • • • • • Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5V to 14.5V 3.5Vpp analog signal capability RON 65Ω m ax. @ VDD=14V, 25°C ∆RON ≤ 1 0Ω @ VDD=14V, 25°C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Low power consumption ISO-CMOS technology ISSUE 2 March 1997 O rdering Information MT093AE MT093AP 40 Pin Plastic DIP 44 Pin PLCC 0° to 70°C D escription The Zarlink MT093 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8x12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven input bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. Applications • • • • • PBX systems Mobile radio Test equipment /instrumentation Analog/digital multiplexers Audio/Video switching STROBE DATA RESET VDD VSS AX0 AX1 AX2 AX3 AY0 AY1 AY2 1 1 •••••••••••••••• 7 to 96 Decoder Latches 8 x 12 Switch Array 96 Xi I/O (i=0-11) 96 ••••••••••••••••••• Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 3-65 MT093 ISO-CMOS 40 PIN PLASTIC DIP Figure 2 - Pin Connections Pin Description Pin # PDIP PLCC Name Y3 AY2 RESET AX3,AX0 NC X6-X11 Description 1 2 3 4,5 6,7 8-13 14 15 16 17 18 1 2 3 4,5 6-8 9-14 15-17 18 19 20 19 20 21 22, 23 24, 25 26, 27 28 - 33 34 35 36 37 21 22 23 24,25 26,27 28-31 32-37 38,39 40 41 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. Y2 Address Line (Input). Master RESET (Input): this is used to turn off all switches. Active High. X3 and X0 Address Lines (Inputs). No Connection. X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. NC No Connection. Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. NC No Connection. Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. VSS Ground Reference. Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. AX1,AX2 X1 and X2 Address Lines (Inputs). AY0,AY1 Y0 and Y1 Address Lines (Inputs). NC No Connection. X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. NC No Connection. Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. NC No Connection. Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. 3-66 Y7 Y6 STROBE Y5 VSS Y4 AX1 AX2 AY0 AY1 NC 44 PIN PLCC Y3 AY2 RESET AX3 AX0 NC NC X6 X7 X8 X9 X10 X11 NC Y7 NC Y6 STROBE Y5 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD Y2 DATA Y1 NC Y0 NC X0 X1 X2 X3 X4 X5 NC NC AY1 AY0 AX2 AX1 Y4 NC NC X6 XY X8 X9 X10 X11 NC NC NC 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 NC AX0 AX3 RESET AY2 Y3 VDD Y2 DATA Y1 Y0 NC NC X0 X1 X2 X3 X4 X5 NC NC NC ISO-CMOS Pin Description Pin # PDIP PLCC MT093 Name 42 43 44 DATA Y2 VDD Description DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. Positive Power Supply. 38 39 40 F unctional Description The MT093 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address input lines (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input line. Data is asynchronously written into memory whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input line will asynchronously return all memory locations to logical “0” turning off all crosspoint switches. A ddress Decode The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of STROBE in order for correct data to be written to the latch. 3-67 MT093 ISO-CMOS Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated. Parameter 1 2 3 4 5 6 Supply Voltage Analog Input Voltage Digital Input Voltage Current on any I/O Pin Storage Temperature Package Power Dissipation PLASTIC DIP Symbol VDD VSS VINA VIN I TS PD -65 Min -0.3 -0.3 -0.3 VSS-0.3 Max 16.0 VDD+0.3 VDD+0.3 VDD+0.3 ±15 +150 0.6 Units V V V V mA °C W * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated. Characteristics 1 2 3 4 Operating Temperature Supply Voltage Analog Input Voltage Digital Input Voltage Sym TO VDD VINA VIN Min 0 4.5 VSS VSS Typ 25 Max 70 14.5 3.5 VDD Units °C V V V Test Conditions DC Electrical Characteristics†Characteristics 1 Quiescent Supply Current Voltages are with respect to VSS=0V, VDD =14V unless otherwise stated. Sym IDDQ Min Typ‡ 1 7 Max 100 15 ±1 0.8 Units µA mA µA V V µA Test Conditions All digital inputs at VIN=VSS or VDD All digital inputs at VIN=2.4V IVXi - VYjI = VDD - VSS 2 3 4 5 Off-state Leakage Current Input Logic “0” level Input Logic “1” level Input Leakage (digital pins) IOFF VIL VIH ILEAK 2.4 10 All digital inputs at VIN = VSS or VDD † DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. DC Electrical Characteristics- Switch Resistance - VIDC/VODC is the external DC offset applied at the analog I/O pins. Characteristics Sym 25°C Typ Max 65 60°C Typ Max 70°C Typ Max 75 Units Test Conditions 1 On-state VDD=14V Resistance RON 45 Ω VSS=0V, IVXi-VYjI = 0.25V VIDC=6.75V VODC=6.5V VDD=14V, VSS=0, VIDC=6.75V VODC=6.5V IVXi-VYjI = 0.25V 2 Difference in on-state resistance between two switches ∆RON 5 10 10 10 Ω 3-68 ISO-CMOS MT093 AC Electrical Characteristics† - Crosspoint Performance-VDC is the external DC offset applied at the analog I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated. Characteristics 1 2 3 Switch I/O Capacitance Feedthrough Capacitance Frequency Response Channel “ON” 20LOG(VOUT/VXi)=-3dB Total Harmonic Distortion Feedthrough Channel “OFF” Feed.=20LOG (VOUT/VXi) Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk=20LOG (VYj/VXi). Sym CS CF F3dB Min Typ‡ 20 0.2 45 Max Units pF pF MHz Test Conditions f=1 MHz f=1 MHz Switch is “ON”; VINA = 2Vpp sinewave; RL = 1kΩ Switch is “ON”; VINA = 2Vpp sinewave f= 1kHz; RL=1kΩ All Switches “OFF”; VINA= 2Vpp sinewave f= 1kHz; RL= 1kΩ. VINA=2Vpp sinewave f= 10MHz; RL = 75Ω. VINA=2Vpp sinewave f= 10kHz; RL = 600Ω. VINA=2Vpp sinewave f= 10kHz; RL = 1kΩ. VINA=2Vpp sinewave f= 1kHz; RL = 10kΩ. RL=1kΩ; CL=50pF 4 5 THD FDT 0.05 -95 % dB 6 Xtalk -45 -90 -85 -80 dB dB dB dB 50 ns 7 Propagation delay through switch tPS † Timing is over recommended temperature range. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better. AC Electrical Characteristics† - Control and I/O Timings- VDC is the external DC offset applied at the analog I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 Control Input crosstalk to switch (for DATA, STROBE, Address) Digital Input Capacitance Switching Frequency Setup Time DATA to STROBE Hold Time DATA to STROBE Setup Time Address to STROBE Hold Time Address to STROBE STROBE Pulse Width RESET Pulse Width STROBE to Switch Status Delay DATA to Switch Status Delay RESET to Switch Status Delay Sym CXtalk CDI FO tDS tDH tAS tAH tSPW tRPW tS tD tR Min Typ‡ 50 10 Max Units mVpp pF Test Conditions VIN=3V+VDC squarewave; RIN=1kΩ, RL=10kΩ. f=1MHz RL= 1kΩ, RL= 1kΩ, RL= 1kΩ, RL= 1kΩ, RL= 1kΩ, RL= 1kΩ, RL= 1kΩ, RL= 1kΩ, RL= 1kΩ, CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF 10 20 20 20 20 40 80 80 100 70 200 200 200 MHz ns ns ns ns ns ns ns ns ns † Timing is over recommended temperature range. Digital Input rise time (tr) and fall time (tf) = 10ns. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. * 3-69 MT093 ISO-CMOS tRPW 50% RESET tSPW 50% tAS ADDRESS 50% 50% tAH DATA 50% tDS ON SWITCH* OFF tD tS tR tR tDH 50% 50% 50% 50% STROBE Figure 3 - Control Memory Timing Diagram AX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 AX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ↓ 0 0 ↓ 0 0 ↓ 0 0 ↓ 0 0 ↓ 0 0 ↓ 0 0 ↓ 0 AX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 AX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 AY0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ↓ 1 0 ↓ 0 1 ↓ 1 0 ↓ 0 1 ↓ 1 0 ↓ 0 1 ↓ 1 AY1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ↓ 0 1 ↓ 1 1 ↓ 1 0 ↓ 0 0 ↓ 0 1 ↓ 1 1 ↓ 1 AY2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ↓ 0 0 ↓ 0 0 ↓ 0 1 ↓ 1 1 ↓ 1 1 ↓ 1 1 ↓ 1 Connection X0-Y0 X1-Y0 X2-Y0 X3-Y0 X4-Y0 X5-Y0 ➀ No Connection ➀ No Connection X6-Y0 X7-Y0 X8-Y0 X9-Y0 X10-Y0 X11-Y0 ➀ No Connection ➀ No Connection X0-Y1 ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ X11-Y1 X0-Y2 X11-Y2 X0-Y3 X11-Y3 X0-Y4 X11-Y4 X0-Y5 X11-Y5 X0-Y6 X11-Y6 X0-Y7 X11-Y7 ➀ T his address has no effect on device status. 3-70 Table 1. Address Decode Truth Table For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. 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