MT8816AE

ISO-CMOS MT8816 8 x 16 Analog Switch Array Data Sheet Features • • • • • • • • • • Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5 V to 13.2 V 12Vpp analog signal capability RON 65 Ω max. @ VDD = 12 V, 25°C ∆RON ≤10 Ω @ VDD = 12 V, 25°C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Separate analog and digital reference supplies Low power consumption ISO-CMOS technology Ordering Information MT8816AE MT8816AP MT8816APR MT8816AP1 MT8816APR1 MT8816AE1 40 44 44 44 44 40 Pin Pin Pin Pin Pin Pin PDIP PLCC PLCC PLCC* PLCC* PDIP* February 2005 Tubes Tubes Tape & Reel Tubes Tape & Reel Tubes * Pb Free Matte Tin -40°C to +85 °C Description The Zarlink MT8816 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 16 array of crosspoint switches along with a 7 to 128 line decoder and latch circuits. Any one of the 128 switches can be addressed by selecting the appropriate seven address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion. Applications • • • • • • Key systems PBX systems Mobile radio Test equipment/instrumentation Analog/digital multiplexers Audio/Video switching CS STROBE DATA RESET VDD VEE VSS AX0 AX1 AX2 AX3 AY0 AY1 AY2 1 1 •••••••••••••••• 7 to 128 Decoder Latches 8 x 16 Switch Array 128 ••••••••••••••••••• Xi I/O (i=0-15) 128 Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT8816 AX3 RESET AY2 Y3 VDD Y2 DATA Y1 CS Data Sheet 40 PIN PLASTIC DIP Figure 2 - Pin Connections Pin Description Pin # PDIP PLCC Name 1 2 3 4,5 7,8 Y3 AY2 RESET Description Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. Y2 Address Line (Input). Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. Active High. 1 2 3 4,5 6,7 8-13 14 15 16 17 18 AX3,AX0 X3 and X0 Address Lines (Inputs). X14, X15 X14 and X15 Analog (Inputs/Outputs): these are connected to the X14 and X15 rows of the switch array. X6-X11 NC Y7 VSS Y6 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. No Connection Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. Digital Ground Reference. Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 9-14 6,15,16 17 18 19 20 STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. Y5 VEE Y4 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. Negative Power Supply. Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. 19 20 21 22, 23 21 22 23 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs). 2 Zarlink Semiconductor Inc. VSS Y6 STROBE Y5 VEE Y4 AX1 AX2 AY0 AY1 NC 44 PIN PLCC Y3 AY2 RESET AX3 AX0 X14 X15 X6 X7 X8 X9 X10 X11 NC Y7 VSS Y6 STROBE Y5 VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD Y2 DATA Y1 CS Y0 NC X0 X1 X2 X3 X4 X5 X12 X13 AY1 AY0 AX2 AX1 Y4 X14 X15 X6 X7 X8 X9 X10 X11 NC NC Y7 NC AX0 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 Y0 NC X0 X1 X2 X3 X4 X5 X12 X13 NC MT8816 Pin Description (continued) Pin # PDIP PLCC Data Sheet Name Description 24, 25 26, 27 28 - 33 34 35 36 37 38 39 40 26,27 30,31 32-37 28,29, 38 39 40 41 42 43 44 AY0,AY1 Y0 and Y1 Address Lines (Inputs). X13, X12 X13 and X12 Analog (Inputs/Outputs): these are connected to the X13 and X12 rows of the switch array. X5-X0 NC Y0 CS Y1 DATA Y2 VDD X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. No Connection. Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. Chip Select (Input): this is used to select the device. Active High. Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. Positive Power Supply. 3 Zarlink Semiconductor Inc. MT8816 Functional Description Data Sheet The MT8816 is an analog switch matrix with an array size of 8 x 16. The switch array is arranged such that there are 8 columns by 16 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 128 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs are high and are latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return all memory locations to logical “0” turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (VSS and VEE) are provided for the MT8816 to enable switching of negative analog signals. The range for digital signals is from VDD to VSS while the range for analog signals is from VDD to VEE. VSS and VEE pins can be tied together if a single voltage reference is needed. Address Decode The seven address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch. 4 Zarlink Semiconductor Inc. MT8816 Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated. Parameter 1 2 3 4 5 Supply Voltage Analog Input Voltage Digital Input Voltage Current on any I/O Pin Storage Temperature Symbol VDD VSS VINA VIN I TS -65 Min. -0.3 -0.3 -0.3 VSS-0.3 Data Sheet Max. 16.0 VDD+0.3 VDD+0.3 VDD+0.3 ±15 +150 0.6 Units V V V V mA °C W 6 Package Power Dissipation PLASTIC DIP PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics 1 2 3 4 Operating Temperature Supply Voltage Analog Input Voltage Digital Input Voltage Sym. TO VDD VSS VINA VIN Min. -40 4.5 VEE VEE VSS Typ. 25 Max. 85 13.2 VDD-4.5 VDD VDD Units °C V V V V Test Conditions DC Electrical Characteristics†- Voltages are with respect to VEE = VSS = 0 V, VDD =12 V unless otherwise stated. Characteristics 1 Quiescent Supply Current Sym. IDD Min. Typ.‡ 1 0.4 5 2 3 4 5 6 Off-state Leakage Current (See G.9 in Appendix) Input Logic “0” level Input Logic “1” level Input Logic “1” level Input Leakage (digital pins) IOFF VIL VIH VIH ILEAK 2.0+VSS Max. 100 1.5 15 ±500 0.8+VS S Units µA mA mA nA V V V Test Conditions All digital inputs at VIN=VSS or VDD All digital inputs at VIN=2.4V + VSS; VSS=7.0 V All digital inputs at VIN=3.4 V IVXi - VYjI = VDD - VEE See Appendix, Fig. A.1 VSS=7.5V; VEE=0 V VSS=6.5V; VEE=0 V All digital inputs at VIN = VSS or VDD ±1 3.3 0.1 10 µA † DC Electrical Characteristics are over recommended temperature range. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. 5 Zarlink Semiconductor Inc. MT8816 DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins. Characteristics Sym. 25°C Typ. Max. 70°C Typ. Max. 85°C Typ. Max. Units Data Sheet Test Conditions 1 On-state VDD=12V Resistance VDD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) Difference in on-state resistance between two switches (See G.4 in Appendix) RON 45 55 120 65 75 185 75 85 215 80 90 225 Ω Ω Ω VSS=VEE=0 V,VDC=VDD/2, IVXi-VYjI = 0.4 V See Appendix, Fig. A.2 2 ∆RON 5 10 10 10 Ω VDD=12V, VSS=VEE=0, VDC=VDD/2, IVXi-VYjI = 0.4 V See Appendix, Fig. A.2 otherwise stated. AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to VDD= 5 V, VSS= 0 V, VEE= -7 V, unless Characteristics 1 2 3 Switch I/O Capacitance Feedthrough Capacitance Frequency Response Channel “ON” 20LOG(VOUT/VXi)=-3 dB Total Harmonic Distortion (See G.5, G.6 in Appendix) Feedthrough Channel “OFF” Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix). -80 dB Sym. CS CF F3dB Min. Typ.‡ 20 0.2 45 Max. Units pF pF MHz Test Conditions f=1 MHz f=1 MHz Switch is “ON”; VINA = 2Vpp sinewave; RL = 1 kΩ See Appendix, Fig. A.3 Switch is “ON”; VINA = 2Vpp sinewave f= 1 kHz; RL=1 kΩ All Switches “OFF”; VINA= 2Vpp sinewave f= 1 kHz; RL= 1 kΩ. See Appendix, Fig. A.4 VINA=2Vpp sinewave f= 10 MHz; RL = 75 Ω. VINA=2Vpp sinewave f= 10 kHz; RL = 600 Ω. VINA=2Vpp sinewave f= 10 kHz; RL = 1 kΩ. VINA=2Vpp sinewave f= 1 kHz; RL = 10 kΩ. Refer to Appendix, Fig. A.5 for test circuit. RL=1 kΩ; CL=50 pF 4 5 THD FDT 0.01 -95 % dB 6 Xtalk -45 -90 -85 dB dB dB 7 Propagation delay through switch tPS 30 ns † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better. 6 Zarlink Semiconductor Inc. MT8816 otherwise stated. Data Sheet AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD = 5 V, VSS = 0 V, VEE = -7V, unless Characteristics 1 Control Input crosstalk to switch (for CS, DATA, STROBE, Address) Digital Input Capacitance Switching Frequency Setup Time DATA to STROBE Hold Time DATA to STROBE Setup Time Address to STROBE Hold Time Address to STROBE Setup Time CS to STROBE Hold Time CS to STROBE STROBE Pulse Width RESET Pulse Width STROBE to Switch Status Delay DATA to Switch Status Delay RESET to Switch Status Delay Sym. CXtalk Min. Typ.‡ 30 Max. Units mVpp Test Conditions VIN=3 V squarewave; RIN=1 kΩ, RL=10 kΩ. See Appendix, Fig. A.6 f=1 MHz 2 3 4 5 6 7 8 9 10 11 12 13 14 CDI FO tDS tDH tAS tAH tCSS tCSH tSPW tRPW tS tD tR 10 10 10 10 10 10 20 40 10 20 pF MHz ns ns ns ns ns ns ns ns RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, RL= 1 kΩ, CL=50 pF CL=50 pF CL= 50pF CL=50 pF CL=50 pF CL=50 pF CL=50 pF CL=50 pF CL=50 pF CL=50 pF CL=50 pF ¿ ¿ ¿ ¿ ¿ ¿ ¿ ¿ ¿ ¿ ¿ 40 50 35 100 100 100 ns ns ns † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5 ns. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. ¿ Refer to Appendix, Fig. A.7 for test circuit. 7 Zarlink Semiconductor Inc. MT8816 Data Sheet tCSS 50% tCSH 50% tRPW 50% tSPW 50% 50% 50% 50% CS RESET STROBE tAS ADDRESS 50% 50% tAH DATA 50% tDS ON OFF tD tDH 50% SWITCH* tS tR tR Figure 3 - Control Memory Timing Diagram * See Appendix, Fig. A.7 for switching waveform 8 Zarlink Semiconductor Inc. MT8816 AX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 Data Sheet AY1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ↓ 0 1 ↓ 1 1 ↓ 1 0 ↓ 0 0 ↓ 0 1 ↓ 1 1 ↓ 1 AX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 AX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 AX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 0 ↓ 1 AY0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ↓ 1 0 ↓ 0 1 ↓ 1 0 ↓ 0 1 ↓ 1 0 ↓ 0 1 ↓ 1 AY2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ↓ 0 0 ↓ 0 0 ↓ 0 1 ↓ 1 1 ↓ 1 1 ↓ 1 1 ↓ 1 Connection* X0-Y0 X1-Y0 X2-Y0 X3-Y0 X4-Y0 X5-Y0 X12-Y0 X13-Y0 X6-Y0 X7-Y0 X8-Y0 X9-Y0 X10-Y0 X11-Y0 X14-Y0 X15-Y0 X0-Y1 ↓↓ X15-Y1 X0-Y2 ↓↓ X15-Y2 X0-Y3 ↓↓ X15-Y3 X0-Y4 ↓↓ X15-Y4 X0-Y5 ↓↓ X15-Y5 X0-Y6 ↓↓ X15-Y6 X0-Y7 ↓↓ X15-Y7 Table 1 - Address Decode Truth Table * Switch connections are not in ascending order 9 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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