MT8889C

MT8889C Integrated DTMF Transceiver with Adaptive Micro Interface F eatures • • • • • • Central office quality DTMF transmitter/ receiver Low power consumption High speed adaptive micro interface Adjustable guard time Automatic tone burst mode Call progress tone detection to -30dBm DS5433 ISSUE 7 March 2001 O rdering Information MT8889CE 20 Pin Plastic DIP MT8889CS 20 Pin SOIC MT8889CN 24 Pin SSOP -40°C to +85°C Applications • • • • • Credit card systems Paging systems Repeater systems/mobile radio Interconnect dialers Personal computers The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT8889C utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. Description The MT8889C is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability. F unctional Description The MT8889C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain setting amplifier and a DTMF generator, TONE ∑ D/A Converters Row and Column Counters Transmit Data Register Status Register Data Bus Buffer D0 D1 D2 D3 Tone Burst Gating Cct. IN+ INGS OSC1 OSC2 Oscillator Circuit Bias Circuit VDD VRef VSS + Dial Tone Filter Control Logic Interrupt Logic IRQ/CP High Group Filter Low Group Filter Control Logic Digital Algorithm and Code Converter Control Register A Control Register B I/O Control DS/RD CS R/W/WR RS0 Steering Logic Receive Data Register ESt St/GT Figure 1 - Functional Block Diagram 1 MT8889C IN+ INGS VRef VSS OSC1 OSC2 TONE R/W/WR CS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD St/GT ESt D3 D2 D1 D0 IRQ/CP DS/RD RS0 IN+ INGS VRef VSS OSC1 OSC2 NC NC TONE R/W/WR CS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD St/GT ESt D3 D2 D1 D0 NC NC IRQ/CP DS/RD RS0 20 PIN PLASTIC DIP/SOIC 24 PIN SSOP Figure 2 - Pin Connections Pin Description Pin # 20 1 2 3 4 5 6 7 8 9 10 11 12 13 24 1 2 3 4 5 6 7 10 11 12 13 14 15 Name IN+ INGS VRef VSS Non-inverting op-amp input. Inverting op-amp input. Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage output (VDD/2). Ground (0V). Description OSC1 DTMF clock/oscillator input. Connect a 4.7MΩ resistor to VSS if crystal oscillator is used. OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. TONE Output from internal DTMF transmitter. R/W (Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible. (WR) CS RS0 DS (RD) Chip Select input. This signal must be qualified externally by either address strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12. Register Select input. Refer to Table 3 for bit interpretation. TTL compatible. (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only required when the device is being accessed. TTL compatible. IRQ/ Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes CP low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter, see Figure 8. D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1 (Intel). TTL compatible. ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 1417 18 18-21 22 19 23 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. VDD NC Positive power supply (5V typical). No Connection. 20 24 8, 9, 16,17 2 MT8889C which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected. The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the MT8889C internal registers. C1 R1 IN+ INC2 R4 R5 GS Input Configuration The input arrangement of the MT8889C provides a differential-input operational amplifier as well as a bias source (VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 3. Figure 4 shows the necessary connections for a differential input configuration. R3 R2 VRef MT8889C DIFFERENTIAL INPUT AMPLIFIER C1 = C2 = 10 nF R1 = R4 = R5 = 100 kΩ R2 = 60kΩ, R3 = 37.5 kΩ R3 = (R2R5)/(R2 + R5) VOLTAGE GAIN (AV diff) - R5/R1 INPUT IMPEDANCE (ZINdiff) = 2 R12 + (1/ωC)2 Receiver Section Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals. IN+ Figure 4 - Differential Input Configuration FLOW FHIGH DIGIT D3 D2 D1 D0 697 697 697 770 770 770 852 852 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 1 2 3 4 5 6 7 8 9 0 * # A B C D 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 C RIN IN- RF GS 852 941 VRef VOLTAGE GAIN (AV) = RF / RIN MT8889C 941 941 697 770 852 941 Figure 3 - Single-Ended Input Configuration 0 = LOGIC LOW, 1= LOGIC HIGH Table 1. Functional Encode/Decode Table 3 MT8889C Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state. VDD MT8889C VDD St/GT ESt R1 C1 Vc tGTA = (R1C1) In (VDD / VTSt) tGTP = (R1C1) In [VDD / (VDD-VTSt)] F igure 5 - Basic Steering Circuit G uard Time Adjustment The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7): t REC ≥ t DPmax + t GTPmax - t DAmin t REC ≤ t DPmin + t GTPmin - t DAmax t ID ≥ t DAmax + t GTAmax - t DPmin t DO ≤ t DAmin + t GTAmin - t DPmax The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most tGTP = (RPC1) In [VDD / (VDD-VTSt)] tGTA = (R1C1) In (VDD/VTSt) VDD C1 St/GT RP = (R1R2) / (R1 + R2) Steering Circuit Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. R1 ESt R2 a) decreasing tGTP; (tGTP < tGTA) tGTP = (R1C1) In [VDD / (VDD-VTSt)] VDD C1 St/GT tGTA = (RpC1) In (VDD/VTSt) RP = (R1R2) / (R1 + R2) R1 ESt R2 b) decreasing tGTA; (tGTP > tGTA) F igure 6 - Guard Time Adjustment 4 MT8889C applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independent tone present (tGTP) and tone absent (tGTA) guard times. This may be necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 9. DTMF signals cannot be detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the filter, are hardlimited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and consequently the IRQ/CP pin will remain low. LEVEL (dBm) -25 Call Progress Filter A call progress mode, using the MT8889C, can be selected allowing the detection of various tones, which identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common, however, call progress tones can only be detected when CP mode has been selected. EVENTS tREC Vin tDP ESt tGTP A tREC TONE #n tDA B tID C 0 = Reject 250 500 750 FREQUENCY (Hz) = May Accept = Accept Figure 8 - Call Progress Response D tDO TONE #n + 1 E F TONE #n + 1 tGTA VTSt tPStRX St/GT RX0-RX3 DECODED TONE # (n-1) #n tPStb3 # (n + 1) b3 b2 Read Status Register IRQ/CP Figure 7 - Receiver Timing Diagram 5 MT8889C EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. EXPLANATION OF SYMBOLS Vin DTMF COMPOSITE INPUT SIGNAL. ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. 4-BIT DECODED DATA IN RECEIVE DATA REGISTER RX 0-RX 3 b3 DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL. b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ. INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS IRQ/CP CLEARED AFTER THE STATUS REGISTER IS READ. tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. tID MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS. MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. tDO tDP TIME TO DETECT VALID FREQUENCIES PRESENT. tDA TIME TO DETECT VALID FREQUENCIES ABSENT. tGTP GUARD TIME, TONE PRESENT. tGTA GUARD TIME, TONE ABSENT. Figure 9 - Description of Timing Events DTMF Generator The DTMF transmitter employed in the MT8889C is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB to com-pensate for high group attenuation on long loops. The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During 6 write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM. The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 6 that the distortion products are very low in amplitude. MT8889C Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz Figure 10 - Spectrum Plot Burst Mode ACTIVE INPUT OUTPUT FREQUENCY (Hz) SPECIFIED ACTUAL %ERROR In certain telephony applications it is required that DTMF signals being generated are of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms±1 ms which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register indicating that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode) is selected, the burst/pause duration is doubled to 102 ms ±2 ms. Note that when CP mode and Burst mode have been selected, DTMF tones may be transmitted only and not received. In applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter. L1 L2 L3 L4 H1 H2 H3 H4 697 770 852 941 1209 1336 1477 699.1 766.2 847.4 948.0 1215.9 1331.7 1471.9 +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 1633 1645.0 +0.73 Table 2. Actual Frequencies Versus Standard Requirements Distortion Calculations The MT8889C is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The internal summing amplifier is followed by a firstorder lowpass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated using Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. Single Tone Generation A single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B description for details. V22f + V23f + V24f + .... V2nf THD (%) = 100 Vfundamental Equation 1. THD (%) For a Single Tone 7 MT8889C The Fourier components of the tone output correspond to V2f.... Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated using Equation 2. VL and VH correspond to the low group amplitude and high group amplitude, respectively and V2IMD is the sum of all the intermodulation components. The internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as shown in Figure 10. V22L + V23L + .... V2nL + V22H + V23H + .. V2nH + V2IMD THD (%) = 100 V2L + V2H kinds of microprocessors. Key functions of this interface include the following: • • Continuous activity on DS/RD is not necessary to update the internal status registers. senses whether input timing is that of an Intel or Motorola controller by monitoring the DS (RD), R/W ( WR) and CS inputs. generates equivalent CS s ignal for internal operation for all processors. differentiates between multiplexed and nonmultiplexed microprocessor buses. Address and data are latched in accordingly. compatible with Motorola and Intel processors. • • • Equation 2. THD (%) For a Dual Tone DTMF Clock Circuit The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal specification is as follows: Frequency: 3.579545 MHz Frequency Tolerance: ±0.1% Resonance Mode: Parallel Load Capacitance: 18pF Maximum Series Resistance:150 ohms Maximum Drive Level: 2mW e.g. CTS Knights MP036S Toyocom TQC-203-A-9S Figure 17 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the MC6809, the chip select (CS) input signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800 and MC6802, CS is formed by NANDing VMA and address decode output. On the falling edge of CS, the internal logic senses the state of data strobe (DS). When DS is low, Motorola processor operation is selected. Figure 18 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS) input is formed by NANDing address strobe (AS) and address decode output. Again, the MT8889C examines the state of DS on the falling edge of CS to determine if the micro has a Motorola bus (when DS is low). Additionally, the Texas Instruments TMS370CX5X is qualified to have a Motorola interface. Figure 12(a) summarizes connection of these Motorola processors to the MT8889C DTMF transceiver. Figures 19 and 20 are the timing diagrams for the Intel 8031/8051 (12 MHz) and 8085 (5 MHz) microcontrollers with multiplexed address and data buses. The MT8889C latches in the state of RD on the falling edge of CS. When RD is high, Intel processor operation is selected. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS can be generated. Figure 12(b) summarizes the connection of these Intel processors to the MT8889C transceiver. NOTE: The adaptive micro interface relies on highto-low transition on CS to recognize the microcontroller interface and this pin must not be tied permanently low. A number of MT8889C devices can be connected as shown in Figure 11 such that only one crystal is required. Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left unconnected. MT8889C OSC1 OSC2 MT8889C OSC1 OSC2 MT8889C OSC1 OSC2 3.579545 MHz Figure 11 - Common Crystal Connection Microprocessor Interface The MT8889C design incorporates an adaptive interface, which allows it to be connected to various 8 MT8889C The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-only status register indicates the current transceiver state (see Table 8). A software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see Figure 15). Refer to Tables 4-7 for bit descriptions of the two control registers. The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external pull-up resistor (see Figure 13). Motorola RS0 R/W Intel WR RD FUNCTION Write to Transmit Data Register Read from Receive Data Register Write to Control Register Read from Status Register 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 Table 3. Internal Register Functions b3 RSEL b2 IRQ b1 CP/DTMF b0 TOUT Table 4. CRA Bit Positions b3 C/R b2 S/D b1 TEST b0 BURST ENABLE Table 5. CRB Bit Positions MC6800/6802 A0-A15 MT8889 CS RS0 MC68HC11 A8-A15 AS AD0-AD3 DS RW MT8889C CS D0-D3 RS0 DS/RD R/W/WR VMA D0-D3 RW Φ2 (a) D0-D3 R/W/WR DS/RD MC6809 A0-A15 Q E D0-D3 R/W MT8889 8031/8051 8080/8085 MT8889C CS RS0 A8-A15 CS D0-D3 RS0 DS/RD R/W/WR (b) ALE D0-D3 R/W/WR DS/RD P0 RD WR Figure 12 a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros 9 MT8889C BIT b0 b1 NAME TOUT CP/DTMF DESCRIPTION Tone Output Control. A logic high enables the tone output; a logic low turns the tone output off. This bit controls all transmit tone functions. Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode; a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and transmitting DTMF signals. In CP mode a retangular wave representation of the received tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control register A, b2=1). In order to be detected, CP signals must be within the bandwidth specified in the AC Electrical Characteristics for Call Progress. Note: DTMF signals cannot be detected when CP mode is selected. Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the interrupt function. When IRQ is enabled and DTMF mode is selected (control register A, b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been received for a valid guard time duration, or 2) the transmitter is ready for more data (burst mode only). Register Select. A logic high selects control register B for the next write cycle to the control register address. After writing to control register B, the following control register write cycle will be directed to control register A. Table 6. Control Register A Description b2 IRQ b3 RSEL BIT b0 NAME BURST DESCRIPTION Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. When activated, the digital code representing a DTMF signal (see Table 1) can be written to the transmit register, which will result in a transmit DTMF tone burst and pause of equal durations (typically 51 msec). Following the pause, the status register will be updated (b1 Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been enabled. When CP mode (control register A, b1) is enabled the normal tone burst and pause durations are extended from a typical duration of 51 msec to 102 msec. When BURST is high (de-activated) the transmit tone burst duration is determined by the TOUT bit (control register A, b0). b1 TEST Test Mode Control. A logic high enables the test mode; a logic low de-activates the test mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the signal present on the IRQ/CP pin will be analogous to the state of the DELAYED STEERING bit of the status register (see Figure 7, signal b3). Single or Dual Tone Generation. A logic high selects the single tone output; a logic low selects the dual tone (DTMF) output. The single tone generation function requires further selection of either the row or column tones (low or high group) through the C/R bit (control register B, b3). Column or Row Tone Select. A logic high selects a column tone output; a logic low selects a row tone output. This function is used in conjunction with the S/D bit (control register B, b2). Table 7. C ontrol Register B Description b2 S/D b3 C/R 10 MT8889C BIT b0 b1 NAME IRQ TRANSMIT DATA REGISTER EMPTY (BURST MODE ONLY) RECEIVE DATA REGISTER FULL DELAYED STEERING STATUS FLAG SET Interrupt has occurred. Bit one (b1) or bit two (b2) is set. Pause duration has terminated and transmitter is ready for new data. Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. STATUS FLAG CLEARED Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode. Cleared after Status Register is read. Cleared upon the detection of a valid DTMF signal. b2 b3 Table 8. S tatus Register Description VDD MT8880C C1 DTMF/CP INPUT R2 R1 IN+ INGS VRef VSS OSC1 R5 X-tal DTMF OUTPUT C4 RL OSC2 TONE R/W/WR CS Notes: R1, R2 = 100 kΩ 1% R3 = 374 kΩ 1% R4 = 3.3 kΩ 10% R5 = 4.7 MΩ 10% RL = 10 k Ω (min.) C1 = 100 nF 5% C2 = 100 nF 5% C3 = 100 nF 10%* C4 = 10 nF 10% X-tal = 3.579545 MHz VDD St/GT ESt D3 D2 D1 D0 IRQ/CP DS/RD RS0 To µP or µC R3 C2 R4 C3 * Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8889C can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. Figure 13 - Application Circuit (Single-Ended Input) 11 MT8889C 5.0 VDC MMD6150 (or equivalent) 2.4 kΩ 5.0 VDC TEST POINT 3 kΩ TEST POINT 130 pF 24 kΩ MMD7000 (or equivalent) 100 pF Test load for D0-D3 pins Test load for IRQ/CP pin Figure 14 - Test Circuits INITIALIZATION PROCEDURE A software reset must be included at the beginning of all programs to initialize the control registers after power up. The initialization procedure should be implemented 100ms after power up. Description: Motorola Intel Data RS0 R/W WR RD b3 b2 b1 b0 1) Read Status Register 1 1 1 0 X X X X 2) Write to Control Register 1 0 0 1 0 0 0 0 3) Write to Control Register 1 0 0 1 0 0 0 0 4) Write to Control Register 1 0 0 1 1 0 0 0 5) Write to Control Register 1 0 0 1 0 0 0 0 6) Read Status Register 1 1 1 0 X X X X TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones. Sequence: RS0 1) Write to Control Register A 1 (tone out, DTMF, IRQ, Select Control Register B) 2) Write to Control Register B 1 (burst mode) 3) Write to Transmit Data Register 0 (send a digit 7) 4) Wait for an Interrupt or Poll Status Register 5) Read the Status Register 1 R/W 0 0 0 WR RD 0 1 0 0 1 1 b3 1 0 0 b2 1 0 1 b1 0 0 1 b0 1 0 1 1 1 0 X X X X -if bit 1 is set, the Tx is ready for the next tone, in which case ... Write to Transmit Register 0 0 0 (send a digit 5) -if bit 2 is set, a DTMF tone has been received, in which case .... Read the Receive Data Register 0 1 1 -if both bits are set ... Read the Receive Data Register Write to Transmit Data Register 1 0 1 0 1 0 X X X X 0 0 1 0 1 0 0 1 X 0 X 1 X 0 X 1 NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms ( ±2 ms) AFTER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms) Figure 15 - Application Notes 12 MT8889C Absolute Maximum Ratings* Parameter 1 2 3 4 5 Power supply voltage VDD-VSS Voltage on any pin Current at any pin (Except VDD and VSS) Storage temperature Package power dissipation TST PD -65 Symbol VDD VI VSS-0.3 Min Max 6 VDD+0.3 10 +150 1000 Units V V mA °C mW * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Parameter 1 2 Positive power supply Operating temperature Sym VDD TO Min 4.75 -40 Typ‡ 5.00 Max 5.25 +85 Units V °C Test Conditions 3 Crystal clock frequency fCLK 3.575965 3.579545 3.583124 MHz ‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics† Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D i g i t a l Data Bus ESt and St/GT IRQ/ CP O U T P U T S S U P I N P U T S VSS=0 V. Sym VDD IDD PC VIHO VILO VTSt VOLO VOHO IOZ VRef ROR VIL VIH IIZ Min 4.75 Typ‡ 5.0 7.0 Max 5.25 11 57.8 Units V mA mW V Test Conditions Operating supply voltage Operating supply current Power consumption High level input voltage (OSC1) Low level input voltage (OSC1) Steering threshold voltage Low level output voltage (OSC2) High level output voltage (OSC2) Output leakage current (IRQ) VRef output voltage VRef output resistance Low level input voltage High level input voltage Input leakage current 3.5 1.5 2.2 2.3 2.5 0.1 4.9 1 2.4 2.5 1.3 0.8 2.0 10 10 2.6 Note 9* Note 9* VDD=5V No load Note 9* No load Note 9* VOH=2.4 V No load, VDD=5V V V V V µA V kΩ V V µA VIN=VSS to VDD 15 16 17 18 19 Source current Sink current Source current Sink current Sink current IOH IOL IOH IOL IOL -1.4 2.0 -0.5 2 4 -6.6 4.0 -3.0 4 16 mA mA mA mA mA VOH=2.4V VOL=0.4V VOH=4.6V VOL=0.4V VOL=0.4V † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing. * See “Notes” following AC Electrical Characteristics Tables. 13 MT8889C Electrical Characteristics Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V. Characteristics 1 2 3 4 5 6 7 8 9 Input leakage current Input resistance Input offset voltage Power supply rejection Common mode rejection DC open loop voltage gain Unity gain bandwidth Output voltage swing Allowable capacitive load (GS) Sym IIN RIN VOS PSRR CMRR AVOL BW VO CL RL 50 50 40 40 1.0 0.5 VDD-0.5 100 10 25 Min Typ Max 100 Units nA MΩ mV dB dB dB MHz V pF kΩ V CL = 20p CL = 20p RL ≥ 100 kΩ to VSS PM>40° VO = 4Vpp RL = 50kΩ 1 kHz Test Conditions VSS ≤ VIN ≤ VDD 10 Allowable resistive load (GS) 11 Common mode range VCM 1.0 VDD-1.0 Figures are for design aid only: not guaranteed and not subject to production testing. Characteristics are over recommended operating conditions unless otherwise stated. MT8889C AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 R X Valid input signal levels (each tone of composite signal) Sym Min -29 27.5 Typ‡ Max +1 869 Units dBm mVRMS Notes* 1,2,3,5,6 1,2,3,5,6 † Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13. AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 R X Positive twist accept Negative twist accept Freq. deviation accept Freq. deviation reject Third tone tolerance Noise tolerance Dial tone tolerance ±1.5%± 2Hz ±3.5% -16 -12 22 dB dB dB Sym Min Typ‡ Max 8 8 Units dB dB fC=3.579545 MHz Notes* 2,3,6,9 2,3,6,9 2,3,5 2,3,5 2,3,4,5,9,10 2,3,4,5,7,9,10 2,3,4,5,8,9 † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing. * *See “Notes” following AC Electrical Characteristics Tables. 14 MT8889C AC Electrical Characteristics†- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated. Characteristics 1 2 3 4 Accept Bandwidth Lower freq. (REJECT) Upper freq. (REJECT) Call progress tone detect level (total power) Sym fA fLR fHR -30 Min 310 290 540 Typ‡ Max 500 Units Hz Hz Hz dBm Conditions @ -25 dBm, Note 9 @ -25 dBm @ -25 dBm † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing AC Electrical Characteristics†- DTMF Reception - Typical DTMF tone accept and reject requirements. values are user selectable as per Figures 5, 6 and 7. Actual Characteristics 1 2 3 Minimum tone accept duration Maximum tone reject duration Minimum interdigit pause duration Sym tREC tREC tID Min Typ‡ 40 20 40 Max Units ms ms ms Conditions 4 Maximum tone drop-out duration tDO 20 ms † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing AC Electrical Characteristics† - Voltages are with respect to ground (VSS), unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 X T A L T O N E O U T T O N E I N Sym tDP tDA tPStb3 tPStRX tBST tPS tBSTE tPSE VHOUT VLOUT dBP THD fD RLT fC tCLRF DCCL Min 3 0.5 Typ‡ 11 4 13 8 Max 14 8.5 Units ms ms µs µs Conditions Note 11 Note 11 See Figure 7 See Figure 7 DTMF mode DTMF mode Call Progress mode Call Progress mode RL=10kΩ RL=10kΩ RL=10kΩ 25 kHz Bandwidth RL=10kΩ fC=3.579545 MHz Tone present detect time Tone absent detect time Delay St to b3 Delay St to RX0-RX3 Tone burst duration Tone pause duration Tone burst duration (extended) Tone pause duration (extended) High group output level Low group output level Pre-emphasis Output distortion (Single Tone) Frequency deviation Output load resistance Crystal/clock frequency Clock input rise and fall time Clock input duty cycle 50 50 100 100 -6.1 -8.1 0 2 -35 ±0.7 10 52 52 104 104 -2.1 -4.1 3 ms ms ms ms dBm dBm dB dB ±1.5 50 110 % kΩ MHz ns % 3.5759 3.5795 3.5831 40 50 60 Ext. clock Ext. clock 19 Capacitive load (OSC2) CLO 30 pF † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing. 15 MT8889C AC Electrical Characteristics†- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DS/RD/WR clock frequency DS/RD/WR cycle period DS/RD/WR low pulse width DS/RD/WR high pulse width DS/RD/WR rise and fall time R/W setup time R/W hold time Address setup time (RS0) Address hold time (RS0) Data hold time (read) DS/RD to valid data delay (read) Data setup time (write) Data hold time (write) Chip select setup time Chip select hold time Input Capacitance (data bus) Output Capacitance (IRQ/CP) Sym fCYC tCYC tCL tCH tR,tF tRWS tRWH tAS tAH tDHR tDDR tDSW tDHW tCSS tCSH CIN COUT 45 10 45 40 5 5 35 23 20 0 40 22 100 20 150 100 20 Min Typ‡ 4.0 250 Max Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF Conditions Figure 16 Figure 16 Figure 16 Figure 16 Figure 16 Figures 17 & 18 Figures 17 & 18 Figures 17 - 20 Figures 17 - 20 Figures 17 - 20 Figures 17 - 20 Figures 17 - 20 Figures 17 - 20 Figures 17 - 20 Figures 17 - 20 † Characteristics are over recommended operating conditions unless otherwise stated ‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load. 2) D igit sequence consists of all 16 DTMF tones. 3) Tone duration=40 ms. Tone pause=40 ms. 4) N ominal DTMF frequencies are used. 5) Both tones in the composite signal have an equal amplitude. 6) The tone pair is deviated by ± 1.5 % ±2 Hz. 7) Bandwidth limited (3 kHz) Gaussian noise. 8) The precise dial tone frequencies are 350 and 440 Hz ( ±2 %). 9) Guaranteed by design and characterization. Not subject to production testing. 10) R eferenced to the lowest amplitude tone in the DTMF signal. 11) For guard time calculation purposes. tCYC tR DS/RD/WR tCH tF tCL Figure 16 - DS/RD/WR Clock Pulse 16 MT8889C tRWS DS tRWH Q clk* A0-A15 (RS0) R/W(read) 16 bytes of Addr tDDR Read Data (D3-D0) tDHR R/W (write) tDSW➀ Write data (D3-D0) tCSS tAH CS = (E + Q).Addr [MC6809] CS = VMA.Addr [MC6800, MC6802] *microprocessor pin tAS tAH tAS tCSS tCSH➀ tDHW tCSH➀ Figure 17 - MC6800/MC6802/MC6809 Timing Diagram ➀ tDSW i s from data to DS falling edge; t CSH is from DS rising edge to CS r ising edge tRWS DS tRWH R/W tAS Read AD3-AD0 (RS0, D0-D3) Write AD3-AD0 (RS0-D0-D3) tAH Addr * non-mux High Byte of Addr Addr tDDR tDHR Data Addr tDSW tCSH Data tDHW AS * CS = AS.Addr tCSS * microprocessor pins Figure 18 - MC68HC11 Bus Timing (with multiplexed address and data buses) 17 MT8889C tCSS ALE* RD tAS P0* (RS0, D0-D3) P2 * (Addr) tAH A0-A7 tDDR Data tDHR A8-A15 Address tCSH CS = ALE.Addr * microprocessor pins Figure 19 - 8031/8051/8085 Read Timing Diagram ALE* tCSS WR tDSW tDHW Data tAS P0* (RS0, D0-D3) P2 * (Addr) tAH A0-A7 A8-A15 Address tCSH CS = ALE.Addr * microprocessor pins Figure 20 - 8031/8051/8085 Write Timing Diagram 18 Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A C eA e b eB eC Plastic Dual-In-Line Packages (PDIP) - E Suffix 8-Pin DIM Min A A2 b b2 C D D1 E E1 e eA L eB eC 0 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.355 (9.02) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 16-Pin Plastic Max Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.780 (19.81) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014(0.356) 0.800 (20.32) 18-Pin Plastic Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.880 (22.35) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.920 (23.37) 20-Pin Plastic Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.980 (24.89) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 1.060 (26.9) Plastic 0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.400 (10.16) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) NOTE: Controlling dimensions in parenthesis ( ) are in millimeters. General-8 Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) α A C eA e b eB Plastic Dual-In-Line Packages (PDIP) - E Suffix 22-Pin DIM Min A A2 b b2 C D D1 E E E1 E1 e eA eA eB L α 0.115 (2.93) 0.160 (4.06) 15° 0.100 BSC (2.54) 0.400 BSC (10.16) 0.330 (8.39) 0.380 (9.65) 0.125 (3.18) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 1.050 (26.67) 0.005 (0.13) 0.390 (9.91) 0.430 (10.92) 24-Pin Plastic Max Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.150 (29.3) 0.005 (0.13) 0.600 (15.24) 0.290 (7.37) 0.485 (12.32) 0.246 (6.25) 0.670 (17.02) .330 (8.38) 0.580 (14.73) 0.254 (6.45) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.290 (32.7) 28-Pin Plastic Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.380 (35.1) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.565 (39.7) 40-Pin Plastic Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.980 (50.3) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 2.095 (53.2) Plastic 0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.120 (28.44) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.100 BSC (2.54) 0.600 BSC (15.24) 0.300 BSC (7.62) 0.430 (10.92) 0.115 (2.93) 0.200 (5.08) 15° 0.100 BSC (2.54) 0.600 BSC (15.24) 0.100 BSC (2.54) 0.600 BSC (15.24) 0.115 (2.93) 0.200 (5.08) 15° 0.115 (2.93) 0.200 (5.08) 15° Shaded areas for 300 Mil Body Width 24 PDIP only Package Outlines Pin 1 E A C L H e D 4 mils (lead coplanarity) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) A & B Maximum dimensions include allowable mold flash B L A1 DIM A A1 B C D E e H L 16-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.398 (10.1) 0.291 (7.40) 18-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.447 (11.35) 0.291 (7.40) 20-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.496 (12.60) 0.291 (7.40) 24-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.5985 (15.2) 0.291 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.614 (15.6) 0.299 (7.40) Min 28-Pin Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.7125 (18.1) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.413 (10.5) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.030 (0.51) 0.013 (0.318) 0.4625 (11.75) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.512 (13.00) 0.299 (7.40) 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.697 (17.7) 0.291 (7.40) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) Lead SOIC Package - S Suffix NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters. 2. Converted inch dimensions are not necessarily exact. General-7 Package Outlines Pin 1 E A C L H e Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin 5) A & B Maximum dimensions include allowable mold flash D A2 A1 B 20-Pin Dim 24-Pin Min 0.002 (0.05) 28-Pin Min Max 0.079 (2) 0.002 (0.05) 48-Pin Min 0.095 (2.41) 0.008 (0.2) Min A A1 B C D E e A2 H L 0.27 (6.9) 0.2 (5.0) 0.002 (0.05) 0.0087 (0.22) Max 0.079 (2) Max 0.079 (2) Max 0.110 (2.79) 0.016 (0.406) 0.0135 (0.342) 0.010 (0.25) 0.013 (0.33) 0.008 (0.21) 0.295 (7.5) 0.22 (5.6) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.008 (0.2) 0.31 (7.9) 0.2 (5.0) 0.33 (8.5) 0.22 (5.6) 0.39 (9.9) 0.2 (5.0) 0.42 (10.5) 0.22 (5.6) 0.62 (15.75) 0.291 (7.39) 0.63 (16.00) 0.299 (7.59) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.089 (2.26) 0.395 (10.03) 0.02 (0.51) 0.099 (2.52) 0.42 (10.67) 0.04 (1.02) Small Shrink Outline Package (SSOP) - N Suffix General-11 Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A C eA e b eB eC Plastic Dual-In-Line Packages (PDIP) - E Suffix 8-Pin DIM Min A A2 b b2 C D D1 E E1 e eA L eB eC 0 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.355 (9.02) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 16-Pin Plastic Max Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.780 (19.81) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014(0.356) 0.800 (20.32) 18-Pin Plastic Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.880 (22.35) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.920 (23.37) 20-Pin Plastic Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.980 (24.89) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 1.060 (26.9) Plastic 0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.400 (10.16) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) NOTE: Controlling dimensions in parenthesis ( ) are in millimeters. General-8 Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) α A C eA e b eB Plastic Dual-In-Line Packages (PDIP) - E Suffix 22-Pin DIM Min A A2 b b2 C D D1 E E E1 E1 e eA eA eB L α 0.115 (2.93) 0.160 (4.06) 15° 0.100 BSC (2.54) 0.400 BSC (10.16) 0.330 (8.39) 0.380 (9.65) 0.125 (3.18) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 1.050 (26.67) 0.005 (0.13) 0.390 (9.91) 0.430 (10.92) 24-Pin Plastic Max Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.150 (29.3) 0.005 (0.13) 0.600 (15.24) 0.290 (7.37) 0.485 (12.32) 0.246 (6.25) 0.670 (17.02) .330 (8.38) 0.580 (14.73) 0.254 (6.45) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.290 (32.7) 28-Pin Plastic Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.380 (35.1) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.565 (39.7) 40-Pin Plastic Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.980 (50.3) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 2.095 (53.2) Plastic 0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.120 (28.44) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.100 BSC (2.54) 0.600 BSC (15.24) 0.300 BSC (7.62) 0.430 (10.92) 0.115 (2.93) 0.200 (5.08) 15° 0.100 BSC (2.54) 0.600 BSC (15.24) 0.100 BSC (2.54) 0.600 BSC (15.24) 0.115 (2.93) 0.200 (5.08) 15° 0.115 (2.93) 0.200 (5.08) 15° Shaded areas for 300 Mil Body Width 24 PDIP only Package Outlines Pin 1 E A C L H e D 4 mils (lead coplanarity) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) A & B Maximum dimensions include allowable mold flash B L A1 DIM A A1 B C D E e H L 16-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.398 (10.1) 0.291 (7.40) 18-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.447 (11.35) 0.291 (7.40) 20-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.496 (12.60) 0.291 (7.40) 24-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.5985 (15.2) 0.291 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.614 (15.6) 0.299 (7.40) Min 28-Pin Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.7125 (18.1) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.413 (10.5) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.030 (0.51) 0.013 (0.318) 0.4625 (11.75) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.512 (13.00) 0.299 (7.40) 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.697 (17.7) 0.291 (7.40) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) Lead SOIC Package - S Suffix NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters. 2. Converted inch dimensions are not necessarily exact. General-7 Package Outlines Pin 1 E A C L H e Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin 5) A & B Maximum dimensions include allowable mold flash D A2 A1 B 20-Pin Dim 24-Pin Min 0.002 (0.05) 28-Pin Min Max 0.079 (2) 0.002 (0.05) 48-Pin Min 0.095 (2.41) 0.008 (0.2) Min A A1 B C D E e A2 H L 0.27 (6.9) 0.2 (5.0) 0.002 (0.05) 0.0087 (0.22) Max 0.079 (2) Max 0.079 (2) Max 0.110 (2.79) 0.016 (0.406) 0.0135 (0.342) 0.010 (0.25) 0.013 (0.33) 0.008 (0.21) 0.295 (7.5) 0.22 (5.6) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.008 (0.2) 0.31 (7.9) 0.2 (5.0) 0.33 (8.5) 0.22 (5.6) 0.39 (9.9) 0.2 (5.0) 0.42 (10.5) 0.22 (5.6) 0.62 (15.75) 0.291 (7.39) 0.63 (16.00) 0.299 (7.59) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.089 (2.26) 0.395 (10.03) 0.02 (0.51) 0.099 (2.52) 0.42 (10.67) 0.04 (1.02) Small Shrink Outline Package (SSOP) - N Suffix General-11 Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A C eA e b eB eC Plastic Dual-In-Line Packages (PDIP) - E Suffix 8-Pin DIM Min A A2 b b2 C D D1 E E1 e eA L eB eC 0 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.355 (9.02) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 16-Pin Plastic Max Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.780 (19.81) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014(0.356) 0.800 (20.32) 18-Pin Plastic Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.880 (22.35) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.920 (23.37) 20-Pin Plastic Min Max 0.210 (5.33) 0.115 (2.92) 0.014 (0.356) 0.045 (1.14) 0.008 (0.203) 0.980 (24.89) 0.005 (0.13) 0.300 (7.62) 0.240 (6.10) 0.325 (8.26) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 1.060 (26.9) Plastic 0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.014 (0.356) 0.400 (10.16) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.92) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) NOTE: Controlling dimensions in parenthesis ( ) are in millimeters. General-8 Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 L b2 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) α A C eA e b eB Plastic Dual-In-Line Packages (PDIP) - E Suffix 22-Pin DIM Min A A2 b b2 C D D1 E E E1 E1 e eA eA eB L α 0.115 (2.93) 0.160 (4.06) 15° 0.100 BSC (2.54) 0.400 BSC (10.16) 0.330 (8.39) 0.380 (9.65) 0.125 (3.18) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 1.050 (26.67) 0.005 (0.13) 0.390 (9.91) 0.430 (10.92) 24-Pin Plastic Max Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.150 (29.3) 0.005 (0.13) 0.600 (15.24) 0.290 (7.37) 0.485 (12.32) 0.246 (6.25) 0.670 (17.02) .330 (8.38) 0.580 (14.73) 0.254 (6.45) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.290 (32.7) 28-Pin Plastic Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.380 (35.1) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.565 (39.7) 40-Pin Plastic Min Max 0.250 (6.35) 0.125 (3.18) 0.014 (0.356) 0.030 (0.77) 0.008 (0.204) 1.980 (50.3) 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 2.095 (53.2) Plastic 0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.120 (28.44) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.100 BSC (2.54) 0.600 BSC (15.24) 0.300 BSC (7.62) 0.430 (10.92) 0.115 (2.93) 0.200 (5.08) 15° 0.100 BSC (2.54) 0.600 BSC (15.24) 0.100 BSC (2.54) 0.600 BSC (15.24) 0.115 (2.93) 0.200 (5.08) 15° 0.115 (2.93) 0.200 (5.08) 15° Shaded areas for 300 Mil Body Width 24 PDIP only Package Outlines Pin 1 E A C L H e D 4 mils (lead coplanarity) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) A & B Maximum dimensions include allowable mold flash B L A1 DIM A A1 B C D E e H L 16-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.398 (10.1) 0.291 (7.40) 18-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.447 (11.35) 0.291 (7.40) 20-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.496 (12.60) 0.291 (7.40) 24-Pin Min 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.5985 (15.2) 0.291 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.614 (15.6) 0.299 (7.40) Min 28-Pin Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.7125 (18.1) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.413 (10.5) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.030 (0.51) 0.013 (0.318) 0.4625 (11.75) 0.299 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.020 (0.51) 0.013 (0.318) 0.512 (13.00) 0.299 (7.40) 0.093 (2.35) 0.004 (0.10) 0.013 (0.33) 0.009 (0.231) 0.697 (17.7) 0.291 (7.40) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.394 (10.00) 0.016 (0.40) 0.419 (10.65) 0.050 (1.27) Lead SOIC Package - S Suffix NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters. 2. Converted inch dimensions are not necessarily exact. General-7 Package Outlines Pin 1 E A C L H e Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin 5) A & B Maximum dimensions include allowable mold flash D A2 A1 B 20-Pin Dim 24-Pin Min 0.002 (0.05) 28-Pin Min Max 0.079 (2) 0.002 (0.05) 48-Pin Min 0.095 (2.41) 0.008 (0.2) Min A A1 B C D E e A2 H L 0.27 (6.9) 0.2 (5.0) 0.002 (0.05) 0.0087 (0.22) Max 0.079 (2) Max 0.079 (2) Max 0.110 (2.79) 0.016 (0.406) 0.0135 (0.342) 0.010 (0.25) 0.013 (0.33) 0.008 (0.21) 0.295 (7.5) 0.22 (5.6) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.008 (0.2) 0.31 (7.9) 0.2 (5.0) 0.33 (8.5) 0.22 (5.6) 0.39 (9.9) 0.2 (5.0) 0.42 (10.5) 0.22 (5.6) 0.62 (15.75) 0.291 (7.39) 0.63 (16.00) 0.299 (7.59) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.635 BSC) 0.089 (2.26) 0.395 (10.03) 0.02 (0.51) 0.099 (2.52) 0.42 (10.67) 0.04 (1.02) Small Shrink Outline Package (SSOP) - N Suffix General-11 h ttp://www.zarlink.com World Headquarters - Canada Tel: +1 (613) 592 0200 Fax: +1 (613) 592 1010 North America - West Coast Tel: (858) 675-3400 Fax: (858) 675-3450 North America - East Coast Tel: (978) 322-4800 Fax: (978) 322-4888 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink Semiconductor’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All rights reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE