MT88E41AS

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For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ MT88E41 CMOS Extended Voltage Calling Number Identification Circuit (ECNIC) Data Sheet Features • • • • • • • • • • 1200 baud BELL 202 and CCITT V.23 Frequency Shift Keying (FSK) demodulation Compatible with Bellcore GR-30-CORE and SRTSV-002476 High input sensitivity: -36dBm minimum FSK Detection Level Simple serial 3-wire data interface eliminating the need for a UART Power down mode Internal gain adjustable amplifier Carrier detect status output Uses 3.579545 MHz crystal 2.7 - 5.5V operation Low power CMOS technology DS5717 Issue 3 February 1998 Ordering Information MT88E41AE 16 Pin Plastic DIP MT88E41AS 16 Pin SOIC MT88E41AN 20 Pin SSOP -40 °C to +85 °C Description The MT88E41 Extended Voltage Calling Number Identification Circuit (ECNIC) is a CMOS integrated circuit providing an interface to various calling line information delivery services that utilize 1200 baud BELL 202 or CCITT V.23 FSK voiceband data transmission schemes. The ECNIC receives and demodulates the signal and outputs data into a simple 3-wire serial interface. Typically, the FSK modulated data containing information on the calling line is sent before alerting the called party or during the silent interval between the first and second ring using either CCITT V.23 recommendations or Bell 202 specifications. The ECNIC accepts and demodulates both CCITT V.23 and BELL 202 signals. Along with serial data and clock, the ECNIC provides a data ready signal to indicate the reception of every 8-bit character sent from the Central Applications • Calling Number Delivery (CND), Calling Name Delivery (CNAM) and Calling Identity on Call Waiting (CIDCW) features of Bellcore CLASSSM service Feature phones Phone sets, adjunct boxes FAX machines Telephone answering machines Database query systems Battery powered applications • • • • • • GS ININ+ + Receive Bandpass Filter FSK Demodulator Data and Timing Recovery DATA DR DCLK CAP VRef Bias Generator Carrier Detector CD Clock Generator to other circuits PWDN OSC1 OSC2 VSS VDD IC1 IC2 Figure 1 - Functional Block Diagram CLASSSM i s a service mark of Bellcore SEMICMF.019 1 MT88E41 Data Sheet Office. The received data can be processed externally by a microcontroller, stored in memory, or displayed as is, depending on the application. IN+ INGS VRef CAP OSC1 OSC2 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD IC2 IC1 PWDN CD DR DATA DCLK 16 PIN PLASTIC DIP/SOIC IN+ INGS VRef CAP NC OSC1 NC OSC2 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD IC2 NC NC IC1 PWDN CD DR DATA DCLK 20 PIN SSOP Figure 2 - Pin Connections Pin Description Table Pin # Name 16 1 2 3 4 5 6 7 8 9 20 1 2 3 4 5 7 9 10 11 IN+ INGS VRef Non-inverting Op-Amp (Input). Inverting Op-Amp (Input). Gain Select (Output). Gives access to op-amp output for connection of feedback resistor. Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs. Description CAP Capacitor. Connect a 0.1µF capacitor to VSS. OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an external clocking source. OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin should be left open. VSS Power supply ground. DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz (3.5795MHz divided by 2976). Every clock burst is initiated by the DATA stop bit start bit sequence. When the input DATA is 1202.8 baud, the positive edge of each DCLK pulse coincides with the middle of the data bits output at the DATA pin. No DCLK pulses are generated during the start or stop bits. Typically, DCLK is used to clock the eight data bits from the 10 bit data word into a serial-to-parallel converter. DATA Data (Output). Serial data output corresponding to the FSK input and switching at the input baud rate. Mark frequency at the input corresponds to a logic high, while space frequency corresponds to a logic low at the DATA output. With no FSK input, DATA is at logic high. This output stays high until CD has become active. DR Data Ready (Open Drain Output). This output goes low after the last DCLK pulse of each word. This can be used to identify the data (8-bit word) boundary on the serial output stream. Typically, DR is used to latch the eight data bits from the serial-to-parallel converter into a microcontroller. Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been present for a specified time on the line. A time hysteresis is provided to allow for momentary discontinuity of carrier. 10 12 11 13 12 14 CD 2 SEMICMF.019 Data Sheet Pin Description Table (continued) Pin # Name 16 13 14 15 16 20 15 16 19 20 6, 8, 17, 18 Description MT88E41 PWDN Power Down (Input). Active high, Schmitt Trigger input. Powers down the device including the input op-amp and the oscillator. IC1 IC2 VDD NC Internal Connection 1. Connect to VSS. Internal Connection 2. Internally connected, leave open circuit. Positive power supply voltage. No Connection. SEMICMF.019 3 MT88E41 1.0 Functional Description Data Sheet The MT88E41 Extended Voltage Calling Number Identification Circuit (ECNIC) is a device compatible with the Bellcore proposal (GR-30-CORE) on generic requirements for transmitting asynchronous voiceband data to Customer Premises Equipment (CPE) from a serving Stored Program Controlled Switching System (SPCS) or a Central Office (CO). This data transmission technique is applicable in a variety of services like Calling Number Delivery (CND), Calling Name Delivery (CNAM) or Calling Identity Delivery on Call Waiting (CIDCW) as specified in Custom Local Area Signalling Service (CLASSSM) calling information delivery features by Bellcore. With CND, CNAM and CIDCW service, the called subscriber has the capability to display or to store the information on the calling party which is sent by the CO and received by the ECNIC. In the CND service, information about a calling party is embedded in the silent interval between the first and second ring. During this period, the ECNIC receives and demodulates the 1200 baud FSK signal (compatible with Bell-202 specification) and outputs data into a 3-wire serial interface. In the CIDCW service, information about a second calling party is sent to the subscriber, (while the subscriber is engaged in another call). During this period, the ECNIC receives and demodulates the FSK signal as in the CND case. The ECNIC is designed to provide the data transmission interface required for the above service at the called subscriber location either in the on-hook case as in CND, or the off-hook case, as in CIDCW. The functional block diagram of the ECNIC is shown in Figure 1. Note however, for CIDCW applications, a separate CAS (CPE Alerting Signal) detector is required. C1 R1 IN+ IN- C2 R4 R5 GS R3 R2 VRef DIFFERENTIAL INPUT AMPLIFIER MT88E41 C1 = C2 = 10 nF R1 = R4 = R5 = 100 kΩ R2 = 60kΩ, R3 = 37.5 kΩ R3 = (R2R5) / (R2 + R5) INPUT IMPEDANCE VOLTAGE GAIN (AVdiff) = R5/R1 (ZINdiff) = 2 R12 + (1/ωC)2 Figure 3 - Differential Input Configuration 4 SEMICMF.019 Data Sheet IN+ MT88E41 C RIN IN- RF GS VOLTAGE GAIN (AV) = RF / RIN VRef MT88E41 Figure 4 - Single-Ended Input Configuration In Europe, Caller ID and CIDCW services are being proposed. These schemes may be different from their North American counterparts. In most cases, 1200 baud CCITT V.23 FSK is used instead of Bell 202. Because the ECNIC can also demodulate 1200 baud CCITT V.23 with the same performance, it is suitable for these applications. Although the main application of the ECNIC is to support CND and CIDCW service, it may also be used in any application where 1200 baud Bell 202 and/or CCITT V.23 FSK data reception is required. 1.1 Input Configuration The input arrangement of the MT88E41 provides an operational amplifier, as well as a bias source (VRef) which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 4. Figure 3 shows the necessary connections for a differential input configuration. 1.2 User Interface The ECNIC provides a powerful 3-pin interface which can reduce the external hardware and software requirements. The ECNIC receives the FSK signal, demodulates it, and outputs the extracted data to the DATA pin. For each received stop bit start bit sequence, the ECNIC outputs a fixed frequency clock string of 8 pulses at the DCLK pin. Each clock rising edge corresponds to the centre of each DATA bit cell (providing the incoming baud rate matches the DCLK rate). DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift register or a micro-controller. The ECNIC also outputs an end of word pulse (data ready) at the DR pin. The data ready signal indicates the reception of every 10-bit word sent from the Central Office. This output is typically used to interrupt a micro-controller. The three outputs together, eliminate the need for a UART (Universal Asynchronous Receiver Transmitter) or the high software overhead of performing the UART function (asynchronous serial data reception). Note that the 3-pin interface may also output data generated by voice since these frequencies are in the input frequency detection band of the device. The user may choose to ignore these outputs when FSK data is not expected, or force the ECNIC into its powerdown mode. 1.3 Power Down Mode For applications requiring reduced power consumption, the ECNIC can be forced into power down when it is not needed to receive FSK data. This is done by pulling the PWDN pin high. In powerdown mode, the crystal oscillator, op-amp and internal circuitry are all disabled and the ECNIC will not react to the input signal. DATA and DCLK are at logic high, and DR and CD are at high impedance or at logic high when pulled up with resistors.The ECNIC can be awakened for reception of the FSK signal by pulling the PWDN pin to ground (see Figure 9). SEMICMF.019 5 MT88E41 1.4 Carrier Detect Data Sheet The presence of the FSK signal is indicated by a logic low at the carrier detect (CD) output. This output has built in hysteresis to prevent toggling when the received signal is shortly interrupted. Note that the CD output is also activated by voice since these frequencies are in the input frequency detection band of the device. The user may choose to ignore this output when FSK data is not expected, or force the ECNIC into its powerdown mode. MT88E41 OSC1 OSC2 MT88E41 OSC1 OSC2 MT88E41 OSC1 OSC2 3.579545 MHz to the next MT88E41 Figure 5 - Common Crystal Connection 1.5 Crystal Oscillator The ECNIC uses a crystal oscillator as the master timing source for filters and the FSK demodulator. The crystal specification is as follows: Frequency: Frequency tolerance: Resonance mode: Load capacitance: Maximum series resistance: Maximum drive level (mW): e.g. CTS MP036S 3.579545 MHz ±0.1%(-40°C+85°C) Parallel 18 pF 150 ohms 2 mW A number of MT88E41 devices can be connected as shown in Figure 5 such that only one crystal is required. The connection between OSC2 and OSC1 can be D.C. coupled as shown, or A.C. coupled using 30pF capacitors. Alternatively, the OSC1 inputs on all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected. 1.6 VRef and CAP Inputs VRef is the output of a low impedance voltage source equal to VDD/2 and is used to bias the input op-amp. A 0.1µF capacitor is required between CAP and VSS to suppress noise on VRef. 6 SEMICMF.019 Data Sheet 2.0 Applications MT88E41 The circuit shown in Figure 6 illustrates the use of the MT88E41 device in a typical FSK receiver system. Bellcore Special Report SR-TSV-002476 specifies that the FSK receiver should be able to receive FSK signal levels as follows: Received Signal Level at 1200Hz: -32dBm to -12dBm Received Signal Level at 2200Hz: -36dBm to -12dBm This condition can be attained by choosing suitable values of R1 and R2. The MT88E41 configured in a unity gain mode as shown in Fig. 6 meets the above level requirements. For applications requiring detection of lower FSK signal level, the input op amp may be configured to provide adequate gain. VDD C1 R1 IN + IN GS R2 VRef CAP C2 Notes: R1, R2 = 100 kΩ 1% R3, R4 = 100 kΩ 10% C1, C2, C3 = 0.1µF 20% X-tal = 3.579545 MHz X-tal MT88E41 VDD IC2 IC1 PWDN CD DR DATA DCLK To Controller R3 C3 R4 OSC1 OSC2 VSS Figure 6 - Application Circuit (Single-Ended Input) SEMICMF.019 7 MT88E41 Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated. Parameter 1 2 3 4 5 DC Power Supply Voltage VDD to VSS Voltage on any pin Current at any pin (except VDD and VSS) Storage Temperature Package Power Dissipation Symbol VDD VP I I/O TST PD -65 Min -0.3 -0.3 Data Sheet Max 6 VDD+0.3 ±10 +150 500 Units V V mA °C mW *Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated Characteristics 1 2 3 4 DC Power Supply Voltage Clock Frequency Tolerance on Clock Frequency Operating Temperature Sym VDD fOSC ∆fc -40 Min 2.7 3.579545 Typ Max 5.5 ±0.1 +85 Units V MHz % °C Test Conditions DC Electrical Characteristics† Characteristics 1 S U P P L Y DATA DCLK DR CD Sym IDDQ Min Typ* Max Units µA µA mA mA V V mA Test Conditions PWDN=VDD Standby Supply Current VDD=2.7V VDD=5.5V Operating Supply Current VDD=2.7V VDD=5.5V Low Level Output Voltage High Level Output Voltage Sink Current Schmitt Input High Threshold Schmitt Input Low Threshold 7 15 IDD 1 3 VOL VOH IOL VT+ VTVHYS IIN VRef RRef 0.5VDD - 0.05 VDD-0.4 14 28 2 5 0.4 2 PWDN=VSS 3 4 5 IOL=2.5mA IOH=0.8mA VOL=0.4V 2.5 0.48*VDD 0.28*VDD 0.2 10 0.5VDD + 0.05 2 0.68*VDD 0.48*VDD V V V µA V kΩ VSS ≤ VIN ≤ VDD No Load PWDN 6 7 8 VRef Schmitt Hysterisis Input Current Output Voltage Output Resistance 9 † DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25°C and are for design aid only. 8 SEMICMF.019 Data Sheet Electrical Characteristics† - Gain Setting Amplifier Characteristics 1 2 3 4 5 6 7 8 9 Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Ratio Common Mode Rejection DC Open Loop Voltage Gain Unity Gain Bandwidth Output Voltage Swing Maximum Capacitive Load (GS) Sym IIN Rin VOS PSRR CMRR AVOL fC VO CL RL VCM 50 1.0 VDD-1.0 MT88E41 Min Typ‡ Max 1 5 25 30 30 30 .2 0.5 40 40 32 0.3 VDD-0.5 Units µA MΩ mV dB dB dB MHz Vpp pF kΩ V Test Conditions VSS ≤ VIN ≤ VDD 1kHz ripple on VDD VCMmin ≤ VIN ≤ VCMmax Load ≥ 50kΩ 100 10 Maximum Resistive Load (GS) 11 Common Mode Range Voltage † Electrical characteristics are over recommended operating conditions, unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. AC Electrical Characteristics† - FSK Detection Characteristics 1 Input Detection Level 2 Input Baud Rate 3 Input Frequency Detection Bell 202 1 (Mark) Bell 202 0 (Space) CCITT V.23 1 (Mark) CCITT V.23 0 (Space) 4 Input Noise Tolerance 20 log( SNR 20 dB 2, 3, 4, 5 Sym Min -36 12.3 1188 1188 2178 1200 1200 2200 Typ‡ Max -9 275 1212 1212 2222 Units dBm mV baud Hz Hz Hz Hz 1, 2, 3 1, 2, 3 7 Notes* 1280.5 1300 1319.5 2068.5 2100 2131.5 † AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. SEMICMF.019 9 MT88E41 AC Electrical Characteristics† - Timing Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DR DCLK DR DCLK DATA DCLK DATA CD PWDN OSC1 Data Sheet Sym tPU tPD tIAL tIAH Min Typ‡ 35 100 Max 50 1000 25 Units ms µs ms ms ms 11 Notes* Power-up time Power-down time Input FSK to CD low delay Input FSK to CD high delay Hysteresis Rate Input FSK to DATA delay Rise time Fall time DATA to DCLK delay DCLK to DATA delay Frequency High time Low time DCLK to DR delay Rise time Fall time Low time 8 8 1188 1200 1 1212 5 200 200 6 6 1200 416 416 1202.8 416 416 416 1205 417 417 417 10 200 415 416 417 bps ms ns ns µs µs Hz µs µs µs µs ns µs 6,12 tIDD tR tF tDCD tCDD tCH tCL tCRD tRR tFF tRL 8 8 6, 7, 10 6, 7, 10 7 7 7 7 9 9 7 415 415 415 † AC Electrical Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing. *Notes: 1. dBm=decibels above or below a reference power of 1mW into 600Ω. 2. Using unity gain test circuit shown in Figure 6. 3. Mark and Space frequencies have the same amplitude. 4. Band limited random noise (200-3200Hz). 5. Referenced to the minimum input detection level. 6. FSK input data at 1200 ±12 baud. 7. OSC1 at 3.579545 MHz ±0.2%. 8. 10k to VSS, 50pF to VSS. 9. 10k to VDD, 50pF to VSS. 10. Function of signal condition. 11. The device will stop functioning within this time, but more time may be required to reach IDDQ. 12. For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations. 10 SEMICMF.019 Data Sheet tDCD tR DATA tCDD MT88E41 tF DCLK tCL tR tCH tF Figure 7 - DATA and DCLK Output Timing tFF tRR DR tRL Figure 8 - DR Output Timing SEMICMF.019 11 MT88E41 2 sec channel seizure Mark state checksum Data Sheet TIP/RING First Ringing 500ms (min) Input FSK Data 200ms (min) Second Ringing PWDN tPU tPD OSC2 CD * tIAL tIAH DATA High (Input Idle) High (Input Idle) DCLK DR * * with external pull-up resistor Figure 9 - Input and Output Timing (Bellcore CND Service) 12 SEMICMF.019 Data Sheet start stop TIP/RING b7 tIDD start DATA b7 stop b0 b1 b2 b3 b4 b5 b6 b7 stop start b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 start stop 1 0 b0 b1 b2 b3 b4 b5 b6 b7 MT88E41 start stop 1 0 b0 b1 b2 start b0 b1 b2 stop DCLK tCRD DR * * with external pull-up resistor Figure 10 - Serial Data Interface Timing SEMICMF.019 13 MT88E41 Data Sheet 14 SEMICMF.019 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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