MT8941BPR

MT8941B Advanced T1/CEPT Digital Trunk PLL Data Sheet Features • • Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse) Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kHz ≥ 64 dB Jitter-free “FREE-RUN” mode Uncommitted two-input NAND gate Low power CMOS technology Ordering Information MT8941BE 24 Pin PDIP Tubes MT8941BP 28 Pin PLCC Tubes MT8941BPR 28 Pin PLCC Tape & Reel MT8941BP1 28 Pin PLCC* Tubes MT8941BPR1 28 Pin PLCC* Tape & Reel *Pb Free Matte Tin February 2005 • • • • • -40° C to +85 ° C Description The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmission link and the ST-BUS are provided by the second PLL locked to an internal or an external 8 kHz frame pulse signal. The MT8941B offers improved jitter performance over the MT8940. The two devices also have some functional differences, which are listed in the section on “Differences between MT8941B and MT8940”. Applications • • Synchronization and timing control for T1 and CEPT digital trunk transmission links ST- BUS clock and frame pulse source F0i DPLL #1 C12i 2:1 MUX Variable Clock Control CVb CV ENCV MS0 MS1 MS2 MS3 C8Kb Mode Selection Logic Frame Pulse Control Input Selector 4.096 MHz Clock Control DPLL #2 F0b C4b C4o ENC4o C2o C2o ENC2o C16i Clock Generator Ai Bi 2.048 MHz Clock Control Yo VDD VSS RST Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT8941B Data Sheet 24 PIN PDIP Figure 2 - Pin Connections Pin Description Pin # DIP PLCC Name Description 1 1 ENCV Variable clock enable (TTL compatible input) - This input directly controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1 is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input. MS0 C12i MS1 F0i F0b Mode select ‘0’ input (TTL compatible) - This input in conjunction with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.) 12.352 MHz Clock input (TTL compatible) - Master clock input for DPLL #1. Mode select-1 input (TTL compatible) - This input in conjunction with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.) Frame pulse input (TTL compatible) - This is the frame pulse input at 8 kHz. DPLL #1 locks to the falling edge of this input to generate T1 (1.544 MHz) clock. Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending on the minor mode selected for DPLL #2, it provides the 8 kHz frame pulse output or acts as an input to an external frame pulse. Mode select-2 input (TTL compatible) - This input in conjunction with MS3 (pin 17) selects the minor mode of operation for DPLL #2. (Refer to Table 3.) 16.384 MHz Clock input (TTL compatible) - Master clock input for DPLL #2. 2 3 4 5 6 2 3 6 7 8 7 8 9 10 9 10 11 12 MS2 C16i ENC4o Enable 4.096 MHz clock (TTL compatible input) - This active high input enables C4o (pin 11) output. When LOW, the output C4o is in high impedance condition. C8Kb Clock 8 kHz Bidirectional (TTL compatible input and Totem-pole output) - This is the 8 kHz input signal on the falling edge of which the DPLL #2 locks during its NORMAL mode. When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz internal signal provided by DPLL #1 which is also connected internally to DPLL #2. 2 Zarlink Semiconductor Inc. C8Kb C4o VSS C4b C2o C2o NC ENVC MS0 C12i MS1 F0i F0b MS2 C16i ENC4o C8Kb C4o VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD RST CV CVb Yo Bi Ai MS3 ENC2o C2o C2o C4b 4 3 2 1 28 27 26 NC C12i MS0 ENCV VDD RST CV 12 13 14 15 16 17 18 NC MS1 F0i F0b MS2 C16i ENC4o 5 6 7 8 9 10 11 • 25 24 23 22 21 20 19 NC CVb Yo Bi Ai MS3 ENC2o 28 PIN PLCC MT8941B Pin Description (continued) Pin # DIP PLCC Data Sheet Name C4o Description Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin 13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC4o (pin 9). Ground (0 Volt) Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input to an external clock at 4.096 MHz. Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a falling edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC2o (pin 16). Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is controlled by ENC2o (pin 16). 11 13 12 13 14 15 VSS C4b 14 16 C2o 15 17 C2o 16 19 ENC2o Enable 2.048 MHz clock (TTL compatible input) - This active high input enables both C2o and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance condition. MS3 Ai, Bi Yo CVb Mode select 3 input (TTL compatible) - This input in conjunction with MS2 (pin 7) selects the minor mode of operation for DPLL #2. (Refer to Table 3.) Inputs A and B (TTL compatible) -These are the two inputs of the uncommitted NAND gate. Output Y (Totem pole output) - Output of the uncommitted NAND gate. Variable clock Bidirectional (TTL compatible input and Totem-pole output) - When acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the 1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an input to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz to DPLL #2. Variable clock (Three state output) - This is the inverse output of the signal appearing on pin 21, the high impedance state of which is controlled by ENCV (pin 1). Reset (Schmitt trigger input) - This input (active LOW) puts the MT8941B in its reset state. To guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the device. VDD (+5 V) Power supply. No Connection. 17 18, 19 20 21 20 21, 22 23 24 22 23 26 27 CV RST 24 28 4, 5, 18, 25 VDD NC 3 Zarlink Semiconductor Inc. MT8941B Functional Description Data Sheet The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals to the interface circuits for T1 and CEPT (30+2) Primary Multiplex Digital Transmission links. As shown in the functional block diagram (see Figure 1), the MT8941B has two digital phase-locked loops (DPLLs), associated output controls and the mode selection logic circuits. The two DPLLs, although similar in principle, operate independently to provide T1 (1.544 MHz) and CEPT (2.048 MHz) transmission clocks and ST-BUS timing signals. The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock frequency is corrected. Master clock (12.352 MHz / 16.384 MHz) Frequency Correction ÷8 Output (1.544 MHz / 2.048 MHz) Input (8 kHz) Phase Comparison ÷ 193 / ÷ 256 Figure 3 - DPLL Principle The MT8941B achieves the frequency correction in both directions by using three methods; speed-up, slow-down and no-correction. As shown in Figure 4, the falling edge of the 8 kHz input signal (C8Kb for DPLL #2 or F0i for DPLL # 1) is used to sample the internally generated 8 kHz clock and the correction signal (CS) once in every frame (125 µs). If the sampled CS is “1”, then the DPLL makes a speed-up or slow-down correction depending upon the sampled value of the internal 8 kHz signal. A sampled ”0” or “1” causes the frequency correction circuit to respectively stretch or shrink the master clock by half a period at one instant in the frame. If the sampled CS is “0”, then the DPLL makes no correction on the master clock input. Note that since the internal 8 kHz signal and the CS signal are derived from the master clock, a correction will cause both clocks to stretch or shrink simultaneously by an amount equal to half the period of the master clock. Once in synchronization, the falling edge of the reference signal (C8Kb or F0i) will be aligned with either the falling or the rising edge of CS. It is aligned with the rising edge of CS when the reference signal is slower than the internal 8 kHz signal. On the other hand, the falling edge of the reference signal will be aligned with the falling edge of CS if the reference signal is faster than the internal 8 kHz signal. C8Kb (DPLL #2) or F0i (DPLL #1) Internal 8 kHz correction CS F0b (DPLL #2) speed-up region correction slow-down region sampling edge tCS no-correction tCSF DPLL #1: tCS = 4 × TP12 ± 0.5 × TP12 DPLL #2: tCS = 512 × TP16 ± 0.5 × TP16 tCSF = 766 × TP16 where, TP12 is the 12.352 MHz master clock oscillator period for DPLL #1 and TP16 is the 16.384 MHz master clock period for DPLL #2. Figure 4 - Phase Comparison 4 Zarlink Semiconductor Inc. MT8941B Input-to-Output Phase Relationship Data Sheet The no-correction window size is 324 ns for DPLL #1 and 32 µs for DPLL #2. It is possible for the relative phase of the reference signal to swing inside the no-correction window depending on its jitter and the relative drift of the master clock. As a result, the phase relationship between the input signal and the output clocks (and frame pulse in case of DPLL #2) may vary up to a maximum of window size. This situation is illustrated in Figure 4. The maximum phase variation for DPLL #1 is 324 ns and for DPLL #2 it is 32 µs. However, this phase difference can be absorbed by the input jitter buffer of Zarlink’s T1/CEPT devices. The no-correction window acts as a filter for low frequency jitter and wander since the DPLL does not track the reference signal inside it. The size of the no-correction window is less than or equal to the size of the input jitter buffer on the T1 and CEPT devices to guarantee that no slip will occur in the received T1/CEPT frame. The circuit will remain in synchronization as long as the input frequency is within the lock-in range of the DPLLs (refer to the section on “Jitter Performance and Lock-in Range” for further details). The lock-in range is wide enough to meet the CCITT line rate specification (1.544 MHz ±32 ppm and 2.048 MHz ±50 ppm) for the High Capacity Terrestrial Digital Service. The phase sampling is done once in a frame (8 kHz) for each DPLL. The divisions are set at 8 and 193 for DPLL #1, which locks to the falling edge of the input at 8 kHz to generate T1 (1.544 MHz) clock. For DPLL #2, the divisions are set at 8 and 256 to provide the CEPT/ST-BUS clock at 2.048 MHz synchronized to the falling edge of the input signal (8 kHz). The master clock source is specified to be 12.352 MHz for DPLL #1 and 16.384 MHz for DPLL #2 over the entire temperature range of operation. The inputs MS0 to MS3 are used to select the operating mode of the MT8941B, see Tables 1 to 4. All the outputs are controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is available for use in applications involving Zarlink’s MT8976/ MH89760 (T1 Interfaces) and MT8979/MH89790 (CEPT Interfaces). Modes of Operation The operation of the MT8941B is categorized into major modes and minor modes. The major modes are defined for both DPLLs by the mode select pins MS0 and MS1. The minor modes are selected by pins MS2 and MS3 and are applicable only to DPLL #2. There are no minor modes for DPLL #1. Major modes of DPLL #1 DPLL #1 can be operated in three major modes as selected by MS0 and MS1 (Table 1). When MS1 is LOW, it is in NORMAL mode, which provides a T1 (1.544 MHz) clock signal locked to the falling edge of the input frame pulse F0i (8 kHz). DPLL #1 requires a master clock input of 12.352 MHz (C12i). In the second and third major modes (MS1 is HIGH), DPLL #1 is set to DIVIDE an external 1.544 MHz or 2.048 MHz signal applied at CVb (pin 21). The division can be set by MS0 to be either 193 (LOW) or 256 (HIGH). In these modes, the 8 kHz output at C8Kb is connected internally to DPLL #2, which operates in SINGLE CLOCK mode. Major modes of DPLL #2 There are four major modes for DPLL #2 selectable by MS0 and MS1, as shown in Table 2. In all these modes DPLL #2 provides the CEPT PCM30 timing, and the ST-BUS clock and framing signals. In NORMAL mode, DPLL #2 provides the CEPT/ST-BUS compatible timing signals locked to the falling edge of the 8 kHz input signal (C8Kb). These signals are 4.096 MHz (C4o and C4b) and 2.048 MHz (C2o and C2o) clocks, and the 8 kHz frame pulse (F0b) derived from the 16.384 MHz master clock. This mode can be the same as the FREERUN mode if the C8Kb pin is tied to VDD or VSS. 5 Zarlink Semiconductor Inc. MT8941B M S 0 X 0 1 M S 1 0 1 1 Mode of Operation NORMAL DIVIDE-1 DIVIDE-2 Data Sheet Function Provides the T1 (1.544 MHz) clock synchronized to the falling edge of the input frame pulse (F0i). DPLL #1 divides the CVb input by 193. The divided output is connected to DPLL #2. DPLL #1 divides the CVb input by 256. The divided output is connected to DPLL #2. Note: X: indicates don’t care Table 1 - Major Modes of DPLL #1 M S 0 0 M S 1 0 Mode of Operation NORMAL Function Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz input signal at C8Kb. Provides CEPT/ST-BUS timing and framing signals with no external inputs, except the master clock. Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal provided by DPLL #1. Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal provided by DPLL #1. 1 0 FREE-RUN 0 1 SINGLE CLOCK-1 SINGLE CLOCK-2 1 1 Table 2 - Major Modes of DPLL #2 6 Zarlink Semiconductor Inc. MT8941B M S 2 1 0 M S 3 1 1 Data Sheet Functional Description Provides CEPT/ST-BUS 4.096 MHz and 2.048 MHz clocks and 8kHz frame pulse depending on the major mode selected. Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz clocks depending on the major mode selected while F0b acts as an input. However, the input on F0b has no effect on the operation of DPLL #2 unless it is in FREE-RUN mode. Overrides the major mode selected and accepts properly phase related external 4.096 MHz clock and 8 kHz frame pulse to provide the ST-BUS compatible clock at 2.048 MHz. Overrides the major mode selected and accepts a 4.096 MHz external clock to provide the ST-BUS clock and frame pulse at 2.048 MHz and 8 kHz, respectively. Table 3 - Minor Modes of DPLL #2 0 0 1 0 In FREE-RUN mode, DPLL #2 generates the stand-alone CEPT and ST-BUS timing and framing signals with no external inputs except the master clock set at 16.384 MHz. The DPLL makes no correction in this configuration and provides the timing signals without any jitter. The operation of DPLL #2 in SINGLE CLOCK-1 mode is identical to SINGLE CLOCK-2 mode, providing the CEPT and ST-BUS compatible timing signals synchronized to the internal 8 kHz signal obtained from DPLL#1 in DIVIDE mode. When SINGLE CLOCK-1 mode is selected for DPLL #2, it automatically selects the DIVIDE-1 mode for DPLL #1, and thus, an external 1.544 MHz clock signal applied at CVb (pin 21) is divided by DPLL #1 to generate the internal signal at 8 kHz on to which DPLL #2 locks. Similarly when SINGLE CLOCK-2 mode is selected, DPLL #1 is in DIVIDE-2 mode, with an external signal of 2.048 MHz providing the internal 8 kHz signal to DPLL #2. In both these modes, this internal signal is available on C8Kb (pin 10) and DPLL #2 locks to the falling edge to provide the CEPT and ST-BUS compatible timing signals. This is in contrast to the Normal mode where these timing signals are synchronized with the falling edge of the 8 kHz signal on C8Kb. Minor modes of DPLL #2 The minor modes for DPLL #2 depends upon the status of the mode select bits MS2 and MS3 (pins 7 and 17). 7 Zarlink Semiconductor Inc. MT8941B Mode # M S 0 M S 1 M S 2 M S 3 Data Sheet Operating Modes DPLL #1 NORMAL MODE: Provides the T1 (1.544 MHz) clock synchronized to the falling edge of the input frame pulse (F0i). NORMAL MODE NORMAL MODE NORMAL MODE DPLL #2 Properly phase related External 4.096 MHz clock and 8 kHz frame pulse provide the STBUS clock at 2.048 MHz. NORMAL MODE: F0b is an input but has no function in this mode. External 4.096 MHz provides the ST-BUS clock and Frame Pulse at 2.048 MHz and 8 kHz, respectively. NORMAL MODE: Provides the CEPT/ST-BUS compatible timing signals locked to the 8 kHz input signal (C8Kb). Same as mode ‘0’. SINGLE CLOCK-1 MODE F0b is an input but has no function in this mode. Same as mode 2. SINGLE CLOCK-1 MODE: Provides the CEPT/ST-BUS compatible timing signals locked to the 8 kHz internal signal provided by DPLL #1. Same as mode ‘0’. F0b is an input and DPLL #2 locks on to it only if it is at 16 kHz to provide the ST-BUS control signals. Same as mode 2. FREE-RUN MODE: Provides the ST-BUS timing signals with no external inputs except the master clock. Same as mode ‘0’. SINGLE CLOCK-2 MODE: F0b is an input but has no function in this mode. Same as mode 2. SINGLE CLOCK-2 MODE: Provides the CEPT/ST-BUS compatible timing signals locked to the 8 kHz internal signal provided by DPLL #1. 0 0 0 0 0 1 2 0 0 0 0 0 1 1 0 3 4 5 6 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 DIVIDE-1 MODE DIVIDE-1 MODE DIVIDE-1 MODE DIVIDE-1 MODE: Divides the CVb input by 193. The divided output is connected to DPLL #2. NORMAL MODE NORMAL MODE 7 8 9 10 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 NORMAL MODE NORMAL MODE DIVIDE-2 MODE DIVIDE-2 MODE DIVIDE-2 MODE DIVIDE-2 MODE: Divides the CVb input by 256. The divided output is connected to DPLL#2. 11 12 13 14 1 1 1 1 0 1 1 1 1 0 0 1 1 0 1 0 15 1 1 1 1 Table 4 - Summary of Modes of Operation - DPLL #1 and #2 When MS3 is HIGH, DPLL #2 operates in any of the major modes selected by MS0 and MS1. When MS3 is LOW, it overrides the major mode selected and DPLL#2 accepts an external clock of 4.096 MHz on C4b (pin 13) to provide the 2.048 MHz clocks (C2o and C2o) and the 8 kHz frame pulse (F0b) compatible with the ST-BUS format. The mode select bit MS2 controls the direction of the signal on F0b (pin 6). When MS2 is LOW, the F0b pin is an 8 kHz frame pulse input. This input is effective only when MS3 is also LOW and pin C4b is fed by a 4.096 MHz clock, which has a proper phase relationship with the signal on F0b (refer Figure 18). Otherwise, the input on pin F0b will have no bearing on the operation of DPLL #2, unless it is in FREE-RUN mode as selected by MS0 and MS1. In FREE-RUN mode, the input on F0b is treated the same way as the C8Kb input is in NORMAL mode. The frequency of the signal on F0b should be 16 kHz for DPLL #2 to lock and generate the ST-BUS compatible clocks at 4.096 MHz and 2.048 MHz. 8 Zarlink Semiconductor Inc. MT8941B Data Sheet When MS2 is HIGH, the F0b pin provides the frame pulse output compatible with the ST-BUS format and locked to the internal or external input signal as determined by the other mode select pins. Table 4 summarizes the modes of the two DPLL. It should be noted that each of the major modes selected for DPLL #2 can have any of the minor modes, although some of the combinations are functionally similar. The required operation of both DPLL #1 and DPLL #2 must be considered when determining MS0-MS3. Mode # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 F0b (kHz) i:8 i:X o:8 o:8 i:8 i:X o:8 o:8 i:8 i:16 o:8 o:8 i:8 i:X o:8 o:8 C4b (MHz) i:4.096 o:4.096 i:4.096 o:4.096 i:4.096 o:4.096 i:4.096 o:4.096 i:4.096 o:4.096 i:4.096 o:4.096 i:4.096 o:4.096 i:4.096 o:4.096 C8Kb (kHz) i:X i:8 i:X i:8 i:X o:8 i:X o:8 i:X i:X i:X i:X i:X o:8 i:X o:8 CVb (MHz) o:1.544 o:1.544 o:1.544 o:1.544 i:1.544 i:1.544 i:1.544 i:1.544 o:1.544 o:1.544 o:1.544 o:1.544 i:2.408 i:2.408 i:2.408 i:2.408 Note: i: Input o: Output X: “don’t care” input. Connect to V DD o r V SS. Table 5 - Functions of the Bidirectional Signals in Each Mode The direction and frequency of each of the bidirectional signals are listed in Table 5 for each of the given modes in Table 4. Jitter Performance and Lock-in Range The output jitter of a DPLL is composed of the intrinsic jitter, measured when no jitter is present at the input, and the output jitter resulting from jitter on the input signal. The spectrum of the intrinsic jitter for both DPLLs of the MT8941B is shown in Figure 5. The typical peak-to-peak value for this jitter is 0.07UI. The transfer function, which is the ratio of the output jitter to the input jitter (both measured at a particular frequency), is shown in Figure 6 for DPLL #1 and Figure 7 for DPLL #2. The transfer function is measured when the peak-to-peak amplitude of the sinusoidal input jitter conforms to the following: 10 Hz - 100 Hz 100 Hz - 10 kHz > 10 kHz : 13.6 µs : 20 dB/decade roll-off : 97.2 ns The ability of a DPLL to phase-lock the input signal to the reference signal and to remain locked depends upon its lock-in range. The lock-in range of the DPLL is specified in terms of the maximum frequency variation in the 8 kHz reference signal. It is also directly affected by the oscillator frequency tolerance. Table 6 lists different values for the lock-in range and the corresponding oscillator frequency tolerance for DPLL #1 and DPLL #2. The smaller the tolerance value, the larger the lock-in range. 9 Zarlink Semiconductor Inc. MT8941B Data Sheet The T1 and CEPT standards specify that, for free running equipment, the output clock tolerance must be less than or equal to ±32ppm and ±50ppm respectively. This requirement restricts the oscillators of DPLL #1 and DPLL #2 to have maximum tolerances of ±32ppm and ±50ppm respectively. Oscillator Clock* Tolerance (±ppm) 5 10 20 32 50 100 150 175 Lock-in Range (±Hz) DPLL #1 2.55 2.51 2.43 2.33 2.19 1.79 1.39 1.19 DPLL #2 1.91 1.87 1.79 1.69 1.55 1.15 .75 .55 Note: * Please refer to the section on “Jitter Performance and Lock-in Range” for recommended oscillator tolerances for DPLL #1 & #2. Table 6 - Lock-in Range vs. Oscillator Frequency Tolerance Figure 5 - The Spectrum of the Inherent Jitter for either PLL 10 Zarlink Semiconductor Inc. MT8941B Data Sheet Figure 6 - The Jitter Transfer Function for PLL1 Figure 7 - The Jitter Transfer Function for PLL2 However, if DPLL #1 and DPLL #2 are daisy-chained as shown in Figures 9 and 10, the output clock tolerance of DPLL #1 will be equal to that of the DPLL #2 oscillator when DPLL #2 is free-running. In this case, the oscillator tolerance of DPLL #1 has no impact on its output clock tolerance. For this reason, it is recommended to use a ±32 ppm oscillator for DPLL #2 and a ±100 ppm oscillator for DPLL #1. 11 Zarlink Semiconductor Inc. MT8941B Differences between MT8941B and MT8940 Data Sheet The MT8941B and MT8940 are pin and mode compatible for most applications. However, the user should take note of the following differences between the two parts. a) Distributed Timing Data Bus Line Card 1 8 kHz Reference Signal M U X MT8940 Clocks Line Card n 8 kHz Reference Signal MT8940 Clocks b) Centralized Timing Data Bus Line Card 1 8 kHz Reference Signal M U X MT8941B Clocks Line Card n 8 kHz Reference Signal Figure 8 - Application Differences between the MT8940 and MT8941B 12 Zarlink Semiconductor Inc. MT8941B Besides the improved jitter performance, the MT8941B differs from the MT8940 in five other areas: Data Sheet 1. Input pins on the MT8941B do not incorporate internal pull-up or pull-down resistors. In addition, the output configuration of the bidirectional C8Kb pin has been converted from an open drain output to a Totem-pole output. 2. The MT8941B includes a no-correction window to filter out low frequency jitter and wander as illustrated in Figure 4. Consequently, there is no constant phase relationship between reference signal F0i of DPLL # 1 or C8Kb of DPLL #2 and the output clocks of DPLL #1 or DPLL #2. Figure 4 shows the new phase relationship between C8Kb and the DPLL #2 output clocks. Figure 8 illustrates an application where the MT8941B cannot replace the MT8940 and suggests an alternative solution. 3. The MT8941B must be reset after power-up in order to guarantee proper operation, which is not the case for the MT8940. 4. For the MT8941B, DPLL #2 locks to the falling edge of the C8Kb reference signal. DPLL#2 of the MT8940 locks on to the rising edge of C8Kb. 5. While the MT8940 is available only in a 24 pin plastic DIP, the MT8941B has an additional 28 pin PLCC package option. Applications The following figures illustrate how the MT8941B can be used in a minimum component count approach in providing the timing and synchronization signals for the Zarlink T1 or CEPT interfaces, and the ST-BUS. The hardware selectable modes and the independent control over each PLL adds flexibility to the interface circuits. It can be easily reconfigured to provide the timing and control signals for both the master and slave ends of the link. Synchronization and Timing Signals for the T1 Transmission Link Figures 9 and 10 show examples of how to generate the timing signals for the master and slave ends of a T1 link. At the master end of the link (Figure 9), DPLL #2 is the source of the ST-BUS signals derived from the crystal clock. The frame pulse output is looped back to DPLL #1 (in NORMAL mode), which locks to it to generate the T1 line clock. The timing relationship between the 1.544 MHz T1 clock and the 2.048 MHz ST-BUS clock meets the requirements of the MH89760/760B. The crystal clock at 12.352 MHz is used by DPLL #1 to generate the 1.544 MHz clock, while DPLL #2 (in FREE-RUN mode) uses the 16.384 MHz crystal oscillator to generate the ST-BUS clocks for system timing. The generated ST-BUS signals can be used to synchronize the system and the switching equipment at the master end. 13 Zarlink Semiconductor Inc. MT8941B Data Sheet Crystal Clock (12.352 MHz) MT8941B MS0 MS1 MS2 MS3 F0i C12i ENCV C8Kb C16i ENC4o ENC2o CVb C1.5i C2i C4b C2o F0b F0i DSTi DSTo CSTi CSTo TxT TxR RxT RxR VSS RST RECEIVE TRANSMIT VDD MH89760B MT8980/81 ST-BUS SWITCH T1 LINK (1.544 Mbps) Crystal Clock (16.384 MHz) Mode of Operation for the MT8941B VDD C R DPLL #1 - NORMAL (MS0 = X; MS1 = 0) DPLL #2 - FREE-RUN (MS0=1; MS2=1; MS3=1) Figure 9 - Synchronization at the Master End of the T1 Transmission Link Crystal Clock (12.352 MHz) MT8941B MS0 MS1 MS2 MS3 F0i C12i ENCV C8Kb C16i ENC4o ENC2o VDD MH89760B C1.5i C2i C4b C2o F0b F0i E8Ko DSTi DSTo CSTi CSTo TxT TxR RxT RxR TRANSMIT MT8980/81 ST-BUS SWITCH CVb RECEIVE T1 LINK (1.544 Mbps) Crystal Clock (16.384 MHz) VSS RST Mode of Operation for the MT8941B C R VDD DPLL #1 - NORMAL (MS1=0) DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1) Figure 10 - Synchronization at the Slave End of the T1 Transmission Link 14 Zarlink Semiconductor Inc. MT8941B Data Sheet MT8941B MS0 MS1 MS2 MS3 F0i C12i ENCV C8Kb Crystal Clock (16.384 MHz) MT8980/81 MH89790B DSTi C2i C2o F0i DSTo CSTi0 CSTi1 F0b CSTo OUTA OUTB Yo RxT RxR TRANSMIT CEPT PRIMARY MULTIPLEX DIGITAL LINK ST-BUS SWITCH VDD C4b C16i ENC4o ENC2o VSS RST RECEIVE VDD C R Mode of Operation for the MT8941B DPLL #1 - NOT USED DPLL #2 - FREE-RUN (MS0=1; MS1=0; MS2=1; MS3=1) Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link At the slave end of the link (Figure 10) both the DPLLs are in NORMAL mode, with DPLL #2 providing the ST-BUS timing signals locked to the 8 kHz frame pulse (E8Ko) extracted from the received signal on the T1 line. The regenerated frame pulse is looped back to DPLL #1 to provide the T1 line clock, which is the same as the master end. The 12.352 MHz and 16.384 MHz crystal clock sources are necessary for DPLL #1 and #2, respectively. Synchronization and Timing Signals for the CEPT Transmission Link The MT8941B can be used to provide the timing and synchronization signals for the MH89790/790B, Zarlink’s CEPT (30+2) Digital Trunk Interface Hybrid. Since the operational frequencies of the ST-BUS and the CEPT primary multiplex digital trunk are the same, only DPLL #2 is required. 15 Zarlink Semiconductor Inc. MT8941B Data Sheet MT8980/81 MT8941B MS0 MS1 MS2 MS3 F0i C12i Crystal Clock (16.384 MHz) VDD MH89790B DSTi C2i DSTo CSTi0 CSTi1 CSTo OUTA TRANSMIT F0i E8Ko ST-BUS SWITCH C4b ENCV C8Kb C16i ENC4o ENC2o C2o F0b Yo VSS RST OUTB RxT RxR RECEIVE CEPT PRIMARY MULTIPLEX DIGITAL LINK Mode of Operation for the MT8941B C R VDD DPLL #1 - NOT USED DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1) Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link Figures 11 and 12 show how the MT8941B can be used to synchronize the ST-BUS to the CEPT transmission link at the master and slave ends. Generation of ST-BUS Timing Signals The MT8941B can source the properly formatted ST-BUS timing and control signals with no external inputs except the crystal clock. This can be used as the standard timing source for ST-BUS systems or any other system with similar clock requirements. Figure 13 shows two such applications using DPLL #2. In one case, the MT8941B is in FREE-RUN mode with an oscillator input of 16.384 MHz. In the other case, it is in NORMAL mode with the C8Kb input tied to VDD. For these applications, DPLL #2 does not make any corrections and therefore, the output signals are free from jitter. DPLL #1 is completely free. 16 Zarlink Semiconductor Inc. MT8941B DPLL #1 - NOT USED DPLL #2 - FREE-RUN MODE (MS0=1; MS1=0;MS2=1; MS3=1) MS0 MS1 MS2 MS3 F0i C12i ENCV C8Kb C16i ENC4o ENC2o Ai Bi VSS RST Data Sheet MT8941B MS0 MS1 MS2 MS3 F0i C12i ENCV C8Kb C16i ENC4o ENC2o Ai Bi VSS RST VDD C4o C4b MT8941B VDD C4o C4b ST-BUS ST-BUS Crystal Clock (16.384 MHz) C2o C2o F0b TIMING SIGNALS Crystal Clock (16.384 MHz) C2o C2o F0b TIMING SIGNALS DPLL #1 - NOT USED DPLL #2 - NORMAL MODE (MS0=0; MS1=0; MS2=1; MS3=1) R VDD C C R VDD Figure 13 - Generation of the ST-BUS Timing Signals Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated. Parameter 1 2 3 4 5 6 7 Supply Voltage Voltage on any pin Input/Output Diode Current Output Source or Sink Current DC Supply or Ground Current Storage Temperature Package Power Dissipation - Plastic DIP - PLCC Symbol VDD VI IIK/OK IO IDD/ISS TST PD PD -55 Min. -0.3 VSS-0.3 Max. 7.0 VDD+0.3 ±10 ±25 ±50 125 1200 600 Units V V mA mA mA oC mW mW * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 ‡ Sym. VDD VIH VIL Min. 4.5 2.0 VSS Typ.‡ 5.0 Max. 5.5 VDD 0.8 Units V V V oC Test Conditions Supply Voltage Input HIGH Voltage Input LOW Voltage -40 25 85 Operating Temperature TA Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 17 Zarlink Semiconductor Inc. MT8941B DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. VDD=5.0V±5%; VSS=0V; TA=-40 to 85°C. Characteristics 1 S U P Supply Current Sym. IDD Min. Typ.‡ 8 Max. 15 Units mA Data Sheet Test Conditions Under clocked condition, with the inputs tied to the same supply rail as the corresponding pull-up /down resistors. 2 3 4 5 6 7 8 I N Input HIGH voltage (For all the inputs except pin 23) Positive-going threshold voltage (For pin 23) Input LOW voltage (For all the inputs except pin 23) Negative-going threshold voltage (For pin 23) VIH V+ VIL VIOH IOL IIL 2.0 3.0 4.0 0.8 1.0 -4 4 -100 -30 1.5 V V V V mA mA µA VOH=2.4 V VOL=0.4 V VIN=VSS O U T Output current HIGH Output current LOW Leakage current on bidirectional pins and all inputs except C12i, C16i, RST, MS1, MS0 Leakage current on pins MS1, MS0 9 10 IIL 35 120 µA VIN=VDD ‡ IIL Leakage current on all three-10 ±1 +10 µA VI/O=VSS or VDD state outputs and C12i, C16i, RST inputs Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 18 Zarlink Semiconductor Inc. MT8941B Data Sheet AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 14) Characteristics 1 2 3 4 5 6 7 D P L L #1 CVb output (1.544 MHz) rise time CVb output (1.544 MHz) fall time CVb output (1.544 MHz) clock period CVb output (1.544 MHz) clock width (HIGH) CVb output (1.544 MHz) clock width (LOW) CV delay (HIGH to LOW) CV delay (LOW to HIGH) Sym. tr1.5 tf1.5 tP15 tW15H tW15L t15HL t15LH 607 318 277 0 -7 Min. Typ.‡ 6 6 648 689 324 363 10 3 Max. Units ns ns ns ns ns ns ns Test Conditions 85 pF Load 85 pF Load † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. Figure 14 - Timing Information for DPLL #1 in NORMAL Mode AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 15) Characteristics 1 2 3 4 5 D P L L #1 C8Kb output (8 kHz) delay (HIGH to HIGH) C8Kb output (8 kHz) delay (LOW to LOW) C8Kb output duty cycle Inverted clock output delay (HIGH to LOW) Inverted clock output delay (LOW to HIGH) tICHL tICLH 0 0 Sym. tC8HH tC8LL Min. 0 Typ.‡ 10 13 66 50 10 7 25 18 Max. 25 34 Units ns ns % % ns ns Test Conditions 85 pF Load 85 pF Load In Divide -1 Mode In Divide - 2 Mode † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 19 Zarlink Semiconductor Inc. MT8941B Data Sheet Figure 15 - DPLL #1 in DIVIDE Mode tWFP F0b VOH VOL tP4o tFPL tW4oH C4b VOH VOL tW4oL t4oLH VOH VOL t42HL VOH VOL tW2oL t2oLH t2oHL C2o VOH VOL t42LH tW2oH t4oHL tFPH tfC4 trC4 C4o tP2o tfC2 trC2 C2o Figure 16 - Timing Information on DPLL #2 Outputs 20 Zarlink Semiconductor Inc. MT8941B Data Sheet AC Electrical Characteristics†-Voltages are with respect to ground (VSS) unless otherwise stated.(Refer to Figure 16) Characteristics 1 2 3 4 5 6 7 8 9 10 11 #2 12 13 14 15 16 17 18 19 C4b output clock period C4b output clock width (HIGH) C4b output clock width (LOW) C4b output clock rise time C4b clock output fall time Frame pulse output delay (HIGH to LOW) from C4b Frame pulse output delay (LOW to HIGH) from C4b D P L L Frame pulse (F0b) width C4o delay - LOW to HIGH C4o delay - HIGH to LOW C4b to C2o delay (LOW to HIGH) C4b to C2o delay (HIGH to LOW) C2o clock period C2o clock width (HIGH) C2o clock width (LOW) C2o clock rise time C2o clock fall time C2o delay - LOW to HIGH C2o delay - HIGH to LOW Sym. tP4o tW4oH tW4oL trC4 tfC4 tFPL tFPH tWFP t4oLH t4oHL t42LH t42HL tP2o tW2oH tW2oL trC2 tfC2 t2oLH t2oHL -5 0 5 0 0 225 0 0 0 0 457 207 238 6 6 2 7 488 Min. 213 85 116 6 6 13 8 245 15 20 3 6 519 280 244 Typ.‡ 244 Max. 275 159 122 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 85 pF Load 85 pF Load 85 pF Load 85 pF Load 85 pF Load 85 pF Load 85 pF Load Test Conditions 85 pF Load † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 21 Zarlink Semiconductor Inc. MT8941B Data Sheet AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 14) Characteristics 1 2 3 Master clocks input rise time Master clocks input fall time Sym. tr tf tP12 80.943 80.958 Min. Typ.‡ Max. 10 10 80.974 Units ns ns ns For DPLL #1, while operating to provide the T1 clock signal. For DPLL #2, while operating to provide the CEPT and ST-BUS timing signals. With the Master frequency tolerance at ±32 ppm. Test Conditions Master clock period C (12.352 MHz)* L 4O C Master clock period K (16.384MHz)* S 5 6 Duty Cycle of master clocks Lock-in Range DPLL #1 DPLL #2 tP16 61.023 45 -2.33 -1.69 61.035 50 61.046 55 +2.33 +1.69 ns % Hz † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Please review the section on "Jitter Performance and Lock-in Range". tr Master clock inputs 2.4 V 1.5 V 0.4 V tP12 or tP16 tf Figure 17 - Master Clock Inputs AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 18) Characteristics 1 2 3 4 F0b input pulse width (LOW) C4b input clock period Frame pulse (F0b) setup time Frame pulse (F0b) hold time Sym. tWFP tP4o tFS tFH Min. Typ.‡ 244 244 50 25 Max. Units ns ns ns ns Test Conditions † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 22 Zarlink Semiconductor Inc. MT8941B Data Sheet Figure 18 - External Inputs on C4b a nd F0b f or the DPLL #2 AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated. (Refer to Figure 19) Characteristics 1 2 3 4 O U T P U T Delay from Enable to Output (HIGH to THREE STATE) Delay from Enable to Output (LOW to THREE STATE) Delay from Enable to Output (THREE STATE to HIGH) Delay from Enable to Output (THREE STATE to LOW) Sym. tPHZ tPLZ tPZH tPZL 50 Min. Typ.‡ Max. 16 12 11 16 Units ns ns ns ns Test Conditions 85 pF Load 85 pF Load 85 pF Load 85 pF Load † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. tf 6 ns tr 6 ns 3.0 V 2.7 V 1.3 V 0.3 V tPZL Enable Input tPLZ Output LOW to OFF Output HIGH to OFF Outputs Enabled 10% tPHZ 90% 1.3 V tPZH 1.3 V Outputs Disabled Outputs Enabled Figure 19 - Three State Outputs and Enable Timings 23 Zarlink Semiconductor Inc. MT8941B AC Electrical Characteristics† - Uncommitted NAND Gate Voltages are with respect to ground (VSS) unless otherwise stated. Data Sheet Characteristics 1 2 Propagation delay (LOW to HIGH), input Ai or Bi to output Propagation delay (HIGH to LOW), input Ai or Bi to output Sym. tPLH tPHL Min. Typ.‡ Max. 11 15 Units ns ns Test Conditions 85 pF Load 85 pF Load † Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 24 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE