MT8985APR

CMOS ST-BUSTM Family MT8985 Enhanced Digital Switch Data Sheet Features • • • • • • • • • 256 x 256 channel non-blocking switch Programmable frame integrity for wideband channels Automatic identification of ST-BUS/GCI interface backplanes Per channel tristate control Patented message mode Non-multiplexed microprocessor interface Single +5 volt supply Available in DIP-40, PLCC-44 and QFP-44 packages Pin compatible with MT8980 device Ordering Information September 2005 MT8985AE 40 Pin PDIP Tubes MT8985AP 44 Pin PLCC Tubes MT8985AL 44 Pin MQFP Trays MT8985APR 44 Pin PLCC Tape & Reel MT8985AP1 44 Pin PLCC* Tubes MT8985APR1 44 Pin PLCC* Tape & Reel MT8985AE1 40 Pin PDIP* Tubes MT8985AL1 44 Pin MQFP* Trays *Pb Free Matte Tin -40° C to +85 ° C Switch (DX). It is pin compatible with the MT8980D and retains all of the MT8980D's functionality. This VLSI device is designed for switching PCM-encoded voice or data, under microprocessor control, in digital exchanges, PBXs and any ST-BUS/MVIP environment. It provides simultaneous connections for up to 256 64 kb/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s stream. As the main function in switching applications, the device provides per-channel selection between variable or constant throughput delays. The constant throughput delay feature allows grouped channels such as ISDN H0 to be switched through the device maintaining its sequence integrity. The MT8985 is ideal for medium sized mixed voice/data switch and voice processing applications. Applications • • • • • • Medium size digital switch matrices Hyperchannel switching (e.g., ISDN H0) ST-BUS/MVIP™ interface functions Serial bus control and monitoring Centralized voice processing systems Data multiplexer Description The MT8985 Enhanced Digital Switch device is an upgraded version of the popular MT8980D Digital C4i F0i VDD VSS ODE STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 Serial to Parallel Converter Data Memory Frame Counter Output MUX Parallel to Serial Converter STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 Control Register Connection Memory Control Interface DS CS R/W A5/ A0 DTA D7/ D0 CSTo Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT8985 Changes Summary The following table captures the changes from the May 2005 issue. Page 7 Item Figure 3 - “Address Memory Map“ NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC Data Sheet Change • corrected Address Memory Map NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 A3 A4 A5 DS R/W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 D5 D6 D7 CS 40 PIN PLASTIC DIP STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 NC A3 A4 A5 DS R/W CS D7 D6 D5 NC 44 PIN PLCC Figure 2 - Pin Connections 2 Zarlink Semiconductor Inc. NC A3 A4 A5 DS R/W CS D7 D6 D5 NC 44 PIN QFP 12 13 14 15 16 17 18 19 20 21 22 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 MT8985 Pin Description Pin # 40 DIP 44 44 PLCC QFP Data Sheet Name Description 1 2-9 10 11 2 40 DTA Data Acknowledgement (Open Drain Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. 3-5 41-43 STi0- ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32 7-11 1-5 STi7 channels at data rates of 2.048 Mbit/s. 12 13 6 7 VDD F0i +5 Volt Power Supply rail. Frame Pulse (Input): This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS and GCI. Clock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams. 12 14 8 C4i 13-18 15-17 9-11 A0-A5 Address 0 to 5 (Inputs). These lines provide the address to MT8985 internal 19-21 13-15 registers. 19 22 16 DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. Read/Write (Input). This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Chip Select (Input). Active low input enabling a microprocessor read or write of control register or internal memories. 20 21 23 24 17 18 R/W CS 22-29 25-27 19-21 D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data 29-33 23-27 in the internal control register, connect memory high, connect memory low and data memory. 30 34 28 VSS Ground Rail. 31-38 35-39 29-33 STo7- ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These 41-43 35-37 STo0 streams are composed of 32 channels at data rates of 2.048 Mbit/s. 39 44 38 ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial outputs. If this input is low STo0-7 are high impedance. If this input is high each channel may still be put into high impedance by software control. CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations. NC No Connection. 40 1 39 6, 18, 12,22 34, 28, 44 40 3 Zarlink Semiconductor Inc. MT8985 Functional Description Data Sheet With the integration of voice, video and data services into the same network, there has been an increasing demand for systems which ensure that data at N x 64 Kbit/s rates maintain frame sequence integrity while being transported through time slot interchange circuits. Existing requirements demand time slot interchange devices performing switching with constant throughput delay while guaranteeing minimum delay for voice channels. The MT8985 device provides both functions and allows existing systems based on the MT8980D to be easily upgraded to maintain the data integrity while multiple channel data are transported. The device is designed to switch 64 kbit/s PCM or N x 64 kbit/s data. The MT8985 can provide both frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis. By using Zarlink Message mode capability, the microprocessor can access input and output time slots on a per channel basis to control devices such as the Zarlink MT8972, ISDN Transceivers and T1/CEPT trunk interfaces through the ST-BUS interface. Different digital backplanes can be accepted by the MT8985 device without user's intervention. The MT8985 device provides an internal circuit that automatically identifies the polarity and format of frame synchronization input signals compatible to ST-BUS and GCI interfaces. Device Operation A functional block diagram of the MT8985 device is shown in Figure 1. The serial ST-BUS streams operate continuously at 2.048 Mb/s and are arranged in 125 µs wide frames each containing 32 8-bit channels. Eight input (STi0-7) and eight output (STo0-7) serial streams are provided in the MT8985 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as required in ST-BUS and GCI specifications. Data Memory The received serial data is converted to parallel format by the on-chip serial to parallel converters and stored sequentially in a 256-position Data Memory. The sequential addressing of the Data Memory is generated by an internal counter that is reset by the input 8 kHz frame pulse (F0i) marking the frame boundaries of the incoming serial data streams. Depending on the type of information to be switched, the MT8985 device can be programmed to perform time slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, the variable delay mode can be selected ensuring minimum throughput delay between input and output data. In multiple or grouped channel data applications, the constant delay mode can be selected maintaining the integrity of the information through the switch. Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input (connection mode) or it can be originated from the microprocessor (message mode). If a channel is configured in connection mode, the source of the output data is the Data Memory. If a channel is configured in message mode, the source of the output data is the Connect Memory Low. Data destined for a particular channel on the serial output stream is read from the Data or Connect Memory Low during the previous channel time slot. This allows enough time for memory access and internal parallel to serial conversion. Connection and Message Modes In connection mode, the addresses of input source for all output channels are stored in the Connect memory Low. The Connect Memory Low locations are mapped to each location corresponding to an output 64 kb/s channel. The contents of the Data memory at the selected address are then transferred to the parallel to serial converters. By having the output channel to specify the input channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcasting facility in the switch. 4 Zarlink Semiconductor Inc. MT8985 Data Sheet In message mode the CPU writes data to the Connect Memory Low locations which correspond to the output link and channel number. The contents of the Connect Memory Low are transferred to the parallel to serial converter one channel before it is to be output. The Connect Memory Low data is transmitted each frame to the output until it is changed by the CPU. The per-channel functions available in the MT8985 are controlled by the Connect Memory High bits, which determine whether individual output channels are selected into specific conditions such as: message or connection mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. In addition, the Connect Memory High provides one bit to allow the user to control the state of the CSTo output pin. If an output channel is set to three-state condition, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel three-state control, all channels on the TDM outputs can be placed in high impedance at one time by pulling the ODE input pin in LOW. This overrides the individual perchannel programming on the Connect Memory High bits. The Connect Memory data is received via the Microprocessor Interface at D0-D7 lines. The addressing of the MT8985 internal registers, Data and Connect memories is performed through address input pins and some bits of the device's Control register. The higher order address bits come from the Control register, which may be written or read through the microprocessor interface. The lower order address bits come directly from the external address line inputs. For details on the device addressing, see Software Control and Control register description. Serial Interface Timing The MT8985 master clock (C4i) is a 4.096 MHz allowing serial data link configuration at 2.048 Mb/s to be implemented. The MT8985 frame synchronization pulse can be formatted according to ST-BUS or GCI interface specifications; i.e., the frame pulse can be active in HIGH (GCI) or LOW (ST-BUS). The MT8985 device automatically detects the presence of an input frame pulse and identifies the type of backplane present on the serial interface. Upon determining the correct interface connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. In ST-BUS mode, every second falling edge of the 4.096 MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. In GCI mode, every second rising edge of the 4.096 MHz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries. Delay through the MT8985 The transfer of information from the input serial streams to the output serial streams results in a delay through the MT8985 device. The delay through the MT8985 device varies according to the mode selected in the V/C bit of the connect memory high. Variable Delay Mode The delay in this mode is dependent only on the combination of source and destination channels and it is not dependent on the input and output streams. The minimum delay achievable in the MT8985 device is 3 time slots. In the MT8985 device, the information that is to be output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if the input channel has to be output in the two channels succeeding (n+1 and n+2) the channel position as the information is input. The information switched to the third timeslot after the input has entered the device (for instance, input channel 0 to output channel 3 or input channel 30 to output channel 1), is always output three channels later. Any switching configuration that provides three or more timeslots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. Table 1 shows the possible delays for the MT8985 device in Variable Delay mode: 5 Zarlink Semiconductor Inc. MT8985 Input Channel n n Output Channel m=n, n+1 or n+2 m>n+2 Throughput Delay m-n + 32 timeslots m-n time slots Data Sheet n m