MT90502

MT90502 Multi-Channel AAL2 SAR Preliminary Datasheet Features • AAL2 Segmentation Reassembly device capable of simultaneously processing up to 1023 active CIDs (AAL2 Channel Identifier) and 1023 active VCs (Virtual Circuits). Support for up to 255 CIDs per VC. Maximum of 1023 CIDs. Implements AAL2 Common Part Sub-layer (CPS) functions specified in ITU I.363.2. Implements AAL2 Service Specific Convergence Sub-layer (SSCS) functions for G.711 PCM and G.726 ADPCM voice. Supports 44-byte PCM or ADPCM packet profiles specified in AF-VMOA-0145.00. CPS packet payload can support up to 64-bytes. Supports over-subscription of 10:1. H.100/H.110 compatible TDM bus for PCM or ADPCM data. Supports both master and slave TDM bus clock operation. TDM bus also supports compressed voice such as ITU G.723, G.728 and G.729 through HDLC encapsulation. Three UTOPIA Level 1 ports configurable as Memory Bank A SSRAM (max: 1M x18) SDRAM (max: 8M x16) DS5420 ISSUE 1 November 2001 Ordering Information MT90502AG 456 Pin Plastic BGA 0 to +70°C PHY or ATM allowing for connection to an external AAL5 SAR processor, or for chaining multiple MT90502 devices. Ports A & B are configurable as a single 8-bit UTOPIA Level 2 PHY port with 5 ADDR lines. UTOPIA module provides a cell switching function with a header translation. Performs silence suppression for PCM and ADPCM. Comfort noise generation. Capability to inject and recover CPS packets through the CPU host processor bus. 8-bit or 16-bit microprocessor port, configurable to Motorola or Intel timing. Single rail 3.3 V, 456 PBGA. IEEE 1149 (JTAG) interface. Memory Bank B (Optional) SSRAM (max: 1M x18) SDRAM (max: 8M x16) • • • • • • • • • • • • • • • • MT90502 Dual Memory Controller UTOPIA Module RX CPS Packets AAL2 SAR Receiver Port A RxA Port TxA Port TDM Bus 4096 x 64 kbps TDM Module Port B Clock and Frame Pulse TX CPS Packets AAL2 SAR Transmitter Port C RxB Port TxB Port RxC Port TxC Port Clock Recovery and Generation CPU Interface JTAG Interface Figure 1 - MT90502 Functional Block 1 MT90502 Applications • • • • • Gateway ATM Edge Switch Next Generation Digital Loop Carrier Multiservice Switching Platform 3rd Generation Mobile System Equipment Preliminary Datasheet Description The MT90502 Multi-Channel AAL2 SAR bridges a standard TDM (Time Division Multiplexed) backplane to a standard ATM (Asynchronous Transfer Mode) bus. The device provides the CPS (Common Part Sublayer) and SAR (Segmentation and Reassembly) engines. The MT90502 has the capability of simultaneously processing 1023 bi-directional CIDs (AAL2 Channel Identifiers) and 1023 bi-directional VCs (Virtual Circuits). The device can be connected directly to an H.110 compatible bus. The TDM bus consists of 32 bi-directional serial data streams operating at 2.048, 4.096, or 8.192 Mbits/s. The MT90502 directly accepts G.711 PCM (Pulse Code Modulation) and G.726 ADPCM (Adaptive Differential Pulse Code Modulation) traffic for packetisation. For these two data formats, the device also implements silence suppression and comfort noise generation. To support other voice compression algorithms, the MT90502 connects directly to commercially available DSPs through synchronous serial data streams. The Variable Bit Rate (VBR) traffic is HDLC encapsulated and carried over the serial data streams. The interface to the ATM domain is provided by three UTOPIA Level 1 ports (Ports A, B, and C). All three of the UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Ports A and B combined, architects a compliant UTOPIA Level 2 Multi-PHY port. The MT90502 provides the capability of routing ATM cells to different UTOPIA interfaces, SAR engine or CPU. This feature can be used to connect another MT90502 (to support up to 2046 CID channels or 2046 phone calls) and/or to connect an external AAL1 and/or AAL5 SAR. 2 Preliminary Datasheet MT90502 1.0 Pin-out..................................................................................................................................7 1.1 Pin Description Tables ................................................................................................................................ 8 2.0 Functional Description .....................................................................................................15 2.1 CPU Interface............................................................................................................................................ 15 2.1.1 CPU Interrupts ..................................................................................................................................... 15 2.1.1.1 Example Interrupt Flow .................................................................................................................. 15 2.1.1.1.1 Interrupt Initialisation ................................................................................................................ 16 2.1.1.1.2 Interrupt Servicing ................................................................................................................... 16 2.1.2 Intel/Motorola Interface ........................................................................................................................ 16 2.1.2.1 Extended Indirect Accessing .......................................................................................................... 18 2.1.2.1.1 Extended Indirect Writes ......................................................................................................... 18 2.1.2.1.2 Extended Indirect Reads ......................................................................................................... 19 2.1.2.2 Extended Direct Accessing ............................................................................................................ 19 2.1.2.2.1 Extended Direct Writes ............................................................................................................ 19 2.1.2.2.2 Extended Direct Reads ............................................................................................................ 19 2.1.3 MT90502 Reset Procedure.................................................................................................................. 20 2.2 TDM Transmission .................................................................................................................................... 21 2.2.1 Low-Latency Loopback Channels........................................................................................................ 22 2.2.2 Treatment of PCM/ADPCM Data ......................................................................................................... 22 2.2.2.1 CPS-Packet Length ........................................................................................................................ 24 2.2.2.2 TDM Data Formats ......................................................................................................................... 24 2.2.2.3 Phase Alignment ............................................................................................................................ 29 2.2.2.4 PCM/ADPCM CPS-Packet Assembly Structure ............................................................................ 31 2.2.3 Treatment of HDLC Data ..................................................................................................................... 32 2.2.3.1 HDLC Streams ............................................................................................................................... 32 2.2.3.2 Address Bytes ................................................................................................................................ 32 2.2.3.3 Control Bytes and Length ............................................................................................................... 34 2.2.3.4 “Raw” AAL2 CPS-Packets ............................................................................................................. 34 2.2.4 CPS-Packet Final Assembly ................................................................................................................ 35 2.2.4.1 CPU CPS-Packets ......................................................................................................................... 36 2.2.4.2 CPS-Packet Descriptor Queue ...................................................................................................... 38 2.2.4.3 TDM Frame Buffer ......................................................................................................................... 39 2.3 TX SAR ..................................................................................................................................................... 40 2.3.1 Overview.............................................................................................................................................. 40 2.3.2 AAL2 Cell Assembly Process .............................................................................................................. 40 2.3.2.1 AAL2 Cell Assembly Procedure ..................................................................................................... 42 2.3.3 AAL0 Cells ........................................................................................................................................... 43 2.4 RX SAR ..................................................................................................................................................... 44 2.4.1 RX AAL2 VC Structure ........................................................................................................................ 44 2.4.2 CID Structure ....................................................................................................................................... 45 2.4.3 CPS-Packet Disassembly Structures .................................................................................................. 46 2.4.4 CPS-Packet Loss Compensation ........................................................................................................ 52 2.4.5 CPU CPS-Packets ............................................................................................................................... 52 2.4.6 Treatment of Data Cells ....................................................................................................................... 53 2.4.7 Errors and Events ................................................................................................................................ 53 2.5 TDM Reception ......................................................................................................................................... 56 2.5.1 Overview.............................................................................................................................................. 56 2.5.2 RX Channel Association Memory ........................................................................................................ 57 2.5.3 RX Channel Underrun Condition ......................................................................................................... 57 2.5.4 Compression........................................................................................................................................ 59 2.5.5 HDLC ................................................................................................................................................... 60 2.6 UTOPIA ..................................................................................................................................................... 62 2.6.1 Overview.............................................................................................................................................. 62 3 MT90502 Preliminary Datasheet 2.6.2 UTOPIA Interfaces............................................................................................................................... 63 2.6.3 LED Operation ..................................................................................................................................... 63 2.6.4 Errors on Received Cells ..................................................................................................................... 63 2.6.5 Cell Routing ......................................................................................................................................... 64 2.6.5.1 Mask & Match Process .................................................................................................................. 64 2.6.5.2 Look-Up Tables Entries ................................................................................................................. 65 2.6.5.3 LUT Addressing ............................................................................................................................. 66 2.6.6 UTOPIA Clocks.................................................................................................................................... 67 2.6.7 External Interface Signals.................................................................................................................... 69 2.6.8 UTOPIA Flow Control .......................................................................................................................... 69 2.7 H.100/H.110 Interface ................................................................................................................................70 2.7.1 Overview.............................................................................................................................................. 70 2.7.2 Bus Signaling....................................................................................................................................... 70 2.7.3 H.100/H.110 Slave............................................................................................................................... 70 2.7.4 Operating as a Slave ........................................................................................................................... 71 2.7.5 Operating as a Master ......................................................................................................................... 71 2.7.6 H.100/H.110 Clock Selection Guide .................................................................................................... 72 2.8 Clock Recovery ..........................................................................................................................................75 2.8.1 Overview.............................................................................................................................................. 75 2.8.1.1 Adaptive Clock Recovery Modules ................................................................................................ 75 2.8.1.1.1 adapx_ref clock generation ...................................................................................................... 75 2.8.1.2 Multiplexers .................................................................................................................................... 75 2.8.2 Adaptive Clock Recovery Modules ...................................................................................................... 75 2.8.2.1 adapx_ref Clock Generation .......................................................................................................... 78 2.8.3 Multiplexers.......................................................................................................................................... 78 2.9 Silence Suppression ..................................................................................................................................83 2.9.1 Overview.............................................................................................................................................. 83 2.9.2 Simple Silent Suppression................................................................................................................... 83 2.9.2.1 Silent Bit Indication ........................................................................................................................ 83 2.9.2.2 Last Byte Indication ........................................................................................................................ 83 2.9.2.3 Match and Mask Determines Silence ............................................................................................ 83 2.9.3 Complex Silent Suppression................................................................................................................ 84 2.9.3.1 Complex Silent Suppression Operation ......................................................................................... 85 2.9.3.1.1 PCM Law Table ........................................................................................................................ 85 2.9.3.1.2 DC Offset Calculation ............................................................................................................... 86 2.9.3.1.3 Signal Energy Calculation ........................................................................................................ 86 2.9.3.2 CPS-Packet Silence State ............................................................................................................. 87 2.9.3.2.1 Silence Suppression State Table ............................................................................................. 87 2.9.3.2.2 SID Transmission Operation .................................................................................................... 87 2.9.3.2.3 SID Reception Operation ......................................................................................................... 87 2.9.4 Voice/Silence Timer............................................................................................................................. 90 2.10 HDLC .......................................................................................................................................................94 2.10.1 HDLC Overview ................................................................................................................................. 94 2.10.2 HDLC Format..................................................................................................................................... 94 2.10.3 HDLC Bit-Wise Format ...................................................................................................................... 97 2.10.4 HDLC Byte-Wise Format ................................................................................................................... 97 2.11 Memory ....................................................................................................................................................97 2.11.1 Memory Map...................................................................................................................................... 97 2.11.2 Memory Structures ............................................................................................................................ 98 2.11.3 Mem_Clk and Upclk......................................................................................................................... 103 2.11.4 Memory Controller ........................................................................................................................... 104 2.11.4.1 Overview .................................................................................................................................... 104 2.11.4.2 Functionality ............................................................................................................................... 104 2.11.5 Initializing SSRAM and SDRAM ...................................................................................................... 104 2.11.6 Memory Configuration ..................................................................................................................... 105 4 Preliminary Datasheet MT90502 3.0 Register List ....................................................................................................................107 3.1 CPU Register .......................................................................................................................................... 107 3.2 Main Registers ........................................................................................................................................ 110 3.3 TX Registers............................................................................................................................................ 125 3.4 RX Registers ........................................................................................................................................... 126 3.5 TX TDM Registers................................................................................................................................... 131 3.6 UTOPIA Registers................................................................................................................................... 136 3.7 H.100/H.110 Registers ............................................................................................................................ 152 3.8 Miscellaneous Registers ......................................................................................................................... 166 3.9 RX TDM Registers .................................................................................................................................. 169 4.0 Electrical Specification...................................................................................................171 4.1 DC Characteristics .................................................................................................................................. 171 4.2 AC Characteristics................................................................................................................................... 173 4.3 Intel/Motorola Interface............................................................................................................................ 173 4.3.1 UTOPIA Interface .............................................................................................................................. 181 4.3.2 External Memory Interface................................................................................................................. 181 4.3.3 H.100/H.110 Interface........................................................................................................................ 182 5.0 Glossary of Terminology................................................................................................186 5.1 Standard Terms and Abbreviations......................................................................................................... 186 5.2 Terms specific to AAL2 ........................................................................................................................... 187 5.3 Terms specific to this specification.......................................................................................................... 187 5.4 Register types ......................................................................................................................................... 187 5.5 Units and Conventions ............................................................................................................................ 188 6.0 Mechanical Drawing .......................................................................................................189 5 MT90502 Preliminary Datasheet 6 Preliminary Datasheet 1.0 Pin-out 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 MT90502 1 A BC DE FG H J K L MN P R TU VW Y AA AB AC AD AE AF Figure 2 - 456 PBGA The following tables contain each pin of the MT90502’s main functional areas. A description of each pin is also provided. Notes: • • • • • • • • All outputs are +3.3 VDC. All input and output pins that are designated (F) can withstand 5 VDC b eing applied to them. All input and output pins that are designated (F) are tested with a 50 pF load unless otherwise specified. Designations under the “rst” (reset condition) table column are: X = undefined; Z = high impedance; 1 = high (+3.3 V DC). I/O types include: Output (O), Input (I), Bidirectional (I/O), Power (PWR) and Ground (GND). All buses have pins listed in order from MSB to LSB. Pins with more than one function have their functions numbered. Unused H.100/H.110 input pins should be tied high with an external pull-up. 7 MT90502 1.1 Pin Description Tables Preliminary Datasheet Pin AC3 F25, F23, J24, J23 AA3, AA4, Y1, Y2, Y3, Y4, W1, W2, W3, W4, V1, V2, V3, V4, U1 T2 T1 U4 T4 rst Name upclk cpu_mode[3:0] cpu_a[14:0] I/O I I I Type LVTTL (F) LVTTL (F) LVTTL (F) CPU Clock. Description CPU Interface Mode Select (4 bits). CPU Address bus. cpu_wr_r/w cpu_rd_ds cpu_ale cpu_a_das I I I I LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) Intel Write or Motorola Read/Write Intel Read or Motorola Data Strobe Address Latch Enable Direct Access Select. ‘1’ selects the direct address space. ‘0’ selects the indirection registers contained in the CPU interface. This pin can be connected to the MSB of an address bus. CPU chip select CPU Data bus U3 T3, R1, R2, R3, R4, P1, P2, P3, P4, N1, N2, N3, N4, M1, M2, M3 U2 AC2 AC1 Z cpu_cs cpu_d[15:0] I I/O LVTTL (F) LVTTL 6 mA (F) Z Z Z cpu_rdy_dtack interrupt1 interrupt2 I/O O O LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL 6 mA (F) Intel Ready or Motorola Data Ack. Interrupt 1 (configurable polarity) Interrupt 2 (configurable polarity) Table 1 - CPU Bus Interface Pins C21 A19 D21 D12 D14 A13 rst Z Z Name txa_led rxa_led rxa_alarm I/O I/O I/O I I/O O O Type LVTTL 12 mA (F) LVTTL 12 mA (F) LVTTL (F) LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL 6 mA (F) Description UTOPIA port A TX LED UTOPIA port A RX LED UTOPIA port A PHY alarm UTOPIA port A TX clock UTOPIA port A TX Start of Cell 1. UTOPIA port A TX Enable in ATM mode 2. UTOPIA port A TX Cell Available in PHY mode 1. UTOPIA port A TX Cell Available in ATM mode 2. UTOPIA port A TX Enable in PHY mode UTOPIA port A TX Data bus UTOPIA port A TX Parity UTOPIA port A RX clock UTOPIA port A RX Start of Cell Z Z Z txa_clk txa_soc 1. txa_enb 2. txa_clav B13 1. txa_clav 2. txa_enb I LVTTL (F) C15, B15, A15, C14, B14, A14, D13, C13 D15 A9 C12 Z Z Z txa_d[7:0] txa_prty rxa_clk rxa_soc O O I/O I LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL (F) Table 2 - UTOPIA Interface Pins 8 Preliminary Datasheet Pins B9 MT90502 rst Z Name 1. rxa_enb 2. rxa_clav I/O O Type LVTTL 6 mA (F) Description 1. UTOPIA port A RX Enable in ATM mode 2. UTOPIA port A RX Cell Available in PHY mode 1. UTOPIA port A RX Cell Available in ATM mode 2. UTOPIA port A RX Enable in PHY mode UTOPIA port A RX Data bus UTOPIA port A RX Parity UTOPIA port B TX LED UTOPIA port B RX LED UTOPIA port B PHY alarm UTOPIA port B TX clock UTOPIA port B TX Start of Cell 1. UTOPIA port B TX Enable in ATM mode 2. UTOPIA port B TX Cell Available in PHY mode 1. UTOPIA port B TX Cell Available in ATM mode 2. UTOPIA port B TX Enable in PHY mode UTOPIA port B TX Data bus UTOPIA port B TX Parity UTOPIA port B RX clock 1. UTOPIA port B RX Start of Cell 2. txa_addr[4] when port A and B are combined 1. UTOPIA port B RX Enable in ATM mode 2. UTOPIA port B RX Cell Available in PHY mode 1. UTOPIA port B RX Cell Available in ATM mode 2. UTOPIA port B RX Enable in PHY mode 1. UTOPIA port B RX Data bus [4:0] 2. rxa_addr[4:0] when port A and B are combined 1. UTOPIA port B RX Data bus [7:5] 2. txa_addr[2:0] when port A and B are combined 1. UTOPIA port B RX Parity. 2. txa_addr[3] when port A and B are combined. C9 1. rxa_clav 2. rxa_enb I LVTTL (F) A12, C11, B11, A11, D10, C10, B10, A10 B12 D17 C17 B17 D5 D8 A6 Z Z Z Z Z rxa_d[7:0] rxa_prty txb_led rxb_led rxb_alarm txb_clk txb_soc 1. txb_enb 2. txb_clav I I I/O I/O I I/O O O LVTTL (F) LVTTL (F) LVTTL 12 mA (F) LVTTL 12 mA (F) LVTTL (F) LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL 6 mA (F) B6 1. txb_clav 2. txb_enb I LVTTL (F) B8, A8, D7, C7, B7, A7, D6, C6 C8 E4 A4 Z Z Z txb_d[7:0] txb_prty rxb_clk 1. rxb_soc 2. txa_addr[4] O O I/O I LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL (F) D3 Z 1. rxb_enb 2. rxb_clav O LVTTL 6 mA (F) C1 1. rxb_clav 2. rxb_enb I LVTTL (F) A2, D4, A1, B1, C2 1. rxb_d[4:0] 2. rxa_addr[4:0] I LVTTL (F) A3, B3, B2 1. rxb_d[7:5] 2. txa_addr[2:0] I LVTTL (F) B4 1. rxb_prty 2. txa_addr[3] I LVTTL (F) Table 2 - UTOPIA Interface Pins (continued) 9 MT90502 Pins J4 D2 G1 Preliminary Datasheet rst Z Z Z Name txc_clk txc_soc 1. txc_enb 2. txc_clav I/O I/O O O Type LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL 6 mA (F) Description UTOPIA port C TX clock UTOPIA port C TX Start of Cell 1. UTOPIA port C TX Enable in ATM mode 2. UTOPIA port C TX Cell Available in PHY mode 1. UTOPIA port C TX Cell Available in ATM mode 2. UTOPIA port C TX Enable in PHY mode UTOPIA port C TX Data bus UTOPIA port C TX Parity UTOPIA port C RX clock UTOPIA port C RX Start of Cell 1. UTOPIA port C RX Enable in ATM mode 2. UTOPIA port C RX Cell Available in PHY mode 1. UTOPIA port C RX Cell Available in ATM mode 2. UTOPIA port C RX Enable in PHY mode UTOPIA port C RX Data bus UTOPIA port C RX Parity G2 1. txc_clav 2. txc_enb I LVTTL (F) E3, E2, E1, F3, F2, F1, G4, G3 D1 L1 H3 L2 Z Z Z txc_d[7:0] txc_prty rxc_clk rxc_soc O O I/O I O LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL 6 mA (F) LVTTL (F) LVTTL 6 mA (F) Z 1. rxc_enb 2. rxc_clav L3 1. rxc_clav 2. rxc_enb I LVTTL (F) H1, J3, J2, J1, K4, K3, K2, K1 H2 rxc_d[7:0] rxc_prty I I LVTTL (F) LVTTL (F) Table 2 - UTOPIA Interface Pins (continued) Pin A22 A21 A24 B22 A17 A16 D18 rst Z Z Z Z Z Z Z Name ct_c8_a ct_c8_b ct_frame_a ct_frame_b ct_netref1 ct_netref2 ct_mc I/O I/O I/O I/O I/O I/O I/O I/O Type LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) PCI (F) Description H.100 8MHz clock A H.100 8MHz clock B H.100 Frame A H.100 Frame B H.100 Netref 1 H.100 Netref 2 H.100 Message Channel. If this pin is connected to the H100 bus, gpio[2] must be used to drive it. H.100 serial data bus C25, D25, E26, E25, E24, F26, F24, G26, G25, G24, G23, H24, J26, J25, K26, K24, L23, L24, M25, M24, N25, P24, P23, R24, R25, T26, U23, U26, V23, V24, V26, W23 Z ct_d[31:0] I/O Table 3 - H.100/H.110 Interface Pins 10 Preliminary Datasheet Pin B20 C20 C18 A18 D20 C19 B21 MT90502 Name sclk sclkx2 c16p c16n c2 c4 frcomp rst Z Z Z Z Z Z Z I/O O O O O O O O Type LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) LVTTL 24 mA (F) Description H.100 SCBUS system clock H.100 SCBUS system clock x 2 H.100 H-MVIP 16 MHz clock positive output H.100 H-MVIP 16 MHz clock negative output H.100 MVIP-90 2 MHz clock H.100 MVIP-90 4 MHz clock H.100 compatibility frame pulse Table 3 - H.100/H.110 Interface Pins (continued) Pin AF2 AF11, AD10, AF10, AD9, AF9, AE8, AC7, AE7, AD7, AF8, AD8, AE9, AC9, AE10, AC10, AE11 AD11, AF7 AF4, AE3 AE5 AE4, AF5 AE12 AD12 AF12 AD6, AE6, AF6, AD5, AF3, AC12, AE13, AF13, AF14, AD13, AE14, AC14, AE15, AC15, AE16, AF16, AD15, AF15, AD14 AE22, AD22, AF24, Z AE24, AD25, AC25, AB24, AB26, AB25, AC26, AD26, AE26, AE23, AF23, AD21, AE21 AF22, AA24 W25, W26 Y25 W24, Y26 AC20 AD20 Z 1 Z Z Z Z Z rst Name mem_clk mema_d[15:0] I/O I I/O Type LVTTL LVTTL 6 mA Description memory clock (common to both bank A and B). It is also employed as the internal master clock. SDRAM/SSRAM bank A data bus Z 1 Z Z Z Z Z mema_p[1:0] mema_cs[1:0] mema_r/w mema_bws[1:0] mema_cas mema_ras mema_we mema_a[18:0] I/O O O O O O O O LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA SDRAM/SSRAM bank A parity bits SSRAM bank A Chip selects 1, 0 SSRAM bank A Read/Write SSRAM bank A Byte Write Selects 1:0 SDRAM bank A Column Address Select SDRAM bank A Row Address Select SDRAM bank A Write Enable SDRAM/SSRAM bank A address bus memb_d[15:0] I/O LVTTL 6 mA SDRAM/SSRAM bank B data bus memb_p[1:0] memb_cs[1:0] memb_r/w memb_bws[1:0] memb_cas memb_ras I/O O O O O O LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA LVTTL 6 mA SDRAM/SSRAM bank B parity bits SSRAM bank B Chip selects 1,0 SSRAM bank B Read/Write SSRAM bank B Byte Write Selects 1,0 SDRAM bank B Column Address Select SDRAM bank B Row Address Select Table 4 - Memory Interface Pins 11 MT90502 AF21 AA25, AA26, Y23, Y24, AC21, AE20, AC19, AF20, AE19, AD19, AF19, AE18, AC17, AE17, AD16, AF17, AD17, AF18, AD18 Z memb_we memb_a[18:0] O O LVTTL 6 mA LVTTL 6 mA Preliminary Datasheet SDRAM bank B Write Enable SDRAM/SSRAM bank B address bus Table 4 - Memory Interface Pins (continued) Pin AA1 AF26, AC24, AB23, AA23, T24, R26, N23, M23 Z rst Name reset gpio[7:0] I/O I I/O Type LVTTL (F) Description Global Hardware Reset (active low) LVTTL 6 mA General Purpose I/Os (F) Table 5 - Miscellaneous Pins Pin A26 D22 A25 C23 A23 Name trst tck tdi tms tdo I/O I I I I O Type LVTTL (F) LVTTL (F) LVTTL (F) LVTTL (F) LVTTL 6 mA (F) Table 6 - JTAG Pins Pin AB2 A5 AB3 AE2 B5 AB1 AE1 Name pll_clk PLLVDD1 PLLVDD2 PLLVDD3 PLLGND1 PLLGND2 PLLGND3 I/O I Type LVTTL (F) Description PLL reference clock used for H.100 Master clock generation PLL Power Pin (3.3V). Place one .01uF, one 10uF and one 100pF capacitor near PLL_VDD1 / PLL_GND1 pins. PLL Power Pin (3.3V). Place one .01uF, one 10uF and one 100pF capacitor near PLL_VDD2 / PLL_GND2 pins. PLL Power Pin (3.3V). Place one .01uF, one 10uF and one 100pF capacitor near PLL_VDD3 / PLL_GND3 pins. PLL Ground Pin (0V). PLL Ground Pin (0V). PLL Ground Pin (0V). Description JTAG Test Reset JTAG Test Clock JTAG Test Data In JTAG Test Mode Select JTAG Test Data Out Table 7 - Phase Lock Loop (PLL) Pins VSS (0V): D9, D11, E5, E6, E9, E10, E13, E14, E17, E18, E21, E22, F4, F5, F22, H4, J5, J22, K5, K22, L4, L11, L12, L13, L14, L15, L16, M4, M11, M12, M13, M14, M15, M16, N5, N11, N12, N13, N14, N15, N16, N22, P5, P11, P12, P13, P14, P15, P16, P22, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, U5, U22, V5, V22, AA5, AA22, AB5, AB6, AB9, AB10, AB13, AB14, AB17, AB18, AB21, AB22, AF25. Table 8 - VSS (0V) Pins VDD3 (3.3 V): C3, C24, D23, E7, E8, E11, E12, E15, E16, E19, E20, G5, G22, H5, H22, L5, L22, M5, M22, R5, R22, T5, T22, W5, W22, Y5, Y22, AB7, AB8, AB11, AB12, AB15, AB16, AB19, AB20, AC4, AC23, AD3, AD24, AF1 Table 9 - VDD3 (3.3V) Pins 12 Preliminary Datasheet MT90502 Note: If MT90502 is only connected to 3.3V devices on the H.100/H.110 bus, then 3.3V can be connected to the following pins. If any devices are 5V then these pins must be connected to 5V. VDD5 (3.3 V or 5.0 V): B25, D24, H26, L26, P25, U24 Table 10 - VDD5 (3.3V or 5.0V) Pins Not Connected (Leave Floating): A20, B16, B18, B19, B23, B24, B26, C4, C5, C16, C22, C26, D16, D19, D26, E23, H23, H25, K23, K25, L25, M26, N24, N26, P26, R23, T23, T25, U25, V25, AA2, AB4, AC5, AC6, AC8, AC11, AC13, AC16, AC18, AC22, AD1, AD2, AD4, AD23, AE25 Table 11 - Not Connected (Leave Floating) Pins Type CPU Bus UTOPIA Port A UTOPIA Port B UTOPIA Port C H.100/H.110 Memory Miscellaneous JTAG PLL Power Ground No Connect Total: 71 101 110 48 81 Input 25 13 13 12 0 1 1 4 1 Output 2 12 12 12 7 54 0 1 0 I/O 17 4 4 2 39 36 8 0 0 3 46 79 45 45 3 Power Ground N/C Total 44 29 29 26 46 91 9 5 7 46 79 45 456 Note: Pins are listed under their main (default) function for UTOPIA ports A and B Table 12 - Pinout Summary 13 MT90502 Preliminary Datasheet 14 Preliminary Datasheet 2.0 2.1 MT90502 Functional Description CPU Interface The MT90502 CPU module provides an interface permitting programmability from an external microprocessor or CPU. The CPU module permits read/write access to the MT90502’s internal registers, internal memory and external memories. The CPU interface is comprised of the following: [1] Direct Access Select (DAS) as the MSB bit concatenated with a 15-bit address bus [2] 16-bit data bus [3] 2 interrupt signals [4] associated control signals. The CPU interface can be configured to operate in either Intel or Motorola mode. The MT90502 supports both 8-bit or 16-bit data bus and multiplexed or non-multiplexed address/data pins. If the CPU is operating in 16-bit byte mode with the LSB of its address bus as a byte field, then the cpu_a[14:0] pins of the MT90502 can be connected to the a[15:1] pins of the CPU. If both the MT90502 and the CPU are in 16-bit word mode, then the cpu_a[14:0] pins should be connected to the a[14:0] pins of the CPU. A reduced set of registers, the ‘CPU Interface Registers’ (000h to 00Ah), are employed to optimise access time and to permit the CPU to execute indirect read/write accesses. The CPU also engages these registers to perform direct read/write accesses. The MT90502 and CPU timing relationship is described in Section 4.3, “Intel/Motorola Interface,” on page 173. The CPU Control Register (100h) provides a software reset capability that allows the CPU to reset the MT90502 except for the CPU interface. The CPU interface can only be reset by a hardware reset. 2 .1.1 CPU Interrupts The CPU interface provides a programmable global interrupt capability. The interrupt signal names are ‘interrupt1’ and ‘interrupt2’, pins AC2 and AC1 respectively. Both interrupts have programmability to select their polarity (open collector drive) via registers ‘interrupt1_conf’ and ‘interrupt2_conf’, addresses 214h and 216h respectively. Interrupt1 provides the capability to program a minimum acceptable period between interrupts. The period is programmed in µs units via the ‘interrupt1_conf’ register. This provides a ‘frequency interrupt controller’ facility and masks the assertion of further interrupts until the specified period of time has elapsed. The mask period will start when the interrupt1_treated [15] bit in the register ‘interrupt_flags’ (address 210h) is set. When Interrupt2 is enabled it is always activated when an interrupt condition occurs. The operation of the CPU interrupt network is common for all modules. When an interrupt is asserted, an interrupt flag is set to identify the module where the interrupt was generated. Each module has one or more Interrupt Enable Registers where a set interrupt enable bit enables an interrupt source. On completion of the ISR the interrupt must be cleared as the interrupt will remain asserted until it is de-asserted by the user. All Interrupt Enable Registers have a mirror Status Register. Hence, the bit positioning of the interrupt enables and the corresponding status bits are identical. Note: Interrupt pins are always tri-stated when inactive. 2.1.1.1 Example Interrupt Flow Upon the initialisation of the Global Interrupt pins the following methodology is adopted to identify the source of the interrupt. For this example Interrupt2 is employed and the CPU module will be the source of the interrupt. 15 MT90502 2.1.1.1.1 Interrupt Initialisation • • Preliminary Datasheet • Set interrupt polarity, register interrupt2_conf[15:14]. Enable Interrupt2 for the CPU module by setting bit 0 in interrupt2_enable register (21Ah). The MT90502 will generate an interrupt on interrupt2 according to the modules enabled in interrupt2_enable. Set the individual CPU interrupt sources by enabling the respective bits in the ‘status0_ie’ register (104h). Within the ‘status0_ie’ register there are two possible interrupt sources: internal_read_timeout_ie and cpu_read_done_ie. In the MT90502 Register Description the interrupt bits are labelled IE (Interrupt Enable) in the ‘Type’ column. This register offers the facility to mask/disable unwanted interrupts. 2.1.1.1.2 Interrupt Servicing When interrupt2 is asserted (‘interrupt2’ pin): • • • Read the interrupt flags to ascertain the module raising the interrupt. The CPU module interrupt flag is located in register interrupt_flags (210h), this bit is named cpureg_interrupt_active. If the cpureg_interrupt_active bit is set, locate the source of the CPU interrupt by reading the ‘status0’ at 102h, either internal_read_timeout and/or cpu_read_done. To de-assert the interrupt the user must write a 1 to register 102h bits 3 and/or 4, internal_read_timeout and cpu_read_done respectively. Only then will the interrupt be de-asserted. Intel/Motorola Interface Control Register Read/Write Data Register Address High Register Address Low Register 2.1.2 000h 004h 008h 00Ah The MT90502 CPU interface supports both Intel and Motorola modes with an 8-bit or 16-bit data bus and multiplexed or non-multiplexed address/data pins. The MT90502 supports 68MB of addressable space, therefore indirection addressing is necessary. The CPU interface directly addresses four control words, delegated for indirection accessing. The Indirection Register contents are shown in Table 14 to Table 17 inclusively. The timing relationship pertaining to the CPU Interface Registers and Extended Access is defined in Section 4.3 on page 173. 16 Preliminary Datasheet MT90502 ale cpu_ale* cpu_ale* cpu_ale* cpu_ale* address pins cpu_a[14:0]** (word address) cpu_d[15:1]** (word address) cpu_a[14:0]** (byte address) cpu_a[14:8]** & cpu_d[7:0] (byte address) cpu_a[14:0]** (word address) cpu_d[15:1]** (word address) cpu_a[14:0]** (byte address) cpu_a[14:8]**& cpu_d[7:0] (byte address) data pins cpu_d[15:0] cpu_d[15:0] cpu_d[7:0] cpu_d[7:0] direct_access cpu_a_das cpu_a_das cpu_a_das cpu_a_das cpu_mode [3:0] 0000 0001 0010 0011 Interface Type Intel, 16 bit data bus, non-multiplexed Intel, 16 bit data bus, multiplexed Intel, 8 bit data bus, non-multiplexed Intel, 8 bit data bus, multiplexed Motorola, 16 bit data bus, non-multiplexed Motorola, 16 bit data bus, multiplexed Motorola, 8 bit data bus, non-multiplexed Motorola, 8 bit data bus, multiplexed Reserved 0100 0101 0110 0111 cpu_ale* cpu_ale* cpu_ale* cpu_ale* cpu_d[15:0] cpu_d[15:0] cpu_d[7:0] cpu_d[7:0] cpu_a_das cpu_a_das cpu_a_das cpu_a_das 1xxx * The cpu_ale pin is interpreted in all modes. However, it is not necessary in the non-multiplexed modes and can be tied to VCC. * *The address placed on the cpu_a[14:0] pin is a word address in 16-bit mode and a byte address in 8-bit mode. The address, when placed on the cpu_d pins, is always a byte address. Table 13 - CPU Interface Mode Selection Field read_burst_length reserved access_req Bit 6:0 7 8 Type RW RO PC Reset 01h 0h 0h Description Number of words to prefetch: 00h = 128; 01h= 1; 02h = 2, etc. This field is set to 01h for individual (non-sequential) reads. Reserved. Set by software when an extended access is initialized. Reset by hardware when the access is completed. Used for extended indirect access only. Extended address bits 3:1. Invalid for extended direct access. Active high write enables. 00 = read access. 01 = write to lower byte. 10 = write to upper byte. 11 = write to entire word. This field is ignored for extended direct reads and all byte wide extended direct accesses. Read/Write Parity bits. extended_a[3:1] write_enable 11:9 13:12 RW RW 0h 0h extended_parity 15:14 RW 0h Table 14 - Control Register (000h) 17 MT90502 Field extended_data[15:0] Bit 15:0 Type RW Reset 0000h Preliminary Datasheet Description The extended indirect read/write data word register. Invalid for extended direct access. Table 15 - Read/Write Data Register (004h) Field extended_a[32:20] Reserved Bit 12:0 15:13 Type RW RO Reset 000h 0h Description Upper extended address [32:20]. Table 16 - Address High Register (008h) Field extended_a[19:4] Bit 15:0 Type RW Reset 0000h Description Lower extended address [19:4]. In extended direct addressing, bits 19:16 are employed for 16-bit data bus; bits 19:15 are employed or 8-bit data bus. Table 17 - Address Low Register (00Ah) 2.1.2.1 Extended Indirect Accessing Extended Indirect Accessing solely employees the registers 000h to 00Ah to access the 68MB of addressable memory space. Synopsis: The access address is written to registers 000h, 008h, and 00Ah. The MT90502 will read/write to that address and fetch/place the data value from/to register 004h. For all extended indirect accesses the CPU_A_DAS bit will be held low. 2.1.2.1.1 Extended Indirect Writes The following steps must be executed to perform an extended indirect write: 1. 2. 3. 4. 5. Write the upper address, extended_a[32:20], to register 008h. This write may not be required if previous value holds true. Write the lower address, extended_a[19:4], to register 00Ah. This write may not be required if previous value holds true. Write the write data, extended_data[15:0], to register 004h. This write may not be required if previous value holds true. Write write_enable, extended_parity, access_req=‘1’ and extended_a [3:1] in a single access to register 000h. Read the access_req bit located in the Control Register[8] to determine when the write cycle has completed. The software will set access_req [8] in register 000h (see Step 4 above). The hardware will reset the bit when the data write cycle has completed. Therefore, this bit can be polled to determine when the data write cycle has completed. 18 Preliminary Datasheet 2.1.2.1.2 Extended Indirect Reads 1. 2. 3. 4. MT90502 Write the upper address, extended_a[32:20], to register 008h. This write may not be required if previous value holds true. Write the lower address, extended_a[19:4], to register 00Ah. This write may not be required if previous value holds true. Write write_enable = 00, access_req=‘1’ and extended_a [3:1] in a single access to register 000h. Wait until access_req is cleared, then read the data from the data field extended_data[15:0], register 004h. Optional parity check may be ascertained by performing a read on the extended_parity[15:14], register 000h. The software will set access_req[8] register 000h and the hardware will reset it when the data is ready to be read from register 004h. 2.1.2.2 Extended Direct Accessing Extended Direct Accessing employs the high and low address registers to perform page addressing. The address within the page is provided directly by the CPU address bus. Similarly, the data is fetched/placed directly on the CPU data bus. Synopsis: The access address is written to registers 008h and 00Ah. This will perform only the page addressing. Upon assertion of the address within the page, the MT90502 will read/write the data with respect to that address. The CPU_A_DAS bit is set when the data read/write occurs. When operating the CPU interface in direct mode with a 16-bit data bus, extended_a[19:16], are employed for the lower address word register 00Ah. However, when operating the CPU interface in direct mode with an 8-bit data bus, bits [19:15] are used for the lower address word. 2.1.2.2.1 Extended Direct Writes 1. 2. 3. 4. Write the upper address, extended_a[32:20], to register 008h. This write may not be required if previous value holds true. Write the lower address extended_a[19:16] or [19:15] to register 00Ah. The remaining bits [15:4] or [14:4] are ignored. This write may not be required if previous value holds true. Write write_enable[13:12] (this write may not be required if previous value holds true) and extended_parity[15:14]. The extended parity write is optional. Write the data value to the address within the corresponding memory page with the CPU_A_DAS bit set. 2 .1.2.2.2 Extended Direct Reads 1. 2. 3. 4. Write the upper address, extended_a[32:20], to register 008h. This write may not be required if previous value holds true. Write the lower address, extended_a[19:16] or [19:15], to register 00Ah. The remaining bits [15:4] or [14:4] are ignored. This write may not be required if previous value holds true. Assert the lower address within the memory page and fetch the read data with CPU_A_DAS set. An optional read may be performed to obtain the parity values, extended_parity[15:14] register 000h. 19 MT90502 2.1.3 MT90502 Reset Procedure Preliminary Datasheet The following reset procedure is required to power-up the MT90502. The reset procedure must be adhered at power-up employing the nreset pin. All register accesses in the reset procedure may be performed in either Direct or Indirect mode. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Assert the nreset pin for approximately 1000 mem_clk periods. De-assert the nreset pin. Clear sreset bit in CPU Control Register (100h). Configure mem_clk, upclk, and the led flashing frequencies in the CPU Registers (108h, 10Ah and 10Ch). Configure the fast_clock PLL via registers 16Ch and 172h. Configure the H.100/H.110 PLL in the CPU Register 174h. Set active levels for interrupt pins in the Main Registers (214h and 216h). Configure the UTOPIA port clocks in the Main Registers (220h, 222h, 224h, 228h, 22Ah and 22Ch). Configure external memories in the Main Registers (230h, 232h, 234h, 240h and 242h). Wait 10µs. Set sreset bit in CPU Control Register (100h). Initialise the SDRAM in the Main Registers (250h, 252h, 254h, 256h, 258h and 25Ah). 20 Preliminary Datasheet 2.2 TDM Transmission MT90502 The TDM transmission module reads TDM data received by the H.100/H.110 interface, arranges the data in AAL2 CPS-Packets, and places the CPS-Packets in a FIFO for treatment by the TX SAR. The TX TDM module is capable of treating PCM data, ADPCM data and HDLC packets. Each channel can be configured as PCM, ADPCM or HDLC individually. For HDLC packets, zero-extraction (bit-wise or byte-wise - see Section 2.10 on page 94), and extraction of address, control and CRC bytes is performed. The received data is formatted into CPS-Packets that include CID, LI and UUI information. TDM Byte Received from H.100/H.110 TX Channel Associated Link-List Consulted Write byte to Low Latency Loopback Memory Byte Written to HDLC Buffer in SSRAM (after Zero Extraction) Byte Written to xxPCM Buffer in SSRAM CPS-Packet Transmission Requests CPS-Packet Sent via TX CPU CPSP Buffer CPS-Packet To Cell Process Cell Sent on UTOPIA Figure 3 - TX Cell Flow There are 32 streams on the H.100/H.110 bus, running at 2.048, 4.096 or 8.192MHz. Each individual time slot or DS0 channel on the H.100/H.110 bus is assigned a unique TSST (Time Slot/STream) number, according to the time slot number, stream number and the rate of the stream. Time slot * 32 + Stream, TSST= (Time slot * 2 + 1) * 32 + Stream, (Time slot * 4 + 3) * 32 + Stream, if Stream frequency is 8.192MHz; if Stream frequency is 4.096MHz; if Stream frequency is 2.048MHz. The time slot ranges are 0 to 31 for 2.048MHz streams, 0 to 63 for 4.096MHz stream, or 0 to 127 for 8.192MHz streams. Inside the MT90502 the TSST number is used to address any TDM channel position on the H.100/H.110 bus. A TX TDM frame buffer exists in internal memory that contains the most recently received TDM bytes from each of the 4096 TSSTs. From the frame buffer, up to 1023-bytes are read each frame, according to the TSST link-list in TX Channel Association Memory (TX CAM). The TX CAM entry contains a channel number, an associated TSST, and a link to where the next valid entry exists in the TX CAM. The entries in the TX CAM must be linked sequentially according to TSST but can exist in any order in memory. Each entry in TX CAM is one of the following four types: 1. The TSST in that entry carries PCM or ADPCM data. An xxPCM Channel Number should be assigned. 2. The TSST in that entry belongs to an HDLC stream. An HDLC Stream Number should be assigned. 21 MT90502 Preliminary Datasheet 3. The TSST in that entry is a loopback channel. A Low-Latency Loopback (LLL) Channel Number should be assigned. 4. The TSST in that entry is a phasing channel. The device will use the data on that TSST to synchronize its internal phase/sub-phase operation. Each TSST that carries PCM, ADPCM or HDLC data needs a CPS-Packet assembly structure in TX TDM Control memory to have CPS-Packets assembled. The xxPCM channel number and HDLC Stream Number are used to indicate the memory location of the CPS-Packet assembly structure and the CPS-Packet final assembly structure. 2.2.1 Low-Latency Loopback Channels A low-latency loopback (LLL) is a connection between any TX TDM channel and any RX TDM channel. Up to 128 loopback connections can be established. Channels designated as LLL channels in the TX CAM are written directly into the appropriate location in the LLL memory of the RX TDM module. Once there, they are routed out to TSSTs that are assigned the same LLL channel numbers in RX CAM. 2.2.2 Treatment of PCM/ADPCM Data PCM and ADPCM data is accumulated in a CPS-Packet circular buffer in TX SSRAM until the number of bytes pending equals the length of the AAL2 CPS-Packet to be assembled, as specified in the number of EDUs (# EDU) field of the PCM/ADPCM CPS-Packet assembly structure for that xxPCM channel. The TX TDM is capable of treating PCM at 64 kbps and compressed ADPCM at 40, 32, 24, or 16 kbps. For the compressed ADPCM channels, instead of capturing all 8-bits in an incoming TDM byte, the MT90502 will only sample 5-, 4-, 3-, or 2-bits of the byte, according to the data rate. The MT90502 can be configured to sample either the MSBs or the LSBs of TDM bytes; the configuration applies to all compressed channels. 22 Preliminary Datasheet MT90502 b15 b14 b13 b12 b11 b10 +0 +2 +4 +6 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 HDLC Stream/xxPCM Channel Number TSST[11:0] Link to next entry HDLC Stream or xxPCM Channel Structure b15 b14 b13 +0 +2 +4 +6 b12 b11 b10 1 b9 0 b8 00LL b7 0 b6 b5 b4 b3 b2 b1 b0 LLL Channel Number Link to next entry TSST[11:0] LLL Channel Structure b15 b14 b13 b12 b11 b10 +0 +2 +4 +6 1 b9 0 b8 0 b7 1 b6 0 b5 0 b4 0 b3 0 b2 0 b1 b0 XPI TSST[11:0] Link to next entry Phasing Channel Structure Reserved TX CAM Notes: • • • • • • • The TX CAM consists of 1024 8-byte structures in internal memory at addresses 4000h to 5FF8h. One TX CAM entry exists for each selected TSST. The HDLC Stream/xx PCM Channel Number is used to locate the CPS-Packet assembly structure, the CPS-Packet final assembly structure (see Figures 12, 13, 14, 15 and 16) and the CPS-Packet buffer for the associated TSST. Link to next entry: A pointer to the next entry in the linked list of TX CAM entries. 000h indicates the end of the linked list (return to start). Entry 0 in the linked list is always examined at the start of frame and is never associated to a valid TDM channel. The TX CAM entries are each consulted once every frame. TX CAM entries can exist in any order in memory but must be linked in order of TSST. XPI: External Phase Indicator: “00” = 24 frame phase; “01” = 80 frame phase; “10” = 64 frame phase (also used for 8, 16 and 32 frame phase); “11” = 88 frame phase Figure 4 - TX Channel Association Memory (TX CAM) 23 MT90502 CPS-Packet Circular Buffers (one table only, in SSRAM) +0h +100h CPS-Pk Circ Buf 0 CPS-Pk Circ Buf 1 Preliminary Datasheet +(100h*(N-2)) +(100h*(N-1)) CPS-Pk Circ Buf N-2 CPS-Pk Circ Buf N-1 The TX CPS-Packet Circular Buffers are 256-bytes in size, located in TX SSRAM at addresses +4000h to +BF00h, +8000h to +17F00h, +10000h to +2FF00h and +20000h to +5FF00h for 128, 256, 512 and 1023 channels respectively. Number of consecutive Circular Buffers is N = {128, 256, 512, 1023} Figure 5 - TX CPS-Packet Circular Buffers 2.2.2.1 CPS-Packet Length An Encoding Data Unit (EDU) consists of 8 PCM or ADPCM data blocks. A data block is 8-bits for uncompressed PCM and 5-, 4-, 3-, or 2-bits for ADPCM compression rates of 40, 32, 24, or 16 kbps, respectively. AAL2 CPS-Packets may contain 1-, 2-, 3-, 4-, 5-, or 8-EDUs. The MT90502 also supports 44-byte PCM, 44-byte 32K ADPCM and 40-byte 32K-ADPCM CPS-Packets as per ATM Forum requirement for Loop Emulation Service. 40/80 frame PCM/ADPCM represents 40-byte 32K ADPCM, and 44/88 frame PCM/ADPCM represents both 44-byte PCM and 44-byte 32K ADPCM. 2.2.2.2 TDM Data Formats Two different formats are available for transferring PCM/ADPCM samples on the H.100/H.110 bus. The first format, Format A, uses a single time slot on the H.100/H.110 bus to transfer a sample. This format does not allow distinguishing between PCM and ADPCM samples and therefore does not allow automatic switching between PCM and ADPCM samples. If a channel is configured as ADPCM, its compression rate can be determined on a byte by byte basis. This is done by using a certain byte format (see Figure 8) on the TDM bus in which the nibble is placed in either the high bits or the low bits of the byte, followed by a '1' and padding the rest of the byte with '0's. By so doing, the compression rate of the sample is coded implicitly into the byte. As a CPS-Packet can contain only one encoding scheme or compression rate, the compression rate may change only on CPS-Packet boundaries. Dynamic compression can be performed between all ADPCM compression rates. The second format, Format B, uses two time slots on the H.100/H.110 bus to transfer a single PCM/ADPCM sample. Using two time slots will provide explicit indication of PCM or ADPCM sample in both the Tx and Rx direction. This will allow for dynamic switching between PCM and ADPCM encoding schemes. Both Format A and B allow the MT90502 to send a reset signal to the external decompressor to indicate the end of a silent period. For silence suppression to function properly, both the ADPCM compressor and decompressor must be synchronously reset in between continuous talk spurts. This reset must take place before each non-silent packet that was preceded by a silent packet, given that silence suppression is enabled. The external decompressor must reset itself when it sees either b7 or b0, depending on the placement of ADPCM nibbles, is set in ADPCM samples. For Format B, a reset signal (PCM-R=11) will also be given when a voice (non-padding) sample is received that was preceded by a padding sample. 24 Preliminary Datasheet MT90502 The 32 TDM streams on the H.100/H.110 bus are grouped into 8 quads (stream[3:0] is quad 0, stream[7:4] is quad 1, etc.), and the choice of data transfer format can be made on each individual quad using bits 13:6 in register 700h. Figure 6 to Figure 11 show the different data formats for PCM/ADPCM samples for each of the different compression rates, encoding schemes and transfer modes. Format A for xxPCM samples (without Auto PCM-ADPCM Switching) TSSTs on H.100/H.110 b7 TSSTx TSSTy b6 b5 b4 b3 b2 b1 b0 TX xxPCM Sample RX xxPCM Sample Italic goes from MT90502 to H.100/H.110 Plain goes from H.100/H.110 to MT90502 Figure 6 - PCM/ADPCM Data Format A 25 MT90502 Format A for RX xxPCM Samples (without Auto PCM-ADPCM Switching) Format of ADPCM Samples in low bits (with Decompressor reset) b7 1 b7 1 b7 1 b7 1 b6 0 b6 0 b6 0 b6 0 b5 1 b5 0 b5 0 b5 0 b4 1 b4 0 b4 0 b3 1 b3 0 b2 1 b4 b3 b2 b1 b0 Preliminary Datasheet Format of ADPCM Samples in low bits (no Decompressor reset) b7 0 b0 b7 0 b0 b7 0 b0 b7 0 b6 0 b6 0 b6 0 b6 0 b5 1 b5 0 b5 0 b5 0 b4 1 b4 0 b4 0 b3 1 b3 0 b2 1 b4 b3 b2 b1 b0 ADPCM 40 kbps b3 b2 b1 ADPCM 40 kbps b3 b2 b1 b0 32 kbps b2 b1 24 kbps b1 32 kbps b2 b1 24 kbps b1 b0 b0 16 kbps 16 kbps Format of ADCM Samples in high bits (with Decompressor reset) b7 b6 b5 b4 b3 b2 1 b3 1 b4 1 b5 1 b4 0 b3 0 b3 0 b2 0 b2 0 b2 0 b1 0 b1 0 b1 0 b1 0 b0 1 b0 1 b0 1 b0 1 Format of ADPCM Samples in high bits (no Decompressor reset) b7 b6 b5 b4 b3 b2 1 b3 1 b4 1 b5 1 b4 0 b3 0 b3 0 b2 0 b2 0 b2 0 b1 0 b1 0 b1 0 b1 0 b0 0 b0 0 b0 0 b0 0 ADPCM 40 kbps b7 b6 b5 b4 ADPCM 40 kbps b7 b6 b5 b4 32 kbps b7 b6 24 kbps b7 b6 b5 32 kbps b7 b6 24 kbps b7 b6 b5 16 kbps 16 kbps Format of PCM Padding Samples in ADPCM only time slots b7 PCM[7] Format of PCM samples b6 1 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 PCM[5:0] PCM Note that switching between ADPCM and PCM requires software intervention when using Format A It is recommended that b6 of PCM padding bytes be 1 - this is in-line with the requirement that the padding buffers contain all low energy samples, u-law max value of 471 out of 8159 and A-law max value of 252 out of 4096 - and that ADPCM samples be placed in the low bits. This will allow the decompressor to differentiate PCM padding bytes from ADPCM samples, in order to bypass the decompressor during a silence period. Figure 7 - PCM/ADPCM RX Data Format A 26 Preliminary Datasheet Format A for TX xxPCM Samples (without Auto PCM-ADPCM Switching) Format of ADPCM Samples in high bits b7 b6 b5 b4 b3 b2 1 b3 1 b4 1 b5 1 b4 0 b3 0 b3 0 b2 0 b2 0 b2 0 b1 0 b1 0 b1 0 b1 0 b0 0 b0 0 b0 0 b0 0 MT90502 Format of ADPCM Samples in low bits b7 0 b7 0 b7 0 b7 0 b6 0 b6 0 b6 0 b6 0 b5 1 b5 0 b5 0 b5 0 b4 1 b4 0 b4 0 b3 1 b3 0 b2 1 b4 b3 b2 b1 b0 ADPCM 40 kbps b7 b6 b5 b4 ADPCM 40 kbps b3 b2 b1 b0 32 kbps b7 b6 24 kbps b7 b6 b5 32 kbps b2 b1 24 kbps b1 b0 b0 16 kbps 16 kbps Format of PCM Sample b7 b6 b5 b4 s b3 b2 b1 b0 PCM Note: switching between ADPCM and PCM requires software intervention in Format A. Figure 8 - PCM/ADPCM TX Data Format A MT90502 Format B for xx PCM (with Auto PCM-ADPCM Switching) TSST Grouping on H.100/H.110 b7 TSST n TSST n+1 TSST n+2 TSST n+3 PCM-R PCM b6 b5 b4 b3 b2 b1 b0 TX PCM Unsigned Magnitude TX xxPCM Sample Reserved RX xxPCM Sample Italic g oes from MT90502 to H.100/H.110 Plain goes form H.100/H.110 to MT90502 Streams are assigned to this mode in groups of 4 only. n = 0, 3, 7, 11, .... Figure 9 - PCM/ADPCM Data Format B 27 MT90502 Format B for RX xxPCM Samples (with Auto PCM-ADPCM Switching) Format of PCM Samples (for both padding and voice) (with Decompressor reset indicated) PCM-R 1 1 b7 b6 b5 b4 b3 b2 b1 b0 PCM-R 1 0 Preliminary Datasheet Format of PCM Samples (for both padding and voice) (no Decompressor reset indicated) b7 b6 b5 b4 b3 b2 b1 b0 PCM Sample Format of ADPCM Samples in low bits (with Decompressor reset indicated) PCM Sample Format of ADPCM Samples in low bits (no Decompressor reset indicated) PCM-R 0 1 b7 1 b7 1 b7 1 b7 1 b6 0 b6 0 b6 0 b6 0 b5 1 b5 0 b5 0 b5 0 b4 b3 b2 b1 b0 PCM-R 0 0 b7 0 b7 0 b7 0 b7 0 b6 0 b6 0 b6 0 b6 0 b5 1 b5 0 b5 0 b5 0 b4 b3 b2 b1 b0 ADPCM 40 kbps b4 1 b4 0 b4 0 b3 1 b3 0 b2 1 b3 b2 b1 b0 ADPCM 40 kbps b4 1 b4 0 b4 0 b3 1 b3 0 b2 1 b3 b2 b1 b0 PCM-R 0 1 PCM-R 0 0 32 kbps b2 b1 24 kbps b1 b0 b0 32 kbps b2 b1 24 kbps b1 b0 b0 PCM-R 0 1 PCM-R 0 0 PCM-R 0 1 PCM-R 0 0 16 kbps 16 kbps Format of ADPCM Samples in high bits (with Decompressor reset indicated) PCM-R 0 1 b7 b7 b6 b5 b4 b3 b2 1 b3 1 b4 1 b5 1 b4 0 b3 0 b3 0 b2 0 b2 0 b2 0 b1 0 b1 0 b1 0 b1 0 b0 1 b0 1 b0 1 b0 1 Format of ADPCM Samples in high bits (no Decompressor reset indicated) PCM-R 0 0 b7 b7 b6 b5 b4 b3 b2 1 b3 1 b4 1 b5 1 b4 0 b3 0 b3 0 b2 0 b2 0 b2 0 b1 0 b1 0 b1 0 b1 0 b0 0 b0 0 b0 0 b0 0 ADPCM 40 kbps b6 b5 b4 ADPCM 40 kbps b6 b5 b4 PCM-R 0 1 PCM-R 0 0 32 kbps b7 b6 24 kbps b7 b6 b5 32 kbps b7 b6 24 kbps b7 b6 b5 PCM-R 0 1 PCM-R 0 0 PCM-R 0 1 PCM-R 0 0 16 kbps 16 kbps Figure 10 - PCM/ADPCM RX Data Format B 28 Preliminary Datasheet MT90502 Format B for TX xxPCM Samples (with Auto PCM-ADPCM Switching) Format of ADPCM Samples in high bits PCM 1 PCM 0 PCM 0 PCM 0 PCM 0 PCM 0 b7 b7 b7 b7 b6 b5 b7 b6 b5 b4 b3 b2 b1 b0 Format of ADPCM Samples in low bits PCM 1 b7 b6 b5 b4 b3 b2 b1 b0 PCM b4 b3 b2 1 b3 1 b4 1 b5 1 b5 0 b4 0 b4 0 b3 0 b3 0 b3 0 b2 0 b2 0 b2 0 b2 0 b1 0 b1 0 b1 0 b1 0 b1 0 b0 0 b0 0 b0 0 b0 0 b0 0 PCM b7 0 b7 0 b7 0 b7 0 b7 0 b6 0 b6 0 b6 0 b6 0 b6 0 b5 1 b5 0 b5 0 b5 0 b5 0 b4 1 b4 0 b4 0 b4 0 b3 1 b3 0 b3 0 b2 1 b2 0 b4 b3 b2 b1 b0 PCM 0 PCM 0 PCM 0 PCM 0 PCM 0 ADPCM 40 kbps b6 b5 b4 ADPCM 40 kbps b3 b2 b1 b0 32 kbps b6 24 kbps b6 b5 32 kbps b2 b1 24 kbps b1 b0 b0 16 kbps b7 0 b6 0 16 kbps b1 0 b0 0 Silence packets end with this sample. (See Section 2.9.2.2.) Figure 11 - PCM/ADPCM TX Data Format B 2.2.2.3 Phase Alignment In the MT90502 CPS-Packet assembly engine, any given frame can begin a CPS-Packet. Once this frame is established, packets will always be formed every 8 x #EDU frames. In order to control the trade-off between delay and bandwidth efficiency, the MT90502 supports phasing of CPS-Packet construction. For any given EDU value the MT90502 selects a frame as phase 0 and sub-phase 0. Phase specifies the EDU relative to phase 0 and sub-phase specifies a sample offset within the EDU. For example if a 5 EDU connection opened with a phase of 1 and sub-phase of 2 then it will begin assembly 10 frames after a connection of phase 0, sub-phase 0. Internal phase and sub-phase counters exist to co-ordinate the accumulation of sufficient data for a CPS-Packet with the construction of CPS-Packets. There are multiple independent phase counters, one for each #EDU. Channels with the same setting of #EDU share the same phase counter. Phase counters count from 0 to 1, 2, 3, 4, 7, 9 and 10. One global sub-phase counter exists which counts from 0 to 7 and increments on every frame. Each time the sub-phase counter reaches 0, the phase counters increment. A CPS-Packet is created for a channel when the channel’s phase counter equals the channel’s phase number, and the sub-phase counter equals the channel’s sub-phase number. Both phase and sub-phase numbers are user programmed in the PCM/ADPCM CPS-Packet Assembly Structure, shown in Figure 12. The MT90502 has the capability of aligning the transmission of PCM and ADPCM CPS-Packets containing the same number of EDUs and destined to the same VC in order to obtain less delay and higher bandwidth efficiency. To accomplish this, the phase and sub-phase fields of the PCM/ADPCM CPS-Packet assembly structure must match the phase and sub-phase field of all other channels that are to be phase aligned on the same VC. Programming the phase and sub-phase fields is done by the CPU upon configuration of the CPS-Packet assembly structure. 29 MT90502 Preliminary Datasheet By default, all phase and sub-phase counters are free running. Each counter picks up an arbitrary frame as phase 0 or sub-phase 0, then starts its counting. The phasing information, e.g. which frame is phase 0 and sub-phase 0, is internal to the device in this case. For certain applications some external devices must be aware of what phase and sub-phase the current frame represents, so that they can know where the CPS-Packet boundary is. An example is ADPCM compressor which should only change its compression rate at CPS-Packet boundaries. To indicate a CPS-Packet boundary a phasing TSST structure is introduced to allow an external device to send phasing information to the MT90502. Once a TSST is configured as phasing channel in TX CAM, the data on that TSST will overwrite internal counter(s). When the MT90502 sees a 00h on that TSST, it takes that frame as phase 0 and sub-phase 0. When there is a 01h, it interprets it as phase 0 sub-phase 1, and so on. The external device driving a phasing channel must ensure that a proper counting pattern appears on this channel every frame. Up to four phasing channels can be created, each with a different XPI value. When loading data to internal counters, extra MSBs will be truncated. For example using a XPI value of ‘10’, a counting pattern of 0 to 63 also serves as two cycles of 0 to 31, during which two 4-EDU CPS-Packets will be assembled. XPI 00 01 10 11 Counting Pattern 0 to 23 0 to 39 0 to 63 0 to 87 #EDU = 3 Replacing Internal Counters #EDU = 5, and 40/80 frame PCM/ADPCM #EDU = 1, 2, 4, 8 #EDU = 44/88 frame PCM/ADPCM Table 18 - XPI Selection Table 30 Preliminary Datasheet 2.2.2.4 PCM/ADPCM CPS-Packet Assembly Structure MT90502 PCM/ADPCM CPS-Packet Assembly Structures are located in internal TX TDM Control Memory. Each PCM or ADPCM channel will find an entry to its CPS-Packet Assembly Structure by the xxPCM Channel Number assigned in the TX CAM. TX TDM Control Memory PCM/ADPCM CPS-Packet Assembly Structure b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 +8 # EDU Comp 0 S 0 CPSP Buf RP [7:1] Partial Byte Storage[7:x] / Phase[3] Sub Phase Phase[2:0] SS RPV 0 Fields in Italic are used by hardware only. Fields in Plain are written to by the CPU/Software. Index of structure given by PCM Channel number in TX CAM. Structures are located in internal TX TDM Control Memory (8000h to BFF0h). Each structure is 16-bytes in size. Note: The write pointer to the xxPCM Circular Buffers is global. Different write pointers exist for each compression type and phase. #EDU: The number of EDUs per PCM CPS-Packet assembled. “000” = 1 EDU, “001” = 2 EDUs; “010” = 3 EDUs; “011” = 4 EDUs; “100” = 5 EDUs; “101” = 44/88 frame PCM/ADPCM; “110” = 40/80 frame PCM/ADPCM; “111” = 8 EDUs. Compression: “000” = PCM; “001” = ADPCM 40 kbps; “010” = ADPCM 32 kbps; “011” = ADPCM 24 kbps; “100” = ADPCM 16 kbps; “101” = ADPCM auto-detect; “110” = PCM & ADPCM auto-detect (TDM Format B must be chosen); “111” = reserved. Partial Byte Storage[7:x] / Phase[3] : Used by hardware to store ADPCM samples that have not formed complete bytes yet. When #EDU indicates 44/88-frame or 40/80 frame mode, the partial byte requires only 4 bits (ADPCM-32) and is stored in bits 7:4. The LSB contains Phase[3] (programed by the CPU/Software). CPSP Buf : TX SAR’s pointer of up to where it has read in the channel’s circular buffer. Used to detect overflows. RPV : Indicates that the CPSP Buf RP is valid, and thus that Circular Buffer Overflows can be detected. Written to ‘1’ any time the CPSP Buf RP is written. S: Silent Bit. Indicates if the current CPS-Packet is silent so far or not. SS : Silence Suppression. “000” = no silence suppression; “001” = associated odd stream bit represents silence; “010” = A Match; “011” = B Match; “100” = silence indicated as in Fig 10; others = reserved Sub Phase : Phase alignment of the channel within the 8 sub-phases possible in an EDU. Phase[3:0] : Phase alignment of the channel among the different EDUs it may contain. This number ranges between 0 and #EDU field. When #EDU is 44/88-frame packets are assembled every 44 or 88 frames. Phase and sub-phase specify where assembly should start for 88 frame packets and when assembling 44 frame packets one will begin on the specified phase/sub-phase and another will begin 44 frames later by default. Therefore, there are eleven (0-10) phases in 44/88 frame mode. Similarly in 40/80 frame mode there are ten (0-9) phases. Bit 3 of the phase is encoded in Partial Byte Storage[1]. Reserved Figure 12 - PCM/ADPCM CPS-Packet Assembly Structure 31 MT90502 2.2.3 Treatment of HDLC Data Preliminary Datasheet Other than PCM and ADPCM data, MT90502 can also send/receive generic AAL2 CPS-Packets directly to/from the H.100/H.110 bus. Those CPS-Packets must be encapsulated in HDLC format before they can be put onto H.100/H.110 bus. The HDLC encapsulation of the data allows an external SSCS engine (e.g. G.723, G.728 or G.729) to pass over CPS-Packets or CPS-Packet payloads to the MT90502 through TDM bus. HDLC data is accumulated until a flag is received signifying the end of an HDLC packet (see Section 2.10 on page 94). Then, either bit-wise or byte-wise zero-extraction (configurable for the entire chip in register 500h) is performed on the HDLC data. At this stage, the HDLC packets can be re-formatted as AAL2 CPS-Packets for treatment by the TX SAR. 2.2.3.1 HDLC Streams Any number from 1 to 128 of consecutive time slots on a single H.100/H.110 stream can be grouped as a single HDLC stream to carry HDLC packets. For each TSST, an entry in TX CAM lists the HDLC stream number associated with that TSST; these stream numbers are the same for all TSSTs carrying data for a single HDLC stream. Within a single HDLC stream, one or more HDLC channels can be transported. An HDLC channel carries CPS-Packets destined to the same AAL2 channel. Up to 1023 channels, whether they are xxPCM channels or HDLC channels, are supported by MT90502. Each HDLC stream must be assigned N consecutive assembly structures in TX TDM Control Memory, as seen in Figure 13, “HDLC CPS-Packet Assembly Structure,” on page 33. N is always the same as the number of HDLC channels carried by that HDLC stream with only one exception, that is, when the number of HDLC channels is one, and the TSSTs occupied by the HDLC stream is more than one, N must be 2. 2.2.3.2 Address Bytes HDLC packets may contain zero, one, or two address bytes that immediately follow the start flag. For HDLC packets containing one or two address bytes, the last address byte can be used to indicate a channel number. If the last address byte is used to indicate a channel number, each of the 256 possible channel numbers can be directed to a different CPS-Packet final assembly structure. Each CPS-Packet, based on its HDLC channel number, can be directed to a different VC/CID. If the value of the last address byte exceeds the allowed number of HDLC channels for that HDLC stream, the channel number 0 will be used for that CPS-Packet. All address bytes not used to indicate a channel number are discarded by the TX TDM module and do not appear in an AAL2 CPS-Packet. The HDLC stream number added to the HDLC address byte will yield the HDLC channel number. Whether or not the address byte(s) will be used to indicate a channel number is determined independently for each HDLC stream using the “Header Type” field of the HDLC CPS-Packet assembly structure (see Figure 13 on page 33). 32 Preliminary Datasheet TX TDM Control Memory (AAL2 header not present in HDLC data) HDLC CPS-Packet Assembly Structure b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 +0h +2h +4h +6h +8h CPSP Buf RP [7:0] HBC Count 1s V RX Control Byte CPSP Buf SOP [7:1 ] CPSP Buf RP [7:1] History Bits & Valid [7:0] CRC RPV 1 Base HDLC Structure for all HDLC Streams b0 MT90502 Header Type +10h +12h +14h +16h +18h CPSP Buf WP [7:0] HDLC Channel Number V RX Control Byte CPSP Buf SOP [7:1] CPSP Buf RP [7:1] Number of Channels RPV Second HDLC Structure on a HDLC Stream +20h +22h +24h +26h +28h CPSP Buf WP [7:0] V RX Control Byte CPSP Buf SOP [7:1] CPSP Buf RP [7:1] RPV Third and up to N successive HDLC Structures on a HDLC Stream Reserved Fields in Italic are used by hardware only. Fields in Plain are written to by the CPU/Software. Index of the base structure given by HDLC Stream Number in TX CAM. Structures located in internal TX TDM Control Memory (8000h to BFF0h). Each structure is 16-bytes in size. V: Header Type: Valid. When 0, this HDLC channel will be ignored. When 1, it will be processed. This valid bit has no effect on the operation of the HDLC stream. Header type. 0000 = Plain; 0001 = One byte address; 0010 = Two byte address; 0011 = One byte address + Control; 0100 = Two byte address + Control; 0101 = One byte address (SCS); 0110 = Two byte address (SCS); 0111 = One byte address + Control (SCS); 1000 = Two byte address + Control (SCS). SCS: Sub-Channel Scheme where address byte is used to differentiate HDLC channels. Address bytes are ignored in non-SCS modes. CRC: CPSP Buf WP: 0 = CRC not present; 1 - 16-bit CRC present. CPS-Packet Buffer Write Pointer. Points to the next byte that will be written in the CPS-Packet Circular Buffer. CPSP Buf RP[7:1] Pointer to the next word that will be read by the TXSAR’s Cell Assembly Process. If a byte is written at this word, an error will be flagged. RPV: CPSP Buf SOP[7:1] HBC: RX Control Byte: History Bits & Valid: HDLC Channel Number: Number of Channels: Indicates that the CPSP Buf RP is valid, and that Circular Buffer Overflows can be detected. Written to 1 any time the CPSP Buf RP is written. Pointer to the start of the current CPS-Packet (being assembled now). HDLC Byte Count. Counts the first few bytes of each CPS-Packet. This counter will not increment beyond ‘1000’. It will be reset upon the reception of a flag. Control byte received in the last HDLC packet. Eight history bits used to do zero extraction and to indicate the validity of the received data. 00000001 = no leftover bits, 1xxxxxxx=7 leftover bits. Should be initialized to 00000001. HDLC Channel Number of the Current HDLC Packet being received. Number of channels in this HDLC Stream. Valid range is 0 to 255. 0 means 256. Figure 13 - HDLC CPS-Packet Assembly Structure 33 MT90502 HDLC CPS-Packet Assembly Structure b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 +0h +2h +4h +6h +8h CPSP Buf RP [7:0] HBC Count 1s V UUI [4:0] CPSP Buf SOP [7:1] CPSP Buf RP [7:1] History Bits & Valid [7:0[ 1 CRC b0 Preliminary Datasheet TX TDM Control Memory (AAL2 header present in HDLC data) Header Type Base HDLC Structure for all HDLC Streams +10h +12h +14h +16h +18h CPSP Buf WP [7:0] HDLC Channel Number V UUI [4:0] CPSP Buf SOP [7:1] CPSP Buf RP [7:1] Number of HDLC Channels Second HDLC Structure Channels on a HDLC Stream +20h +22h +24h +26h +28h CPSP Buf WP [7:0] V UUI [4:0] CPSP Buf SOP [7:1] CPSP Buf RP [7:1] Third and up to N successive HDLC Structures on a HDLC Stream Fields in Italic are used by hardware only. Fields in Plain are written to by the CPU/Software. Index of the base structure given by HDLC Stream Number in TX CAM. structures located in internal TX TDM Control Memory (8000h to BFF0h). Each structure is 16-bytes in size. Reserved UUI: The 5 MSBs of the control byte of the HDLC CPS-Packet. These can be used as the UUI value on AAL2. For all other fields, refer to the previous figure. Figure 14 - HDLC CPS-Packet Assembly Structure 2.2.3.3 Control Bytes and Length In addition to a zero, one, or two byte address, an HDLC packet may also contain a control byte and a two-byte CRC. The 5 MSBs of the HDLC control byte can be used as the UUI in the AAL2 CPS-Packet formed from that HDLC packet. The TX TDM calculates the length of each HDLC packet and stores it in the Length field of the each TX TDM Write Cache entry. 2.2.3.4 “Raw” AAL2 CPS-Packets The data field of an HDLC packet can contain an AAL2 CPS-Packet with or without a header. This is configured for all HDLC streams in register 500h. When the packaging_type field of register 500h is set to ‘1’, all HDLC packets will carry complete CPS-Packets with both header and payload. They will be treated as “raw” AAL2 CPS-Packets. For “raw” AAL2 CPS-Packets, the CID is ignored and replaced by the CID in the CPS-Packet final assembly structure. The LI is ignored and re-calculated by the TX TDM module. The UUI is passed on as the UUI for the AAL2 CPS-Packet. The HEC is ignored and regenerated based on the new CID/UUI/LI. 34 Preliminary Datasheet 2.2.4 CPS-Packet Final Assembly MT90502 Once PCM/ADPCM and HDLC data is segmented into CPS-Packets, the CPS-Packet final assembly structure is referenced and the packaging is completed through the addition of the CID, UUI, LI and HEC. Finally, the CPS-Packets are directed to the correct location in the CPS-Packet Buffer (according to the channel number for that CPS-Packet) from which the TX SAR will read them. The UUI can be sourced from a “raw” AAL2 CPS-Packet, the 5 MSBs of the control byte of an HDLC packet, or, the LSBs can be a one-bit to four-bit free-running counter. When the UUI is used as a counter, the MSB must be 0. CPS-Packet Final Assembly Structure (xxPCM w/o Silence Suppression) CPS-Packet Final Assembly Structure Table +0000h +0020h CPSPFAS Channel 0 CPSPFAS Channel 1 +0h +2h +4h +7FC0h +7FE0h CPSPFAS Channel 1022 CPSPFAS Channel 1023 +6h +8h +Ah +Ch +Eh +10h +12h CPS-Packet Final Assembly structures are located in TX SSRAM at addresses +1000h to +1FE0h, +2000h to +3FE0h, +4000h to +7FE0h and +8000h to +FFE0h for 128, 256, 512 and 1023 channels repsectively. Each structure is 32 bytes in size. Reserved +14h +16h +18h +1Ah +1Ch +1Eh # of EDU b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VC Number[9:0] CID Seq I SUI Pack Del Cnt Send UU[3:0] The number of structures in this table can be programmed to {128, 256, 512, 1023} Fields in Italic are used by Hardware only Fields in Plain are written to by the CPU/Software. CPS-Packet Byte Count[31:16] CPS-Packet Byte Count[15:0] CPS-Packet Count[31:16] CPS-Packet Count[15:0] : VC Number Number of the VC in which the CPS-Packet of this AAL2 Channel will be routed. Packet Delete Count: Indicates the number of packet that must be deleted (not sent) before the AAL2 Channels starts. 0 means send immediately. 15 means never send. 1 to 14 means delete the first 1 to 14 CPS-Packets generated. At start-up, this field may be set to 1 or more in order to never send garbage on an AAL2 Channel. CID Channel ID on AAL2 VCs that will be annexed to the CPS-Packets. : Seq I This value indicates by how much the sequence number should increment each time a packet is sent. If 0, incremented by 1. If 1, incremented by 2, and so on. : Send UUI: Send this UUI value. These are the four lower bits of the UUI that will be sent in all AAL2 CPS-Packets. The 0 to 3 lower bits of this field can be substituted by the 0 to 3 lower bits of the CPS-Packet Count, depending on the Send UUI Increment Field. SUI: Send UUI Increment. When “000” = 4 bits used as counter; “001” = 3 bits used as counter; “010” = 2 bits used as counter; “011” = 1 bits used as counter; “100” = 0 bits used as counter; others = resereved. # EDU: Number of EDUs in each CPS-Packet. “000” = one EDU; “001” = two EDUs; “010” = three EDUs; “011” = four EDUs; “100” = five EDUs; “101” = 44/88 frame PCM/ADPCM32; “110” = 40/80 frame PCM/ADPCM32; “111” = eight EDUs. : CPS-Packet Byte CountByte counter of all payload bytes sent (payload is defined as the LI+1 in each CPS-Packet). CPS-Packet Count: CPS-Packet counter of all sent packets. Figure 15 - CPS-Packet Final Assembly Structure (PCM/ADPCM) The CPS-Packet final assembly structure contains two monitoring fields: a 32-bit byte count and a 32-bit CPS-Packet count. The CPS-Packet count indicates the number of complete CPS-Packets that have been generated using this structure, and the byte count indicates the number of data bytes contained in all those CPS-Packets, excluding the AAL2 headers. 35 MT90502 CPS-Packet Final Assembly Structure (HDLC Channel) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 +0h +2h +4h +6h +8h +Ah +Ch +Eh +1h +12h +14h +16h +18h +1Ah +1Ch +1Eh VC Number [9:0] CID SUI b2 b1 b0 Preliminary Datasheet VC Number: Number of the VC in which the CPS-Packets of this AAL2 Channel will be routed. Packet Delete Count: Indicates the number of packets that must be deleted (not sent) before the AAL2 Channel starts. 0 means send immediately. 15 means never send. 1 to 14 mean delete the first 1 to 14 first CPS-Packets generated. At start-up, this field may be set to 1 or more in order to never send garbage on an AAL2 Channel. CID: Channel ID on AAL2 VCs that will be annexed to the CPS-Packets. Send UUI: Send this UUI value. These are the four lower bits of the UUI that will be sent in all AAL2 CPS-Packets. The 0 to 4 lower bits of this field can be substituted by the 0 to 4 lower bits of the CPS-Packet Count, depending on the Send UUI Increment Field. Pack Del Cnt[3:0] Send UUI [3:0] CPS-Packet Byte Count [31:16] CPS-Packet Byte Count [15:0] CPS-Packet Count [31:16] CPS-Packet Count [15:0] Fields in Italic are used by hardware only. Fields in Plain are written to by the CPU/Software. CPS-Packet Final Assembly structures are fixed and are located in TX SSRAM memory at addresses +1000h to +1FE0h, +2000h to +3FE0h, +4000h to +7FE0h and +8000h to +FFE0h for 128, 256, 512 and 1023 channels respectively. Each structure is 32-bytes in size. SUI: Send UUI Increment. When “000” = 4 bits used as counter, “001” = 3 bits used as counter, “010” = 2 bits used as counter, “011” = 1 bit used as counter, “100” = 0 bits used as counter, “101” = send the UUI value contained in the HDLC CPS-Packet control byte. Others = reserved. Once in “raw” CPS-Packet mode, Send UUI and SUI are ignored. CPS-Packet Byte Count: Byte counter of all payload bytes sent (payload is defined as the LI+1 in each CPS-Packet). CPS-Packet Count: CPS-Packet counter of all sent packets. Figure 16 - CPS-Packet Final Assembly Structure (HDLC Channel) 2.2.4.1 CPU CPS-Packets The TX TDM module allows the generation of CPU sourced CPS-Packets. When the CPU requires to transmit an AAL2 CPS-Packet onto a certain VC, it programs the VC number in register 520h, and writes the CPS-Packet's descriptor structure in registers 522h to 526h. The format of the CPS-Packet descriptor structure is given in Figure 17. Word 0 must be written into register 522h, Bytes +2 and +5 to register 524h and Bytes +4 and +5 to register 526h. Finally, it writes a '1' to the cps_packet_request bit in register 520h, which begins the request. When the bit clears, the process has concluded and the CPS-Packet has been added to the TX VC's queue. The following process is used to send a CPU CPS-Packet: 1) The payload of the CPS-Packet must be written into some unused portion of the external SSRAM (bank A). The format for writing the payload to memory is shown in the following example. In the example, the CPS-Packet payload is 25-bytes. address cpsp_base + 0 (word 0): cpsp_base + 2 (word 1): ... cpsp_base + 24 (word 12): bits [15:8] payload 0 payload 2 ... payload 24 bits[7:0] payload 1 payload 3 ... xxxxxxxx Table 19 - Format for writing CPS-Packet payload to memory 36 Preliminary Datasheet MT90502 2) A CPS-Packet descriptor is written to registers 522h, 524h, and 526h. The value to which each field must be set is indicated in Figure 17, “CPS-Packet Descriptor Queue,” on page 38. CPS-Packet base address: Base address of CPS-Packet’s payload bytes. The address is relative to the base address of bank A. Thus, if payload bytes 0 and 1 of the CPS-Packet are located at address 400126h, then the address inserted is 00126h. WB: Set to ‘1’. Write back must be disabled for CPU sourced CPS-Packets. CID: The value of the CID of the sent CPS-Packet. Any 8-bit value is valid, with the exception of 00h, which is illegal (AAL2 specification). CPU: Set to ‘1’. Indicates that the CPS-Packet is sourced by the CPU. Size: As mentioned earlier, the payload of the TX CPU CPS-Packets can be inserted in any unoccupied portion of SSRAM bank A. A portion of bank A may be reserved for a virtual buffer. This buffer may be used to store the payload bytes of all CPU sourced CPS-Packets. In the case where the payload of a CPS-Packet is inserted at the end of the buffer and wraps to the beginning, the Size field indicates where to wrap to. Take for example a CPS-Packet of 10 payload bytes, and the Size field set to “0000” (256 bytes). Thus, the CPS-Packet must reside in a 256 byte boundary of the external memory. Now suppose that the CPS-Packet is written to address 1FEh. This implies that the payload bytes must be written as follows: address 100h (word 1): 102h (word 2): 104h (word 3): 106h (word 4): ... 1FEh (word 0): bits [15:8] payload 2 payload 4 payload 6 payload 8 ... payload 0 bits[7:0] payload 3 payload 5 payload 7 payload 9 ... payload 1 Table 20 - Example of written payload bytes Length: Set to the length of the CPS-Packet, minus 1 (i.e. LI field). UUI: The value of the UUI field of the sent CPS-Packet. Any 5-bit value is valid. Note: CPU CPS-Packets sent out on voice CIDs must use UUIs 16-31. They can use all UUIs on management CIDs (1-7). 3) Once the descriptor is written to the registers, the TX TDM module of the MT90502 is made aware of the CPS-Packet through register 520h. The VC number of an open AAL2 VC is written in bits [9:0], and the request bit, bit [10] of the register, is set to ‘1’. Finally, the register is written to. The CPU CPS-Packet has been written when the request bit of the register is cleared by hardware. 37 MT90502 2.2.4.2 CPS-Packet Descriptor Queue Preliminary Datasheet CPSPDQ Table in SDRAM CPS-Packet Descriptor Queue (one per VC) +0h Descriptor 0 Descriptor 1 Descriptor 2 Descriptor 3 +0h +2h +4h CPSP +6h b15 CPS-Packet Descriptor (one per pending CPS-Packet) b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 CPS-Packet Base Address [20:5] CPSPBA [4:0] Size WB Length [5:0] CID UUI +00000h +01000h CPSPDQ - VC 0 CPSPDQ - VC 1 +8h +10h +18h +3FE000h +3FF000h CPSPDQ - VC 1022 CPSPDQ - VC 1023 +FF0h +FF8h Descriptor 510 Descriptor 511 Reserved The number of CPSPDQ in this table can be programmed to {128, 256, 512, 1023}. CPS-Packet Descriptor structures are fixed and are located at the beginning of SDRAM memory (2000000h). Each structure is 8-bytes in size. Note: This structure is used by the hardware only. CPSPBA: CPS-Packet Base Address [20:0]: Word pointer pointing to the beginning of a CPS-Packet. Note that the CPS-Packet as such wraps at the boundary of its circular buffer. Size: Indicates the “wrap” boundary of the CPS-Packet. “0000” = 256 bytes; “0001” = 256 x 2^ 1; “0002” = 256 x 2^2; ... “1101” = 2M bytes. CID: Channel ID that will be passed on in the AAL2 CPS-Packet. Length: Length of the data part of the packet. Defined in the same way as the LI. UUI: User to User indicator that will be passed on in the AAL2 CPS-Packet. CPU: CPU Sourced CPS-Packet. “0” = CPS-Packet from TDM bus; “1” = CPS-Packet from CPU. WB: When “1”, the TX RX SAR will NOT write back the CPSP Read Pointer in the TXTDM PCM Control Structure. Figure 17 - CPS-Packet Descriptor Queue 38 Preliminary Datasheet 2.2.4.3 TDM Frame Buffer TDM Frame Buffer Stream 0 Timeslot 0 Timeslot 1 . . . LLL byte CPS-Packet assembly structure -- see Figure 13 . . . . . . HDLC byte . . . PCM byte . . . ADPCM byte . . . 8000h+0Ah*x History Bits & Valid [7:0] +y*100h Zero Extractor +z*100h CPS-Packet circular buffer z CPS-Packet assembly structure -- see Figure 12 8000h+0Ah*z Partial Byte Storage [7:1] . . . MT90502 to LLL Buffer. TX SAR CPSP Buf RP Write Back CPS-Packet Circular Buffers +0h CPS-Packet circular buffer x . . . CPS-Packet circular buffer y Notes: • Channels dedicated to HDLC (indicated by the CPS-Packet assembly structure for that channel) undergo zero-extraction before being placed in the correct CPS-Packet circular buffer. • ADPCM information is accumulated in the CPS-Packet assembly structure for that channel until an entire byte has been collected. • CPS-Packet assembly structures for PCM channels are consulted to direct PCM bytes to the correct CPS-Packet circular buffer • LLL (Low latency loopback) bytes are placed directly into the RX TDM Frame Buffer to exit the chip on the H.100/H.110 bus. • The TX SAR can be configured to alter the read pointer on a per-channel basis. Timeslot 127 Stream 1 Timeslot 0 Timeslot 1 +x*100h Timeslot 127 . . . . . Stream 31 Timeslot 0 Timeslot 1 . . . CPS-Packet circular buffer N-1 Timeslot 127 TDM Frame Buffer Notes: • TDM Frame Buffer is an internal memory inaccessible to the user. It contains the latest byte to enter the chip from each TSST on the H.100/H.110 bus. • Bytes are taken from the TDM Frame Buffer and treated according to the TX CAM entry for that TSST. • TSSTs for which no TX CAM entry exists are ignored. CPS-Packet Circular Buffer Notes: • Each buffer is 256 bytes long. • N consecutive circular buffers exist in SSRAM (N = number of channels, as set by sar_capacity -- see register 0240h). • Location of buffers within SSRAM is dependent on sar_capacity. • Buffers are in order by HDLC/PCM channel number (see TX CAM). • When a CPS-Packet is assembled, data from the buffer is placed in an ATM cell and the CPS-Packet read pointer (CPSP Buf RP) in the assembly structure is adjusted. Figure 18 - TDM Frame Buffer 39 MT90502 2.3 2.3.1 TX SAR Overview Preliminary Datasheet The purpose of the TX SAR Module is to assemble AAL2 CPS-Packets into AAL2 ATM cells to be transmitted to the UTOPIA Module. The TX SAR Module has no external interfaces, and does not control any of the MT90502's pins. However, it is the connecting block between the Tx TDM module and the UTOPIA Module in the data transmission direction. 2 .3.2 AAL2 Cell Assembly Process The AAL2 cell assembly process is directed by the TX AAL2 VC Structure (see Figure 19 on page 40). This structure is referenced and references all the structures necessary to compile an AAL2 ATM cell. It is employed by the TX SAR module to raise an event for an AAL2 ATM cell. It constructs the ATM cell payload by referencing the CPS-Packets via the CPS-Packet Descriptor Queue (SDRAM), which contains the CPS-Packet addresses in the CPS-Packet Circular Buffer (TX SSRAM). The structure also contains the ATM header data, time-out data, next CPU transmit CPS-Packet pointer, UTOPIA port destination and a free running counter of transmitted ATM cells. It is the responsibility of the software to program the following in the TX AAL2 VC Structure (Figure 19). • time-out period • ATM header associated with the VC • the TXD (TX Destination) field Relative Mapping in SRAM Memory +00h +20h VC Number 0 VC Number 1 +0h +2h +4h +7FC0h +7FE0h VC Number 1022 VC Number 1023 +6h +8h +Ah The number of VC Structures in this table can be programmed to {128, 256, 512, 1023} +Ch +Eh +10h +12h TX AAL2 VC Structure b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Packet Descriptor Write Pointer[8:0] V Pending Pay load Bytes Cell Expired Time-stamp Current Packet Offset[6:0] Packet Descriptor Read Pointer[8:0] PS SA TXD Pending Packet Timeout Period[13:0] Header[31:16] Header[15:0] Transmitted Cell Count[31:16] Transmitted Cell Count[15:0] CPU Sourced CPS-Packet Control[16:1] The TX AAL2 VC Structures are of fixed size and are located at the beginning of the TX SSRAM memory space (+0000h) through to addresses +0FE0h, +1FE0h, +3FE0h and +7FE0h for 128, 256, 512 and 1023 channels respectively. Each structure is 32 bytes in size. Fields in Italic are used by Hardware only. Fields in Plain are written to by the CPU/Software. Reserved Figure 19 - TX AAL2 VC Structure 40 Preliminary Datasheet Byte Address Offset/Bits Used 0/b[15:7] MT90502 Description of Field Written by the TX TDM module to denote the address of next CPS-Packet Descriptor in the CPSPDQ. The CPSPDQ is deemed full when the Packet Descriptor Write Pointer is one less than the Packet Descriptor Read Pointer. Indicates the number of pending payload bytes (CPS-Packet payload and header bytes) available to the associated VC. The range is 0 to 46. This field is updated by the TX TDM process with the remaining ATM cell pending payload bytes when a Cell Assembly Event is raised. Reset is performed by the TXSAR's scanning process. Associated to the Cell Expired Time-Stamp. If this bit is '1', then the time-stamp must be taken into account. Otherwise, it is ignored and no cells can be assembled. This is an absolute time stamp at which a pending cell must be transmitted. This field is set by the TDM process any time a CPS-Packet is written that starts at or overlaps a cell boundary. It will be written to the current time plus the Pending Packet Time-out Period field in this structure. This field will be cleared by the TDM process any time no CPS-Packets are pending. It will also be cleared by the TXSAR's scanning process if it is detected to have timed-out, and a cell Transmission Event is scheduled by this same process. The time unit for the time-out is 125 µs. Read pointer to the current CPS-Packet (Descriptor) in the CPSPDQ. Updated by the TXSAR. This field indicates how many bytes are remaining in a CPS-Packet when the CPS-Packet is straddling two cells. When this bit is '1', the pending packet time-out period will be ignored, and the V bit will never be written back to '1'. When '1', a maximum of one CPS-Packet will be contained in each cell. The remainder of the last cell to contain a CPS-Packet will always be zero padded to make sure that no other CPS-Packets join it. This is the maximum period set by the software that a Pending CPS-Packet exist before transmission. The value is in multiples of 125µs. 0 means between 0 and 124µs. 000 do not send 0xx1 UTOPIA TX Port A 0x1x UTOPIA TX Port B 01xx UTOPIA TX Port C 1000 UTOPIA RX Port A 1001 UTOPIA RX Port B 1010 UTOPIA RX Port C others reserved ATM Cell Header in the following order (starting from bit 31): GFC, VPI, VCI, PT, CLP Field Packet Descriptor Write Pointer Pending Payload Bytes 0/b[6:1] V: Valid Bit +2/b[15] Cell Expired Time Stamp +2/b[14:0] Packet Descriptor Read Pointer Current Packet Offset PS: Prevent Scanning SA: Send Always +4/b[15:7] +4/b[6:0] +6/b[15] +6/b[14] Pending Packet Time-out Period TXD: Transmission Destination +6/b[13:0] +8/b[15:12] Header[31:0] +A/b[15:0] +C/b[15:0] Table 21 - AAL2 VC Structure Fields 41 MT90502 Field Transmitted Cell Count CPU Sourced CPS-Packet Control Byte Address Offset/Bits Used +E/b[15:0] +10/b[15:0] +12/b[15:0] Preliminary Datasheet Description of Field Free running transmitted cell counter. This field points to the first word of the next CPU sourced CPS-Packet. Table 21 - AAL2 VC Structure Fields (continued) 2.3.2.1 AAL2 Cell Assembly Procedure • • • • • • • The CPS-Packet Assembly Structure raises a CPS-Packet event upon the alignment of the sub-phase and phase (See Figure 12 - PCM/ADPCM CPS-Packet Assembly Structure). The CPS-Packet Assembly Structure is mapped to the CPS-Packet Final Assembly Structure by the absolute address of both structures. The CPS-Packet Final Assembly Structure reads the ‘CPS-Packet Descriptor Write Pointer’ in the AAL2 VC Structure to determine the next address to write the current CPS-Packet. The CPS-Packet Assembly Structure retrieves the payload data from the TX TDM Frame Buffer and writes it to the CPS-Packet Circular Buffer in TX SSRAM. In preparation for the next CPS-Packet, the CPS-Packet Final Assembly Structure then updates (i.e. writes) the ‘Packet Descriptor Write Pointer’ in the ‘AAL2 VC Structure’. The ‘Pending Payload Byte’ field is updated by the TX TDM module when a CPS-Packet event is raised. When more than one CPS-Packet event is raised within the same CT_FRAME, each CPS-Packet event generates its corresponding CPS-Packets Final Assembly Structure in the TX TDM process. The TX SAR sequentially steps through each CPS-Packet Final Assembly Structure and for each process consults the associated AAL2 VC Structure to determine if enough payload has accumulated to generate a VC Send Event (see Figure 20, “Cell Assembly Event Queue,” on page 43). If enough payload is present then the TX SAR raises a VC Send Event and updates the Pending Payload Byte field with the remaining number of pending payload bytes. However, a VC Send Event may also be generated via the time-out period specified in the AAL2 VC Structure. All VCs have a time-out period that specifies the maximum time that any CPS-Packet destined to that VC can wait before a cell containing them is assembled. The time-out period is defined in CT Frames (i.e. multiples of 125µs) in the AAL2 VC Structure. The ATM header information is contained within the AAL2 VC Structure. The Packet Descriptor Read Pointer in the AAL2 VC Structure points indirectly to the complete CPS-Packet via the CPS-Packet Base Address in the Descriptor of the CPS-Packet Descriptor Queue. The CPS-Packet Descriptor Queue contains Descriptors for each complete CPS-Packet. The Descriptors contained the CPS-Packet header information and the absolute address of the CPS-Packet in the TX SSRAM. The VC Number in the CPS-Packet Final Assembly Structure points to the VC Send Event structure. A VC Send Event structure is only generated when enough payload is obtained to fill an ATM cell or the cell has past the expiry period. This is denoted by the Pending Payload Byte or Cell Expiry Time Stamp field in the AAL2 VC Structure. Upon a VC Send Event, the TX SAR writes a complete ATM cell (see Figure 21 on page 43) to the TX SAR Input FIFO (4 cell depth). • • • • • 42 Preliminary Datasheet Cell Assembly Event Queue (located in TX SSRAM) +000h +004h +FF8h +FFCh Event 0 Event 1 Event 1022 Event 1023 +0h +2h VC Send Event b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 VC Number[9:0] MT90502 b2 b1 b0 Num of Payload Bytes VC Number [9:0]: Number of the VC in which a cell must be assembled. Num of Payload Bytes: Indicates the number of payload bytes that will be packaged in the cell that will be assembled. Range 1 to 47. The Cell Assembly Event Queue is located in TX SSRAM at addresses +2000h to +21FCh, +4000h to +43FCh, +8000h to +87FCh and +10000h to +10FFCh for 128, 256, 512 and 1023 channels respectively. Each structure is 4-bytes in size. The number of structures in this table is programmed with respect to the max. number of channels:{128, 256, 512, 1023}. Note: This structure is used by hardware only. Figure 20 - Cell Assembly Event Queue . Cell Format of TX SAR Input FIFO b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 +0h +2h +4h +6h +30h +32h +34h +36h +38h +3Ah +3Ch +3Eh TXD: The TX Destination field, as defined in the TX AAL2 VC Structure. TX SAR Input FIFO structure is 64-bytes in size, located in internal memory at 2000h to 20C0h. The AAL0 Input FIFO structure is 64-bytes in size, located in internal memory at 2100h to 21C0h. Note: This structure used by hardware only. Reserved b2 b1 b0 OAM CLP GFC/VPI VCI [11:0] Payload Byte 0 Payload Byte 2 Payload Byte 44 Payload Byte 46 TXD VPI VCI [15:12] PTI Payload Byte 1 Payload Byte 3 Payload Byte 45 Payload Byte 47 Figure 21 - TX Cell Format 2.3.3 AAL0 Cells The TX SAR has the ability to insert AAL0 cells in the transmission direction. AAL0 cells are generated by the CPU and are directed to a 4-cell internal FIFO memory. It is necessary for the CPU to read the AAL0_MONITOR register (310h) to ascertain if the 4-cell internal FIFO memory can accommodated the pending AAL0 cell. The destination of the AAL0 cell is determined by the TX Destination field. The aal0_input_fifo is 4 cells deep in the MT90502, however, it is the hardware that manages the pointers. The software will write the cell to the first entry (0x2100 to 0x213E) and then it will set the register indicating that there is a new cell. There is more than 1 cell to write at a time and the aal0_input_cell_written is set after each cell. 43 MT90502 2.4 RX SAR Preliminary Datasheet The RX SAR module performs processing on ATM cells received from the UTOPIA module. Cells placed in the RX SAR Output FIFO by the UTOPIA module are first read, then divided into the component CPS-Packets, and finally written into the appropriate CPS-Packet data circular buffer in external memory. The processing involves • identifying the VC corresponding to the cell • examining the cell for errors • determining the routing of each CID, and • disassembling the cell’s CPS-Packets. The status of the circular buffers is monitored for underruns and overruns. The RX SAR module also directs data cells to the data cell FIFO from which the CPU can read them. The RX SAR module supports PCM and ADPCM CPS-Packets of 1, 2, 3, 4, 5, or 8 EDUs, 32K ADPCM 80 frame CPS-Packets, 32K ADPCM 88 frame CPS-Packets, PCM 44 frame CPS-Packets, HDLC CPS-Packets of 1 to 64-bytes in length, and can accommodate packets straddling multiple cells. 2.4.1 RX AAL2 VC Structure For each VC directed to the RX SAR, an RX AAL2 VC structure exists in external memory. The RX AAL2 VC structures contain the following: • information required to detect errors • a free-running received cell counter • bytes received of from a CPS-Packet that is straddling the current and next AAL2 cells. When a VC is opened, the lost bit must be set, the error report enable bit must be set (if per-VC errors are to be reported) or reset (if no per-VC errors are to be reported), and the received cell counter must be initialized to 0. 44 Preliminary Datasheet RX AAL2 VC Structure MT90502 +00h +80h +100h VC Number 0 VC Number 1 VC Number 2 b15 b14 b13 b12 b11 b10 b9 b8 +0h +2h ER +4h +6h +8h +Ah +Ch +Eh +10h CID [7:0] UUI[2:0] HEC CPS-Payload 1 CPS-Payload 3 CPS-Payload 59 CPS-Payload 61 LI[5:0] b7 b6 b5 b4 b3 b2 b1 b0 LST SN Straddle Offset [6:0] Received Cell Counter [31;16] Received Cell Counter [15:0] +1FE80h +1FF00h +1FF80h VC Number 1021 VC Number 1022 VC Number 1023 LI [5:0] CPS-Payload 0 CPS-Payload 2 CPS-Payload 4 CPS-Payload 60 CPS-Payload 62 UUI [4:3] The RX AAL2 VC structures are fixed structures located at the beginning of RX SSRAM memory through 0 to addresses +3F80h, +7F80h, +FF80h and +1FF80h for 128, 256, 512 and 1023 channels respectively. Each structure is 128 bytes in size. +12h +14h +16h +50h +52h Reserved Fields in Italic are used by hardware only. Fields in Plain are written to by the CPU/Software. LI: LST: SN: Straddle Offset: ER: Length of the packet currently in transition. Lost Bit. Indicates that the RX SAR detected an error in the last cell it received. Must be set to “1” at start-up. Expected Sequence Number of next cell. The number of bytes that have been received so far in the transitioning packet. Error Report Enable. When “1’, the RX SAR will report cell-level errors, Sequence Number errors, Offset, Parity, and AAL2 HEC errors. Received Cell Counter: Free running counter of the number of cells received by this VC so far. Figure 22 - RX AAL2 VC Structure 2.4.2 CID Structure Once cells are received by the RX SAR, they are broken down into their component CPS-Packets, and analysed on a per-CID basis. The RX SAR contains 255 RX CID descriptor structures per VC, each one indicating where CPS-Packets containing that CID should be routed. Each CPS-Packet can be treated either as a PCM channel, an HDLC channel, a CPU CPS-Packet, or it can be discarded entirely. This routing is based on the UUI of the CPS-Packet. 45 MT90502 RX CID Structure +00000h +00800h +01000h +01800h +02000h VC Number 0 VC Number 1 VC Number 2 VC Number 3 VC Number 4 +7E8h +7F0h VC Number 1021 VC Number 1022 VC Number 1023 +0h The RX CID Structures are located in SDRAM. Each structure is 2048-bytes in size. Fields in Plain are written to by the CPU/Software. +2h +4h +6h UUI31 UUI23 UUI30 UUI22 +7F8h +00h +008h +010h Preliminary Datasheet CID Descriptor 1 CID Descriptor 2 CID Descriptor 253 CID Descriptor 254 CID Descriptor 255 +1FE800h +1FF000h +1FF800h RX CID Descriptor Structure b15 b14 b13 b12 b11 b10 b9 b8 UUI0-15 UUI29 UUI21 UUI28 UUI20 b7 b6 b5 b4 b3 UUI27 UUI26 UUI19 UUI18 b2 b1 b0 CPS-Packet Dis. Structure Number [9:0] UUI25 UUI17 UUI24 UUI16 Reserved CPS-Packet Disassembly Structure Number: Points to the CPS-Packet disassembly structure to which all PCM or HDLC packets on this CID belong. UUIx: Determines the destination of any CPS-Packet with the corresponding UUI. “00”=delete; “01”=CPU packets, sent to RX CPU CPS-Packet buffer; “10”=PCM; “11”HDLC. Figure 23 - RX CID Structure The CPS-Packet Disassembly Structure field indicates for PCM and HDLC channels the CPS-Packet disassembly structure to be used for CPS-Packets identified by the CID Descriptor Structure. UUIs 0 to 15 are routed together because the 4 LSBs of the UUI can be used as a sequence counter. The remaining 16 UUIs are routed separately. Each one can be destined to the CPU, to the PCM or HDLC channel, or deleted entirely. 2.4.3 CPS-Packet Disassembly Structures CPS-Packets routed to PCM or HDLC channels are treated by the CPS-Packet disassembly structure. Though the CPS-Packet disassembly structure is in the same location for PCM and HDLC channels, the fields are interpreted as one or the other depending on the value of the appropriate UUI field in the corresponding CID descriptor structure. The fields in the CPS-Packet disassembly structure indicate the form of the channel and the type of treatment required on the CPS-Packet to be disassembled. 46 Preliminary Datasheet HDLC/xxPCM CPS-Packet Disassebly Structure Space MT90502 CPS-Packet Disassembly Structure (xxPCM) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0000h +0020h +0040h +0060h +0080h CPS-Packet Dis. Struct. 0 CPS-Packet Dis. Struct. 1 CPS-Packet Dis. Struct. 2 CPS-Packet Dis. Struct. 3 CPS-Packet Dis. Struct. 4 +0h +2h +4h +6h +8h +Ah I C LC LE Max PDV (in frames) [9:0] Circ. Buffer Write Pointer[15:0] Initialization Lead[7:1] SM SE ADJ B Circ. Buffer Write Pointer[23:16] 2’s complement Delay Adjust[11:0] Lowest Delay Encountered (in frames) [11:0] Highest Delay Encountered (in frames) [11:0] CPS-Packet Counter[15:0] SPR A Last UUI[3:0] +7FA0h +7FC0h +7FE0h CPS-Packet Dis. Struct. 1021 CPS-Packet Dis. Struct. 1022 CPS-Packet Dis. Struct. 1023 +Ch +Eh +10h # of EDU LI0 SL Expected LI TDM RP / First written byte Offset RL RU # Seq Bits / UUI M CPS-Packet Disassembly structures located in RX SSRAM memory. Address range of strucutres is +6000h to +6FE0h, +C000h to +DFE0h, +18000h to +1BFE0h and +30000h to +37FE0h for 128, 256, 512 and 1023 channels respectively. Index of structure is given by CPS-Packet Disassembly Structure Number (+00h [b9:b0]) in CID Descriptor Structure. Each structure is 32-bytes in size. Reserved Fields in Italic are used by Hardware only. Fields in Plain are written to by the CPU/Software. Figure 24 - CPS-Packet Disassembly Structure (PCM/ADPCM) Byte Address Offset/Bits Used +0/b15:b13 Field C Name of Field Compression Ratio Description of Field ‘000’ = 64 kbps, ‘010’ = 40 kbps, ‘011’ = 24 kbps, ‘100’ = 16 kbps, ‘101’ = ADPCM auto-detect (can change between 16, 24, 32 and 40 kbps), ‘110’ = PCM & ADPCM auto-detect (can change between 16, 24, 32, 40, 64 kbps), others = reserved. 0: CPS-Packet Loss Compensation circuit disabled. 1: CPS-Packet Loss Compensation circuit enabled. LC CPS-Packet Loss Compensation Enable Loss Error Report Enable +0/b11 LE +0/b10 This bit must be set in order for CPS-Packet loss errors (e.g. losses due to silence suppression or to network quality) to be reported on this CID. CPS-Packet loss errors are detected by circular buffer overflow, or due to CPS-Packet descriptor queue overrun (in HDLC), and by sequence number errors (in PCM). This indicates the maximum quantity of PDV that the AAL2 Channel will incur. It is measured in frames (i.e. 125 us). A value of 0 implies that there is no PDV on the AAL2 Channel. The maximum value for this field depends on the Number of EDUs and the size of the RX Circular Buffers. It is defined as ((Size of circular buffer) - 8*(Number of EDUs) -4) /2. Pointer to the next memory location to be written upon the arrival of the next CPS-Packet. Structure initialized by hardware bit. Written to ‘0’ by software upon opening the channel, written to ‘1’ by hardware upon receiving the first CPS-Packet. Max PDV (in frames) [9:0] Max PDV (in frames) +0/b9:b0 Circ. Buffer Write Pointer [23:0] I Circular buffer write pointer Structure Initialized bit +2/b15:b0, +4/b7:b0 +4/b15 Table 22 - CPS-Packet Disassembly Structure (PCM/ADPCM) Fields 47 MT90502 Field Initialisation Lead [7:1] Name of Field Initialisation Lead Byte Address Offset/Bits Used +4/b14:b8 Preliminary Datasheet Description of Field Delay in frames that the first byte of the first CPS-Packet will go through before being sent on the TDM bus. This can be set to a lower value in order to minimise delay or to a higher value to avoid slips during the first CPS-Packets of the connection. Its value cannot exceed the Max PDV field. Typically, this field would be set to (Max PDV)/2 when initializing in the middle, or to 1 or 2 when initializing close to the edge. Action to be taken upon a slip. ‘0x’ = Slip to edge of circular buffer on underruns ‘1x’ = Slip to middle of circular buffer on underruns ‘x0’ = Slip to edge of circular buffer on overruns ‘x1’ = Slip to middle of circular buffer on overruns When ‘0’, underrun and overrun slips will not be reported. When ‘1’, they will be reported. Written to ‘1’ by software when a delay adjustment must be done by the hardware. Hardware will clear this field once the delay adjustment has been performed. Two’s complement number that will be added to the write pointer when the next CPS-Packet arrives. A value of 0 will not modify the delay. A value of -1 will reduce the delay by one frame. A value of +1 will increase the delay by one frame. Any time an adjustment is performed the Lowest and Highest delay fields will be adjusted accordingly. When ‘1’, any byte matching the “silent_pattern” (contained in register 0410h) will not be written to the external memory, causing silent padding to be inserted instead. When ‘1’, a pulse will be sent to the clock recovery module indicating that a reference packet (a timing CPS-Packet) has been received. This bit corresponds to clock recovery channel A which is independent of clock recovery channel B. When ‘1’ a pulse will be sent to the clock recovery module indicating that a reference packet (a timing CPS-Packet) has been received. This bit corresponds to clock recovery channel B which is independent of clock recovery channel A. Lowest delay inserted by the hardware’s buffer. This is a signed number: 0 is a valid delay of less than one frame, -1 is an invalid delay and indicates that one or more slips have occurred. Last received UUI bits 3:0. SM Slip Mode +6/b15:b14 SE ADJ Slip Error Report Enable Delay Adjustment pending 2’s Complement Delay Adjust +6/b13 +6/b12 2’s complement Delay Adjust[11:0] +6/b11:b0 SPR Silence Suppression Enable Clock recovery reference A +8/b14 A +8/b13 B Clock recovery reference B +8/b12 Lowest Delay Encountered (in frames) [11:0] Lowest delay encountered +8/b11:b0 Last UUI [3:0] Last UUI +A/b15:b12 Table 22 - CPS-Packet Disassembly Structure (PCM/ADPCM) Fields (continued) 48 Preliminary Datasheet Field Highest Delay Encountered (in frames) [11:0] CPS-Packet Counter[15:0] # of EDU Name of Field Highest delay encountered Byte Address Offset/Bits Used +A/b11:b0 MT90502 Description of Field Highest delay inserted by the hardware’s buffers. This is a signed number. All delays up to Max PDV in Frames are acceptable. Beyond this point, one or more slips have occurred. Free running count of received CPS-Packets (SID and non-SID included). Number of data units in each packet. ‘000’ = 8 frames or 1 EDU ‘001’ = 16 frames or 2 EDU ‘010’ = 24 frames or 3EDU ‘011’ = 32 frames or 4EDU ‘100’ = 40 frames or 5 EDU ‘101’ = 44/88 frames PCM/ADPCM32 ‘110’ = 40/80 frames PCM/ADPCM32 ‘111’ = 64 frames or 8 EDU When ‘1’, the last packet received was a SID. This field is used to generate the ADPCM reset if the first voice packet after a SID contains ADPCM data. This bit should be initialized to ‘1’ so that the first ADPCM packet resets the decoder. Positive offset between the circular buffer write pointer used to write the first byte of a CPS-Packet and the TDM_circular_buffer_read_pointer + 1. initialize to “00_0000_0000” Indicates how to treat CPS-Packets with the LI field equal to 0. ‘00’ = reserved. ‘01’ = CPS-Packet is SID, discard CPS-Packet. ‘10’ = CPS-Packet is SID, treat CPS-Packet. ‘11’ = CPS-Packet is SID, treat CPS-Packet and generate report structure. The LI expected in all voice packets. If the received LI does not match the Expected LI and RL = ‘1’, then an error report structure will be generated. Note: the CPS-Packet will still be treated. Report each CPS-Packet received in which the LI does not match Expected LI. Report each CPS-Packet received in which the UUI does not match expected UUI. ‘10000’ = 4 sequence bits ‘x1000’ = 3 sequence bits & UUI[3] in match ‘xx100’ = 2 sequence bits & UUI[3:2] in match ‘xxx10’ = 1 sequence bit & UUI[3:1] in match ‘xxxx1’ = 0 sequence bits & UUI[3:0] in match CPS-Packet counter Number of EDU +C/b15:b0 +E/b15:b13 SL SID Last +E/b10 TDM RP / First written byte Offset TDM RP/First written byte offset Length indicator of zero +E/b9:b0 LI0 +10/b15:b14 Expected LI Expected LI +10/b13:b8 RL RU # Seq Bits/UUI M Report Length Errors Report UUI Errors Number of Sequence Bits in the UUI and UUI Match +10/b7 +10/b6 +10/b4:b0 Table 22 - CPS-Packet Disassembly Structure (PCM/ADPCM) Fields (continued) 49 MT90502 S R A M M a p p in g - H D L C /x x P C M C P S -P a c k e t D is a s s e b ly S tr u c tu r e S p a c e +0h +2h +4h +6h +8h +A h +7FA 0h +7FC 0h +7FE 0h C P S -P a c k e t D is . S tru c t. 1 0 2 1 C P S -P a c k e t D is . S tru c t. 1 0 2 2 C P S -P a c k e t D is . S tru c t. 1 0 2 3 +Ch +E h +10h E x p e c te d L I A B Preliminary Datasheet C P S -P a c k e t D is a s s e m b ly S tr u c tu r e (H D L C fo r m a t) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0000h +0020h +0040h +0060h +0080h C P S -P a c k e t D is . S tru c t. 0 C P S -P a c k e t D is . S tru c t. 1 C P S -P a c k e t D is . S tru c t. 2 C P S -P a c k e t D is . S tru c t. 3 C P S -P a c k e t D is . S tru c t. 4 H CRC LE I C irc . B u ffe r W rite P o in te r[9 :1 ] C irc . B u ffe r R e a d P o in te r[9 :1 ] H D L C S tre a m N u m b e r[9 :0 ] H D L C A d d re s s [1 5 :0 ] SUE C o n tro l B y te [7 :0 ] C P S -P a c k e t C o u n te r[1 5 :0 ] RL RU # S e q B its / U U I M F ie ld s in Ita lic a re u s e d b y H a rd w a re o n ly . F ie ld s in P la in a re w ritte n to b y th e C P U /S o f tw a re . C P S -P a c k e t D is a s s e m b ly s tru c tu re s lo c a te d in R X S S R A M m e m o ry . A d d re s s ra n g e o f s tru c u tre s is + 6 0 0 0 h to + 6 F E 0 h , + C 0 0 0 h to + D F E 0 h , + 1 8 0 0 0 h to + 1 B F E 0 h a n d + 3 0 0 0 0 h to + 3 7 F E 0 h f o r 1 2 8 , 2 5 6 , 5 1 2 a n d 1 0 2 3 c h a n n e ls re s p e c tiv e ly . In d e x o f s tru c tu re is g iv e n b y C P S -P a c k e t D is a s s e m b ly S tru c tu re N u m b e r (+ 0 0 h [b 9 :b 0 ]) in C ID D e s c rip to r S tru c tu re . E a c h s tru c tu re is 3 2 -b y te s in s iz e . R e s e rv e d Figure 25 - CPS-Packet Disassembly Structure (HDLC Format) Byte Address Offset/Bits Used +0/b14:b12 Field H Name of Field Header Type Description of Field Gives the format of the HDLC header ‘000’ = no header bytes ‘001’ = one byte address ‘010’ = two byte address ‘011’ = one byte address + control ‘100’ = two byte address + control others = reserved Indicates if a 16-bit trailing CRC is to be appended to the CPS-Packet. This bit must be set in order for CPS-Packet loss errors (e.g. losses due to silence suppression or to network quality) to be reported on this CID. CPS-Packet loss errors are detected by circular buffer overflow, or due to CPS-Packet descriptor queue overrun (in HDLC), and by sequence number errors (in PCM). Reset by software upon opening the channel, set by hardware upon receiving the first CPS-Packet. Points to the location in the circular buffer used to contain HDLC packets where the next CPS-Packet will be written. Points to the location in the circular buffer used to contain HDLC packets where the next byte is to be read to be sent on the TDM bus Pointer to beginning of the HDLC Stream structure in the RX_TDM control memory to which this channel must be routed. Directing many HDLC streams to the same HDLC Stream structure allows many HDLC channels to point to a single stream. CRC LE CRC enable Loss Error Report Enable +0/b11 +0/b10 I Circ. Buffer Write Pointer [9:1] Circ. Buffer Read Pointer [9:1] HDLC Stream Number [9:0] Structure Initialized bit Circular Buffer Write Pointer Circular Buffer Read Pointer HDLC Stream Number +0/b9 +0/b8:b0 +2/b8:b0 +4/b9:b0 Table 23 - CPS-Packet Disassembly Structure (HDLC format) Fields 50 Preliminary Datasheet Field HDLC Address[15:0] A Name of Field HDLC Address [15:0] Clock recovery reference A Byte Address Offset/Bits Used +6/b15:b0 +8/b13 Description of Field MT90502 Address used to form the HDLC header. This field is ignored if the Header Type is ‘000’ When ‘1’, a pulse will be sent to the clock recovery module indicating that a reference packet (a timing CPS-Packet) has been received. This bit corresponds to clock recovery channel A which is independent of clock recovery channel B. When ‘1’, a pulse will be sent to the clock recovery module indicating that a reference packet (a timing CPS-Packet) has been received. This bit corresponds to clock recovery channel B which is independent of clock recovery channel A. Send UUI in control byte enable. When set and when Header Type is ‘011’ or ‘100’, the 5 MSBs of the HDLC control byte will be the UUI. Control byte used to form the HDLC control byte. This field is ignored if the Header Type is not ‘011’ or ‘100’. Free running count of received CPS-Packets (SID included). The LI expected in all voice packets. If the received LI does not match the Expected LI and RL = ‘1’, then an error report structure will be generated. Note: the CPS-Packet will still be treated. Report each CPS-Packet received in which the LI does not match Expected LI. Report each CPS-Packet received in which the UUI does not match expected UUI. ‘10000’ = 4 sequence bits ‘x1000’ = 3 sequence bits & UUI[3] in match ‘xx100’ = 2 sequence bits & UUI[3:2] in match ‘xxx10’ = 1 sequence bit & UUI[3:1] in match ‘xxxx1’ = 0 sequence bits & UUI[3:0] in match B Clock recovery reference B +8/b12 SUE Send UUI enable HDLC Control Byte CPS-Packet counter Expected LI +8/b8 Control Byte [7:0] CPS-Packet Counter[15:0] Expected LI +8/b7:b0 +C/b15:b0 +10/b13:b8 RL RU # Seq Bits/UUI M Report Length Errors Report UUI Errors Number Sequence Bits in the UUI and UUI Match +10/b7 +10/b6 +10/b4:b0 Table 23 - CPS-Packet Disassembly Structure (HDLC format) Fields (continued) Note: A and B bits in both the PCM and HDLC CPS-Packet disassembly structures are used to signal the chip when a timing reference CPS-Packet has been received. As the UTOPIA module can also generate these signals based on timing reference cells, each of these bits should be set in only one location: either in a single LUT or in a single CPS-Packet disassembly structure. The compression rate of the ADPCM CPS-Packets can be dynamically determined using the EDU field and the LI field of the CPS-Packet. Once the compression rate is determined for a CID, the ADPCM samples will be formatted according to the compression rate (see Figure 26 on page 52) and placed in the Rx Circular Buffer. To alter the monitored delay, software can generate a delay adjustment by writing the ADJ field to ‘1’ and the 2’s Complement Delay Adjust field to the number of bytes by which the delay should be altered. 51 MT90502 Format of RX Circular Buffer Preliminary Datasheet Valid Voice Samples (nibble in upper bits): b8 1 b8 1 b8 1 b8 1 b8 1 b7 b7 b6 b7 b6 b5 b4 b3 b2 b1 b0 Valid Voice Samples (nibble in lower bits): b8 1 b7 b6 b5 b4 b3 b2 b1 b0 PCM Sample b5 b4 b3 b2 1 b3 1 b4 1 b4 0 b3 0 b3 0 b2 0 b2 0 b2 0 b1 0 b1 0 b1 0 b1 0 b0 0 b0 0 b0 0 b0 0 PCM Sample b7 0 b7 0 b7 0 b7 0 b6 0 b6 0 b6 0 b6 0 b5 1 b5 0 b5 0 b5 0 b4 b3 b2 b1 b0 b8 1 b8 1 b8 1 b8 1 ADPCM 40kbps b7 b6 b5 b4 ADPCM 40kbps b4 1 b4 0 b4 0 b3 1 b3 0 b3 b2 b1 b0 32kbps b6 b5 32kbps b2 b1 b0 24 kbps b7 b6 b5 1 24 kbps b2 1 b1 b0 16 kbps 16 kbps b8 SID Entries: 0 b7 1 b6 b5 b4 b3 b2 b1 b0 0-127 = tones/silence/null pattern. Tone Buffer Number b8 Write back bytes: 0 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 Write Back rx9.cdd Figure 26 - Format of RX Circular Buffer For HDLC CPS-Packets, the RX SAR performs zero-insertion and appends the HDLC header and CRC (as necessary) to the packet before writing it to the circular buffer. The RX SAR can be configured to either bit-wise or byte-wise zero-insertion (one method for all of the HDLC channels). It can also write packets either with or without an AAL2 header. 2.4.4 CPS-Packet Loss Compensation The MT90502 is capable of calculating the elapsed time between the reception of two CPS-Packets. Based on the time elapsed and the difference in the sequence number in the UUI of the received CPS-Packet and that of the previous CPS-Packet, a count of how many CPS-Packets have been lost can be found. The circular buffer write pointer is adjusted to take the number of CPS-Packets lost into account before beginning to write the received bytes. This algorithm is only successful if the PDV between packets is smaller than a complete wrap of the UUI sequence counter. An enable bit (LC) in the CPS-Packet disassembly structure allows the CPS-Packet loss compensation to be turned on or off. 2.4.5 CPU CPS-Packets If the CID Description Structure denotes a CPS-Packet as a CPU CPS-Packet, the CPS-Packet will be written into the CPU CPS-Packet FIFO in external memory and a CPU CPS-Packet report structure will be generated (see Section 2.4.7, Errors and Events on page 53). The CPU is alerted to the presence of CPU CPS-Packets through the CPU CPS-Packet report structures. The CPU CPS-Packet base address can be read from the CPS-Packet report structure. The size of the CPU CPS-Packet FIFO is programmable (register 440h) as is its base address (register 440h). The size of the FIFO can vary from 16 KB to 128 KB. The CPU is responsible for updating the read pointer (register 442h) following each read. 52 Preliminary Datasheet 2.4.6 Treatment of Data Cells MT90502 Data cells, such as those containing OAM information, are placed in a programmable length FIFO in external memory. The length of the FIFO is stored in register 430h. The CPU can read one or more data cells from the FIFO at any time, after obtaining the address of the FIFO (register 430h) and the read pointer (register 432h). The CPU is responsible for updating the read pointer following each read. The write pointer, incremented by hardware, indicates the location where the next data cell will be written. The FIFO is empty is the read pointer points to the same location as the write pointer. The CPU can be alerted to the presence of data cells via an interrupt that triggers if either of two events occur: 1. the interrupt can be generated when the FIFO becomes more than half full, or 2. the interrupt can be generated if a data cell has been present in the FIFO for longer than a programmable period of time (registers 460h, 462h). When ready to process the information, the CPU obtains a read pointer to the information from register 432h and reads the information through 26-word accesses. Cells with the OAM bit set in the PTI portion of the header can be directed to the data cell FIFO on a per VC basis. The same is true for non-OAM cells. In addition, unknown non-OAM cells and/or unknown OAM cells can also be sent to the data cell FIFO. All unknown non-OAM cells are directed to the same location(s), and all unknown OAM cells are directed to the same location(s). 2.4.7 Errors and Events An Error/Event Report FIFO exists in RX SSRAM whose base address and size are configured through register 438h. Four types of structures, as shown in Figure 26, are available to cover all errors or events listed in Table 24. Once an error or event occurs, a corresponding 4-word structure will be generated and written into Report FIFO. The error/event structure contains all the details pertaining to that error or event. Similar to the data cell FIFO, the CPU can read the error/event FIFO at any time after obtaining the base address (register 438h) and the read pointer of the error/event FIFO (register 43Ch). Again, an interrupt can be generated that triggers if either of two events occur. Those events are • the FIFO becomes more than half full, or • an error/event report structure has been present in the FIFO for longer than a programmable period of time (registers 464h, 466h). When ready to process the information, the CPU obtains a read pointer to the information from register 43Ch and reads the information through 4-word accesses. Note: Both PCM and HDLC CPS-Packets will generate a report structure when they are initialized. Apart from the generation of the error report structure, no action is taken on errors/events. 53 MT90502 RX SAR Report Structures Preliminary Datasheet Reserved Per VC Report Structure b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 SN OFSHEC PAR +4 +6 VC Number[9:0] 0 0 0 Per CPU CPS-Packet Report Structure b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 VC Number[9:0] CPU CPS-Packet Base Address[20:5] 0 0 0 1 +4 CPU CPSPBA[4:1] +6 Per CID Report Structure (PCM CPS-Packets) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 UUI[3:2] +2 UUI[1:0] SID U +4 +6 O VC Number[9:0] I L ADJ LM UM 0 CID[7:0] LI[5:0] 0 1 0 First Byte of CPSP[7:0] CPS-Packet Loss[15:0] Per CID Report Structure (HDLC CPS-Packets) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 UUI[3:2] +2 UUI[1:0] PL1 PL2 +4 +6 VC Number[9:0] I LM UM 0 CID[7:0] 0 1 1 LI[5:0] VC Number : Number of the VC on which the error occured. SN : Sequence Number Error. OFS : Offset Error. HEC : AAL2 CPS-Packet Header HEC Error. PAR : Offset Field parity error. PL1 : Complete Packet Lost because of data buffer overflow (HDLC only). PL2 : Complete Packet Lost because of CPSPDQ overflow (HDLC only). SID : SID CPS-packet received. U: Underrun Detected. (xxPCM only) O : Overrun Detected. (xxPCM only) I: CID Initialized. First CPS-Packet has been received. (Both HDLC and PCM) L: Loss of one or many CPS-Packet detected. See CPS-Packet Loss for a count of loss packets. (xxPCM only) ADJ: CDV Adjustment Performed. (xxPCM only) LM : LI Mismatch. UM : UUI Mismatch. First Byte of CPS-Packet : This is the first byte of the CPS-Packet. When SID = ‘1’, this is the SID byte. Figure 27 - RX Error Report FIFO Structures 54 Preliminary Datasheet Category Cell-specific (per VC) Enable Location ER bit in each RX SAR disassembly structure Error/Event Sequence number error Offset Field error ATM HEC error Offset Field parity error CPU CPS-Packet PCM CPS-Packets (per CID) none LE in PCM CPS-Packet disassembly structure Reception of a CPU CPS-Packet SID CPS-Packet received Underrun error Overrun error CID initialized Loss of one or more CPS-Packets error PDV adjustment performed LI mismatch error HDLC CPS-Packets (per CID) LE in HDLC CPS-Packet disassembly structure data buffer overflow error CPS-Packet disassembly queue overflow error CID initialized LI mismatch error Table 24 - RX SAR Errors and Events MT90502 Coverage AAL2 cells AAL2 cells all ATM cells AAL2 cells CPU directed CPS-Packets PCM CPS-Packets PCM CPS-Packets PCM CPS-Packets PCM CPS-Packets PCM CPS-Packets PCM CPS-Packets PCM CPS-Packets HDLC CPS-Packets HDLC CPS-Packets HDLC CPS-Packets HDLC CPS-Packets 55 MT90502 2.5 2.5.1 TDM Reception Overview Preliminary Datasheet The RX TDM Module is responsible for reading bytes written to circular buffers in external memory by the RX SAR and administering the data to the H.100/H.110 interface module (see Section 2.7, “H.100/H.110 Interface,” on page 70). The RX TDM Module is capable of transmitting data in 1023 time slots on the H.100/H.110 bus. RX Cell Flow ATM Cell Received on UTOPIA Port Look-up Table Consulted Cell sent to RX data cell buffer Cell retransmitted on UTOPIA Port Cell Broken up Into CPS-Packets CPS Error Report (optional) CID/UUI Table Consulted CPS-Packet Sent to RX CPU CPS-Packet buffer SSCS Error Report (optional) CPS-Packet Written to a PCM Circular Buffer in SSRAM CPS-Packet Written to an HDLC Circular Buffer in SSRAM (after Zero Insertion) RX Channel Associated Link-List Consulted PCM/HDLC Circular Buffers in SSRAM PCM/HDLC Bytes send on H.100/H.110 Low Latency Loopback Memory H.100/H.110 F igure 28 - RX Cell Flow 56 Preliminary Datasheet 2.5.2 RX Channel Association Memory MT90502 The RX CAM generates a map that indicates which ADPCM channel, PCM channel or HDLC stream TSSTs are associated on the TDM bus. There are 1024 entries in RX CAM; the first entry is the permanent start entry for the map thus does not point to any TSST. The remaining 1023 entries are usable, each of which consists of • • • the PCM channel/ADPCM channel/HDLC stream number, or Loopback channel number. the TSST number the pointer to the next mapped entry. Note that the final entry in the map must always point back to the start entry. Like the TX CAM, all entries in the RX CAM must be linked sequentially in TSST order. RX Channel Association Memory b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 0 HDLC Stream/xxPCM Ch. Number TSST [11:0] Link to next entry +0 +2 +4 +6 1 LLL Ch. Number TSST [11:0] Link to next entry b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Fields in Plain are written to by the CPU/Software. RX TDM CAM structures are 8 bytes is size, located in internal memory at addresses 6000h to 7FF8h. Reserved HDLC Stream/xxPCM Ch. No.: Used to find an entry in RX TDM Control Memory (see Figure 30 and Figure 31). Link to next entry: Pointer to the next entry in the linked list. 000h means end of linked list, return to start. Entry 0 in the linked list is always the start of frame and never points to a valid TDM channel. Figure 29 - RX Channel Association Memory (RX CAM) 2.5.3 RX Channel Underrun Condition When servicing PCM/ADPCM channels, a byte is read every frame from the external circular buffers and transmitted onto the TDM bus. PCM/ADPCM channels can be configured to perform write backs to the circular buffers after the read has been completed. This will ensure erroneous data will not be transmitted onto the TDM bus while an underrun condition occurs. The WB (Write Back type) bits in the RX Control Memory determine what is written back: tone/silent pattern (programmable in silent_pattern_reg 410h) or no Write Back. The PCM/ADPCM entry in RX Control Memory contains several fields that control underrun detection: • 16-bit free-running underrun counter which counts the number of underruns that have occurred on this channel • The U C ( Underrun Count enable) bit enables the counter. The PCM/ADPCM control structure also contains the number of the PCM/ADPCM channel that is managed by the control entry. For underrun detection to work properly, all RX CPS-packet circular buffer contents, including parity bit, must be initialized to zero. 57 MT90502 RX TDM Control Memory Structure (PCM/ADPCM channels) Preliminary Datasheet b15 +0 +2 +4 +6 +8 IL b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Reserved Tone # to insert Underrun Count [15:0] CPS-Packet Dis. Struct Num [9:0] 1 OL URR WB UR UC Fields in Italic are used by Hardware only. Fields in Plain are written to by the CPU/Software. RX TDM Control Memory structures for XXPCM Channels are 16-bytes in size and are located in internal memory at addresses C000h and FFF0h. Tone # to insert: Indicates which tone/silence should be inserted when underruns occur. This can be used to generate DTMF, Dial-tones, Busy Tones, etc. 0-63 = tones in SSRAM; 64-95 = silent noises in SDRAM; 96-127 = insert programmable null byte. This number will be overwritten by SID packet. Underrun Count: Free running counter of the number of underruns detected on this channel. This field is in units of one sample being lost due to CPS-Packet loss or underrun situations. CPS-Packet Disassembly Structure Number:Pointer to the AAL2 channel associated with this TDM channel. This field is used to locate the RX Circular Buffer in SSRAM. IL: OL: URR: WB: UR: UC: Input law (from received CPS-Packet). ‘0’ = u-law; ‘1’ = A-law Output law (sent on TDM bus). ‘0’ = u-law; ‘1’ = A-law. If IL and OL are equal, bytes will not be modified. Otherwise u-law/A-law conversion will be done. Underrun Counter Rollover Report Enable. Write Back Type. ‘00’ = do not write back (replay buffer in case of underrun); ‘01’ = Write-back silent pattern in register 410h; ‘1x’ = reserved Underrun Report Enable. Underrun Count Enable (when ‘0’, the Underrun Counter is disabled; this saves interval bandwidth to the RX TDM Control memory). Figure 30 - RX TDM Control Memory Structure (PCM/ADPCM channels) 58 Preliminary Datasheet MT90502 RX TDM Control Memory Structure (HDLC Streams) b15 +0h +2h +4h +6h +8h +10h +12h +14h +16h +18h +20h +22h +24h +26h +28h +30h +32h +34h +36h +38h +40h +42h +44h +46h +48h NO7 NO7 Negative Offset [5:0] CPS-Packet Dis Struct Num Negative Offset [5:0] CPS-Packet Dis Struct Num CPSP Read [9:0] CPSP Read [9:0] Fields in Italic are used by the Hardware only. Fields in Plain are written to by the CPU/Software. b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Local WP Local RP Fetch WP CPSPDQ RP [11:0] CPSPDQ WP [11:0] Negative Offset [5;0] NO7 NO7 CPS-Packet Dis Struct Num Negative Offset [5:0] CPS-Packet Dis Struct Num Negative Offset [5:0] NO7 NO7 CPS-Packet Dis Struct Num Negative Offset [5:0] CPS-Packet Dis Struct Num Negative Offset [5:0] NO7 NO7 CPS-Packet Dis Struct Num Negative Offset [5:0] CPS-Packet Dis Struct Num CPSP Read [9:0] CPSP Read [9:0] CPSP Read [9:0] CPSP Read [9:0] CPSP Read [9:0] CPSP Read [9:0] CPS-Packet Disassembly Struct Num [9:0] Negative Offset [6:0] CPSPDQ Length [7:3] CPSPDQL [2:0] 0 Base HDLC structure for all HDLC Streams CPSP Read End of Packet Pnt [9:0] End of Packet Pnt [9:0] End of Packet Pnt [9:0] Second HDLC structure on a HDLC stream End of Packet Pnt [9:0] End of Packet Pnt [9:0] End of Packet Pnt [9:0] End of Packet Pnt [9:0] Third and up to N successive HDLC structures on a HDLC stream End of Packet Pnt [9:0] End of Packet Pnt [9:0] Reserved RX TDM Control Memory structures for HDLC Streams are located in internal memory at addresses C000h to FFF0h. CPS-Packet Disassembly Structure Number: Pointer to the AAL2 channel associated with this HDLC stream. This field is used to locate the RX Circular Buffer in SSRAM. CPSPDQ Length: Local WP/RP and Fetch WP: CPSPDQ RP/WP: CPSP Read End of Packet Pnt: Negative Offset: Pointer to the last octet in HDLC packet in the RX Circular Buffer. Current negative offset from the end of packet pointer at which the next byte of the HDLC packet will be read. Pointer to the pre-fetched HDLC packet handles contained in the 2/3/4/channel add on and the 5+ channel add-on. They must be initialized to 0h by software on HDLC stream start-up. Read/write pointer to this HDLC stream’s Packet Descriptor Queue (PDQ) in SSRAM. Packet Descriptor Queue Length. Set to the number of timeslots in the stream. 01h = 1 TSST, 02h = 2 TSST, Max size is 128. Figure 31 - RX TDM Control Memory Structure (HDLC Streams) 2.5.4 Compression The RX TDM supports compression on PCM/ADPCM channels at the following data rates: 40, 32, 24 and 16 kbps. Each frame maintains a 5-, 4-, 3- or 2-bit compressed value in the high or low bits of the TDM byte and the remainder indicates the data rate (see Figure 7 on page 26 and Figure 10 on page 28). 59 MT90502 2.5.5 HDLC Preliminary Datasheet When processing HDLC channels on a per frame basis, the TDM RX Module will transmit either data bytes or HDLC null patterns (All 1s in bit-wise HDLC or 7Eh in byte-wise HDLC). See Section 2.10, HDLC on page 94. HDLC null patterns are transmitted between HDLC packets. The RX SAR communicates packet information to the RX TDM through a packet descriptor queue held in external memory. A maximum of 16 descriptors per channel may be retained in external memory. The descriptor contains the origin channel number of the AAL2 channel, base address, and length of the CPS-Packet within the buffer. CPSPDQ Pointers +000h +004h +008h CPSPDQ Stream 0 CPSPDQ Stream 1 CPSPDQ Stream 2 CPSPDQ Length: Initialized to the number of timeslots in the HDLC stream. CPSPDQ WP and RP: Pointers to the CPS-Packet Descriptor Queue. CPSPDQ structures are located in RX SSRAM Memory. Address range for structures is +7000h to +071FCh, +0E000h to +0E3FCh, +0C000h to +1C7FCh and +38000h to +38FFCh for 128, 256, 512, and 1023 channels respectively. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 CPSPDQ Len[7:4] +2 CPSPDQ Len[3:0] CPSPDQ WP[11:0] CPSPDQ RP[11:0] +FF4h +FF8h +FFCh CPSPDQ Stream 1021 CPSPDQ Stream 1022 Each structure is 4 bytes in size. CPSPDQ Stream 1023 Fields in Italic are used by Hardware only. Fields in Plain are written to by the CPU/Software. Figure 32 - CPS-Packet Descriptor Queue Pointers Structure (HDLC Streams) 60 Preliminary Datasheet CPS-Packet Descriptor SSRAM Mapping - MPDQ Space + 0000h + 0040h + 0080h + 00C0h + 0100h HDLC Stream 0 CPSPDQ MPDQ HDLC Stream 1 CPSPDQ MPDQ HDLC Stream 2 CPSPDQ MPDQ HDLC Stream 3 CPSPDQ MPDQ HDLC Stream 4 CPSPDQ MPDQ +34 +38 + (N-3) * 4 0h + (N-2) * 40h + (N-1) * 40h HDLC Stream N-3 CPSPDQ MPDQ HDLC Stream N-2 CPSPDQ MPDQ HDLC Stream N-1 CPSPDQ MPDQ +3C CPSMini-Packet Descriptor 13 CPSMini-Packet Descriptor 14 CPSMini-Packet Descriptor 15 MT90502 Queue Structures +0 +4 +8 CPSMini-Packet Descriptor 0 CPSMini-Packet Descriptor 1 CPSMini-Packet Descriptor 2 Number of HDLC Streams (sar capacity) is N = 128, 256, 512, 1023. Number of HDLC Streams (sar_capacity) is NCPS-Packet = {128, 256, CPSPDQ structures are 64-bytes in size located in SSRAM memory at addresses +4000h to +5FC0h, 512, 1024} +8000h to +BFC0h, +10000h to +17FC0h and +20000h to +2FFC0h for 128, 256, 512 and 1023 channels respectively. This structure is used by Hardware only. Descriptor Structure Mini-Packet CPS-Packet Descriptor Structure b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Mini-Packet Disassembly Strct. Num[9:0] +0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 CPS-Packet Disassembly Strct. Num[9:0] +2 Mini-Packet Base Add [9:1] Length[6:0] CPS-Packet Base Add[9:1] Length[6:0] +2 Reserved CPS CPS Mini-Packet Disassembly Struct. Num : Indicates which Mini-Packet disassembly structure Indicates which CPS-Packet CPS this Mini-Packet comes from. This will identify the circular buffer in which it is written. CPS CPS-Packet Mini-Packet Base Add : Points to the first byte of the Mini-Packet within the circular buffer. CPS-Packet, Length : Length of the mini-packet, in bytes. Valid range 01h (1- byte) to 40h (64- bytes). Figure 33 - CPS-Packet Descriptor Queue Structures (HDLC Streams) As HDLC supports streams, numerous channel packet descriptor queues can be amalgamated into one packet descriptor per stream. However, it is necessary to specify the length of the packet descriptor queue within the structure that manages the stream; therefore, the MT90502 can determine where to wrap its read and write pointers. The length of the packet descriptor queue is programmed by the CPU/Software in the HDLC control structure (see Figure 30, “RX TDM Control Memory Structure (PCM/ADPCM channels),” on page 58). The CPS-Packet disassembly structures in the RX SAR determine where the HDLC channels are destined. In HDLC, time slot entries in the linked list can point to the same control structure entry, allowing the HDLC single-channel or stream to span consecutive time slots within the same TDM stream. This is employed for HDLC streams where the bandwidth requirements often exceed the constraints of a single time slot. Since multiple entries pointing to the same HDLC channel must all be contained within the same TDM stream, the maximum number of time slots that can be shared by the same HDLC channel is 128. 61 MT90502 2.6 2.6.1 UTOPIA Overview Preliminary Datasheet The purpose of the UTOPIA module is to provide an external interface with the ATM domain. The MT90502 complies with the ATM Forum's specifications: af-phy-0017.000 (PHY & SAR) and af-phy-0039.000 (PHY). The UTOPIA module is responsible for accepting cells from five input interfaces: UTOPIA A, UTOPIA B, UTOPIA C, CPU Origin Data Cell FIFO, and TX SAR (internal). Cells are examined, and based on the origin and information in the header, the cell is sent to one or more (multicast or broadcast) of the four output interfaces: UTOPIA A, UTOPIA B, UTOPIA C or RX SAR (internal). The UTOPIA module employs octet level handshaking. It also appends the HEC to outgoing ATM cells. The UTOPIA module has 2 different configurations and is constructed from three ports, labelled A, B, and C. • Each UTOPIA port (A, B or C) can be independently configured as a 8-bit Level 1 PHY or ATM port, and can operate at up to 32MHz. In this configuration, ports can be employed to daisy-chain other SAR devices to the MT90502, or operate in a ring configuration. Each port can treat 155Mbps of bandwidth. Ports A and B can also be combined to architect one UTOPIA Level 2 port in PHY mode only. It has an 8-bit data bus and a 5-bit address bus. This configuration allows the MT90502 to interface with any UTOPIA Level 2 master device in a multiple-PHY application. • In addition to ports A, B, and C, the UTOPIA can route data cells to the cell FIFO in external SSRAM. RXA UTOPIA 4 Cell input FIFO 16 Cell output FIFO TX SAR CPS-Packet to ATM Cell Assembly TXA UTOPIA RXB UTOPIA 4 Cell input FIFO 64 Cell output FIFO RX SAR ATM Cell to CPS-Packet Disassembly 4 Cell input FIFO 16 Cell output FIFO TXB UTOPIA CPU destined AAL0 Cells RXC UTOPIA 4 Cell input FIFO CPU Origin Data Cells 4 Cell input FIFO 16 Cell output FIFO TXC UTOPIA LUT in SDRAM (64K to 512K VCs/Port) Data Cell FIFO in SSRAM (4KB to 128KB) Figure 34 - SAR and UTOPIA Block The receive interface of each UTOPIA port can be independently enabled or disabled. If disabled, the receive interface will stop accepting cells after the current cell has been received. The transmit interface of each UTOPIA port can be configured to drive output pins (e.g. data bus, SOC and parity) only when this port has been selected. Those pins are tri-stated when the port is not selected. This allows the MT90502 to share a data bus, SOC, and parity lines with other devices (i.e. independent ENB signals and CLAV signals for each PHY device, controlled by a single ATM device). 62 Preliminary Datasheet 2.6.2 UTOPIA Interfaces MT90502 Each of the three ports are divided into two portions: a receive portion and a transmit portion. The TX_SAR and the receive portions are each connected to a 4-cell FIFO. The RX_SAR and the transmit portions are each connected to a 16-cell FIFO. The ports are configurable with the following options: • • • • • • • • • Port A's transmit portion can be ATM or PHY, with an 8-bit data bus.* Port A's receive portion can be ATM or PHY, with an 8-bit data bus.* Ports A and B can be combined to architect one UTOPIA Level 2 multi-PHY port, with an 8-bit data bus. Port B's transmit portion can be ATM or PHY, with an 8-bit data bus.* Port B's receive portion can be ATM or PHY, with an 8-bit data bus.* Port C's transmit portion can be ATM or PHY, with an 8-bit data bus. Port C's receive portion can be ATM or PHY, with an 8-bit data bus. Each receive interface can be independently enabled or disabled. If disabled, the receive interface will stop accepting cells after the current cell has been received. When the transmit portions of a port are in PHY mode, the SOC, data bus, and parity output pins will be tri-sected when the port is not selected. This allows the MT90502 to share a data bus, SOC, and parity lines with other devices (i.e. independent ENB signals and CLAV signals for each PHY device, controlled by a single ATM device). *Not applicable when Port A and B are configured as level-2 multi-PHY port. The RX_CLAV signal is asserted high any time a complete cell can be received. Thus as soon as the first byte of a cell is received, and there is no room for another cell in the input FIFO, the RX_CLAV signal will be asserted low. In the case of a Level-2 PHY, the rx_clav's will only be driven when the address has been placed on the bus during the previous cycle. 2.6.3 LED Operation The UTOPIA module generates four LED signals in order to indicate the status of each of the possible conditions for the A and B ports. The status conditions are: idle, presence of traffic or PHY alarm. When a port is in an idle state, both its LEDs are illuminated. If RX traffic (other than null cells) is flowing, then the RX LED for that port will flash; If TX traffic (other than null cells) is flowing, then the TX LED for that port will flash. If a PHY alarm is detected, the TX LED is static on and the RX LED is static off. The polarity of the LED signals is active-low, i.e., a ‘0’ will turn on the LED. The frequency of the LEDs is controlled in register 10Ch and the LED pins can also be configured to act as general purpose input outputs. The PHY alarm is another testing feature. If a PHY device connected to the MT90502 indicates a trouble with the PHY (through pins rxa_alarm or rxb_alarm), the MT90502 acknowledges receipt of the information by setting the LEDs appropriately (see above). The alarm causes no change in the MT90502, other than from setting the LEDs. 2.6.4 Errors on Received Cells If the MT90502 receives a short cell on any one of its three ports, the cell is discarded and the next cell is started when the second SOC signal is set. 63 MT90502 Preliminary Datasheet If the SOC is not set after the 53rd byte of a received cell, subsequent bytes are ignored until a new SOC is received. Data received on all three ports is examined for parity errors and an interrupt is raised if an error is found. Cells are not discarded if a parity error is detected. Register 60Ah indicates on which port the parity error is detected. The ATM HEC is not examined on received cells. 2.6.5 Cell Routing Cells are read in a cyclic manner from the 4-cell input FIFOs. Cells from the TX_SAR that contain a '0' in the MSB of the TXD field (see Figure 21, “TX Cell Format,” on page 43) are written into the output FIFOs designated by the three LSBs of the TXD field. The TXD field may also indicate that the cell is routed through one of the 3 look-up tables. Therefore, the cell follows the same path as if it came from one of the 3 UTOPIA input ports. Cells written into the RX_SAR FIFO can be directed to the SAR portion (cells to be formatted into TDM streams), to the data cell portion (to be examined by the CPU), or to both. This is indicated by the RXD field (see Figure 35, “RX Cell Format,” on page 64) in cells written into the RX_SAR output FIFO. RX Cell Format (of cells written in each of the internal input cell FIFOs in the UTOPIA interface) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 +0 +2 +4 +6 +30 +32 +34 Port # +36 +38 +3A +3C +3E GFC/VPI VCI [11:0] Payload Byte 0 Payload Byte 2 Payload Byte 44 Payload Byte 46 VC Number VPI OAM b2 b1 b0 CLP VCI [15:12] PTI Payload Byte 1 Payload Byte 3 Payload Byte 45 Payload Byte 47 RXD Reserved RX SAR Output FIFO structure is 64-bytes in size, located in internal memory at addresses 3000h to 3FFEh. Port #: VC Number: RXD: “00” = comes from LUT A, “01” = comes from LUT B, “10” = comes from LUT C; others = reserved indicates the VC to which this cell is destined, if it is destined to the RX SAR. RX Destination. “1x” = Destined to RX SAR, “x1” = destined to AAL0 FIFO. Figure 35 - RX Cell Format 2.6.5.1 Mask & Match Process Cells received on the UTOPIA port are designated as “known” or “unknown” based on the result of a mask & match process (configured for each port). For a cell to be considered “known”, all VPI/VCI bits whose corresponding mask bit is '1' must have the value contained in the corresponding bit of the match register. In addition, the MT90502 can be configured to eliminate null cells (those with VPI = 0 and VCI = 0). For the purpose of null cell elimination, the NNI/UNI can be included on a per-port basis (Register 60Eh). Unknown cells can be discarded or directed to one or more output FIFOs. All unknown non-OAM cells from a port are discarded or directed to the same location(s) and all unknown OAM cells from a port are discarded or directed to the same location(s). Unknown cells can be directed differently for each port on which they were 64 Preliminary Datasheet MT90502 received. Unknown cells cannot be sent to the SAR portion of the RX_SAR. The routing of unknown cells is set in registers 6A4h and 6A6h. Known cells are handled according to the LUT (Look-Up Table) entry for the cell's VPI/VCI. A cell is deemed to be an OAM cell if its MSB of PTI field is set. GFC | VPI | VCI (from cell header) 0010 10000000 00000000 10110010 Match Value Match Result (1 = Mismatch) Mask Value 0000 00000000 00000000 10110010 0010 10000000 00000000 00000000 0000 00111111 00000000 11111111 1 0010 10000000 00000000 10110 1 10 0 0000 00000000 00000000 10110 0 10 0010 10000000 00000000 00000 1 00 1 0000 00111111 00000000 11111 1 11 1 Mask Result (1 = mismatched cell) 0000 00000000 00000000 00000000 Result Routed according to LUT entry 1 0000 00000000 00000000 00000 1 00 Routed as unknown cell For each bit, result = (match XOR header) AND mask F igure 36 - Mask & Match Example 2.6.5.2 Look-Up Tables Entries LUT entries direct cells with known VPI/VCIs to either be discarded or placed in one or more of five possible destinations: the four output FIFOs (UTOPIA A, UTOPIA B, UTOPIA C or RX SAR (internal)) and the data cell FIFO in external SSRAM. OAM cells can be directed independently of non-OAM cells with the same VPI/VCI. OAM cells cannot be directed to the SAR portion of the RX_SAR. All look-up table entries in the three LUTs are the same size. Cells undergoing header translation have their NNI bits, the remaining VPI bits and/or the VCI bits replaced by the corresponding bits in the LUT entry and are then either discarded or sent to one or more of the possible destinations. Note: the 4 MSBs of the header (VPI bits 11:8 in NNI mode, or the GFC field in UNI mode) can be translated separately from the remaining portion of the VPI. The remaining two portions can also be translated separately, 8 bits of VPI and the 16 bits of VCI. The 3 header translation enable bits, NNI, VPI, and VCI denote the translation portion of the header. VCs that undergo header translation cannot be directed to the SAR portion of the RX_SAR as no RX_SAR structure pointer is available in the LUT entry. The look-up engine also contains bits indicating if the received cell is a timing reference cell. A timing reference cell indicates a cell whose arrival frequency, over a long period of time, is constant, and therefore can be used as a reference for the local TDM clock. If a timing reference cell is received, the UTOPIA module will send a pulse to the clock recovery module, indicating that such a cell has been received. Clock recovery information can be gathered from up to two VCs by setting bit A in one LUT entry and bit B in the same or another LUT entry. A maximum of one VC can have bit A set and a maximum of one VC can have bit B set. 65 MT90502 RX SAR Disassembly Structure +0000h +008h +0010h +0018h +0018h Preliminary Datasheet LUT- 0 LUT- 1 LUT- 2 LUT- 3 LUT- 4 LUT- N-3 LUT- N-2 LUT- N-1 v b15 b14 b13 b12 b11 b10 b9 b8 +0 NNI VPI VCI +2 +4 +6 A B Replacement VPI [11:0] Replacement VCI [11:0] b7 b6 b5 b4 b3 NCR b2 b1 b0 OCR VCI [15:12] b15 b14 b13 b12 b11 b10 b9 b8 +0 +2 +4 +6 Reserved b7 b6 b5 b4 b3 NCR VC Number [9:0] b2 b1 b0 +8*(N-3) +8*(N-2) +8*(N-1) 0 0 0 A B OCR N is defined as 2 (Number of considered VPI/VCI bits in concatenation) channels used. Fields in Plain are written by the CPU/Software. NCR: OCR: A & B: LUT A,B, and C structures are 8-bytes in size located in SDRAM at varying base addresses depending on the number of Normal Cell routing. “00000” = discard; “xxxx1” = Send to TXA port; “xxx1x” = Send to TXB port; “xx1xx” = Send to TXC port; “x1xxx” = Send to data cell FIFO (in external memory); “1xxxx” = Send to RX SAR. OAM Cell Routing. “0000” = discard; “xxx1” = Send to TXA port; “xx1x” = Send to TXB port; “xx1xx” = Send to TXC port; “1xxx” = Send to data cell FIFO (in external memory). Clock recovery reference indicators. When “1”, a pulse will be sent to the clock recovery module indicating that a reference packet has been received. These two bits correspond to two independent and redundant clock recovery VCs. Replace the cell VPI [11:8] with the Replacement VPI [11:8] when this bit is “1”. Replace the cell VPI [7:0] with the Replacement VPI [7:0] when this bit is “1”. Replace the cell VCI [15:0] with the Replacement VCI [15:0] when this bit is “1”. VC Number: Points to the RX Disassembly Structure to which this cell corresponds. NNI: VPI: VCI: Figure 37 - SDRAM Mapping - Look-Up Tables Structure 2.6.5.3 LUT Addressing A LUT base address and size exists for each of the three ports (registers 620h, 640h, 660h). The number of entries in the LUT, given by its size, ranges from 17 bits to 20 bits (128K to 1024K entries). A 17- to 20-bit identifier for each entry is created by concatenating the LSBs from the VPI field with LSBs from the VCI field of a cell header. The number of VCI LSBs to be used as the LSBs in the identifier is programmed in registers 622h, 642h and 662h for Port A, B and C, respectively. The remaining MSBs of the identifier are taken from the LSBs of the VPI field. This concatenated value is then multiplied by 8 (insert three LSB zeros). The result, when added to the LUT base address, will point to the base address of the LUT structure for this cell. The LUT, shown in Figure 37 will determine the routing and/or header translation of the cell. 66 Preliminary Datasheet b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 VPI VCI MT90502 vci_na (reg. 622h) = 5 VCI Bits Notes: • All three ports have independent parameters (vci_nx, LUT Base Address). result is a pointer, offset from the LUT Base Address, to the first byte of the LUT entry. LUT Entry Address represents a byte address b10 b1 Concatenated VPI and VCI b2 b1 b0 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 0 00 • b23. . . . . . . . . . . . . . . . . . . . . .. . ..20 Σ b19 . . . . . . . . 0 • Port A LUT Base Address (reg. 620h) 0......................0000 LUT Entry Address b23 b22 b21 b20b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Figure 38 - VPI/VCI Concatenation and LUT Entry Address Example 2.6.6 UTOPIA Clocks Each of the three ports must have a clock to operate the receive interface and a clock to operate the transmit interface. Two or more clocks may have the same source. These clocks can either be input to the MT90502 from an external source or output from the MT90502 from one of three internal UTOPIA clocks. However, the receive clock and transmit clock for a port can either be set as an input or an output. The source of each of the three internal UTOPIA clocks can be one of seven clocks: mem_clk, or any of the six UTOPIA clocks (rxa_clk, rxb_clk, rxc_clk, txa_clk, txb_clk, and txc_clk). The selected clock is divided by n and can be inverted (register 220h). The maximum speed of UTOPIA clock is 32MHz. Other parts of the UTOPIA module, including the look-up engine, the TX_SAR portion, and the RX_SAR portion operate off of mem_clk. 67 MT90502 xxx_clk_oe xxx_clk_inv Preliminary Datasheet TXA_CLK TXB_CLK TXC_CLK RXA_CLK RXB_CLK RXC_CLK txa_clk_in txb_clk_in txc_clk_in rxa_clk_in rxb_clk_in rxc_clk_in mem_clk xxx_clk_divisor_load_now Divisor xxx_clk_src xxx_clk_div Figure 39 - UTOPIA Clocks Selection Label txa_clk_div txa_clk_divisor_load_now txa_clk_inv txa_clk_src txa_clk_oe txb_clk_div txb_clk_divisor_load_now txb_clk_inv txb_clk_src txb_clk_oe txc_clk_div txc_clk_divisor_load_now txc_clk_inv txc_clk_src txc_clk_oe Register 220h 220h 220h 220h 220h 222h 222h 222h 222h 222h 224h 224h 224h 224h 224h Bit Position 5:0 6 7 10:8 11 5:0 6 7 10:8 11 5:0 6 7 10:8 11 Label rxa_clk_div rxa_clk_divisor_load_now rxa_clk_inv rxa_clk_src rxa_clk_oe rxb_clk_div rxb_clk_divisor_load_now rxb_clk_inv rxb_clk_src rxb_clk_oe rxc_clk_div rxc_clk_divisor_laod_now rxc_clk_inv rxc_clk_src rxc_clk_oe Register 228h 228h 228h 228h 228h 22Ah 22Ah 22Ah 22Ah 22Ah 22Ch 22Ch 22Ch 22Ch 22Ch Bit Position 5:0 6 7 10:8 11 5:0 6 7 10:8 11 5:0 6 7 10:8 11 Table 25 - UTOPIA Clocks Selection Registers 68 Preliminary Datasheet 2.6.7 External Interface Signals MT90502 Due to the different possible configurations of the UTOPIA ports, the functions of some pins change, depending on the configuration. The function of the CLAV (cell available) and ENB (enable data transfer) pins alternate when the port is in ATM mode or PHY mode (see Figure 40, “External UTOPIA Interface,” on page 69). Please note that the I/O direction of the pins remain fixed. Port A, B or C ATM Mode PHY Device MT90502 - ATM Mode txa_clk (D12) txa_enb (A13) txa_clav (B13) txa_soc (D14) txa_d (C15 . . .) txa_prty (D15) ATM Device Port A, B or C PHY mode MT90502 - PHY Mode txa_clk (D12) txa_enb (B13) txa_clav (A13) txa_soc (D14) txa_d (C15. . .) txa_prty (D15) txclk txenb txclav txsoc txdata txpar rxclk rxenb rxclav rxsoc rxdata rxpar rxclk rxenb rxclav rxsoc rxdata rxpar rxa_clk (A9) rxa_enb (B9) rxa_clav (C9) rxa_soc (C12) rxa_d (A12 .. .) rxa_prty (B12) txclk txenb txclav txsoc txdata txpar rxa_clk (A9) rxa_enb (C9) rxa_clav (B9) rxa_soc (C12) rxa_d (A12. . .) rxa_prty (B12) Figure 40 - External UTOPIA Interface 2.6.8 UTOPIA Flow Control The UTOPIA module contains the ability to prevent cells in the 4-cell input FIFOs (RXA, RXB, RXC, TX Data Cell FIFO and TX_SAR) from being processed by the UTOPIA module in case the output FIFOs (TXA, TXB, TXC and RX_SAR) exceed programmable levels. For each pair of input and output FIFO, a threshold can be set independently from 0 to 15 (for TXA, TXB and TXC output FIFOs) or 0 to 63 (for RX_SAR output FIFO). Once the cell level in output FIFO exceeds that threshold, cells from that input FIFO are blocked until the output FIFO empties itself below the threshold. There are cell arrival counters and cell departure counters for each port. 69 MT90502 2.7 2.7.1 H.100/H.110 Interface Overview Preliminary Datasheet The H.100/H.110 interface is compatible with the ECTF H.100/H.110 hardware compatibility specification, Computer Telephony BUS (CT-BUS), and its implementation on the PCI computing platform. The TDM interface of the MT90502 can be used to interface as bus master or bus slave with the H.100/H.110 bus. The MT90502 supports up to 32 TDM Streams running at 8.192MHz (up to 4096 time slots). Also, as required in the specification, 16 TDM streams can be configured to run at lower frequencies of 4.096MHz or 2.024MHz. The MT90502 can perform loopback on 128 channels. 2.7.2 Bus Signaling There are four classes of signals on the H.100/H.110 CT-Bus: Core, Compatibility, Optional, and Reserved signals. Core, Compatibility, and Reserved signals are required for all H.100/H.110 compatible devices. These signals are described in Table 26, “CT-Bus Signalling Function,” on page 70. 2 .7.3 H.100/H.110 Slave Class Core Signal CT_FRAME_A CT_C8_A CT_FRAME_B CT_C8_B CT_D[31:0] Function Frame Synchronisation, driven by the “A” clock master. Bit clock driven by the “A” clock master. Configurable frame synchronisation, driven by the “B” clock master. Configurable bit clock - driven by “B” clock master. Serial Data lines that collectively carry 32 signals and are referred to as the CT_D bus. Each signals contain 128 time slots per frame at a clock frequency of 8.192MHz. Secondary network timing reference, providing backup network synchronisation to the CT Bus. Compatibility frame pulse, driven by current clock master, that serves as the frame synchronization signal for the SCBus (Fsync*) and MVIP (F0) signals. SCBus system clock, driven by current clock master. The signal is selectable (2, 4, or 8MHz) and is used to identify the data bits positions on the SCBus. SCBus system clock times two, driven by clock master. MVIP-90 bit clock, driven by current clock master. The clock frequency is 2MHz, nominally symmetrical. MVIP-90 bit clock times two, driven current by clock master. The clock frequency is twice C2, and transitions of C2 are synchronous with the falling edge of C4. H-MVIP 16 MHz Clock, driven by current clock master. This differential signal is used to read and write bits on the serial data lines by H-MVIP boards. Message Channel for inter-device communication. This signal is terminated on each CT Bus interface in the system which has message bus capability. Provides power to active transition devices (cable adapters). Signals reserved for future use. CT_NETREF Compatibility FR_COMP SCLK SCLKx2 C2 C4 C16+, C16Optional CT_MC CT_+5Vdc Reserved Table 26 - CT-Bus Signalling Function The H.100/H110 interface can sample the incoming data on the ct_d[31:0] at different sampling points: 2/4, 3/4 or 4/4 sampling. The desired sampling point can be set by setting the timing configuration register (732h). When transmitting data, the H.100/H.110 can tri-state its pins between 20ns and 0ns before the rising edge of 70 Preliminary Datasheet MT90502 the clock or it can tri-state synchronously on the rising edge of the clock. Both of these options allow flexibility in compatibility with other devices that are not fully H.100/H.110 compliant. 2.7.4 Operating as a Slave Two clocks, A and B, can be configured to set one clock as primary bus master and the other one as backup master. In the event of primary clock failure, the interface can switch over to backup. The MT90502, when operating as a slave, has the choice of clocking on A, clocking on B, clocking on A with B as backup, or clocking on B with A as backup. When set to perform automatic switch-over, the interface monitors the active bus master to determine if its ct_c8 clock edges are within ±35 ns of their expected edge times (122 ns apart) and the ct_frame signal occurs upon the 1024 ct_c8 clock cycle. If ct_c8 or ct_frame errors are reported on the bus master signals, the ct_c8 or ct_frame is considered invalid and the slave will switch to the backup master (if backup has been configured). The MT90502 will always monitor these signals and will report errors on either of the two bus masters in status0 register (702h). 2 .7.5 Operating as a Master When configured as a bus master, the MT90502 can be a bus master on A, B, backup on A or backup on B. The difference between a bus master and a bus backup is that bus master drives all compatibility clocks, and the bus backup does not. When configured as a bus backup, the MT90502 uses the same error signals or error flags to determine if the current bus master is valid or if MT90502 reverts to be the master. Note that the bus mastership can be overridden in registers mastership_hidden0 (774h), mastership_hidden1 776h) and mastership_hidden2 (778h) by ensuring that the MT90502 cannot drive the H.100/H.110 clock and frame signals. If the MT90502 is a backup on the bus and the primary master fails, it will stop synchronising to the master and track the local reference. ct_c8 ct_frame fr_comp(8M,Strdl) fr_comp(4M,Strdl) fr_comp(2M,Strdl) fr_comp(8M,Last) fr_comp(4M,Last) fr_comp(2M,Last) fr_comp(8M,First) fr_comp(4M,First) fr_comp(2M,First) Note: The fr_comp polarity in this drawing is always active low for simplicity. It can also be programmed active high. Figure 41 - TDM Bus Timing - Fr_Comp Generation Once configured as bus master, MT90502 provides compatibility clocks generated by H.100/H.110 module. Figure 42, “TDM Bus Timing - sclkx2 Generation,” on page 72 shows the MT90502’s compatibility signals generated on H.100/H.110 interface. 71 MT90502 ct_c8 ct_frame sclkx2(8M) sclkx2(8M,inverted) sclk(8M) sclk(8M,inverted) sclkx2(4M) sclkx2(4M,inverted) sclk(4M) sclk(4M,inverted) sclkx2(2M) sclkx2(2M,inverted) sclk(2M) sclk(2M,inverted) Preliminary Datasheet Figure 42 - TDM Bus Timing - sclkx2 Generation ct_c8 ct_frame c16+ c16c2 c4 Figure 43 - TDM Bus Timing - Compatibility Clock Generation (other than sclk, sclkx2) The sclk and sclkx2 signals can be programmed in mastership0 register (720h) to have identical or opposite polarities as defined in the H.100/H.110 specifications. In addition, the frequency of sclk can be programmed to be 8.192MHz, 4.096MHz or 2.048MHz. The lower 16 streams on the H.100/H110 bus are grouped into 4 and are capable of operating at the following frequencies: 8.192MHz, 4.096MHz, or 2.048MHz. The MT90502 can be programmed such that all 32 streams are arranged in groups of 4 streams - ct_c[3:0], ct_c[7:4], ct_c[11:8], ct_c[15:12], ct_c[19:16], ct_c23:20], ct_c[27:24] and ct_c[31:28]. Each group can be assigned a desired frequency. These features are programmed in clock_rates register (730h). In addition, the MT90502, instead of supporting the full bandwidth of H.100/H.110, can be configured to only interface with 4, 8 or 16 streams on the bus. This allows the MT90502 to operate at lower frequencies. The lowest streams are used in these cases. 2.7.6 H.100/H.110 Clock Selection Guide Fast_clk is used internally by the MT90502 as its main operating clock. The internal logic used to generate fast_clk is show in Figure 44 on page 73. Typically mem_clk would be selected using pll_source. 72 Preliminary Datasheet pll_bypass pll_source UPCLK MEM_CLK Divisor (1 to 8) Ref Clock out Fast_clk PLL pll_div_x” pll_div_x Feedback MT90502 fast_clk Divisor (1 to 8) pll_div_y Figure 44 - Fast Clock Generation The pll_div_x and pll_div_y should be programmed according to Figure 44, “Fast Clock Generation,” on page 73. The fast_clk frequency is given by the formula · pll_div_y fast_clk = input_frequency × ---------------------- . pll_div_x upclk/mem_clk (MHz) >75 >66 >50 >40 >30 >25 pll_div_x 1 2 1 1 1 1 pll_div_y 2 5 3 4 5 6 Table 27 - Fast Clock PLL Divisor Values Label pll_div_x pll_div_y pll_bypass pll_source Register 16Ch 16Ch 16Ch 16Ch Bit Position 3:1 6:4 7 8 Table 28 - Fast Clock Registers The mastership mode and slaveship mode of the MT90502’s TDM interface can be programmed using register 722h. Mastership mode determines on which bus(es), A or B, the MT90502 will act as a master or backup. When configured as a master on a bus, the MT90502 drives the frame pulse and clock on that bus as well as the compatibility signals (if enabled). When configured as a backup on a bus, the MT90502 drives the frame 73 MT90502 Preliminary Datasheet pulse and clock on that bus, but does not drive the compatibility signals. The slaveship mode configures the MT90502 to synchronize its internal timing to the ct_frame pulse and ct_c8 clock on either the A or the B bus. The slaveship mode is completely independent of the mastership mode. An example configuration would have the mastership mode set for the MT90502 to be a master on A and setting the slaveship mode for the MT90502 to track on A. Register 774h can be used to override the operation of the MT90502 based on the selections made in register 722h. The automatic_master_override bit will enable the rest of the values in this register. The mux0_select_override bit will stop the automatic fallback of the slaveship mode (from A to B or B to A). The mux1_select_override bit will select between using ct_c8_a/ct_c8_b or H.110 PLL output clock as the feedback signal to the H.110 PLL. The mux2_select_override bit will select between ct_c8_a/ct_c8_b or pll_clk as the reference source for the H.110 PLL. The mux3_select_override bit will select between using either an external pll_clk or the H.110 PLL output as the clock used to generate the ct_c8_x and ct_frame_x and clock signals. ÷4 slaveship_mode ct_c8_a ct_c8_b mux2_select_override pll_clk_in_frequency pll_clk ÷n Feedback Output mux1_select_override mastership_mode ct_compatibility_oe compatibility clocks* mux3_select_override ct_c8_frame_a_oe Clock Generation Module A mastership_mode ct_c8_a ct_frame_a H.110 PLL Reference Clock Generation Module B slaveship_swap ct_c8_frame_b_oe ct_c8_b ct_frame_b mux0_select_override ct_frame_a ct_frame_b Monitor Clocks automatic_fallback *fr_comp, sclk, sclkx2, c2, c4, c16+, c16- Figure 45 - H.100/H.110 PLL Clock Selection Label pll_clk_in_frequency ct_c8_frame_a_oe ct_c8_frame_b_oe ct_compatability_oe mastership_mode slaveship_mode automatic_master_override mux0_select_override mux1_select_override mux2_select_override mux3_select_override Register 700h 720h 720h 720h 722h 722h 774h 774h 774h 774h 774h Bit Position 1:0 0 1 2 1:0 3:2 0 1 2 3 5:4 Table 29 - H.100/H110 PLL Clock Selection Registers 74 Preliminary Datasheet 2.8 2.8.1 Clock Recovery Overview MT90502 The purpose of the clock recovery module is to synchronize the TDM clock domain of the MT90502 with other devices on the network through information transmitted across the ATM link. Clock recovery is necessary only when the MT90502 is operating as the TDM clock master. The clock recovery system is composed of several sub-components: 2.8.1.1 Adaptive Clock Recovery Modules These modules generate data on a regular basis which is written to external memory for the CPU to read and is used by the clock recovery algorithm. Counts of mem_clk and adapx_ref clock, as well as the current UUI and LI values, associated with the current cell, are placed in external memory. 2 .8.1.1.1 adapx_ref clock generation These modules divide mem_clk to a desired frequency with a 16-bit integer and 16-bit fraction. These 32 bits are normally determined by the clock recovery algorithm. 2.8.1.2 Multiplexers There are eight general purpose I/Os as well as two ct_netref pins. Each has the ability to multiplex one of 23 signals as outputs. 2.8.2 Adaptive Clock Recovery Modules The MT90502 has two clock recovery modules, A and B. Each module receives pulses obtained either from the UTOPIA module (timing reference VCs) or from the Rx SAR (timing reference CPS-Packets). The signals clkrecov_pulse_a and clkrecov_pulse_b come from one of these modules. The modules which generate the A and B clkrecov_pulses are configured by the A and B bits. These are configured in the UTOPIA section for timing reference VCs or in the Rx SAR section for timing reference CPS-Packets. The VC/CPS-Packet designated A is the timing reference for the A clock recovery module (clkrecov_pulse_a). Similarly, for the B clock recovery module, the clkrecov_pulse_b is generated by the VC/CPS-Packet designated by its B bit. Running in parallel, are counters of the mem_clk and adapx_ref signals. A clock recovery event structure is written to external memory with the arrival of every X pulses of clkrecov_pulse_x. The structure (see Figure 46 on page 76) is composed of the 32-bit “mem_clk” counter, the 32-bit “ref” counter, a 16-bit “mem_clk_cycles_since_last_ref_increment” counter (fraction of the ref), as well as the LI and UUI of the received CPS-Packet. These event structures are written to a buffer in external memory, and the clock recovery module will generate an interrupt when the buffer is more than half full (if enabled in bit 10 of register 210h). Clock recovery events arrive at a fixed rate, therefore the size of the buffer chosen (820h, 828h Table 31, “Buffer Sizes,” on page 81) will completely determine the rate at which it needs to be serviced. To decrease the number of points written to memory, program the keep_one_pulse_out_of_x register (710h & 718h see Table 30, “Clock Recovery Registers,” on page 79) to a value greater than 1. 75 MT90502 Adaptive Clock Recovery Event Information b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 mem_clk_counter[31:16] mem_clk_i_counter[31:16] Preliminary Datasheet +0 +2 +4 +6 +8 +A +C +E mem_clk_counter[15:0] mem_clk_i_counter[15:0] ref_counter[31:16] ref_counter[15:0] mem_clk_i_cycles_since_last_ref_increment[15:0] LI[5:0] UUI[4:0] mem_clk_i_counter : Freerunning mem_clk_i cycle counter. This field is used as a reliable time-stamp in the clock recovery algorithm. ref_counter: Freerunning reference clock cycle counter. This field is used to control wander in the generation of the reference clock. mem_clk_i_cycles_since_last_ref_increment : This field counts the number of mem_clk_i cycles since the last time the ref_counter incremented. This field is used to control wander in the generation of the reference clock. LI & UUI: Length and UUI information of the CPS-Packet that generated this clock recovery mini-packet event information structure. clk1.cdd Reserved Figure 46 - Adaptive Clock Recovery Event Information The base addresses and structures sizes for adaptive clock recovery event structures for module A and module B are programmable in registers 820h ‘pointa_manage’ and 828h ‘pointb_manage’ respectively. The address of the structures to be read can be determined using the read and write pointers located in registers 822h ‘pointa_read’, 824h ‘pointa_write’, 82Ah ‘pointb_read’ and 82Ch ‘pointb_write’. Similar to the event/error FIFO and the data cell FIFO, the read pointers must be updated by the CPU/software and the write pointers are updated by the hardware. 76 Preliminary Datasheet MT90502 clkrecov_pulse_a Keep One Pulse Out of X (Range = 1-1024) gpio_in [0] E mem_clk 8 word Clock Recovery 32 bit freerunning mem_clk counter Structure 16 bit mem_clk count since last ref rising edge Written to clock recovery buffer A in external TX SSRAM 32 bit freerunning ref rising edge counter mem_clk Programmable Fractional Divisor (Range = 2 to 65535) adapa_ref clkrecov_pulse_b Keep One Pulse Out of X (Range = 1-1024) gpio_in [1] mem_clk 32 bit freerunning mem_clk counter E 8 word Clock Recovery Structure 16 bit mem_clk count since last ref rising edge Written to clock recovery buffer B in external TX SSRAM 32 bit freerunning ref rising edge counter mem_clk Programmable Fractional Divisor (Range = 2 to 65535) adapb_ref Figure 47 - Adaptive Clock Recovery Modules 77 MT90502 2.8.2.1 adapx_ref Clock Generation Preliminary Datasheet The second portion of the clock recovery circuit is concerned with generating the adapx_ref signal. When the CPU reads the information placed in the clock recovery event buffer, the clock recovery algorithm can subsequently calculate any correction required to the rate of the adapx_ref clock. A typical configuration would see the adapx_ref signal operating at 8kHz. This is outputted to a PLL which multiplies the frequency up to 16.384MHz. Finally, the 16MHz clock is used as the driving clock for the TDM section, pll_clk (pin AB2). The adapx_ref clocks are generated by dividing mem_clk by a 16-bit integer (712h & 71Ah) and 16-bit fraction (714h & 71Ch). This allows a highly precise division (with mem_clk running at 50 MHz and the target clock speed 8 kHz, it gives a precision of 2.4 ppb). fmem_clk f adapx_ref = ---------------------------------------------fraction integer + -------------------65536 The fractional divider will introduce jitter into the adapx_ref signal of a maximum of one mem_clk cycle. If it is desired that no jitter be added by the adapx_ref module, set fraction to 0 (this will reduce precision to 160 ppm from 2.4ppb). The integer and fraction are programmed by the clock recovery algorithm. The adapx_ref signal can be driven onto any of the eight GPIOs on the MT90502, or to one of the ct_netrefs (see Figure 49). It can be externally routed to a PLL used to multiply it up from 8 kHz to 16.384 MHz and then rerouted into the MT90502 on the pll_clk pin. 2.8.3 Multiplexers Message Channel Circuit gpio_in[2] 0 ct_mc ct_mc_in ct_c8_selected ct_frame_selected MC Clock Generator mc_clock Figure 48 - Message Channel 78 Preliminary Datasheet MT90502 gpio_x_output_select ct_c8_a ct_c8_b ct_frame_a ct_frame_b ‘0’/‘1’ ct_c8_selected ct_frame_selected ct_netref1 ct_netref2 gpio_in[1] gpio_in[2 gpio_in[3] gpio_in[4] gpio_in[5] gpio_in[6] gpio_in[7] adapa_ref adapb_ref clkrecov_pulse_a clkrecov_pulse_b mc_clock ct_mc ct_netrefx_output_select Glitch Free Mux gpio_in[0] gpio_x_output_enable, ct_netrefx_output_enable gpio[7:0], ct_netref1, ct_netref2 Edges and Level Monitor Figure 49 - GPIO Functionality There are eight GPIO multiplexers in the clock recovery section of the MT90502. In addition, there are two multiplexers for the two ct_netref signals of the H.110 bus. See registers 740h - 748h (Table 30, “Clock Recovery Registers,” on page 79). There are 23 possible inputs for each multiplexer (see Table 32, “GPIO mux, Output Selection,” on page 82). Address 210h 218h 21Ah 710h Bits [10] [10] [10] [9:0] Register interrupt_flags interrupt_enable1 interrupt_enable2 adapa0 Bits clkrecov_alarm_interrupt_a ctive clkrecov_alarm_interrupt1_ enable clkrecov_alarm_interrupt2_ enable keep_one_pulse_out_of_x Description Indicates clock recovery buffer is half full. Activates interrupt1 when clkrecov_alarm set. Activates interrupt2 when clkrecov_alarm set. Number of points generated to send to external memory. Table 30 - Clock Recovery Registers 79 MT90502 Address Bits [10] [12:11] [13] 712h 714h 718h [15:0] [15:0] [9:0] [10] [12:11] [13] 71Ah 71Ch 740h [15:0] [15:0] [4:0] [5] [6] [12:8] [13] [14] 742h [4:0] [5] [6] [12:8] [13] [14] 744h [4:0] [5] [6] [12:8] [13] [14] 746h [4:0] [5] gpio_out_reg3 gpio_out_reg2 gpio_out_reg1 adapb1 adapb2 gpio_out_reg0 adapa1 adapa2 adapb0 Register Bits clk_divisor_reset source clk_divisor_load_now div_integer div_fraction keep_one_pulse_out_of_x clk_divisor_reset source clk_divisor_load_now div_integer div_fraction gpio_0_output_select gpio_0_output_constant gpio_0_output_enable gpio_1_output_select gpio_1_output_constant gpio_1_output_enable gpio_2_output_select gpio_2_output_constant gpio_2_output_enable gpio_3_output_select gpio_3_output_constant gpio_3_output_enable gpio_4_output_select gpio_4_output_constant gpio_4_output_enable gpio_5_output_select gpio_5_output_constant gpio_5_output_enable gpio_6_output_select gpio_6_output_constant Preliminary Datasheet Description If ‘0’, reset clock divisor. ‘00’ - reference VC, ‘01’ - gpio[0] all edges, ‘10’ gpio[0] rising edges, ‘11’ gpio[0] falling edges If set to ‘1’, loads adaptive module A’s divisor. Adaptive module A - integer divisor Adaptive module A - fractional component of divisor Number of points generated to send to external memory. If ‘0’, reset clock divisor. ‘00’ - reference VC, ‘01’ - gpio[0] all edges, ‘10’ gpio[0] rising edges, ‘11’ gpio[0] falling edges If set to ‘1’, loads adaptive module A’s divisor. Adaptive module A - integer divisor Adaptive module A - fractional component of divisor See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (see Table 32) ‘0’ - tri-state, ‘1’ - output enabled. see Table 32 Constant value of ‘00110’ (see Table 32) ‘0’ - tri-state, ‘1’ - output enabled. See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (of Table 32) ‘0’ - tri-state, ‘1’ - output enabled. See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (of Table 32) ‘0’ - tri-state, ‘1’ - output enabled. See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (of Table 32) ‘0’ - tri-state, ‘1’ - output enabled. See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (See Table 32 - on page 82). ‘0’ - tri-state, ‘1’ - output enabled. See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (see Table 32, “GPIO mux, Output Selection,” on page 82). Table 30 - Clock Recovery Registers (continued) 80 Preliminary Datasheet Address Bits [6] [12:8] [13] [14] 748h [4:0] [5] [6] [12:8] [13] [14] 802h [1] [2] 804h [1] [2] 820h [8:0] [11:9] 822h 824h 828h [13:0] [13:0] [8:0] [11:9] 82Ah 82Ch [13:0] [13:0] pointb_read pointb_write pointa_read pointa_write pointb_manage pointa_manage satus0_ie status0 gpio_out_reg4 Register Bits gpio_6_output_enable gpio_7_output_select gpio_7_output_constant gpio_7_output_enable ct_netref1_output_select ct_neterf1_output_constant ct_netref1_output_enable ct_netref2_output_select ct_netref2_output_constant ct_netref2_output_enable pointa_buf_overflow pointb_buf_overflow pointa_buf_overflow pointb_buf_overflow pointa_buffer_base_add pointa_buffer_size pointa_rpnt pointa_wont pointb_buffer_base_add pointb_buffer_size pointb_rpnt pointb_wont Description ‘0’ - tri-state, ‘1’ - output enabled. MT90502 See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (of Table 32) ‘0’ - tri-state, ‘1’ - output enabled. See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (See Table 32, “GPIO mux, Output Selection,” on page 82). ‘0’ - tri-state, ‘1’ - output enabled. See Table 32, “GPIO mux, Output Selection,” on page 82. Constant value of ‘00110’ (of Table 32) ‘0’ - tri-state, ‘1’ - output enabled. Overflow occurred in the point A buffer. Overflow occurred in the point B buffer. If ‘1’, pointa_buf_overflow will generate interrupt. If ‘1’, pointb_buf_overflow will generate interrupt. Bits 20:12 of the base address of the clock recovery point buffer. see Table 31 CPU’s read pointer to the clock recovery point FIFO. Chip’s write pointer to the clock recovery point FIFO. Bits 20:12 of the base address of the clock recovery point buffer. See Table 31, “Buffer Sizes,” on page 81. CPU’s read pointer to the clock recovery point FIFO. Chip’s write pointer to the clock recovery point FIFO. Table 30 - Clock Recovery Registers (continued) Register Value 000 001 010 011 100 101 others Memory Allocated 4K 8K 16K 32K 64K 128K reserved Table 31 - Buffer Sizes 81 MT90502 gpio_x_output_select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 Signal ct_c8_a_in ct_c8_b_in ct_frame_a_in ct_frame_b_in ct_c8_selected ct_frame_selected output constant (“0”/“1”) ct_netref1_in ct_netref2_in gpio_in(0) gpio_in(1) gpio_in(2) gpio_in(3) gpio_in(4) gpio_in(5) gpio_in(6) gpio_in(7) adapa_ref adapb_ref clkrecov_pulse_a clkrecov_pulse_b mc_clock ct_mc_in Preliminary Datasheet Table 32 - GPIO mux, Output Selection 82 Preliminary Datasheet 2.9 2.9.1 Silence Suppression Overview MT90502 The Variable Bit Rate properties of the AAL2 standard permits the use of silent suppression. The MT90502 exploits this feature to enable optimal bandwidth usage for voice communications. The MT90502 has the capability to determine if an AAL2 CPS-Packet (transmitted or received) is considered silent. Two configurations can be employed for silent suppression: simple silence suppression and complex silence suppression. Simple silence suppression mode uses an external resource or the match & mask feature determines the silent status of the byte. In complex silence suppression mode the MT90502 determines the silent status on the current CPS-Packet. The MT90502 maintains a maximum channel capacity of 1023 channels with or without silence suppression enabled. 2.9.2 Simple Silent Suppression 2.9.2.1 Silent Bit Indication Simple Silent Suppression relies upon an external resource to perform the silent decision operation unless the match and mask method is employed. The result yielded from the external resource is conveyed to the MT90502 by a silent bit in the associated TSST (see Figure 50 on page 83). A one in silent bit indicates that the accompanying PCM or ADPCM sample is a silence. The position of silent bit is programmable through register 500h. Upon the reception of a complete CPS-Packet of silence, the CPS-Packet is considered silent and the process of generating an SID CPS-Packet is initialized. The Noise Level field in SID packet will contain an idle code (no noise). Simple Silence Suppression TDM Channel Mapping ct_c8 ct_frame ct_d[n] ct_d[n+1] ADPCM Nibble or PCM Byte Silent n is an even number Figure 50 - Simple Silent Suppression Stream Configuration 2.9.2.2 Last Byte Indication This method is only available when TDM Format B is deployed. In this mode, external silence suppression engine shall make the decision whether a CPS-Packet is silence or voice, and indicate a silent packet by putting 00h on the last byte of that packet, together with PCM bit equal to 0 (see Figure 9 on page 27 and Figure 11 on page 29). MT90502 calculates the average energy of the packet based on the Tx PCM unsigned magnitudes received on the first TSST. Tx PCM magnitude given to MT90502 must be an unsigned value without DC offset. Upon detecting silent packet pattern at the end of the packet, the MT90502 will discard that packet and start silence period. Should a SID packet be sent out, MT90502 will insert the calculated energy level into SID byte. 2 .9.2.3 Match and Mask Determines Silence The match and mask filtering operation operates in a similar method as the UTOPIA match and mask. There are two match and mask registers: ‘Silent Pattern Detection Register A’ and ‘Silent Pattern Detection Register B’ address (512h and 514h respectively). The registers are configured to compare selected bits of the PCM value. The mask field determines which bits to compare and the match field detects silent values. If the byte yields a 0 result from the match and mask filter, then the byte is regarded as silent. Upon the reception of a complete CPS-Packet of silence, the CPS-Packet is considered silent and the process of generating an SID CPS-Packet is initialized. 83 MT90502 The Noise Level field in SID packet will contain an idle code (no noise). TDM Data Byte Match Value Match Result (1 = Mismatch) Preliminary Datasheet 10110010 10110010 00000000 11111111 00000000 Considered Silent 10110110 10110010 00000100 11111111 00000100 Not Silent Mask Value Mask Result (1 = mismatched cell) Result For each bit, result = (match XOR header) AND mask Figure 51 - Silent Suppression Mask & Match Example 2.9.3 Complex Silent Suppression Complex silence suppression eliminates the external resource requirement to determine silent byte or silent packet. The MT90502 analyses both the remote (Rx direction) and local (Tx direction) signals and evaluates if silence is to be suppressed. The remote and local signals are processed to determine their average dB value over a CPS-Packet. The mean average dB of the CPS-Packet for both directions are employed to identify the transmission state as defined in the user configurable State Graph (Figure 52 on page 85). 84 Preliminary Datasheet Silence Suppression State Table b15 b14 b13 b12 b11 b10 b9 +0 S[0] S[1] S[2] MT90502 b8 b7 b6 b5 b4 b3 b2 b1 b0 S[3] S[4] S[5] S[6] S[7] +7FE S[16376] S[16377] S[16378] S[16379] S[16380] S[16381] S[16382] S[16383] -Index = (((-Local = (((-Local *128)+(-Remote Energy)) where the local and Remote - Index Energy) Envergy) *128) + (-Remote Energy)) where the Local and Energies range from 0 to -78 dBm0 0 to -78 dBm0 inclusively. Remote Energies range from inclusively. Index refers TheS[index] defined as “00” = voice; “01” = transition; “10” = silence; “11” = - to S State is -The S State is defined as ‘00’=voice; ‘01’=transition - maintain the status of the last reserved. non-transitional packet; ‘10’=silence; ‘11’=reserved. Typical Silence Suppression State Table: 0 dBm0 Transition Voice Local Energy silent2.cdd -48 dBm0 Silence -78 dBm0 -48 dBm0 Remote Energy 0 dBm0 Figure 52 - Complex Silent Suppression Configurable State Graph 2.9.3.1 Complex Silent Suppression Operation 2.9.3.1.1 PCM Law Table PCM A-law and µ-law translation is supported by MT90502 on a per channel basis. For RX PCM channel, input law (from recieved CPS packet) and output law (sent on TDM bus) are controlled through RX TDM Control Memory Structures as shown in Figure 29, “RX Channel Association Memory (RX CAM),” on page 57. For TX PCM channels, law translation is configured in PCM Law Table located at 1000h-11FEh. 85 MT90502 b15 b14 1000h 1002h b13 b12 b11 b10 b9 b8 b7 b6 ch[0] ch[4] ... b5 b4 ch[1] ch[5] ... Preliminary Datasheet b3 b2 ch[2] ch[6] ... b1 b0 ch[3] ch[7] ... ch[x]: Law translation for TX PCM channel number X. 00 - µ-law to µ-law 01 - µ-law to A-law 10 - A-law to µ-law 11 - No translation Figure 53 - PCM Law Table 2.9.3.1.2 DC Offset Calculation The DC component is calculated in both remote and local voice PCM bytes. The MT90502 is able to perform an accumulation of the PCM linear values over a number of PCM samples (see Local and Remote DC Offset Figure 61 on page 91) in the reception direction. Accumulation of DC offset is enabled only when CPS-Packet Assembly Structure is in DC Calculation state. After obtaining DC offsets a short while after a call begins, the CPU is then required to change the Assembly Structure to Transition state, and write the DC Offset Correction into the Structure. After that, the Structure can be configured to Suppression state where suppression circuit is activated. No silence is suppressed in either DC calculation state or Transition state. 2.9.3.1.3 Signal Energy Calculation To obtain the signal energy, the linear PCM value with consideration of the DC offset correction is squared. The MT90502 sums all the byte energy values contained in a CPS-Packet and divides the result by the length of the CPS-Packet to obtain an average energy per byte. Then the MT90502 calculates the linear energy value into its decibel value. The same process is employed with ADPCM; however, an external CODEC is required to convert the ADPCM to PCM. ADPCM silent suppression TDM streams are associated in groups of 4: for example, the ADPCM channel in transmission is mapped on stream 3, while the local PCM channel is mapped on stream 0, the ADPCM reception channel is mapped on stream 2, and the remote PCM channel on stream 1 (see Figure 54 and Figure 55). Complex Silence Suppression TDM Channel Mapping ct_c8 ct_frame ct_d[0] ct_d[1] ct_d[2] ct_d[3] Local PCM Byte Remote PCM Byte Local ADPCM Nibble ct_c8 ct_frame ct_d[0] ct_d[1] Local PCM Byte Remote PCM Byte Figure 54 - Complex Silent Suppression Stream Configuration 86 Preliminary Datasheet MT90502 Tx PCM CT_D[0] UTOPIA Tx PCM CODEC Tx ADPCM Rx ADPCM CT_D[3] MT90502 CT_D[2] Rx PCM Rx PCM CT_D[1] Figure 55 - ADPCM Complex Silent Suppression Stream Configuration 2.9.3.2 CPS-Packet Silence State The procedure is identical for both remote and local channels, as the silence suppression function requires information for both local and remote CPS-Packet mean values to consult the State Graph (see Figure 52) and determine the CPS-Packet status. Therefore, a channel on which complex silence suppression is enabled must have its transmit and receive direction streams mapped on consecutive stream and the same time slot (e.g. see Figure 54, “Complex Silent Suppression Stream Configuration,” on page 86). For example, the transmission stream(odd) 17, time slot 4 the associated reception stream is reception stream(even) 16 time slot 4. 2.9.3.2.1 Silence Suppression State Table To determine a CPS-Packet status (i.e. voice, transitional & silence), the TX TDM will reference the local and remote decibel energy levels in external memory. The table contains 2-bit values indicating a combination of local and remote energy levels. Note the Silent State Graph as shown in Figure 52. The Silence Suppression State Table (4KB) is located in the variable structures of TX SSRAM determined by the ‘Table Offset[20:12]’ field in the CPS-Packet Final Assembly Structure (see Figure 63). The MT90502 can accommodate a different State Table for as many as 512 channels, as different channels may exhibit different line characteristics. The Table Offset field in the CPS-Packet Final Assembly Structure (shown in Figure 63) points to the base address of the Silence Suppression State Table for the associated channel. 2.9.3.2.2 SID Transmission Operation After the transmission of an SID, subsequent silent CPS-Packets are suppressed. However, the UUI sequence count is maintained. Therefore the reception device can determine the number of CPS-Packets suppressed. Upon the detection of silence the first suppressed CPS-Packet will be replaced by an SID packet and will contain the Local Energy determined by the CPS-Packet Assembly Structure, without consideration of the Local Energy Correction. Further SID CPS-Packets will be transmitted if the Local Energy is less than 3dB of the last transmitted SID energy level. Therefore, the energy level transmitted may gradually reduced over the silent period. The ratio of silent packets to total CPS-Packets can be determined by consulting the CPS-Packet Final Assembly Structure, SID Count and CPS-Packet Count fields (see Figure 62 and Figure 63). 2.9.3.2.3 SID Reception Operation In the reception direction, SID CPS-Packets are employed to insert silent/comfort noise in Rx direction. The MT90502 is required to compensate for suppressed CPS-Packets employing the CPS-Packet loss compensation algorithm in the RX SAR (see Section 2.4.4, CPS-Packet Loss Compensation on page 52). 87 MT90502 Preliminary Datasheet Therefore, it is a requirement to enable the CPS-Packet Loss Compensation employing the UUI sequence number counter in silence suppression mode. When the RX SAR receives an SID CPS-Packet and in the CPS-Packet Disassembly Structure (see Figure 24 on page 47), LI0 field is configured for Silent Suppression the SID value will identify the Silent/Tone Buffer Number by referencing the SID Byte to Silence Buffer Structure (see Figure 56 on page 88). The SID energy level is mapped to the Silent/Tone Buffer Number in internal memory 1400h to 15FEh. For each SID byte, the Silence/Tone Buffer Number is stored in the SID Byte to Silence Buffer memory location. Different silence buffers must be used depending on the compression type. There are 5 entries for each SID byte, one per compression type: • • • • • PCM 64kb/s ADPCM 40kb/s ADPCM 32kb/s ADPCM 24kb/s ADPCM 16kb/s b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1400h 1440h 1480h 14C0h 1500h SID Translation PCM (64 kbps) +00h Buffer no. when SID byte is 30 Buffer no. when SID byte is 31 SID Translation ADPCM (40 kbps) SID Translation ADPCM (32 kbps) SID Translation ADPCM (24 kbps) SID Translation ADPCM (16 kbps) +3Ch +3Eh +2Eh Buffer no. when SID byte is 76 Buffer no. when SID byte is 77 +30h Buffer no. when SID byte is 78 Buffer no. when SID byte is 79 Reserved Buffer no. for all other SIDs Reserved Buffer no. when SID byte 127 Buffer no.: 0 - 63 for 64 tone buffers in SSRAM; 64 - 95 for 32 silent buffers in SDRAM; 96 - 127 for 32 null bytes in internal memory; 128 for buffer number of previous SID packet. Figure 56 - SID Byte to Silence Buffer Structure The Silent/Tone Buffer Number is written to the ‘Tone Number to Insert’ field located in the RX TDM Control Memory Structure (see Figure 31 on page 59) which identifies the ‘Silent/Tone Buffers’ (e.g. Figure 57 on page 89) in either SSRAM, SDRAM or null byte insertion, for the associated channel. The contents of the ‘Silent/Tone Buffers’ is inserted on the channel in place of the TDM Circular Buffer. One byte from each silent noise buffer is read at the beginning of each frame and written into internal memory. Therefore a silent/tone value for each active silent channel is primed for the entire frame. The MT90502 can use up to 96 silent noise buffers. In addition, up to 32 null bytes can be used, augmenting the actual number of padding possibilities to 128. At the start of each frame, the MT90502 reads the address, size, and current read pointer of every silent noise buffer, and then reads the corresponding byte. It then updates the read pointer for the next frame and writes it back. 88 Preliminary Datasheet 2600h 2608h Silent/Tone Buffer 0-1 MT90502 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Silent/Tone Buffer 2-3 +0 +2 +4 Base Address of Tone/Silent Buffer Pair [20:6] Size of Tone/Silent buffer Pair Tone/Silent buffer Read Pointer [16;0] 26F0h 26F8h Silent/Tone Buffer 60-61 Silent/Tone Buffer 62-63 Reserved +6 Silent/Tone Buffer Control Memory structures are 8-bytes in size, located in internal memory at addresses 2600h to 26F8h. Base Address of Tone/Silent Buffer Pair: Points to a 64-byte boundary at which this silent buffer pair begins. Size of Tone/Silent Buffer Pair: Indicates the size of this silent buffer pair. 0000h = invalid (this pair is not used)., 0001h = 1byte (per pattern), FFFFh = 65535-bytes (per pattern). Because this controls the size of 2 buffers, a full-sized pair will occupy 128K-bytes. Tone/Silent buffer Read Pointer: Current Read Pointer to this silent buffer pair. This field must be set to 0 by software when initialised. Figure 57 - SSRAM Tone Buffer Control Memory b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 Even Tone Buffer Odd Tone Buffer Index given by Base Address of Tone/Silent Buffer Pair in SSRAM Tone Buffer Control memory (see Figure 57 -SSRAM Tone Buffer Control Memory). +N-1 Even Tone Buffer Odd Tone Buffer Figure 58 - Silent Tone Buffer Pair in TX SSRAM 32 null bytes are stored in two locations in internal Tone Data Buffer Memory. Both locations must have identical copies. Null-byte [0] Null-byte [1] Null-byte [0] Null-byte [1] 1360h 13E0h 137Eh Null-byte [30] Null-byte [31] 13FEh Null-byte [30] Null-byte [31] Figure 59 - Null Bytes in Tone Data Buffer Memory Buffer[0] ... Buffer[30] Buffer[0] ... Buffer[30] ... Buffer[0] ... Buffer[30] Buffer [1] ... Buffer[31] Buffer [1] ... Buffer[31] ... Buffer[1] ... Buffer[31] Byte [size - 1] ... Byte[1] Byte[0] Figure 60 - 32 SDRAM Silence Buffers 89 MT90502 2.9.4 Voice/Silence Timer Preliminary Datasheet When a PCM or ADPCM CPS-Packet is composed entirely of silent bytes, then it is tagged as being a silent CPS-Packet. It is then sent off to the CPS-Packet Final Assembly Structure to be treated. A silent CPS-Packet will not necessarily be discarded: the Final Assembly Structure contains 2 fields, the Voice to Silence Timer and the Silence to Voice Timer, which indicate how long a channel must be silent before it starts being suppressed, and how long a channel must be active before it starts being transmitted again. Usually, the Silence to Voice Timer is close to 0, so that voice is never cut off at the beginning of a talk spurt. However, the Voice to Silence Timer can be much longer, because it is not as important to start suppressing silence as soon as voice trails off: leaving a certain silent time makes the transition to silence suppression much smoother. Note that both Timers are defined in CPS-Packets, which is the most precision possible in this application. To improve the Silence to Voice transition, another field called the TX Delay adds a constant delay of 0 to 4 CPS-Packets to the transmission: in other words, when the system must transmit a new CPS-Packet, it will transmit the one from 2 CPS-Packets ago. Thus, by using a Silence to Voice Timer of 2 CPS-Packets and a TX Delay of 2 CPS-Packets, the Silence to Voice transition will have zero loss, while ensuring that small spikes of noise do not cause the system to believe that continuous voice is being transmitted. 90 Preliminary Datasheet MT90502 PCM/ADPCM CPS-Packet Assembly Structure (in Complex Silence Suppression Mode, dc calcuation state) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 +8 Local DC Off.[7:0] # EDU Comp 1 0 Sub Phase Local DC Offset[20:8] Remot DC Offset[20:8] Rem. DC Off.[7:0] Partial Byte Storage[7:1] 0 Phase PCM/ADPCM CPS-Packet Assembly Structure (in Complex Silence Suppression Mode, transition state) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 +8 # EDU Comp 0 1 Partial Byte Storage[7:1] 0 Sub Phase Phase PCM/ADPCM CPS-Packet Assembly Structure (in Complex Silence Suppression Mode, suppression state) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 +6 +8 Local Energy Mantissa[7:0] Remote Energy Mantissa[7:0] Local DC Correc.[7:0] # EDU Comp 1 1 Sub Phase Phase Local E. Exp[4:0] Remote E. Exp[4:0] Rem. DC Correc.[7:0] Partial Byte Storage[7:1] 0 Fields in Italic are used by Hardware only. Fields in Plain are written to by the CPU/Software. "00" state (addr+8[b9:b8]) is for simple silence suppression or no silence suppression. Structure shown in TDM Transmission section. LocalDC Offset / Remote DC Offset: Sum of all linear values of the PCM bytes received on the Local and Remote PCM channels (21-bits Twos-complement). This sum is sticky and will stay at -1048576 or 1048575 in case of overflow. Local DC Correction / Remote DC Correction: 8 bit twos-complement value used to remove DC offset to the Linear values before being used to calculate the energy of the Local and Remote signals. Local / Remote Energy Mantissa / Exponent : Field used by hardware to calculate the energy sum over a single packet. Exponent is defined as follows: “00001” = 1.0 to 1.99; “00010” = 2.0 to 4.98; etc. The highest bit of mantissa is always ‘1’. The units of this value is the square of the linearised PCM values inputs (-2047 to +2047). Reserved Figure 61 - Silent Suppression PCM/ADPCM CPS-Packet Assembly Structures 91 MT90502 CPS-Packet Final Assembly Structure (Simple Silence Suppression) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 +2 +4 S. to V. Timer +6 +8 +A +C +E SS Timer[8:0] SS VC Number[9:0] CID Seq I Pac Del Cnt [3:0] SUI Voice to SilenceTimer # EDU Send UUI[3:0] TX Delay Preliminary Datasheet : Silence to Voice Timer Time in CPS-Packets to change from silence to voice. 0 means all voice packets will be sent. : Voice to Silence Timer Time in CPS-Packets to change from voice to silence. 0 means all silent packets will not be sent. : TX Delay Delay in CPS-Packets that will be added by the Silence Suppression Algorithm to prevent loss of voice. Range is 0 to 4 CPS-packets. SS Timer: Silence State Timer. Increments when the suppression indication from the TDM bus is active during a whole CPS-Packet and the SS state is cleared, until Voice to Silence Timer is reached. Also increments when the suppression indication from the TDM bus is inactive for any byte in a whole CPS-Packet and the SS state is set, until Silence to Voice Timer is reached. Whenever neither of the previous conditions is met, this timer will reset to 0. When the state counter reaches the Silent to Voice Timer or Voice to Silent Timer, the SS bit will toggle thus the supression state will change. SS: Current Silence Suppression State. ‘0’ = send voice; ‘1’ = suppress. : CPS-Packet 0-3 Base Add base address of the start of the 4 previous CPSpackets in the TX Circular Buffer. 0 is most recent; 3 is oldest CPS-packet. Initialized to 00h at start-up by software. : SID Count Count of the number of SID CPS-Packets sent out. SID packets in this mode are only sent upon the transition from Voice to Silence. : CPS-Packet Byte Count Byte counter of all payload bytes sent (payload is defined as the LI+1 in each CPS-Packet sent). SID packets that are sent will count as one byte. SID packets that are not sent will be counted as 1 byte. : CPS-Packet Count CPS-Packet counter of all packets. All SID packets (might they have been sent or not) are counted in this field. +10 CPSP0 Base [7:3] CPSP0 Code CPSP1 Base [7:3] CPSP1Code MP0 Base Add[7:3] MP0 Code MP1 Base Add[7:3] MP1 Code +12 CPSP2 Base [7:3] CPSP2 Code CPSP3 Base [7:3] CPSP3Code MP2 Base Add[7:3] MP2 MP3 Base Add[7:3] MP3 Code +14 +16 +18 1A 1C 1E SID Count[31:16] SID Count[15:0] CPS-Packet Byte Count[31:16] CPS-Packet Byte Count[15:0] CPS-Packet Count[31:16] CPS-Packet Count[15:0] PS-Packet Final Assembly structures are located in TX SSRAM at ddresses +1000h to +1FE0h, +2000h to +3FE0h, +4000h to +7FE0h and 8000h to +FFE0h for 128, 256, 512 and 1023 channels repsectively. t ach structure is 32-bytes in size. ields in Italic are used by Hardware only. ields in Plain are written to by the CPU/Software. Figure 62 - CPS-Packet Final Assembly Structure (Simple Silence Suppression) 92 Preliminary Datasheet CP S -P acket Final Assem bly S tructure (Com plex S ilence S uppression) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 S eq I Pack D el Cnt[3:0] +0 VC Num ber[9:0] +2 +4 S . to V . Tim er +6 Recent P eriod +8 +A CID SUI V oice to SilenceTim er # of E DU Send UUI[3:0] TX Delay MT90502 Local E nergy Correction M ax Local E nergy(dB m0) Table Offset[20:12] Rem ote Energy Correction M ax Rem ote E nergy(dB m 0) Reserved +C Silent P adding E nergy(dBm 0) +E S S Timer[8:0] Recent M axim um Local E nergy S S G S S IS R ecent CP SP C nt +10 CPSP 0 Base Add[7:3] C PSP0 C ode CPS P1 Base A dd[7:3] CPSP1 C ode +12 CPSP 2 Base Add[7:3] CPSP2 Code CPS P3 Base A dd[7:3] CPSP3 C ode +14 +16 +18 +1A +1C +1E S ID Count[31:16] SID Count[15:0] C PS -P acket Byte Count[31:16] C PS -P acket Byte Count[15:0] C PS -P acket Count[31:16] CP S -P acket Count[15:0] Fields in Italic a re used by Hardware only. Fields in P lain are written to by the CPU /S oftware. CP S -P acket Final Assem bly structures are located in TX S S RAM at addresses +1000h to +1FE 0h, +2000h to +3FE 0h, +4000h to +7FE 0h and +8000h to +FFE 0h for 128, 256, 512 and 1023 channels repsectively. E ach structure is 32 bytes in size. CP S Px Code: “000” = PCM ; “001” = ADP CM 40; “010” = A DP CM 32; “011” = A DPCM 24; “100” = A DP CM 16; “101” = P CM byte m isaligned E DU;others = reserved. Recent P eriod: Num ber of CPS -P ackets on which the m axim um recent energy will be calculated. 0 m eans S ID energy is re-calculated on each CPS -P acket. 15 m eans that the SID energy is recalculated every 16 packets. : Table O ffset[20:12] A bsolute position of the S ilence Suppression State Table in the TX SS RA M to be used with this channel. : Local E nerg y Correction / Rem ote E nerg y Correction S igned two’s com pletem ent offset added to the Local/Rem ote E nergies before indexing into the Table. This value is in dB . A value of 1 m eans a signal of -10 dB will be interpreted as -11 dB . M inim um value is -78 dB , Maxim um value is 49 dB. : M ax Local / Rem ote Energ y M axim um Local / Rem ote E nergy M onitored by hardware of a single CPS -P acket. 0 m eans 0 dBm 0. 78 m eans -78 dBm 0. Can be cleared by software to m onitor over short periods. Recent C PSP Cnt, Silent P adding E nergy & Recent M axim um Local E nergy C ounter used to know when a new S ID energy value has been obtained. This counter will increm ent until it m atches the Recent P eriod field. Then it will be cleared. The CPS -P acket sent when this field is read and m atches the Recent Period will be included in the Recent M axim um Local E nergy calculation . U pon reading a R ecent CPSP Cnt at 0, the field Recent M axim um Local Energy will be ignored (assum ed to be -78 dB ). The S ilent P adding Energy will be set to the M axim um Local Energy upon term inal count when the resulting SS state is voice. W hen resulting SS state is silence, this operation is only perform ed when it will augum ent the value of the S ilent Padding Energy (i.e. m ake the S ilent P adding Energy m ore quiet). In this case, a S ID CP S-Packet will be sent. W hen the first S ID is sent, the E nergy in the S ID is the sam e as the one written back in the S ilent Padding E nergy. G S : Graph S tate. ‘0’ = No voice suppression; ‘1’ = S uppress voice. S S Tim er: Silence State Tim er. Increm ents when the Graph state and the SS bit are not equal, until Voice to Silence Tim er or S ilence to V oice tim er are reached. W henever the previous condition is not m et, this tim er will reset to 0. W hen the state counter reaches the Silent to Voice Tim er or V oice to Silent Tim er, the S S bit will toggle thus the supression state will change. S IS S id In S torage. W hen ‘1’, indicates that a S ID packet would have been generated last tim e had the phase allowed it. This m eans a S ID packet will be generated this tim e if the channel is deem ed to rem ain silent. Figure 63 - CPS-Packet Final Assembly Structure (Complex Silence Suppression) 93 MT90502 2.10 HDLC 2.10.1 HDLC Overview Preliminary Datasheet HDLC data format accommodates data that needs a larger bandwidth than PCM. Any number from 1 to 128 consecutive time slots on a single H.100/H.110 stream can carry data as one HDLC stream thus allowing a higher data transfer rate. Note that an HDLC stream must be contained within one frame and TX and RX HDLC streams carrying the same channel do not have to be of the same length. 2.10.2 HDLC Format The MT90502 can accept or generate an HDLC header that contains 0, 1, or 2 address bytes, as well as a possible control byte that follows the flag. There is also an optional 16-bit CRC that may be added at the end of the packet. The different formats are illustrated in Figure 64 on page 95. The formats are specified for each stream using the “Header Type” and “CRC” fields in the HDLC CPS-Packet Assembly Structure (see Figure 13 on page 33 and Figure 14 on page 34). When using HDLC streams, the low byte of the address is used to select the channel number. All address bytes that are not used to indicate a channel number are discarded by the TX TDM module. The payload gamut of an HDLC CPS-Packet is 1 to 64-bytes. Data is accumulated until a flag is received signifying the end of an HDLC packet. The payload will be processed according to the HDLC type. The MT90502 supports 2 types of HDLC data over the TDM bus: bit-wide form and byte-wide form (registers 400h and 500h). Table 33, “HDLC Packet Formats and Header Types,” on page 96 shows the supported HDLC package formats with corresponding header types as shown in Figure 13. The CRC selection is also made according to Figure 13. Using packaing_type (500h bit-3) enables “Raw” AAL2 CPS-Packets to be sent, as described in Section 2.2.3.4. If there are not multiple HDLC channels in a HDLC stream then SCS will not be used and the address bytes will be discarded. If SCS is used then the address bytes will be used along with the HDLC stream number to calculate the HDLC channel number. 94 Preliminary Datasheet MT90502 Supported HDLC Packet Format (after zero extraction) 0 Byte Header & No CRC: 1 Byte Header & No CRC: 2 Byte Header & No CRC: 0 Byte Header & 2 Byte CRC: 1 Byte Header & 2 Byte CRC: 2 Byte Header & 2 Byte CRC: FLAG FLAG D0 H0 D1 D0 D2 D1 D3 D2 D4 D3 FLAG D4 FLAG FLAG FLAG FLAG H0 D0 H0 H1 D1 D0 D0 D2 D1 D1 D3 D2 D2 D4 D3 D3 CRC0 D4 D4 CRC1 CRC0 FLAG FLAG CRC1 FLAG FLAG H0 H1 D0 D1 D2 D3 D4 CRC0 CRC1 FLAG 1 Byte Header & Control & No CRC: 2 Byte Header & Control & No CRC: 1 Byte Header & Control & 2 Byte CRC: 2 Byte Header & Control & 2 Byte CRC: FLAG H0 Cntrl D0 D1 D2 D3 D4 FLAG FLAG H0 H1 Cntrl D0 D1 D2 D3 D4 FLAG FLAG H0 Cntrl D0 D1 D2 D3 D4 CRC0 CRC1 FLAG FLAG H0 H1 Cntrl D0 D1 D2 D3 D4 CRC0 CRC1 FLAG 2 Byte Header & Control & 2 Byte CRC with AAL2 Header: FLAG H0 H1 Cntrl CID LI/UUI UUI/HC D0 D1 D2 D3 D4 CRC0 CRC1 FLAG Note 1: 1: allall examples a 5 byte payload was used.was payload from 1 to 64 bytes could have been used. In In examples a 5-byte payload Any used. Any payload from 1-to 64-bytes could have been used. Note x x Note ote 2: CRC16 Polynomial : x16+x12+x5+1. At x5+1. At reset, the initial value of CRC is FFFFh and CRC is sent. N 2: CRC-16 Polynomial: 16+ 12+ reset, the initial value of CRC is FFFFh and CRC is XORedwith F0B8h before being X0Redwith FOB8h before being sent. CID/LI/UUI/HEC AAL2 header byte triplet can be used in conjuction with all HDLC encapculation formats from no HDLC header/no Note 3 : The Note 3: the CID/LI/UUI/HEC AAL2 header byte CRC. can be used in conjunction with all HDLC encapsulation formats from no HDLC CRC to the full 3 byte of HDLC header and 2 bytes of triplet HDLC header/no HDLC CRC to the full 3-byte of HDLC header and 2-bytes of CRC. hdlc1.cdd Figure 64 - Supported HDLC Formats 95 MT90502 Packet Format 0-Byte Header & No CRC 1-Byte Header & No CRC 2-Byte Header & No CRC 0-Byte Header & 2-Byte CRC 1-Byte Header & 2-Byte CRC 2-Byte Header & 2-Byte CRC 1-Byte Header & Control & No CRC 2-Byte Header & Control & No CRC 1-Byte Header & Control & 2-Byte CRC 2-Byte Header & Control & 2-Byte CRC 1-Byte Header & No CRC 2-Byte Header & No CRC 1-Byte Header & 2-Byte CRC 2-Byte Header & 2-Byte CRC 1-Byte Header & Control & No CRC 2-Byte Header & Control & No CRC 1-Byte Header & Control & 2-Byte CRC 2-Byte Header & Control & 2-Byte CRC 0-Byte Header & No CRC with AAL2 header 1-Byte Header & No CRC with AAL2 header 2-Byte Header & No CRC with AAL2 header 0-Byte Header & 2-Byte CRC with AAL2 header 1-Byte Header & 2-Byte CRC with AAL2 header 2-Byte Header & 2-Byte CRC with AAL2 header 1-Byte Header & Control & No CRC with AAL2 header 2-Byte Header & Control & No CRC with AAL2 header 1-Byte Header & Control & 2-Byte CRC with AAL2 header 2-Byte Header & Control & 2-Byte CRC 1-Byte Header & No CRC with AAL2 header 2-Byte Header & No CRC with AAL2 header 1-Byte Header & 2-Byte CRC with AAL2 header 2-Byte Header & 2-Byte CRC with AAL2 header 1-Byte Header & Control & No CRC with AAL2 header 2-Byte Header & Control & No CRC with AAL2 header 1-Byte Header & Control & 2-Byte CRC with AAL2 header 2-Byte Header & Control & 2-Byte CRC with AAL2 header Header Type 0000 0001 0010 0000 0001 0010 0011 0100 0011 0100 0101 0110 0101 0110 0111 1000 0111 1000 0000 0001 0010 0000 0001 0010 0011 0100 0011 0100 0101 0110 0101 0110 0111 1000 0111 1000 CRC 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SCS No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Preliminary Datasheet 500h [3] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address Data Discarded Discarded Discarded Discarded Discarded Discarded Discarded Discarded Used Used Used Used Used Used Used Used Discarded Discarded Discarded Discarded Discarded Discarded Discarded Discarded Used Used Used Used Used Used Used Used Table 33 - HDLC Packet Formats and Header Types 96 Preliminary Datasheet 2.10.3 HDLC Bit-Wise Format MT90502 Bit-wise means that every bit of HDLC data coming from the H.100/H.110 bus is examined. A control flag of 7Eh ("01111110") is used to signify the start and end of a packet. When using this form of HDLC, each HDLC packet must begin with a flag and end with a flag, although a single flag may represent both the end of a packet and the beginning of another. A '0' is inserted after every 5 '1's of incoming data (called zero insertion) to differentiate the control flag and data. If neither flags nor data are being transmitted onto the bus, the idle code is transmitted. The idle code is an endless string of '1's. Note that a valid idle code must be at least 7-bits long (7 '1's). 2.10.4 HDLC Byte-Wise Format Byte-wise HDLC format also employs "01111110" (7Eh) as a control flag. A 7Eh payload value is replaced by two bytes - 7Dh and 5Eh, while a 7Dh payload value is replaced by two bytes - 7Dh and 5Dh. A single flag may represent both the end of a packet and the beginning of another. This flag is put into the TX circular buffer with the data. When no data is being transmitted onto the bus, the flag character is sent repeatedly until data is transmitted again. 2.11 Memory 2.11.1 Memory Map The location of the absolute starting and ending addresses of the internal and external memories are shown in Table 34. The complete set of internal registers is listed in Section 3, “Register List,” on page 107. The beginning and ending addresses of the various structure spaces in SSRAM and SDRAM are listed in Section 2.11.2, “Memory Structures,” on page 98. Start Address 0100h 0200h 0300h 0400h 0500h 0600h 0700h 0800h 0900h 1000h 1300h 1400h 2000h 2100h 2200h 2300h 2400h 2600h End Address 01FEh 02FEh 03FEh 04FEh 05FEh 06FEh 07FEh 08FEh 09FEh 11FEh 13FEh 15FEh 20FEh 21FEh 22FEh 23FEh 24FEh 26FEh Name cpureg mainreg txreg rxreg txtdmreg utoreg h100reg miscreg rxtdmreg PCM Law Table Tone Data Buffer Memory SID Byte to Silence Buffer Memory TX SAR Input FIFO AAL0 Input FIFO UTOPIA Port A Input FIFO UTOPIA Port B Input FIFO UTOPIA Port C Input FIFO Tone Buffer Control Memory Table 34 - MT90502 Memory Map 97 MT90502 Start Address 2800h 2C00h 3000h 4000h 6000h 8000h C000h 10000h 400000h 600000h 2000000h 3000000h End Address 2BFEh 2FFEh 3FFEh 5FFEh 7FFEh BFFEh FFFEh 103FEh 4FFFFEh 7FFFFEh 2FFFFFEh 3FFFFFEh Name Preliminary Datasheet UTOPIA Port A Output FIFO UTOPIA Port B Output FIFO RX SAR Output FIFO TX Channel Association Memory RX Channel Association Memory TX TDM Control Memory RX TDM Control Memory UTOPIA Port C Output FIFO SSRAM bank A SSRAM bank B SDRAM bank A SDRAM bank B Table 34 - MT90502 Memory Map (continued) 2.11.2 Memory Structures There are two types of memory structures in the MT90502: fixed structures and variable structures. Fixed structures are of a defined size and base address, and are mapped according to the sar_capacity register field (register 240h), which determines the total channel capacity of the MT90502. The one exception is the RX Circular Buffers, whose size is determined by the rx_circular_buffer_size field (register 240h). The size of variable structures can be configured individually in registers. When two memory banks exist, TX memory employs memory controller A and memory interface pins A, while RX memory uses memory controller B and memory interface pins B. When one memory bank exists, only memory controller A and memory interface pins A are used. TX SSRAM fixed structures are (with sizes in bytes for 128, 256, 512, and 1023 channels) • AAL2 VC structures (4K, 8K, 16K, 32K) • CPS-Packet Final Assembly structures (4K, 8K, 16K, 32K) • Cell Assembly Event Queue (512, 1K, 2K, 4K) • CPS-Packet Circular Buffers (32K, 64K, 128K, 256K) TX SSRAM variable structures are • Clock Recovery Point Buffers (2 buffers the same size, either 4K, 8K, 16K, 32K, 64K, or 128 KB each) • SSRAM Silence Buffers (up to 64, each pair can have a length of 0 to 64 KB per buffer) • Silent Suppression Look-up Tables RX SSRAM fixed structures are (with sizes in bytes for 128, 256, 512, and 1023 channels) • AAL2 VC structures (16K, 32K, 64K, 128K) • CPS-Packet Descriptor Queue (8K, 16K, 32K, 64K) • CPS-Packet Disassembly structures (4K, 8K, 16K, 32K) • CPS-Packet Descriptor Queue Pointers (512, 1K, 2K, 4K) • CPS-Packet Circular Buffers (1 for each channel, all the same size 256, 512, or 1K bytes). RX SSRAM variable structures are • Data (AALO) cell FIFO (one FIFO: 4K, 8K, 16K, 32K, 64K, or 128K bytes) • Error Report structure FIFO (one FIFO: 4K, 8K, 16K, 32K, 64K, or 128K bytes) • CPU CPS-Packet buffer (one buffer: 16K, 32K, 64K, or 128K bytes) TX SDRAM fixed structures are (with sizes in bytes for 128, 256, 512, and 1023 channels) 98 Preliminary Datasheet MT90502 • CPS-Packet Descriptor Queue (512K, 1M, 2M, 4M) TX SDRAM variable structures are • Look-Up Tables 1 (3 tables, each can have a size of 1M, 2M, 4M, or 8 MB) • SDRAM Silent Buffers (32 buffers the same size, either 0, 16K, 32K, or 64K bytes each) RX SDRAM fixed structures are (with sizes in bytes for 128, 256, 512, and 1023 channels) • RX CID table (1K, 2K, 4K, 8K) There are no variable RX SDRAM structures. 1. All three LUTs can have the same base address. The sizes and base addresses of the LUTs are determined in registers 620h, 640h, and 660h. 99 MT90502 TX SSRAM Memory Mapping Preliminary Datasheet 128 Channels + 000000h AAL2 VC Structures (128 Structures = 4K) (128 Structures = 4K) TX AAL2 VC Structures 256 Channels + 000000h AAL2 VC Structures (256 Structures = 8K) (256 Structures = 8K) TX AAL2 VC Structures + 000FE0h + 001000h CPS-Packet Mini-Packet Final Assembly Structures (128 Structures = 4K) + 001FE0h + 002000h CPS-Packet Mini-Packet Final Assembly Structures (256 Structures = 8K) + 001FE0h + 002000h + 003FF0h + 004000h Cell Assembly Event Queue (128 Events = 512B) Cell Assembly Event Queue (256 Events = 1K) + 0021F8h + 002200h + 0043F8h + 004400h + 0037FEh + 004000h CPS-Packet Mini-Packet Circular Buffers* (128 Buffers = 32K) + 007FFEh + 008000h CPS-Packet Mini-Packet Circular Buffers* (256 Buffers = 64K) + 00BF00h + 017F00h 512 Channels + 000000h + 000000h TX AAL2 VC Structures 1023 Channels 1024 Channels TX AAL2 VC Structures (1024 Structures = 32K) AAL2 VC Structures (512 Structures = 16K) (512 Structures = 16K) + 003FE0h + 004000h CPS-Packet Mini-Packet Final Assembly Structures (512 Structures = 16K) + 007FE0h + 008000h CPS-Packet Mini-Packet Final Assembly Structures (1024 Structures = 32K) + 007FF0h + 008000h + 00FFF0h + 010000h Cell Assembly Event Queue (512 Events = 2K) Cell Assembly Event Queue (1024 Events = 4K) + 0087F8h + 008800h + 010FF8h + 011000h + 00FFFEh + 010000h CPS-Packet Mini-Packet Circular Buffers* (512 Buffers = 128K) + 01FFFEh + 020000h CPS-Packet Mini-Packet Circular Buffers* (1024 Buffers = 256K) + 02FF00h + 05FF00h Reserved mapping1.cdd *Note that not all circular buffers have to be used. If memory is not available for certain circular buffers just don’t assign them. Figure 65 - TX SSRAM Memory Mapping for Fixed Structures 100 Preliminary Datasheet R X SSRAM Memory Mapping MT90502 128 Channels +000000h +003F80h +004000h +005FC0h +006000h +006F00h +007000h +0071FCh Mini-Packet Descriptors CPS-Packet Descriptor Queue (128 Structures == 8K) (128 Structures 8K) 256 Channels +000000h +007F80h +008000h +00BFC0h +00C000h +00DF00h +00E000h +00E3FCh Mini-Packet Descriptor CPS-Packet Descriptors Queue (256 Structures = 16K) (256 Structures = 16K) RX AAL2 VC Structures AAL2 VC Structures (128 Structures = 16K) RX AAL2 VC Structures AAL2 VC Structures (256 Structures = 32K) CPS-Packet Disassembly HDLC/PCM Disassembly Structures Structures (128 Structures = 4K) HDLC/PCM Disassembly Structures Structures (256 Structures = 8K) CPS-Packet Disassembly CPS-Packet Descriptor Queue Mini-packet queue pointers Pointers (128 Structures = 512B) (128 Structures = 512B) CPS-Packet Descriptor Mini-packet queue pointersQueue Pointers (256 Structures = 1K) (256 Structures = 1K) +008000h CPS-Packet Circular Buffers* Circular Buffers* (128 Buffers = 32K/128K) (128 Buffers = 32K/128K) +010000h CPS-Packet Circular Buffers* Circular Buffers* (256 Buffers = 64K/256K) (256 Buffers =642K/256K) +027C00h +04FC00h 512 Channels +000000h +00FF80h +010000h +017FC0h +018000h +01BF00h +01C000h +01C7FCh HDLC/PCM Disassembly CPS-Packet Disassembly Structures Structures (512 Structures = 16K) 1023 Channels 1024 Channels +000000h +01FF80h RX AAL2 VC Structures AAL2 VC Structures (512 Structures = 64K) CPS-Packet Descriptor Queue Mini-Packet Descriptors (512 Structures 32K) (512 Structures = = 32K) RX AAL2 VC Structures AAL2 VC Structures (1024 Structures = 128K) CPS-Packet Descriptors Queue Mini-Packet Descriptor (1024 Structures = 64K) (1024 Structures = 64K) CPS-Packet Disassembly HDLC/PCM Disassembly Structures Structures (1024 Structures = 32K) CPS-Packet Descriptor Mini-packet queue pointers Queue Pointers (1024 Structures = 4K) (1024 Structures = 4K) +020000h +02FFC0h +030000h +037F00h +038000h +038FFCh CPS-Packet Descriptor Queue Mini-packet queue pointers Pointers (512 Structures = 2K) (512 Structures = 2K) +020000h CPS-Packet Circular Buffers* Circular Buffers* (512 Buffers = 128K/512K) (512 Buffers = 128K/512K) +040000h (1024Circular Buffers* Buffers = 256K/1024K) (1024 Buffers = 256K/1024K) CPS-Packet Circular Buffers* +09FC00h +13FC00h *Note that not all circular buffers have to be used. If memory is not available for certain circular buffers just don’t assign them. Reserved Figure 66 - RX SSRAM Memory Mapping for Fixed Structures 101 MT90502 Two Banks 1023 Channels 000000h 000000h Preliminary Datasheet CPS-Packet Descriptor Queue Rx CID Structure 2MB 400000h 200000h SDRAM Silent Buffers 0B, 512KB, 1MB or 2MB 400000h+SSB Next x00000h LUT A, B & C 1MB, 2MB, 3MB........ 24MB One Bank 512 Channels 000000h 000000h Two Banks 512 Channels 000000h CPS-Packet Descriptor Queue CPS-Packet Descriptor Queue 200000h 100000h Rx CID Structures 1MB 200000h SDRAM Silent Buffers 0B, 512KB, 1MB or 2MB 200000h+SSB 200000h+SSB Next x00000h SDRAM Silent Buffers 0B, 512KB, 1MB or 2MB Rx CID Table 1MB 300000h+SSB LUT A, B & C 1MB, 2MB, 3MB........ 24MB Next x00000h LUT A, B & C The LUT start address is on the next available 1MB page. 1MB, 2MB, 3MB........ 24MB SSB = SDRAM Silent Buffer Figure 67 - SDRAM Memory Map for 512 & 1023 Channels 102 Preliminary Datasheet MT90502 Two Banks 256 Channels 000000h 000000h CPS-Packet Descriptor Queue 100000h 080000h SDRAM Silent Buffers 100000h+SSB Next x00000h 0B, 512KB, 1MB or 2MB Rx CID Structure 512KB One Bank 256 Channels 000000h CPS-Packet Descriptor Queue 100000h SDRAM Silent Buffers 0B, 512KB, 1MB or 2MB 100000h+SSB Rx CID Table 180000h+SSB Next x00000h 512KB LUT A, B & C 1MB, 2MB, 3MB........ 24MB LUT A, B & C 1MB, 2MB, 3MB........ 24MB Two Banks 128 Channels One Bank 128 Channels 000000h CPS-Packet Descriptor Queue 080000h SDRAM Silent Buffers 0B, 512KB, 1MB or 2MB 080000h+SSB Rx CID Table 0C0000h+SSB Next x00000h 256KB 080000h+SSB Next x00000h LUT A, B & C 1MB, 2MB, 3MB........ 24MB 080000h SDRAM Silent Buffers 0B, 512KB, 1MB or 2MB 000000h 000000h CPS-Packet Descriptor Queue 040000h Rx CID Structures 256KB LUT A, B & C 1MB, 2MB, 3MB........ 24MB The LUT start address is on the next available 1MB page. SSB = SDRAM Silent Buffer Figure 68 - SDRAM Memory Map for 128 and 256 Channels 2.11.3 Mem_Clk and Upclk The memory clock is supplied to the MT90502 by an external source. The memories are connected to an external clock source which also must be coupled to the MT90502’s mem_clk pin. A frequency of 60 MHz for mem_clk is recommended. Frequencies above 60 MHz will not increase performance, but will increase power consumption. At lower clock frequencies, the MT90502 may not be able to operate at its full SAR capacity. Upclk is used by CPU interface circuit. Its frequency should not be less than half of mem_clk. There is no relationship between upclk to mem_clk. 103 MT90502 2.11.4 Memory Controller 2.11.4.1 Overview Preliminary Datasheet The MT90502 uses up to 4 external SSRAM chips and 2 external SDRAM chips on 2 banks for its memory requirements. SSRAM chips can be 128KByte, 256KByte, 512KByte or 1MByte in size. The size of SDRAM chips is either 4Mx16 or 8Mx16. The address and data pins of the memories are shared on either bank (e.g. SDRAM A and SSRAM A share their pins). For applications of 512 channels or less, it is possible to use bank A only. Both banks must be used if sar_capacity is set to 1023. If only 1 bank is employed, TX SSRAM starts from the beginning of bank A, which is 400000h. RX SSRAM starts from rx_base_address programmed in register 242h. If using two banks, however, bank A is always TX SSRAM and bank B is RX SSRAM. A memory controller is used to multiplex the accesses required of these memories. This dual memory controller grants the memory bus to the various agents within the chip in order of urgency, using a priority algorithm, and transforms the memory accesses into the correct pin signals. 2.11.4.2 Functionality The memory controller is responsible for generating even parity on the parity pins of the memories and detecting that the parity is correctly received when reading data from the memory. The MT90502 calculates even parity on all address bits and data bits used to generate each access. When reading from the memory, it performs the same calculation in the opposite direction. Parity errors are reported to register 202h. To render parity generation and detection, configurable masks can be employed to calculate parity on certain bits (registers 230h, 232h and 234h). Parity is calculated on all locations in memory except for the RX circular buffers, in which the parity bits are used for underrun information. It is possible to override this and use parity on these circular buffers through control bits in register 230h. The controller ensures that the SDRAMs are refreshed often enough to avoid corrupt data. A limit (register 254h) exists for how many refresh periods behind the SDRAM can be before a status error is generated. SDRAM is configurable in registers 250h-25Ah. 2.11.5 Initializing SSRAM and SDRAM The SSRAM parity generation and checking can be configured by programming registers 230h mem_parity0, 232h mem_parity1 and 234h mem_parity2. The SSRAM sizes can be configured by programming registers 240h mem_conf0 and 242h mem_conf1 (not programmed if using bank B for RX). The SDRAM can be configured by a series of register writes. Pre-charge all the SDRAM banks, program the mode, perform a CBR refresh (twice), enable the SDRAM and then set the SDRAM for normal operation. 104 Preliminary Datasheet 2.11.6 Memory Configuration MT90502 SSRAM memory chips must be ZBT (zero-bus turnaround) and must be pipelined. SDRAM memory chip must have A12-A13 as bank select pins, A0-A11 as row address and A0-A7/A8 as column address. Typical application circuits for Bank A SSRAM and Bank A SDRAM are shown in Figure 69 on page 105 and Figure 70 on page 106. 60 MHz 60 MHz (optional) (optional) (optional) 64K/128K/256K/512K x 18 Figure 69 - Typical SSRAM Application Circuit 105 MT90502 60 MHz Preliminary Datasheet 60 MHz 4M/8M x 16 Figure 70 - Typical SDRAM Application Circuit 106 Preliminary Datasheet 3.0 3.1 MT90502 Register List CPU Register Address: 100h Label: control Reset Value: 0000 Label sreset Bit Position 0 Type RW Description Active low software reset. Resets the whole chip except the CPU interface. Once low, all registers will be cleared except for CPU registers and Main Registers. When '1', no caching will be done in the CPU Interface, thus guaranteeing a higher average access time, but a lower worst case access time. Reserved. Must always be “0000_0000_0000_0” Reserved. Must always be “0”. low_latency_cpu_accesses 1 RW reserved test_status 14:2 15 RW TS Table 35 - CPU Control Register Address: 102h Label: status0 Reset Value: 0000h Label reserved internal_read_timeout cpu_read_done Bit Position 2:0 3 4 Type Description ROL Reserved. Always read as “000” ROL Internal device time-out. Generally occurs when a clock is missing or misbehaving. ROL This bit is set when a burst of reads is completed. This bit may be used to generate an interrupt after a large read burst has completed (in indirection). For small read bursts, it is not very useful since there is not enough time for the CPU to do anything between the time it starts the read and the time that the read ends. ROL Reserved. Always read as “0000_0000_000” Table 36 - CPU Status Register reserved 15:5 Address: 104h Label: status0_ie Reset Value: 0000h Label reserved internal_read_timeout_ie cpu_read_done_ie reserved Bit Position 2:0 3 4 15:5 Type RO IE IE RO Description Reserved. Always read as “000” When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. Reserved. Always read as “0000_0000_000” Table 37 - CPU Interrupt Enable Register 107 MT90502 Address: 108h Label: mem_clk_freq Reset Value: 0000h Label reserved mem_clk_freq_integer reserved Bit Position 3:0 10:4 15:11 Type RO Reserved Preliminary Datasheet Description RW Frequency of mem_clk in MHz. RW Reserved. Must always be “0000” Table 38 - Mem_clk Frequency Control Register Address: 10Ah Label: upclk_freq Reset Value: 0000h Label reserved upclk_freq_integer reserved Bit Position 3:0 10:4 15:11 Type RO RW RW Reserved Frequency of upclk in MHz. Reserved. Must always be “0000” Description Table 39 - Upclk Frequency Control Register Address: 10Ch Label: led0 Reset Value: 007Fh Label led_flash_freq[8:0] led_test_mode reserved Bit Position 8:0 9 15:10 Type RW RW RW Description Determines the time in ms that the LEDs will be turned off to indicate link activity. If '0', the LED Flashing time will be determined in ms. If '1', the LED Flashing time will be determined in us. Reserved. Must always be “0000_00” Table 40 - LED Timing Control Register Address: 16Ch Label: fastclk_pll_conf0 Reset Value: 0642h Label reserved pll_div_x pll_div_y Bit Position 0 3:1 6:4 Type WO WO WO Description Reserved. Always read as “0” Selects the division of the reference before being fed to the PLL. The reference is either upclk or mem_clk. Selects the division of the feedback before being fed to the PLL. Table 41 - Fast Clock PLL Configuration Register 0 108 Preliminary Datasheet pll_bypass pll_source nreset_pll_async reserved reserved 7 8 9 10 15:11 WO WO WO WO WO MT90502 When '1', mem_clk or upclk are passed directly (without being divided) to fast_clk. 0' = upclk is PLL source; '1' = mem_clk is PLL source. Active low PLL nreset. This value resets the PLL's clock divisors. Reserved. Must write “1”. Reserved. Always read as “0000_0” Table 41 - Fast Clock PLL Configuration Register 0 (continued) Address: 172h Label: fastclk_pll_conf1 Reset Value: 09FCh Label pll_vcod pll_pd pll_div pll_syncen pll_chp reserved Bit Position 1:0 2 7:3 8 13:9 15:14 Type RW RW RW RW RW RW Description Output frequency range selection bits = “00” ‘0’ for normal operation. Power Down = ‘1’. Divider = “11111” Forces PLL into a clock synchronisation mode = ‘1’ Charge Pump settings = “01000” Reserved. Must always be “00” Table 42 - Fast Clock PLL Configuration Register 1 Address: 174h Label: h100pll_conf0 Reset Value: 07FEh Label H100pll_vcod H100pll_pd H100pll_div H100pll_syncen H100pll_chp reserved Bit Position 1:0 2 7:3 8 13:9 15:14 Type RW RW RW RW RW RW Description Output frequency range selection bits = “10” ‘0’ for normal operation. Power Down = ‘1’. Divider = “11111” Forces PLL into a clock synchronisation mode = ‘1’ Charge Pump settings = “00011” Reserved. Must always be “00” Table 43 - H100/H110 PLL Configuration Register 0 109 MT90502 Address: 17Eh Label: chip_and_revision Reset Value: 0101h Label chip_id[7:0] rev_id[7:0] Bit Position 7:0 15:8 Type RO RO Chip ID = 01h. Revision ID = 01h. Preliminary Datasheet Description Table 44 - ID Register 3.2 Main Registers Address: 202h Label: status0 Reset Value: 0000h Label mema_sdram_parity_error0 mema_sdram_parity_error1 memb_sdram_parity_error0 memb_sdram_parity_error1 mema_ssram_parity_error0 mema_ssram_parity_error1 memb_ssram_parity_error0 memb_ssram_parity_error1 memb_bad_cpu_access sdrama_too_late sdramb_too_late reserved Bit Position 0 1 2 3 4 5 6 7 8 9 10 15:11 Type ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL ROL Description Parity error on the high byte of bank A SDRAM. Parity error on the low byte of bank A SDRAM. Parity error on the high byte of bank B SDRAM. Parity error on the low byte of bank B SDRAM. Parity error on the high byte of bank A SSRAM. Parity error on the low byte of bank A SSRAM. Parity error on the high byte of bank B SSRAM. Parity error on the low byte of bank B SSRAM. Indicates that an access was attempted to bank B when the bank was not present. Indicates that bank A SDRAM cannot refresh quickly enough. Information in that memory may be corrupt. Indicates that bank B SDRAM cannot refresh quickly enough. Information in that memory may be corrupt. Reserved. Always read as “0000_0” Table 45 - Main Status Register 110 Preliminary Datasheet Address: 204h Label: status0_ie Reset Value: 0000h Label mema_sdram_parity_error0_ie mema_sdram_parity_error1_ie memb_sdram_parity_error0_ie memb_sdram_parity_error1_ie mema_ssram_parity_error0_ie mema_ssram_parity_error1_ie memb_ssram_parity_error0_ie memb_ssram_parity_error1_ie memb_bad_cpu_access_ie sdrama_too_late_ie sdramb_too_late_ie reserved 2 3 4 5 6 7 8 9 10 15:11 Bit Position Type 0 1 IE IE IE IE IE IE IE IE IE IE IE RO Description MT90502 When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. Reserved. Always read as “0000_0” Table 46 - Main Interrupt Enable Register 111 MT90502 Address: 210h Label: interrupt_flags Reset Value: 0000h Label cpureg_interrupt_active mainreg_interrupt_active txreg_interrupt_active rxreg_interrupt_active txtdmreg_interrupt_active utoreg_interrupt_active h100reg_interrupt_active miscreg_interrupt_active rxtdmreg_interrupt_active aal0alarm_interrupt_active Bit Position 0 1 2 3 4 5 6 7 8 9 Type RO RO RO RO RO RO RO RO RO RO Preliminary Datasheet Description Indicates that the interrupt generated by this module is active. Indicates that the interrupt generated by this module is active. Indicates that the interrupt generated by this module is active. Indicates that the interrupt generated by this module is active. Indicates that the interrupt generated by this module is active. Indicates that the interrupt generated by this module is active. Indicates that the interrupt generated by this module is active. Indicates that the interrupt generated by this module is active. Indicates that the interrupt generated by this module is active. Set when RX AAL0 data cell FIFO is half full or a time-out occurs. Clear by writing ‘1’ to register 468h bit ‘0’ Set when the clock recovery buffer A or buffer B is half-full. Automatically cleared when both buffers are less than half full. Set when the Error/Event FIFO is half full or a time-out occurs. Clear by writing ‘1’ to register 468h bit ‘1’ Reserved. Always Read as “000” When written to '1', another interrupt will not be generates for the number of us indicated in reg 214h. clkrecovalarm_interrupt_active 10 RO erroralarm_interrupt_active reserved interrupt1_treated 11 14:12 15 RO RO PUL Table 47 - Interrupt Flag Register 112 Preliminary Datasheet Address: 214h Label: interrupt1_conf Reset Value: 0000h Label min_interrupt1_period interrupt1_polarity Bit Position 13:0 15:14 Type RW RW Description MT90502 Number of us between interrupts (minimum). When 0000h, these is no minimum interval between interrupts. Interrupt polarity and output enable. “00”=active low (open-collector); “01”=active high (open-collector); “10” = drive low; “11” = drive high. Table 48 - Minimum Interrupt Interval Register Address: 216h Label: interrupt2_conf Reset Value: 0000h Label reserved interrupt2_polarity Bit Position Type 13:0 15:14 Description RW Reserved. Must always be “0000_0000_0000_00” RW Interrupt polarity and output enable. “00”=active low (open-collector); “01”=active high (open-collector); “10” = drive low; “11” = drive high. Table 49 - Interrupt Polarity & O/P Enable Register Address: 218h Label: interrupt1_enable Reset Value: 0000h Label cpureg_interrupt1_enable mainreg_interrupt1_enable txreg_interrupt1_enable rxreg_interrupt1_enable txtdmreg_interrupt1_enable utoreg_interrupt1_enable h100reg_interrupt1_enable miscreg_interrupt1_enable Bit Position 0 1 2 3 4 5 6 7 Type RW RW RW RW RW RW RW RW Description When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. Table 50 - Interrupt 1 Enable Register 113 MT90502 rxtdmreg_interrupt1_enable aal0alarm_interrupt1_enable clkrecovalarm_interrupt1_enabl e erroralarm_interrupt1_enable reserved 8 9 10 11 15:12 RW RW RW RW RW Preliminary Datasheet When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt1 will be active. Reserved. Must always be “0000” Table 50 - Interrupt 1 Enable Register (continued) Address: 21Ah Label: interrupt2_enable Reset Value: 0000h Label cpureg_interrupt2_enable mainreg_interrupt2_enable txreg_interrupt2_enable rxreg_interrupt2_enable txtdmreg_interrupt2_enable utoreg_interrupt2_enable h100reg_interrupt2_enable miscreg_interrupt2_enable rxtdmreg_interrupt2_enable aal0alarm_interrupt2_enable clkrecovalarm_interrupt2_enable erroralarm_interrupt2_enable reserved Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 15:12 Type RW RW RW RW RW RW RW RW RW RW RW RW RW Description When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. When '1' and the corresponding active bit in reg 210h is active, interrupt2 will be active. Reserved. Must always be “0000” Table 51 - Interrupt 2 Enable Register 114 Preliminary Datasheet Address: 220h Label: txa_clk_gen Reset Value: 0403h Label txa_clk_div[5:0] Bit Position 5:0 Type RW Description MT90502 txa_clk clock source division value. The txa_clk clock source (selected using txa_clk_src) can be divided before being sent out on UTOPIA. Note that odd values will force the duty cycle to be maintained, rather than returning it to 50-50. txa_clk_divisor_load_now 6 PUL This bit, when written to '1', will force the new txa_clk_div to be applied immediately (possibly causing glitches on the txa_clk). This bit should only be set to one when loading the divisor when the txa_clk_present bit is cleared. Note that it is possible to dynamically change the divisor value without causing glitches on the output clock if this bit is not written to 1. txa_clk_inv txa_clk_src[2:0] 7 10:8 RW RW When '1', the txa_clk's source will be inverted before being driven out on the txa_clk pin. “000” =txa_clk_in; “001” =txb_clk_in; ”010”=txc_clk_in; “011”=rxa_clk_in; “100” =rxb_clk_in; “101”=rxc_clk_in; “110”=mem_clk; others=reserved. txa_clk output enable. Active high. Set to '1' when the txa_clk is present. If the user does not want to use the txa UTOPIA interface, this bit should be left at '0' regardless of the presence of the txa_clk. When '0', will reset the clock division. Reserved. Must always be “00” txa_clk_oe txa_clk_present 11 12 RW RW txa_clk_divisor_reset reserved 13 15:14 RW RW Table 52 - Tx A Clock Division Register 115 MT90502 Address: 222h Label: txb_clk_gen Reset Value: 0403h Label txb_clk_div[5:0] Bit Position 5:0 Type Preliminary Datasheet Description RW txb_clk clock source division value. The txb_clk clock source (selected using txb_clk_src) can be divided before being sent out on UTOPIA. Note that odd values will force the duty cycle to be maintained, rather than returning it to 50-50. PUL This bit, when written to '1', will force the new txb_clk_div to be applied immediately (possibly causing glitches on the txb_clk). This bit should only be set to one when loading the divisor when the txb_clk_present bit is cleared. Note that it is possible to dynamically change the divisor value without causing glitches on the output clock if this bit is not written to 1. RW When '1', the txb_clk's source will be inverted before being driven out on the txb_clk pin. RW “000”=txa_clk_in; “001” =txb_clk_in; “010”=txc_clk_in; “011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in; “110”=mem_clk; others=reserved. RW txb_clk output enable. Active high. RW Set to '1' when the txb_clk is present. If the user does not want to use the txa UTOPIA interface, this bit should be left at '0' regardless of the presence of the txb_clk. RW When '0', will reset the clock division. RW Reserved. Must always be “00” txb_clk_divisor_load_now 6 txb_clk_inv txb_clk_src[2:0] 7 10:8 txb_clk_oe txb_clk_present 11 12 txb_clk_divisor_reset reserved 13 15:14 Table 53 - Tx B Clock Division Register 116 Preliminary Datasheet Address: 224h Label: txc_clk_gen Reset Value: 0403h Label txc_clk_div[5:0] Bit Position 5:0 Type RW Description MT90502 txc_clk clock source division value. The txc_clk clock source (selected using txc_clk_src) can be divided before being sent out on UTOPIA. Note that odd values will force the duty cycle to be maintained, rather than returning it to 50-50. This bit, when written to '1', will force the new txc_clk_div to be applied immediately (possibly causing glitches on the txc_clk). This bit should only be set to one when loading the divisor when the txc_clk_present bit is cleared. Note that it is possible to dynamically change the divisor value without causing glitches on the output clock if this bit is not written to 1. txc_clk_divisor_load_now 6 PUL txc_clk_inv txc_clk_src[2:0] 7 10:8 RW RW When '1', the txc_clk's source will be inverted before being driven out on the txc_clk pin. “000”=txa_clk_in; “001”=txb_clk_in; ”010”=txc_clk_in; “011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in; “110”=mem_clk; others = reserved. txc_clk output enable. Active high. Set to '1' when the txc_clk is present. If the user does not want to use the txa UTOPIA interface, this bit should be left at '0' regardless of the presence of the txc_clk. When '0', will reset the clock division. Reserved. Must always be “00” txc_clk_oe txc_clk_present 11 12 RW RW txc_clk_divisor_reset reserved 13 15:14 RW RW Table 54 - Tx C Clock Division Register 117 MT90502 Address: 228h Label: rxa_clk_gen Reset Value: 0403h Label rxa_clk_div[5:0] Bit Position Type 5:0 Preliminary Datasheet Description RW rxa_clk clock source division value. The rxa_clk clock source (selected using rxa_clk_src) can be divided before being sent out on UTOPIA. Note that odd values will force the duty cycle to be maintained, rather than returning it to 50-50. PUL This bit, when written to '1', will force the new rxa_clk_div to be applied immediately (possibly causing glitches on the rxa_clk). This bit should only be set to one when loading the divisor when the rxa_clk_present bit is cleared. Note that it is possible to dynamically change the divisor value without causing glitches on the output clock if this bit is not written to 1. rxa_clk_divisor_load_now 6 rxa_clk_inv rxa_clk_src[2:0] 7 10:8 RW When '1', the rxa_clk's source will be inverted before being driven out on the rxa_clk pin. RW “000”=txa_clk_in; “001”=txb_clk_in; “010”=txc_clk_in; “011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in; “110”=mem_clk; others=reserved. RW rxa_clk output enable. Active high. RW Set to '1' when the rxa_clk is present. If the user does not want to use the txa UTOPIA interface, this bit should be left at '0' regardless of the presence of the rxa_clk. RW When '0', will reset the clock division. RW Reserved. Must always be “00” rxa_clk_oe rxa_clk_present 11 12 rxa_clk_divisor_reset reserved 13 15:14 Table 55 - Rx A Clock Division Register 118 Preliminary Datasheet Address: 22Ah Label: rxb_clk_gen Reset Value: 0403h Label rxb_clk_div[5:0] Bit Position 5:0 Type RW Description MT90502 rxb_clk clock source division value. The rxb_clk clock source (selected using rxb_clk_src) can be divided before being sent out on UTOPIA. Note that odd values will force the duty cycle to be maintained, rather than returning it to 50-50. This bit, when written to '1', will force the new rxb_clk_div to be applied immediately (possibly causing glitches on the rxb_clk). This bit should only be set to one when loading the divisor when the rxb_clk_present bit is cleared. Note that it is possible to dynamically change the divisor value without causing glitches on the output clock if this bit is not written to 1. rxb_clk_divisor_load_now 6 PUL rxb_clk_inv rxb_clk_src[2:0] 7 10:8 RW RW When '1', the rxb_clk's source will be inverted before being driven out on the rxb_clk pin. “000”=txa_clk_in; “001”=txb_clk_in; “010”=txc_clk_in; “011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in; “110”=mem_clk; others=reserved. rxb_clk output enable. Active high. Set to '1' when the rxb_clk is present. If the user does not want to use the txa UTOPIA interface, this bit should be left at '0' regardless of the presence of the rxb_clk. When '0', will reset the clock division. Reserved. Must always be “00” rxb_clk_oe rxb_clk_present 11 12 RW RW rxb_clk_divisor_reset reserved 13 15:14 RW RW Table 56 - Rx B Clock Division Register 119 MT90502 Address: 22Ch Label: rxc_clk_gen Reset Value: 0403h Label rxc_clk_div[5:0] Bit Position 5:0 Type RW Preliminary Datasheet Description rxc_clk clock source division value. The rxc_clk clock source (selected using rxc_clk_src) can be divided before being sent out on UTOPIA. Note that odd values will force the duty cycle to be maintained, rather than returning it to 50-50. This bit, when written to '1', will force the new rxc_clk_div to be applied immediately (possibly causing glitches on the rxc_clk). This bit should only be set to one when loading the divisor when the rxc_clk_present bit is cleared. Note that it is possible to dynamically change the divisor value without causing glitches on the output clock if this bit is not written to 1. rxc_clk_divisor_load_now 6 PUL rxc_clk_inv rxc_clk_src[2:0] 7 10:8 RW RW When '1', the rxc_clk's source will be inverted before being driven out on the rxc_clk pin. “000”=txa_clk_in; “001”=txb_clk_in; “010”=txc_clk_in; “011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in; “110”=mem_clk; others = reserved. rxc_clk output enable. Active high. Set to '1' when the rxc_clk is present. If the user does not want to use the txa UTOPIA interface, this bit should be left at '0' regardless of the presence of the rxc_clk. When '0', will reset the clock division. Reserved. Must always be “00” rxc_clk_oe rxc_clk_present 11 12 RW RW rxc_clk_divisor_reset reserved 13 15:14 RW RW Table 57 - Rx C Clock Division Register 120 Preliminary Datasheet Address: 230h Label: mem_parity0 Reset Value: 0000h Label mema_parity_conf[1:0] Bit Type Position 1:0 Description MT90502 RW Selects how the parity bits of memory bank A are used (either as data bits or as parity bits). They should be set to “11” to allow correct Underrun detection in the RX TDM control memory. '0' = parity bits; '1' = user data. RW Selects how the parity bits of memory bank B are used (either as data bits or as parity bits). They should be set to “11” to allow correct Underrun detection in the RX TDM control memory. '0' = parity bits; '1' = user data. RW 1' = automatic parity calculation/checking on CPU accesses; '0' = CPU parity on CPU accesses (read and writes). RO Reserved. Always read as “00” RW The data bits whose corresponding bit is set to '1' in this vector will be used in parity calculation to the external memory. memb_parity_conf[1:0] 3:2 cpu_parity_conf 4 reserved mem_parity_generation_data_mask 7:5 15:8 Table 58 - Memory Parity Register 0 Address: 232h Label: mem_parity1 Reset Value: 0000h Label mem_parity_generation_add_mask[22:16] Bit Type Position 6:0 Description RW The address bits whose corresponding bit is set to '1' in this vector will be used in parity calculation to the external memory. RW Reserved. Must always be “0000_0000_0” reserved 15:7 Table 59 - Memory Parity Register 1 Address: 234h Label: mem_parity2 Reset Value: 0000h Label mem_parity_generation_add_mask[15:0] Bit Position Type 15:0 Description RW The address bits whose corresponding bit is set to '1' in this vector will be used in parity calculation to the external memory. Table 60 - Memory Parity Register 2 121 MT90502 Address: 240h Label: mem_conf0 Reset Value: 0075h Label mema_add_lines memb_add_lines sar_capacity rx_circular_buffer_size Bit Position Type 1:0 3:2 5:4 7:6 RW RW RW RW Preliminary Datasheet Description “11” = 1 Mb per chip; “10” = 512 Kb per chip; “01” = 256Kb per chip; “00” = 128 Kb per chip “11” = 1 Mb per chip; “10” = 512 Kb per chip; “01” = 256Kb per chip; “00” = 128 Kb per chip “00”=128 channels; “01”=256 channels; “10”=512 channels; “11”=1023 channel. Indicates the size of the RX Circular Buffers in external memory. They can be set locally to 256, 512, 1024 bytes. “00”= reserved;”01”=256 bytes; “10”=512 bytes; “11”=1024 bytes. Indicates if memory bank B is present or not. '0' = memb bank absent; '1' = memb bank present. Reserved. Must always be “0000_000” memb_bank_present reserved 8 15:9 RW RW Table 61 - Memory Configuration Register 0 Address: 242h Label: mem_conf1 Reset Value: 0000h Label rx_base_address reserved Bit Position 7:0 15:8 Type RW RW Description Base address of the RX SSRAM in Bank A. Specified in increments of 8K bytes. Not used if bank B is present. Reserved. Must always be “0000_0000” Table 62 - Memory Configuration Register 1 122 Preliminary Datasheet Address: 250h Label: sdram_conf0 Reset Value: 0000h Label sdrama_enable sdramb_enable sdrama_manual_access Bit Position 0 1 2 Type RW RW PUL Description MT90502 When '0', the values placed in the sdram_conf3 register will be placed on the SDRAM A pins. When '0', the values placed in the sdram_conf3 register will be placed on the SDRAM B pins. When written to 1 and sdrama_enable is '0', the values placed in the sdram_conf4 register will be placed on the SDRAM A pins. When written to 1 and sdramb_enable is '0', the values placed in the sdram_conf4 register will be placed on the SDRAM B pins. 0' = 4M x 16 (8 Megabytes), '1' = 8M x 16 (16 Megabytes) 0' = 4M x 16 (8 Megabytes), '1' = 8M x 16 (16 Megabytes) “00” = 1 refresh every 16 cycles, “01” = 1 refresh every 8 cycles, “10” = 1 refresh every 4 cycles. Typical value “00”. Reserved. Must always be “0000_0000”. sdramb_manual_access 3 PUL sdrama_size sdramb_size sdram_refresh_freq reserved 4 5 7:6 15:8 RW RW RW RW Table 63 - SDRAM Configuration Register 0 Address: 252h Label: sdram_conf1 Reset Value: 0400h Label sdram_refresh_cnt Bit Position 15:0 Type RW Description Number of mem_clk cycles per refresh to the SDRAM. Table 64 - SDRAM Configuration Register 1 Address: 254h Label: sdram_conf2 Reset Value: 0200h Label sdram_max_lateness Bit Position 15:0 Type Description RW Maximum number of refreshes that the SDRAM can be late before reporting an error. Table 65 - SDRAM Configuration Register 2 123 MT90502 Address: 256h Label: sdram_conf3 Reset Value: 0000h Label sdram_add_idle reserved Bit Position 13:0 15:14 Type Preliminary Datasheet Description RW While sdram_enable is '0', the value placed in this register will be put on the address lines. RW Reserved. Must always be “00” Table 66 - SDRAM Configuration Register 3 Address: 258h Label: sdram_conf4 Reset Value: 0000h Label sdram_add_man Bit Position 13:0 Type RW Description While sdram_enable is '0', the value placed in this register will be put on the address lines for 1 cycle if sdram_manual_access is written to '1'. Reserved. Must always be “00” reserved 15:14 RW Table 67 - SDRAM Configuration Register 4 Address: 25Ah Label: sdram_conf5 Reset Value: 003Fh Label sdram_cas_idle sdram_ras_idle sdram_we_idle sdram_cas_man Bit Position 0 1 2 3 Type RW RW RW RW Description While sdram_enable is '0', the value placed in this register will be put on the cas line. While sdram_enable is '0', the value placed in this register will be put on the ras line. While sdram_enable is '0', the value placed in this register will be put on the we line. While sdram_enable is '0', the value placed in this register will be put on the cas line for 1 cycle if sdram_manual_access is written to '1'. While sdram_enable is '0', the value placed in this register will be put on the ras line for 1 cycle if sdram_manual_access is written to '1'. While sdram_enable is '0', the value placed in this register will be put on the we line for 1 cycle if sdram_manual_access is written to '1'. Reserved. Must always be “0000_0000_00” sdram_ras_man 4 RW sdram_we_man 5 RW reserved 15:6 RW Table 68 - SDRAM Configuration Register 5 124 Preliminary Datasheet 3.3 TX Registers MT90502 Address: 300h Label: control Reset Value: 0000h Label scanning_enable aal0_cell_written reserved test_status Bit Position 0 1 14:2 15 Type RW Description When '1', the cell time-out scanning process is enabled and will send cells beyond a certain pending time (programmed per VC). PUL Written to '1' after an AAL0 cell has been written by the CPU to the TX AAL0 Cell FIFO. The cell will then be automatically sent. RW TS Reserved. Must always be “0000_0000_0000_0” Reserved. Must always be “0”. Table 69 - TX Control Register Address: 302h Label: status0 Reset Value: 0000h Label aal0_cell_fifo_empty reserved Bit Position 0 15:1 Type ROL ROL Description When '1', CPU can write another 4 AAL0 cells to internal FIFO Reserved. Always read as “0000_0000_0000_000” Table 70 - TX Status Register Address: 304h Label: status0_ie Reset Value: 0000h Label aal0_cell_fifo_empty_ie reserved Bit Position 0 15:1 Type IE RO Description When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. Reserved. Always read as “0000_0000_0000_000” Table 71 - TX Interrupt Enable Register Address: 310h Label: aal0_monitor Reset Value: 0000h Label aal0_cell_write_ok reserved Bit Position 0 15:1 Type RO RO Description When '1', CPU can write another AAL0 cell to internal FIFO Reserved. Always read as “0000_0000_0000_000” Table 72 - TX AAL0 Monitor Register 125 MT90502 3.4 RX Registers Preliminary Datasheet Address: 400h Label: control Reset Value: 0000h Label hdlc_type packaging_type nibble_mode reserved test_status Bit Position 0 1 2 14:3 15 Type RW RW RW RW TS Description ‘0'=Bit wide HDLC Framing; '1'=Byte Wide HDLC Framing. ‘0' = no AAL2 Header in HDLC Data Field; '1' = Raw AAL2 CPS-Packet in HDLC Data Field ‘0' = High bits used for ADPCM nibble, '1' = low bits used for ADPCM nibble Reserved. Must Always be “0000_0000_0000” Reserved. Must always be “0”. Table 73 - RX Control Register Address: 402h Label: status0 Reset Value: 0000h Label cpu_buffer_overflow aal0_overflow error_overflow reserved Bit Position 0 1 2 15:3 Type ROL ROL ROL ROL Description CPU Destined CPS-Packet Buffer Overflow. Overflow in the receive AAL0 cell buffer. Overflow in the error/event structure buffer. Reserved. Always read as “0000_0000_0000_0” Table 74 - RX Status Register Address: 404h Label: status0_ie Reset Value: 0000h Label cpu_buffer_overflow_ie aal0_overflow_ie error_overflow_ie reserved Bit Position 0 1 2 15:3 Type IE IE IE RO Description When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. Reserved. Always read as “0000_0000_0000_0” Table 75 - RX Interrupt Enable Register 126 Preliminary Datasheet Address: 410h Label: silent_pattern_reg Reset Value: 00FFh Label write_back_pattern Bit Position 7:0 Type RW Description MT90502 PCM Silent pattern written back to RX circular buffers by RX TDM module (only if enabled in PCM RX Control Memory structure) Reserved. Must always be “0000_0000” reserved 15:8 RW Table 76 - PCM Silent Pattern Register Address: 428h Label: crc_config0 Reset Value: FFFFh Label crc_preset Bit Position 15:0 Type RW Description HDLC CRC Preset. Must be “1111_1111_1111_1111” for ITU compliance. Table 77 - CRC Configuration Register 0 Address: 42Ah Label: crc_config1 Reset Value: F0B8h Label crc_mask Bit Position 15:0 Type RW Description HDLC CRC End Mask. Must be “1111_0000_1011_1000” for ITU compliance. Table 78 - CRC Configuration Register 1 Address: 430h Label: aal0_manage Reset Value: 0000h Label rx_aal0_base_add rx_aal0_buf_size reserved Bit Position 8:0 11:9 15:12 Type RW RW RW Description Represents bits 20:12 of the byte address at which the AAL0 data cell FIFO is mapped. “000” = 4KByte, “001” = 8KB, “010” = 16KB, “011” = 32KB, “100” = 64KB, “101” = 128KB, others = reserved Reserved. Must always be “0000” Table 79 - AAL0 FIFO Management Register 127 MT90502 Address: 432h Label: aal0_read Reset Value: 0000h Label rx_aal0_rpnt Bit Position 11:0 Type RW Preliminary Datasheet Description The CPU's read pointer to the AAL0 data cell FIFO. This read pointer has an extra bit to allow for a full buffer (for example, 128 cells instead of 127) Reserved. Must always be “0000” reserved 15:12 RW Table 80 - AAL0 Read Pointer Register Address: 434h Label: aal0_write Reset Value: 0000h Label rx_aal0_wpnt Bit Position 11:0 Type RO Description The hardware's write pointer to the AAL0 data cell FIFO. This write pointer has an extra bit to allow for a full buffer (for example, 128 cells instead of 127) Reserved. Always read as “0000” reserved 15:12 RO Table 81 - AAL0 Write Pointer Register Address: 438h Label: error_manage Reset Value: 0000h Label error_base_add error_buf_size reserved Bit Position 8:0 11:9 15:12 Type RW RW RW Description Represents bits 20:12 of the byte address at which the error structure buffer is mapped. “000” = 4KByte, “001” = 8KB, “010” = 16KB, “011” = 32KB, “100” = 64KB, “101” = 128KB, others = reserved Reserved. Must always be “0000” Table 82 - Error Management Register Address: 43Ah Label: error_write Reset Value: 0000h Label error_wpnt Bit Position 14:0 Type RO Description The chip's write pointer to the error structure buffer. This write pointer has an extra bit to allow for a full buffer (for example, 1024 structures instead of 1023) Reserved. Always read as “0” reserved 15 RO Table 83 - Error Write Pointer Register 128 Preliminary Datasheet Address: 43Ch Label: error_readure Reset Value: 0000h Label error_rpnt Bit Position 14:0 Type RW Description MT90502 The CPU's read pointer to the error structure buffer. This read pointer has an extra bit to allow for a full buffer (for example, 1024 structures instead of 1023) Reserved. Must always be “0” reserved 15 RW Table 84 - Error Read Pointer Register Address: 440h Label: cpu_manage0 Reset Value: 0000h Label cpu_cpsp_base_add cpu_cpsp_buf_size reserved Bit Position 6:0 8:7 15:9 Type RW RW RW Description Bits 20:14 of the byte address at which the CPU-destined CPS-Packet buffer is mapped. “00” = 16KByte, “01” = 32KB, “10” = 64KB, “11” = 128KB Reserved. Must always be “0000_000” Table 85 - CPU Management Register 0 Address: 442h Label: cpu_manage1 Reset Value: 0000h Label cpu_cpsp_rpnt Bit Position 15:0 Type RW Description Word read pointer to the CPU-destined CPS-Packet buffer Table 86 - CPU Management Register 1 Address: 460h Label: aal0_timeout_period_high Reset Value: 0000h Label aal0_timeout_period[19:16] reserved Bit Position 3:0 15:4 Type RW RW Description If an AAL0 cell remains in the buffer for the period in this register or more, an alarm will be generated. In us. Reserved. Must always be “0000_0000_0000” Table 87 - AAL0 Timeout Period (High Word) Register 129 MT90502 Address: 462h Label: aal0_timeout_period_low Reset Value: 0000h Label aal0_timeout_period[15:0] Bit Position 15:0 Type RW Preliminary Datasheet Description If an AAL0 cell remains in the buffer for the period in this register or more, an alarm will be generated. In us. Table 88 - AAL0 Timeout Period (Low Word) Register Address: 464h Label: error_timeout_period_high Reset Value: 0000h Label error_timeout_period[19:16] Bit Position 3:0 Type RW Description This timeout period applies both to error reporting structures as well as to CPU-destined CPS-Packets. In us. Reserved. Must always be “0000_0000_0000” reserved 15:4 RW Table 89 - Error Timeout Period (High Word) Register Address: 466h Label: error_timeout_period_low Reset Value: 0000h Label error_timeout_period[15:0] Bit Position 15:0 Type RW Description This timeout period applies both to error reporting structures as well as to CPU-destined CPS-Packets. In us. Table 90 - Error Timeout Period (Low Word) Register Address: 468h Label: pulse_register Reset Value: 0000h Label aal0_treated_pulse error_treated_pulse reserved Bit Position 0 1 15:2 Type PUL PUL PUL Description When the AAL0 buffer has been treated, write this bit to '1' to clear the alarm. When the error buffer has been treated, write this bit to '1' to clear the alarm. Reserved. Always read as “0000_0000_0000_00” Table 91 - AAL0 & Error Treated Register 130 Preliminary Datasheet 3.5 TX TDM Registers MT90502 Address: 500h Label: control Reset Value: 0000h Label nibble_mode hdlc_type reserved packaging_type llman_process_enable silent_bit_position u_law_zero_illegal reserved test_status Bit Position 0 1 2 3 4 7:5 8 14:9 15 Type RW RW RW RW RW RW RW RW TS Description 0' = High bits used for ADPCM nibble, '1' = low bits used for ADPCM nibble HDLC framing method. '0'=Bit wise HDLC Framing; '1'=Byte Wise HDLC Framing. Reserved. Must be “0”. 0' = AAL2 header not present in HDLC data field; '1' = AAL2 header present in HDLC data field. Enables the treatment of incoming TDM bytes from the H100 bus. Indicates the position of the simple silence bit in the associated odd stream. “000” = bit 7, “111” = bit 0 When '1', 00h in u-law will be replaced by 02h before it is placed on RX TDM bus. Reserved. Must always be “0000_0000_00” Reserved. Must always be “0”. Table 92 - TX TDM Control Register Address: 502h Label: status0 Reset Value: 0000h Label llman_process_crashed copying_out_of_bandwidth Bit Position 0 1 Type ROL ROL Description Indicates that the linked-list manager crashed. This indicates corrupt data in the linked list memory. Data copying process between the H.100 interface and the TX TDM was not fast enough. Indicates too low an mem_clk speed for the amount of TDM bandwidth. Means that the frame reading process that reads from the frame memory fell out of sync with the TDM bus. This error will occur naturally at startup. Received packet length on HDLC exceeded 64 bytes. TX SAR did not read data fast enough from circular buffer. Bad data integrity will ensue. CPS-Packet could not be written because all 512 descriptors for the VC were occupied. The 64 X 21 TX SAR write back cache overflow. frame_reading_out_of_bandwidth 2 ROL bad_packet_length circular_buffer_overflow cps_packet_refused_error txsar_wbcache_overflow 3 4 5 6 ROL ROL ROL ROL Table 93 - TDM TX Status Register 131 MT90502 txtdm_wcache_overflow packet_fifo_overflow misaligned_flag bad_idle_code short_packet dcoffset_overflow Reserved 7 8 9 10 11 12 15:13 ROL ROL ROL ROL ROL ROL ROL Preliminary Datasheet The 128 X 72 byte write cache overflow. The 1024 X 41 packet FIFO overflow. HDLC Packet got a misaligned flag (not aligned on a byte boundary) HDLC Packet got idle code in the middle of a packet! HDLC Packet was too short (0 data bytes!) DC offset value caused a linear value to be calculated as more than 4096 Reserved. Always read as “000” Table 93 - TDM TX Status Register (continued) 132 Preliminary Datasheet MT90502 Address: 504h Label: status0_ie Reset Value: 0000h Label llman_process_crashed_ie copying_out_of_bandwidth_ie frame_reading_out_of_bandwidth_ie bad_packet_length_ie circular_buffer_overflow_ie cps_packet_refused_error_ie txsar_wbcache_overflow_ie txtdm_wcache_overflow_ie packet_fifo_overflow_ie misaligned_flag_ie bad_idle_code_ie short_packet_ie dcoffset_overflow_ie Reserved Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 15:13 Type IE IE IE IE IE IE IE IE IE IE IE IE IE Description When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. RO Reserved. Always read as “000” Table 94 - TDM TX Interrupt Enable Register 133 MT90502 Address: 512h Label: silent_pattern_a Reset Value: FFFFh Label silent_bytea_match silent_bytea_mask Bit Position Type 7:0 15:8 Preliminary Datasheet Description RW Silent pattern detection match register A. When a received data byte matches the match and mask registers, it is tagged as silent. RW Silent pattern detection mask register A. When a received data byte matches the match and mask registers, it is tagged as silent. Table 95 - Silent Pattern Detection Match Register A Address: 514h Label: silent_pattern_b Reset Value: FFFFh Label silent_byteb_match silent_byteb_mask Bit Position Type 7:0 15:8 Description RW Silent pattern detection match register B. When a received data byte matches the match and mask registers, it is tagged as silent. RW Silent pattern detection mask register B. When a received data byte matches the match and mask registers, it is tagged as silent. Table 96 - Silent Pattern Detection Match Register B Address: 518h Label: tdm_pointer_monitor Reset Value: 0000h Label global_tdm_pointer Bit Position Type 15:0 Description RO Current value of the global TDM pointer. Table 97 - TDM Pointer Monitor Register Address: 520h Label: cpu_cps_packet0 Reset Value: 0000h Label cps_packet_cpu_vc_number cps_packet_cpu_request Bit Position Type 9:0 10 Description RW VC Number on which a CPU sourced CPS-Packet must be sent. PC Set to '1' by the CPU when a CPU Sourced CPS-Packet is pending transmission. Clear by hardware, when the CPS-Packet has been queue for transmission. PC Reserved. Always read as “0000_0” reserved 15:11 Table 98 - CPU CPS-Packet Register 0 134 Preliminary Datasheet Address: 522h Label: cpu_cps_packet1 Reset Value: 0000h Label cps_packet_cpu_descriptor[47:32] Bit Position 15:0 Type Description MT90502 RW CPU Sourced CPS-Packet Descriptor. Table 99 - CPU CPS-Packet Register 1 Address: 524h Label: cpu_cps_packet2 Reset Value: 0000h Label cps_packet_cpu_descriptor[31:16] Bit Position 15:0 Type Description RW CPU Sourced CPS-Packet Descriptor. Table 100 - CPU CPS-Packet Register 2 Address: 526h Label: cpu_cps_packet3 Reset Value: 0000h Label cps_packet_cpu_descriptor[15:0] Bit Type Position 15:0 Description RW CPU Sourced CPS-Packet Descriptor. Table 101 - CPU CPS-Packet Register 3 135 MT90502 3.6 UTOPIA Registers Preliminary Datasheet Address: 600h Label: control Reset Value: 0000h Label rxa_ena rxb_ena rxc_ena porta_sar_mode portb_sar_mode portc_sar_mode porta_level2_mode Bit Position Type 0 1 2 3 4 5 6 Description RW 0' = RXA Disabled; '1' = RXA Operates Normally. RW 0' = RXB Disabled; '1' = RXB Operates Normally. RW 0' = RXC Disabled; '1' = RXC Operates Normally. RW Puts TXA/RXA in PHY or SAR mode. '1'=PHY Mode; '0'=SAR Mode. RW Puts TXB/RXB in PHY or SAR mode. '1'=PHY Mode; '0'=SAR Mode. RW Puts TXC/RXC in PHY or SAR mode. '1'=PHY Mode; '0'=SAR Mode. RW Puts TXA/RXA in UTOPIA Level 2 mode. This disables port B and requires port A to be configured as PHY. '0' = Level 1; '1' = Level 2. RW 0' = only drive when selected; '1' = always drive DAT/PAR/SOC pins. RW 0' = only drive when selected; '1' = always drive DAT/PAR/SOC pins. RW 0' = only drive when selected; '1' = always drive DAT/PAR/SOC pins. RW When '0', tx_clav/tx_enb pins are in tri-state. RW Reserved. Must always be “0000” TS Reserved. Must always be “0”. txa_always_drive_dat_soc_par txb_always_drive_dat_soc_par txc_always_drive_dat_soc_par clav_enb_oe reserved test_status 7 8 9 10 14:11 15 Table 102 - UTOPIA Control Register 1 136 Preliminary Datasheet Address: 602h Label: status0 Reset Value: 0000h Label phy_alarma phy_alarmb rx_cell_loss outa_cell_loss outb_cell_loss outc_cell_loss cell_loss_rollover tx_arr_rollover rx_dep_rollover ia_arr_rollover oa_dep_rollover ib_arr_rollover ob_dep_rollover ic_arr_rollover oc_dep_rollover aal0_arr_rollover Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type Description MT90502 ROL PHY alarm detected on port A ROL PHY alarm detected on port B ROL Cell loss in RX SAR output FIFO ROL Cell loss in port A output FIFO ROL Cell loss in port B output FIFO ROL Cell loss in port C output FIFO CRL Cell loss counter has wrapped CRL Counter of cells received from TX SAR has wrapped CRL Counter of cells sent to RX SAR has wrapped CRL Counter of cells received from port A has wrapped CRL Counter of cells sent to port A has wrapped CRL Counter of cells received from port B has wrapped CRL Counter of cells sent to port B has wrapped CRL Counter of cells received from port C has wrapped CRL Counter of cells sent to port C has wrapped CRL Counter of cells received from AAL0 input FIFO has wrapped Table 103 - UTOPIA Status Register 0 137 MT90502 Address: 604h Label: status0_ie Reset Value: 0000h Label phy_alarma_ie phy_alarmb_ie rx_cell_loss_ie outa_cell_loss_ie outb_cell_loss_ie outc_cell_loss_ie cell_loss_rollover_ie tx_arr_rollover_ie rx_dep_rollover_ie ia_arr_rollover_ie oa_dep_rollover_ie ib_arr_rollover_ie ob_dep_rollover_ie ic_arr_rollover_ie oc_dep_rollover_ie aal0_arr_rollover_ie Bit Position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type IE IE IE IE IE IE IE IE IE IE IE IE IE IE IE IE Preliminary Datasheet Description When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. Table 104 - UTOPIA Interrupt Enable Register 0 138 Preliminary Datasheet Address: 60Ah Label: status2 Reset Value: 0000h Label reserved rxa_parity_error rxb_parity_error rxc_parity_error reserved Bit Position 2:0 3 4 5 15:6 Type Description MT90502 ROL Reserved. Always read as “000” ROL Parity error on UTOPIA port A ROL Parity error on UTOPIA port B ROL Parity error on UTOPIA port C ROL Reserved. Always read as “0000_0000_00” Table 105 - UTOPIA Status Register 2 Address: 60Ch Label: status2_ie Reset Value: 0000h Label reserved rxa_parity_error_ie rxb_parity_error_ie rxc_parity_error_ie reserved Bit Position Type 2:0 3 4 5 15:6 RO Reserved. Always read as “000” IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. RO Reserved. Always read as “0000_0000_00” Table 106 - UTOPIA Interrupt Enable Register 2 Address: 60Eh Label: control2 Reset Value: 0000h Label rxa_null_elim rxb_null_elim rxc_null_elim phy_alarm_mode reserved Bit Type Position 1:0 3:2 5:4 7:6 15:8 Description Description RW Port A Null Cell Elimination. “00”=no Null-Cell Deletion; “01” = reserved; “10” = Delete Null-Cells (UNI); “11” = Delete Null-Cells (NNI). RW Port B Null Cell Elimination. “00”=no Null-Cell Deletion; “01” = reserved; “10” = Delete Null-Cells (UNI); “11” = Delete Null-Cells (NNI). RW Port C Null Cell Elimination. “00”=no Null-Cell Deletion; “01” = reserved; “10” = Delete Null-Cells (UNI); “11” = Delete Null-Cells (NNI). RW “00” = Never detect PHY Alarm; “01” = active-high signal; “10” = active-low signal; “11” = reserved. RW Reserved. Must always be “0000_0000” Table 107 - UTOPIA Control Register 2 139 MT90502 Address: 612h Label: cell_loss_counter Reset Value: 0000h Label cell_loss Bit Position 15:0 Type Preliminary Datasheet Description CNT Counter of the number of cells lost in all UTOPIA output FIFOs Table 108 - Lost Cells Counter Address: 614h Label: gpio0 Reset Value: 0000h Label phya_tx_led_conf phya_rx_led_conf phyb_tx_led_conf phyb_rx_led_conf phya_alm_input phyb_alm_input phya_tx_led_input phya_rx_led_input phyb_tx_led_input phyb_rx_led_input reserved Bit Position Type 1:0 3:2 5:4 7:6 8 9 10 11 12 13 15:14 Description RW “00”=Tri-state; “01” = used as LED; “10”=Drive Low; “11”=Drive high. RW “00”=Tri-state; “01” = used as LED; “10”=Drive Low; “11”=Drive high. RW “00”=Tri-state; “01” = used as LED; “10”=Drive Low; “11”=Drive high. RW “00”=Tri-state; “01” = used as LED; “10”=Drive Low; “11”=Drive high. RO Indicates if the PHY alarm on port A is currently active RO Indicates if the PHY alarm on port B is currently active RO Indicates if the TX LED on port A is currently active RO Indicates if the RX LED on port A is currently active RO Indicates if the TX LED on port B is currently active RO Indicates if the RX LED on port B is currently active RO Reserved. Always read as “00” Table 109 - General Purpose I/O Register 0 Address: 620h Label: porta_look_up_base Reset Value: 0000h Label luta_base luta_size reserved Bit Position Type 3:0 5:4 15:6 Description RW LUT Base address in megabytes. RW “00”=128K VC; “01”=256K VC; “10”=512K VC; “11”=1024K VC. RW Reserved. Must always be “0000_0000_00” Table 110 - Port A LUT Base Address Register 140 Preliminary Datasheet Address: 622h Label: porta_concatenation Reset Value: 0000h Label vci_na reserved Bit Position Type 4:0 15:5 Description MT90502 RW Number of VCI bits in look-up table. RW Reserved. Must always be “0000_0000_000” Table 111 - Port A VCI Bits in LUT Address: 624h Label: porta_vpi_match Reset Value: 0000h Label vpi_matcha Bit Position Type 11:0 Description RW For a cell from port A to be considered valid, any bits in its VPI whose corresponding bits in reg 626h are '1' must have the value contained in this register. RW Reserved. Must always be “0000” reserved 15:12 Table 112 - Port A VPI Match Register Address: 626h Label: porta_vpi_mask Reset Value: 0000h Label vpi_maska Bit Position Type 11:0 Description RW For a cell from port A to be considered valid, any bits in its VPI whose corresponding bits in this register are '1' must have the value contained in reg 624h. RW Reserved. Must always be “0000” Table 113 - Port A VPI Mask Register reserved 15:12 Address: 628h Label: porta_vci_match Reset Value: 0000h Label vci_matcha Bit Position Type 15:0 Description RW For a cell from port A to be considered valid, any bits in its VCI whose corresponding bits in reg 62Ah are '1' must have the value contained in this register. Table 114 - Port A VCI Match Register 141 MT90502 Address: 62Ah Label: porta_vci_mask Reset Value: 0000h Label vci_maska Bit Position Type 15:0 Description Preliminary Datasheet RW For a cell from port A to be considered valid, any bits in its VCI whose corresponding bits in this register are '1' must have the value contained in reg 628h. Table 115 - Port A VCI Mask Register Address: 62Ch Label: porta_overflow0 Reset Value: FFFFh Label ia_rx_cell_max ia_oa_cell_max ia_ob_cell_max reserved Bit Position Type 5:0 9:6 13:10 15:14 Description RW If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked. 3Fh = no backpressure RW If the cell fill of the port A output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked. Fh = no backpressure RW If the cell fill of the port B output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “00” Table 116 - Port A Overflow Register 0 Address: 62Eh Label: porta_overflow1 Reset Value: 000Fh Label ia_oc_cell_max reserved Bit Position Type 3:0 15:4 Description RW If the cell fill of the port C output FIFO becomes greater than this value, cells from the port A input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “0000_0000_0000” Table 117 - Port A Overflow Register 1 Address: 630h Label: porta_cell_arrival_high Reset Value: 0000h Label ia_arr[31:16] Bit Position Type 15:0 Description CNT Counter of the number of cells received from port A Table 118 - Port A Cell Arrival Counter (High Word) 142 Preliminary Datasheet Address: 632h Label: porta_cell_arrival_low Reset Value: 0000h Label ia_arr[15:0] Bit Position Type 15:0 Description MT90502 CNT Counter of the number of cells received from port A Table 119 - Port A Cell Arrival Counter (Low Word) Address: 634h Label: porta_cell_departure_high Reset Value: 0000h Label oa_dep[31:16] Bit Position 15:0 Type Description CNT Counter of the number of cells sent onto port A Table 120 - Port A Cell Departure Counter (High Word) Address: 636h Label: porta_cell_departure_low Reset Value: 0000h Label oa_dep[15:0] Bit Position 15:0 Type Description CNT Counter of the number of cells sent onto port A Table 121 - Port A Cell Departure Counter (Low Word) Address: 640h Label: portb_look_up_base Reset Value: 0000h Label lutb_base lutb_size reserved Bit Position 3:0 5:4 15:6 Type Description RW LUT Base address in megabytes. RW “00”=128K VC; “01”=256K VC; “10”=512K VC; “11”=1024K VC. RW Reserved. Must always be “0000_0000_00” Table 122 - Port B LUT Base Address Register Address: 642h Label: portb_concatenation Reset Value: 0000h Label Bit Position Type vci_nb reserved 4:0 15:5 RW Number of VCI bits in look-up table. RW Reserved. Must always be “0000_0000_000” Table 123 - Port B VCI Bits in LUT Description 143 MT90502 Address: 644h Label: portb_vpi_match Reset Value: 0000h Label vpi_matchb Bit Position 11:0 Type Preliminary Datasheet Description RW For a cell from port B to be considered valid, any bits in its VPI whose corresponding bits in reg 646h are '1' must have the value contained in this register. RW Reserved. Must always be “0000” Table 124 - Port B VPI Match Register reserved 15:12 Address: 646h Label: portb_vpi_mask Reset Value: 0000h Label vpi_maskb Bit Position 11:0 Type Description RW For a cell from port B to be considered valid, any bits in its VPI whose corresponding bits in this register are '1' must have the value contained in reg 644h. RW Reserved. Must always be “0000” Table 125 - Port B VPI Mask Register reserved 15:12 Address: 648h Label: portb_vci_match Reset Value: 0000h Label vci_matchb Bit Position 15:0 Type Description RW For a cell from port B to be considered valid, any bits in its VCI whose corresponding bits in reg 64Ah are '1' must have the value contained in this register. Table 126 - Port B VCI Match Register Address: 64Ah Label: portb_vci_mask Reset Value: 0000h Label vci_maskb Bit Position Type 15:0 Description RW For a cell from port B to be considered valid, any bits in its VCI whose corresponding bits in this register are '1' must have the value contained in reg 648h. Table 127 - Port B VCI Mask Register 144 Preliminary Datasheet Address: 64Ch Label: portb_overflow0 Reset Value: 1108h Label ib_rx_cell_max Bit Position Type 5:0 Description MT90502 RW If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked. 3Fh = no backpressure RW If the cell fill of the port A output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked. Fh = no backpressure RW If the cell fill of the port B output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “00” Table 128 - Port B Overflow Register 0 ib_oa_cell_max 9:6 ib_ob_cell_max 13:10 reserved 15:14 Address: 64Eh Label: portb_overflow1 Reset Value: 004h Label ib_oc_cell_max Bit Position Type 3:0 Description RW If the cell fill of the port C output FIFO becomes greater than this value, cells from the port B input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “0000_0000_0000” Table 129 - Port B Overflow Register 1 reserved 15:4 Address: 650h Label: portb_cell_arrival_high Reset Value: 0000h Label ib_arr[31:16] Bit Position Type 15:0 Description CNT Counter of the number of cells received from port B Table 130 - Port B Cell Arrival Counter (High Word) Address: 652h Label: portb_cell_arrival_low Reset Value: 0000h Label ib_arr[15:0] Bit Position Type 15:0 Description CNT Counter of the number of cells received from port B Table 131 - Port B Cell Arrival Counter (Low Word) 145 MT90502 Address: 654h Label: portb_cell_departure_high Reset Value: 0000h Label ob_dep[31:16] Bit Position Type 15:0 Preliminary Datasheet Description CNT Counter of the number of cells sent onto port B Table 132 - Port B Cell Departure Counter (High Word) Address: 656h Label: portb_cell_departure_low Reset Value: 0000h Label ob_dep[15:0] Bit Position Type 15:0 Description CNT Counter of the number of cells sent onto port B Table 133 - Port B Cell Departure Counter (Low Word) Address: 660h Label: portc_look_up_base Reset Value: 0000h Label lutc_base lutc_size reserved Bit Position Type 3:0 5:4 15:6 Description RW LUT Base address in megabytes. RW “00”=128K VC; “01”=256K VC; “10”=512K VC; “11”=1024K VC. RW Reserved. Must always be “0000_0000_00” Table 134 - Port C LUT Base Address Register Address: 662h Label: portc_concatenation Reset Value: 0000h Label vci_nc reserved Bit Position Type 4:0 15:5 Description RW Number of VCI bits in look-up table. RW Reserved. Must always be “0000_0000_000” Table 135 - Port C VCI Bits in LUT Address: 664h Label: portc_vpi_match Reset Value: 0000h Label vpi_matchc Bit Position Type 11:0 Description RW For a cell from port C to be considered valid, any bits in its VPI whose corresponding bits in reg 666h are '1' must have the value contained in this register. RW Reserved. Must always be “0000” reserved 15:12 Table 136 - Port C VPI Match Register 146 Preliminary Datasheet Address: 666h Label: portc_vpi_mask Reset Value: 0000h Label vpi_maskc Bit Position Type 11:0 Description MT90502 RW For a cell from port C to be considered valid, any bits in its VPI whose corresponding bits in this register are '1' must have the value contained in reg 664h. RW Reserved. Must always be “0000” reserved 15:12 Table 137 - Port C VPI Mask Register Address: 668h Label: portc_vci_match Reset Value: 0000h Label vci_matchc Bit Position Type 15:0 Description RW For a cell from port C to be considered valid, any bits in its VCI whose corresponding bits in reg 66Ah are '1' must have the value contained in this register. Table 138 - Port C VCI Match Register Address: 66Ah Label: portc_vci_mask Reset Value: 0000h Label vci_maskc Bit Position Type 15:0 Description RW For a cell from port C to be considered valid, any bits in its VCI whose corresponding bits in this register are '1' must have the value contained in reg 668h. Table 139 - Port C VCI Mask Register Address: 66Ch Label: portc_overflow0 Reset Value: 1108h Label ic_rx_cell_max Bit Position Type 5:0 Description RW If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the port C input FIFO will be blocked. 3Fh = no backpressure RW If the cell fill of the port A output FIFO becomes greater than this value, cells from the port C input FIFO will be blocked. Fh = no backpressure RW If the cell fill of the port B output FIFO becomes greater than this value, cells from the port C input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “00” Table 140 - Port C Overflow Register 0 ic_oa_cell_max ic_ob_cell_max reserved 9:6 13:10 15:14 147 MT90502 Address: 66Eh Label: portc_overflow1 Reset Value: 004h Label ic_oc_cell_max reserved Bit Position Type 3:0 15:4 Preliminary Datasheet Description RW If the cell fill of the port C output FIFO becomes greater than this value, cells from the port C input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “0000_0000_0000” Table 141 - Port C Overflow Register 1 Address: 670h Label: portc_cell_arrival_high Reset Value: 0000h Label ic_arr[31:16] Bit Position Type 15:0 Description CNT Counter of the number of cells received from port C Table 142 - Port C Cell Arrival Counter (High Word) Address: 672h Label: portc_cell_arrival_low Reset Value: 0000h Label ic_arr[15:0] Bit Position Type 15:0 Description CNT Counter of the number of cells received from port C Table 143 - Port C Cell Arrival Counter (Low Word) Address: 674h Label: portc_cell_departure_high Reset Value: 0000h Label oc_dep[31:16] Bit Position Type 15:0 Description CNT Counter of the number of cells sent onto port C Table 144 - Port C Cell Departure Counter (High Word) Address: 676h Label: portc_cell_departure_low Reset Value: 0000h Label oc_dep[15:0] Bit Position Type 15:0 Description CNT Counter of the number of cells sent onto port C Table 145 - Port C Cell Departure Counter (Low Word) 148 Preliminary Datasheet Address: 680h Label: aal0_cell_arrival_high Reset Value: 0000h Label aal0_arr[31:16] Bit Position Type 15:0 Description MT90502 CNT Counter of the number of cells received from AAL0 FIFO Table 146 - AAL0 Cell Arrival Counter (High Word) Address: 682h Label: aal0_cell_arrival_low Reset Value: 0000h Label aal0_arr[15:0] Bit Position Type 15:0 Description CNT Counter of the number of cells received from AAL0 FIFO Table 147 - AAL0 Cell Arrival Counter (Low Word) Address: 688h Label: aal0_overflow0 Reset Value: 1108h Label aal0_rx_cell_max Bit Position Type 5:0 Description RW If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the AAL0 input FIFO will be blocked. 3Fh = no backpressure RW If the cell fill of the port A output FIFO becomes greater than this value, cells from the AAL0 input FIFO will be blocked. Fh = no backpressure RW If the cell fill of the port B output FIFO becomes greater than this value, cells from the AAL0 input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “00” aal0_oa_cell_max 9:6 aal0_ob_cell_max 13:10 reserved 15:14 Table 148 - AAL0 Overflow Register 0 Address: 68Ah Label: aal0_overflow1 Reset Value: 004h Label aal0_oc_cell_max Bit Position Type 3:0 Description RW If the cell fill of the port C output FIFO becomes greater than this value, cells from the AAL0 input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “0000_0000_0000” reserved 15:4 Table 149 - AAL0 Overflow Register 1 149 MT90502 Address: 690h Label: tx_sar_cell_arrival_high Reset Value: 0000h Label tx_arr[31:16] Bit Position Type 15:0 Preliminary Datasheet Description CNT Counter of the number of cells received from TX SAR Table 150 - TX_SAR Cell Arrival Counter (High Word) Address: 692h Label: tx_sar_cell_arrival_low Reset Value: 0001h Label tx_arr[15:0] Bit Position Type 15:0 Description CNT Counter of the number of cells received from TX SAR. It is 1 after reset. Table 151 - TX_SAR Cell Arrival Counter (Low Word) Address: 694h Label: rx_sar_cell_departure_high Reset Value: 0000h Label rx_dep[31:16] Bit Position Type 15:0 Description CNT Counter of the number of cells sent to RX SAR Table 152 - RX_SAR Cell Departure Counter (High Word) Address: 696h Label: rx_sar_cell_departure_low Reset Value: 0000h Label rx_dep[15:0] Bit Position Type 15:0 Description CNT Counter of the number of cells sent to RX SAR Table 153 - RX_SAR Cell Departure Counter (Low Word) Address: 698h Label: tx_sar_overflow0 Reset Value: 3F3Fh Label tx_rx_cell_max tx_oa_cell_max tx_ob_cell_max reserved Bit Position Type 5:0 9:6 13:10 15:14 Description RW If the cell fill of the RX SAR output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked. 3Fh = no backpressure RW If the cell fill of the port A output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked. Fh = no backpressure RW If the cell fill of the port B output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “00” Table 154 - TX_SAR Overflow Register 0 150 Preliminary Datasheet Address: 69Ah Label: tx_sar_overflow1 Reset Value: 000Fh Label tx_oc_cell_max reserved Bit Position Type 3:0 15:4 Description MT90502 RW If the cell fill of the port C output FIFO becomes greater than this value, cells from the TX SAR input FIFO will be blocked. Fh = no backpressure RW Reserved. Must always be “0000_0000_0000” Table 155 - TX_SAR Overflow Register 1 Address: 6A0h Label: porta_address Reset Value: 0000h Label porta_add reserved Bit Position Type 4:0 15:5 Description RW The address to which the chip will respond in UTOPIA level 2 addressing. RW Reserved. Must always be “0000_0000_000” Table 156 - Port A Address Register Address: 6A2h Label: hec_byte_control Reset Value: 0055h Label hec_mask reserved Bit Position Type 7:0 15:8 Description RW The value by which the HEC byte will be XORed before being transmitted. RW Reserved. Must always be “0000_0000” Table 157 - HEC Byte Control Register Address: 6A4h Label: unknown_header_routing Reset Value: 0000h Label rxa_ncr Bit Position Type 3:0 Description RW Routing of non-OAM cells from port A that fail the VPI-VCI match and mask test. “xxx1” = send to port A, “xx1x” = send to port B, “x1xx” = send to port C, “1xxx” = send to AAL0. RW Routing of non-OAM cells from port B that fail the VPI-VCI match and mask test. “xxx1” = send to port A, “xx1x” = send to port B, “x1xx” = send to port C, “1xxx” = send to AAL0. RW Routing of non-OAM cells from port C that fail the VPI-VCI match and mask test. “xxx1” = send to port A, “xx1x” = send to port B, “x1xx” = send to port C, “1xxx” = send to AAL0. RW Reserved. Must always be “0000” rxb_ncr 7:4 rxc_ncr 11:8 reserved 15:12 Table 158 - Unknown Header Routing Register 151 MT90502 Address: 6A6h Label: unknown_oam_routing Reset Value: 0000h Label rxa_ocr Bit Position Type 3:0 Preliminary Datasheet Description RW Routing of OAM cells from port A that fail the VPI-VCI match and mask test. “xxx1” = send to port A, “xx1x” = send to port B, “x1xx” = send to port C, “1xxx” = send to AAL0. RW Routing of OAM cells from port B that fail the VPI-VCI match and mask test. “xxx1” = send to port A, “xx1x” = send to port B, “x1xx” = send to port C, “1xxx” = send to AAL0. RW Routing of OAM cells from port C that fail the VPI-VCI match and mask test. “xxx1” = send to port A, “xx1x” = send to port B, “x1xx” = send to port C, “1xxx” = send to AAL0. RW Reserved. Must always be “0000” rxb_ocr 7:4 rxc_ocr 11:8 reserved 15:12 Table 159 - Unknown OAM Routing Register 3.7 H.100/H.110 Registers Address: 700h Label: control Reset Value: 0000h Label pll_clk_in_frequency global_oe number_of_active_streams h100_ct_c8_frame_loopback Bit Position Type 1:0 2 4:3 5 Description RW “00”= 8.192 MHz; “01”= 16.384 MHz; “10”= 32.768 MHz;”11”= 65.536 MHz. RW '0' = internal loopback (all OEs disabled); '1'=global OE enabled. RW “00”= 32 active streams; “01” = 16 active streams; “10” = 8 active streams; “11” = 4 active streams. RW When '1', the ct_c8_X and ct_frame_X are looped back internally, without the need of going out on the actual pins. '0' for normal operation. RW Each bit represents a quad of TDM streams. Bit 6 is quad 0. '0' = Format A; '1' = Format B. RW Reserved. Must always be '0'. TS Reserved. Must always be “0”. tdm_stream_format reserved test_status 13:6 14 15 Table 160 - H.100/H.110 Control Register 152 Preliminary Datasheet Address: 702h Label: status0 Reset Value: 0000h Label mem_clk_alarm0 MT90502 Bit Type Position 0 Description ROL Alarm that can be used to generate a programmable interval interrupt (me 9998888m_clk Alarm Timer 0). This bit is set when the mem_clk_count[31:16] matches the mem_clk_alarm0_count. Write a 1 to clear the bit. ROL Alarm that can be used to generate a programmable interval interrupt (mem_clk Alarm Timer 1). This bit is set when the mem_clk_count[31:16] matches the mem_clk_alarm1_count. Write a 1 to clear the bit. ROL When the ct_frame_a is considered bad by the hardware, this bit is set. The frame is considered bad if it is not low one cycle out of 1024. Write a 1 to clear the bit. ROL When the ct_frame_b is considered bad by the hardware, this bit is set. The frame is considered bad if it is not low one cycle out of 1024. Write a 1 to clear the bit. ROL When the ct_c8_a is considered bad by the hardware, this bit is set. The clock is considered bad if its rising edges are too close or too far apart(i.e. if the rising edge does not arrive within 35 ns to the expected position). Write a 1 to clear the bit. ROL When the ct_c8_b is considered bad by the hardware, this bit is set. The clock is considered bad if its rising edges are too close or too far apart(i.e. if the rising edge does not arrive within 35 ns to the expected position). Write a 1 to clear the bit. ROL When a point is lost due to too much latency to the external memory, this bit is set. This is not a fatal error, but an indication that this phenomenon occurred. Point lost must be compensated for by software using the UUI field in each point. Write a 1 to clear the bit. ROL When a point is lost due to too much latency to the external memory, this bit is set. This is not a fatal error, but an indication that this phenomenon occurred. Point lost must be compensated for by software using the UUI field in each point. Write a 1 to clear the bit. ROL When this bit is high, the H.100 slave has lost its framing on the bus. This bit will cause the H.100 data pins to be tri-stated. Note that this bit will always be set at start-up. Write a 1 to clear the bit. ROL Reserved. Must always be “000” ROL Same as bit 2, except this bit has no effect on the slaveship state. ROL Same as bit 3, except this bit has no effect on the slaveship state. ROL Same as bit 4, except this bit has no effect on the slaveship state. ROL Same as bit 5, except this bit has no effect on the slaveship state. mem_clk_alarm1 1 ct_frame_a_bad 2 ct_frame_b_bad 3 ct_c8_a_bad 4 ct_c8_b_bad 5 adapa_point_lost 6 adapb_point_lost 7 tx_time_slot_pnt_out_of_s ync Reserved ct_frame_a_bad_rol ct_frame_b_bad_rol ct_c8_a_bad_rol ct_c8_b_bad_rol 8 11:9 12 13 14 15 Table 161 - H.100/H.110 Status Register 0 153 MT90502 Address: 704h Label: status0_ie Reset Value: 0000h Label mem_clk_alarm0_ie mem_clk_alarm1_ie ct_frame_a_bad_ie ct_frame_b_bad_ie ct_c8_a_bad_ie ct_c8_b_bad_ie adapa_point_lost_ie adapb_point_lost_ie tx_time_slot_pnt_out_of_sync_ie Reserved ct_frame_a_bad_rol_ie ct_frame_b_bad_rol_ie ct_c8_a_bad_rol_ie ct_c8_b_bad_rol_ie Bit Position Type 0 1 2 3 4 5 6 7 8 11:9 12 13 14 15 Preliminary Datasheet Description IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. RO Reserved. Must always be “000” IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. IE When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. Table 162 - H.100/H.110 Interrupt Enable Register 0 Address: 708h Label: mem_clk_count0 Reset Value: 0000h Label mem_clk_count[31:16] Bit Type Position 15:0 Description RO Free-running mem_clk counter. Table 163 - Memory Clock Counter 0 154 Preliminary Datasheet Address: 70Ah Label: mem_clk_count1 Reset Value: 0000h Label mem_clk_count[15:0] Bit Position 15:0 Type Description MT90502 RO Free-running mem_clk counter. Table 164 - Memory Clock Counter 1 Address: 70Ch Label: mem_clk_alarm0 Reset Value: 0000h Label mem_clk_alarm0_count Bit Position Type 15:0 Description RW Alarm Timer 0 Value. When this value first matches the mem_clk_count[31:16], a status bit is set. Table 165 - Memory Clock Alarm Register 0 Address: 70Eh Label: mem_clk_alarm1 Reset Value: 0000h Label mem_clk_alarm1_count Bit Position 15:0 Type Description RW Alarm Timer 1 Value. When this value first matches the mem_clk_count[31:16], a status bit is set. Table 166 - Memory Clock Alarm Register 1 Address: 710h Label: adapa0 Reset Value: 0001h Label Adapa_keep_one_pulse_out _of_x Adapa_clk_divisor_reset Adapa_source adapa_clk_divisor_load_now Reserved Bit Type Position 9:0 Description RW This field indicates how many clock recovery points should be received per point written to the point memory. Typically, this value would be set to 1. Range 1 to 1024. RW When '0', this will force the Adaptive module A's clock divisor to reset. RW “00” = clkrecov_pulse_a; “01” = gpio[0] (any change); “10” = gpio[0] (rising edge); “11” = gpio[0] (falling edge). PUL When written to '1', this will allow the new div_integer and div_fraction to be used. PUL Reserved. Always read as “00” 10 12:11 13 15:14 Table 167 - Adaptive Module A Register 0 155 MT90502 Address: 712h Label: adapa1 Reset Value: 0002h Label adapa_div_integer Bit Position Type 15:0 Preliminary Datasheet Description RW Adaptive module A's mem_clk divisor (integer part). Range 2 to FFFFh. Table 168 - Adaptive Module A Register 1 Address: 714h Label: adapa2 Reset Value: 0000h Label Adapa_div_fraction Bit Position Type 15:0 Description RW Adaptive module A's mem_clk divisor (fractional part). Range 0 to FFFFh. Table 169 - Adaptive Module A Register 2 Address: 718h Label: adapb0 Reset Value: 0001h Label Adapb_keep_one_pulse_out_of_x Bit Position Type 9:0 Description RW This field indicates how many clock recovery points should be received per point written to the point memory. Typically, this value would be set to 1. Range 1 to 1024. RW When '0', this will force the Adaptive module B's clock divisor to reset. RW “00” = clkrecov_pulse_b; “01” = gpio[1] (any change); “10” = gpio[1] (rising edge); “11” = gpio[1] (falling edge). PUL When written to '1', this will allow the new div_integer and div_fraction to be used. PUL Reserved. Always read as “00” Adapb_clk_divisor_reset Adapb_source Adapb_clk_divisor_load_now Reserved 10 12:11 13 15:14 Table 170 - Adaptive Module B Register 0 Address: 71Ah Label: adapb1 Reset Value: 0000h Label Adapb_div_integer Bit Position Type 15:0 Description RW Adaptive module B's mem_clk divisor (integer part). Range 2 to FFFFh. Table 171 - Adaptive Module B Register 1 156 Preliminary Datasheet Address: 71Ch Label: adapb2 Reset Value: 0000h Label adapb_div_fraction Bit Position Type 15:0 Description MT90502 RW Adaptive module B's mem_clk divisor (fractional part). Range 0 to FFFFh. Table 172 - Adaptive Module B Register 2 Address: 720h Label: mastership0 Reset Value: 0200h Label ct_c8_frame_a_oe ct_c8_frame_b_oe ct_compatibility_oe reserved fr_comp_polarity fr_comp_type fr_comp_frequency Bit Position Type 0 1 2 4:3 5 7:6 9:8 Description RW Controls the output enable of the ct_c8_a and ct_frame_a. '0' = tri-state; '1' = drive pins. RW Controls the output enable of the ct_c8_b and ct_frame_b. '0' = tri-state; '1' = drive pins. RW Controls the output enable of the H100 compatibility signals. '0' = tri-state; '1' = drive pins. RO Reserved. Always read as “00” RW fr_comp pin polarity. '0' = Active low; '1' = active high. RW fr_comp pin timing type. “00”=straddle clock boundary; “01”= active during last bit; “10” = active during first bit; “11” = reserved. RW fr_comp frequency (pulse width). “00” = fr_comp related clock frequency at 2 MHz; “01” = fr_comp related clock frequency at 4 MHz; “10” = fr_comp related clock frequency at 8 MHz; “11”=reserved. RW When '1', it inverts the sclk polarity as defined in the H100 Specifications. RW When '1', it inverts the sclkx2 polarity as defined in the H100 Specifications. RW Selects the sclk frequency for the generation of sclk and sclk2. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. RW Reserved. Must always be “00” sclk_invert sclkx2_invert sclk_frequency reserved 10 11 13:12 15:14 Table 173 - H.100/H.110 Master Register 0 157 MT90502 Address: 722h Label: mastership1 Reset Value: 0002h Label mastership_mode Bit Position Type 1:0 Description Preliminary Datasheet RW Selects the mode of the Master Circuitry. “00” = backup on A; “01” = backup on B; “10” = master on A; “11” = master on B. When ct_c8_frame_a_oe, ct_c8_frame_b_oe, ct_compatibility_oe are '0', this value does not matter. RW Selects the mode of the Slave Circuitry. “00” = Track ct_c8_a & ct_frame_a; “01” = Track ct_c8_b & ct_frame_b; “10” = Track ct_c8_a & ct_frame_a, but if they fail track ct_c8_b & ct_frame_b; “11” = Track ct_c8_b & ct_frame_b, but if they fail track ct_c8_a & ct_frame_a. RW Reserved. Must always be “0000_0000_0000” Table 174 - H.100/H.110 Master Register 1 slaveship_mode 3:2 reserved 15:4 Address: 730h Label: clock_rates Reset Value: AAAAh Label groupa_speed groupb_speed groupc_speed groupd_speed groupe_speed groupf_speed groupg_speed grouph_speed Bit Type Position 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 Description RW Selects the clock speed of H100 streams ct_c[3:0]. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. RW Selects the clock speed of H100 streams ct_c[7:4]. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. RW Selects the clock speed of H100 streams ct_c[11:8]. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. RW Selects the clock speed of H100 streams ct_c[15:12]. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. RW Selects the clock speed of H100 streams ct_c[19:16]. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. RW Selects the clock speed of H100 streams ct_c[23:20]. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. RW Selects the clock speed of H100 streams ct_c[27:24]. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. RW Selects the clock speed of H100 streams ct_c[31:28]. “00” = 2 MHz; “01” = 4 MHz; “10” = 8 MHz; “11” = reserved. Table 175 - Clock Rates Register 158 Preliminary Datasheet Address: 732h Label: timing_conf Reset Value: 0000h Label slave_sampling Bit Position Type 1:0 Description MT90502 RW Selects sampling point for the ct_d pins. The sampling point is relative to the ct_c8 clock period. “00” = falling edge; “01”= 75%; “10” = rising-edge; “11” = reserved. RW Selects if the ct_d output should be tri-stated before the rising edge of the ct_c8 clock or immediately after it. '0' = output enable asserted after rising edge and de-asserted before rising edge; '1' = output enable asserted and de-asserted after rising edge. RW Reserved. Must always be “0000_0000_0000_0” oe_early_disable_override 2 reserved 15:3 Table 176 - Timing Configuration Register Address: 740h Label: gpio_out_reg0 Reset Value: 0000h Label gpio_0_output_select Bit Type Position 4:0 Description RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; “00010”=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in. RW If the gpio_X_output_select selects a constant, this value will be sent out on the gpio_X pin. RW gpio_X pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in. RW If the gpio_X_output_select selects a constant, this value will be sent out on the gpio_X pin. RW gpio_X pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” gpio_0_output_constant gpio_0_output_enable Reserved gpio_1_output_select 5 6 7 12:8 gpio_1_output_constant gpio_1_output_enable Reserved 13 14 15 Table 177 - General Purpose I/O Output Register 0 159 MT90502 Address: 742h Label: gpio_out_reg1 Reset Value: 0000h Label gpio_2_output_select Bit Position Type 4:0 Preliminary Datasheet Description RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in. RW If the gpio_X_output_select selects a constant, this value will be sent out on the gpio_X pin. RW gpio_X pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in. RW If the gpio_X_output_select selects a constant, this value will be sent out on the gpio_X pin. RW gpio_X pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” gpio_2_output_constant gpio_2_output_enable reserved gpio_3_output_select 5 6 7 12:8 gpio_3_output_constant gpio_3_output_enable reserved 13 14 15 Table 178 - General Purpose I/O Output Register 1 160 Preliminary Datasheet Address: 744h Label: gpio_out_reg2 Reset Value: 0000h Label gpio_4_output_select Bit Position Type 4:0 Description MT90502 RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in RW If the gpio_X_output_select selects a constant, this value will be sent out on the gpio_X pin. RW gpio_X pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in RW If the gpio_X_output_select selects a constant, this value will be sent out on the gpio_X pin. RW gpio_X pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” gpio_4_output_constant gpio_4_output_enable reserved gpio_5_output_select 5 6 7 12:8 gpio_5_output_constant gpio_5_output_enable reserved 13 14 15 Table 179 - General Purpose I/O Output Register 2 Address: 746h Label: gpio_out_reg3 Reset Value: 0000h Label gpio_6_output_select Bit Type Position 4:0 Description RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in Table 180 - General Purpose I/O Output Register 3 161 MT90502 gpio_6_output_constant gpio_6_output_enable reserved gpio_7_output_select 5 6 7 12:8 Preliminary Datasheet RW If the gpio_X_output_select selects a constant, this value will be sent out on the gpio_X pin. RW gpio_X pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in RW If the gpio_X_output_select selects a constant, this value will be sent out on the gpio_X pin. RW gpio_X pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” gpio_7_output_constant gpio_7_output_enable reserved 13 14 15 Table 180 - General Purpose I/O Output Register 3 (continued) Address: 748h Label: gpio_out_reg4 Reset Value: 0000h Label ct_netref1_output_select Bit Position Type 4:0 Description RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in. RW If the ct_netrefX_select selects a constant, this value will be sent out on the ct_netrefX pin. RW ct_netrefX pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” RW Output mux selector. “00000”=ct_c8_a_in; “00001”=ct_c8_b_in; 00010=ct_frame_a_in; “00011”=ct_frame_b_in; “00100”=ct_c8_selected; “00101”=ct_frame_selected; “00110”=output_constant ('0'/'1'); “00111”=ct_netref1_in; “01000”=ct_netref2_in; “01001”=gpio_in(0); “01010”=gpio_in(1); “01011”=gpio_in(2); “01100”=gpio_in(3); “01101”=gpio_in(4); “01110”=gpio_in(5); “01111”=gpio_in(6); “10000”=gpio_in(7); “10001”=adapa_ref; “10010”=adapb_ref; “10011”=clkrecov_pulse_a; “10100”=clkrecov_pulse_b; “10101”=mc_clock; “10110”=ct_mc_in ct_netref1_output_constant ct_netref1_output_enable reserved ct_netref2_output_select 5 6 7 12:8 Table 181 - General Purpose I/O Output Register 4 162 Preliminary Datasheet ct_netref2_output_constant ct_netref2_output_enable reserved 13 14 15 MT90502 RW If the ct_netrefX_select selects a constant, this value will be sent out on the ct_netrefX pin. RW ct_netrefX pin output enable. '0'= tri-state; '1'= output enabled. RO Reserved. Always read as “0” Table 181 - General Purpose I/O Output Register 4 (continued) Address: 74Ah Label: gpio_in Reset Value: 0000h Label gpio_0_value gpio_1_value gpio_2_value gpio_3_value gpio_4_value gpio_5_value gpio_6_value gpio_7_value ct_netref1_value ct_netref2_value reserved Bit Position Type 0 1 2 3 4 5 6 7 8 9 15:10 Description RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Current level of the corresponding pin. RO Reserved. Always read as “0000_00” Table 182 - General Purpose I/O Input Register Address: 74Ch Label: gpio_status Reset Value: 0000h Label gpio_0_change gpio_1_change gpio_2_change gpio_3_change gpio_4_change gpio_5_change gpio_6_change gpio_7_change ct_netref1_change Bit Position Type 0 1 2 3 4 5 6 7 8 Description ROL This bit is set if the level of the corresponding pin changes. ROL This bit is set if the level of the corresponding pin changes. ROL This bit is set if the level of the corresponding pin changes. ROL This bit is set if the level of the corresponding pin changes. ROL This bit is set if the level of the corresponding pin changes. ROL This bit is set if the level of the corresponding pin changes. ROL This bit is set if the level of the corresponding pin changes. ROL This bit is set if the level of the corresponding pin changes. ROL This bit is set if the level of the corresponding pin changes. Table 183 - General Purpose I/O Status Register 163 MT90502 ct_netref2_change reserved 9 15:10 Preliminary Datasheet ROL This bit is set if the level of the corresponding pin changes. ROL Reserved. Always read as “0000_00” Table 183 - General Purpose I/O Status Register (continued) Address: 74Eh Label: gpio_status_ie Reset Value: 0000h Label gpio_0_change_ie gpio_1_change_ie gpio_2_change_ie gpio_3_change_ie gpio_4_change_ie gpio_5_change_ie gpio_6_change_ie gpio_7_change_ie ct_netref1_change_ie ct_netref2_change_ie reserved Bit Position Type 0 1 2 3 4 5 6 7 8 9 15:10 IE IE IE IE IE IE IE IE IE IE IE Description When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. Reserved. Always read as “0000_00” Table 184 - General Purpose I/O Status Interrupt Enable Register 164 Preliminary Datasheet Address: 774h Label: mastership_hidden0 Reset Value: 0000h Label automatic_master_override mux0_select_override mux1_select_override mux2_select_override mux3_select_override reserved Bit Position Type 0 1 2 3 5:4 15:6 Description MT90502 RW When '1', the automatic H100 Master programming values are overridden. RW 0' = don't swap; '1' = swap. RW 0'=Divide by 4; '1' = ct_c8 pin. RW 0'=Local Ref; '1' = ct_c8 pin. RW “00”=PLL Used; “01”=32 MHz local ref used; “10”=16 MHz local ref used; “11”=8 MHz local ref used. RW Reserved. Always read as “0000_0000_00” Table 185 - H.100/H.110 Master Hidden Register 0 Address: 776h Label: mastership_hidden1 Reset Value: 0000h Label h100_check_automatic_override h100_min_mem_clk_ct_c8_override h100_max_mem_clk_ct_c8_override h100_sample_tristate_override Reserved Bit Type Position 0 5:1 10:6 11 15:12 Description WO When '1', the following two field will control the ct_c8 frequency checker. RW minimum period (in mem_clk cycles) between 2 H100 ct_c8 clock rising edges. RW Maximum period (in mem_clk cycles) between 2 H100 ct_c8 clock rising edges. WO When '1', the values in the following registers will be used to control the sampling and tri-state delays. WO Reserved. Always read as “0000” Table 186 - H.100/H.110 Master Hidden Register 1 Address: 778h Label: mastership_hidden2 Reset Value: 0000h Label h100_samp_clk_delay_flops h100_samp_clk_delay_buff h100_oe_clk_delay_flops h100_oe_clk_delay_buff Bit Type Position 3:0 7:4 11:8 15:12 Description RW Number of flops used = 8 + value of this register. “1111” is reserved for selecting falling edge ct_c8 clock RW “1111” is reserved for selecting rising edge ct_c8 clock RW Number of flops used = 8 + value of this register RW Table 187 - H.100/H.110 Master Hidden Register 2 165 MT90502 3.8 Miscellaneous Registers Address: 802h Label: status0 Reset Value: 0000h Label cell_assembly_event_buf_overflow pointa_buf_overflow pointb_buf_overflow reserved Bit Type Position 0 1 2 15:3 Preliminary Datasheet Description ROL Overflow in the cell assembly event queue. Fatal chip error. ROL Overflow in the clock recovery point A buffer. ROL Overflow in the clock recovery point B buffer. ROL Reserved. Always read as “0000_0000_0000_0” Table 188 - Miscellaneous Status Register Address: 804h Label: status0_ie Reset Value: 0000h Label cell_assembly_event_buf_overflow pointa_buf_overflow pointb_buf_overflow reserved Bit Type Position 0 1 2 15:3 IE IE IE Description When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. RO Reserved. Always read as “0000_0000_0000_0” Table 189 - Miscellaneous Interrupt Enable Register Address: 810h Label: tone_buffer_control Reset Value: 0000h Label sdram_tone_base sdram_tone_size sdram_tone_enable ssram_tone_enable reserved Bit Type Position 4:0 6:5 7 8 15:9 Description RW Represents bits 23:19 of the byte address to the SDRAM tone buffers RW “00” = 16KBytes, “01” = 32K, “10” = 64K, “11” = reserved. Size is for a single buffer. RW Enables the use of the tones contained in the SDRAM. RW Enables the use of the tones contained in the SSRAM. RW Reserved. Must always be “0000_000” Table 190 - Tone Buffer Control Register 166 Preliminary Datasheet Address: 820h Label: pointa_manage Reset Value: 0000h Label pointa_buffer_base_add pointa_buffer_size reserved Bit Position Type 8:0 11:9 15:12 Description MT90502 RW Bits 20:12 of the base address of the clock recovery point buffer A in external SSRAM RW “000” = 4KBytes, “001” = 8K, “010” = 16K, “011” = 32K, “100” = 64K, “101” = 128K, others = reserved. Size is for a single buffer. RW Reserved. Must always be “0000” Table 191 - Point A Buffer Management Register Address: 822h Label: pointa_read Reset Value: 0000h Label pointa_rpnt Bit Position Type 13:0 Description RW The CUP’s read pointer to the clock recovery point FIFO. This read pointer has an extra bit to allow for a full buffer (for example, 2048 points instead of 2047) RW Reserved. Must always be “00” Reserved 15:14 Table 192 - Point A Read Pointer Register Address: 824h Label: pointa_write Reset Value: 0000h Label pointa_wpnt Bit Position Type 13:0 Description RO The chip's write pointer to the clock recovery point FIFO. This read pointer has an extra bit to allow for a full buffer (for example, 2048 points instead of 2047) RO Reserved. Always read as “00” Reserved 15:14 Table 193 - Point A Write Pointer Register Address: 828h Label: pointb_manage Reset Value: 0000h Label pointb_buffer_base_add pointb_buffer_size reserved Bit Position Type 8:0 11:9 15:12 Description RW Bits 20:12 of the base address of the clock recovery point buffer B in external SSRAM RW “000” = 4KBytes, “001” = 8K, “010” = 16K, “011” = 32K, “100” = 64K, “101” = 128K, others = reserved RW Reserved. Must always be “0000” Table 194 - Point B Buffer Management Register 167 MT90502 Address: 82Ah Label: pointb_read Reset Value: 0000h Label pointb_rpnt reserved Bit Position Type 13:0 15:14 Description Preliminary Datasheet RW The CUP’s read pointer to the clock recovery point FIFO. This read pointer has an extra bit to allow for a full buffer (for example, 2048 points instead of 2047) RW Reserved. Must always be “00” Table 195 - Point B Read Pointer Register Address: 82Ch Label: pointb_write Reset Value: 0000h Label pointb_wpnt reserved Bit Position Type 13:0 15:14 Description RO The chip's write pointer to the clock recovery point FIFO. This read pointer has an extra bit to allow for a full buffer (for example, 2048 points instead of 2047) RO Reserved. Always read as “00” Table 196 - Point B Write Pointer Register Address: 830h Label: cid_base Reset Value: 0000h Label cid_descriptor_base_address reserved Bit Position Type 4:0 15:5 Description RW Bits 23:21 of the CID descriptor’s base address in the SDRAM RW Reserved. Must always be “0000_0000_000” Table 197 - CID Base Address Register 168 Preliminary Datasheet 3.9 RX TDM Registers MT90502 Address: 900h Label: control Reset Value: 0000h Label hdlc_type Bit Position Type 0 3:1 6:4 Description RW 0'=Bit wise HDLC Framing; '1'=Byte Wise HDLC Framing. RW Set to “111” for normal operation. RW “000” = 32 packets, “001” = 64 packets, “010” = 128 packets, “011” = 256 packets, “100” = 512 packets, “101” = 1024, “11x” = reserved RW Reserved. Must always be “0”. RW Enables the treatment of incoming RX SAR bytes going to the H100 bus. RW When '1', the u-law value 00h will be replaced by 02h. RW “00” = don't translate padding, OL bit in Rx TDM Control Structure is ignored for padding bytes; “01” = padding is in u-law only, “10” = padding is in A-law only. TS Reserved. Must always be “0”. rx_tdm_time_slot_lead number_packets_per_frame reserved llman_process_enable u_law_zero_illegal padding_law 7 8 9 11:10 test_status 15 Table 198 - RX TDM Control Register Address: 902h Label: status0 Reset Value: 0000h Label llman_process_crashed underrun_detect underrun_wrap_detect rxtdm_read_cache_overflow rxtdm_write_cache_overflow write_back_cache_overflow rx_tdm_fifo_overflow rxsar_pointer_wb_overflow reserved Bit Type Position 0 1 2 3 4 5 6 7 15:8 Description ROL Indicates that the linked-list manager crashed. This indicates corrupt data in the linked list memory. ROL Underrun detected on a channel. ROL Indicates that the 16-bit underrun counter on a single channel has wrapped. ROL Overflow in the RX TDM read cache. Fatal chip error. ROL Overflow in the RX TDM write cache. Fatal chip error. ROL Overflow in the RX TDM write back cache. ROL Overflow in the RX TDM data FIFO. Fatal chip error. ROL Overflow in the RX SAR pointer write back FIFO. Fatal chip error. ROL Reserved. Always read as “0000_0000” Table 199 - RX TDM Status Register 0 169 MT90502 Address: 904h Label: status0_ie Reset Value: 0000h Label llman_process_crashed_ie underrun_detect_ie underrun_wrap_detect_ie rxtdm_read_cache_overflow_ie rxtdm_write_cache_overflow_ie write_back_cache_overflow_ie rx_tdm_fifo_overflow_ie rxsar_pointer_wb_overflow_ie reserved Bit Position Type 0 1 2 3 4 5 6 7 15:8 IE IE IE IE IE IE IE IE Preliminary Datasheet Description When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. When ‘1’ and the corresponding status bit is ‘1’ an interrupt will be generated. RO Reserved. Always read as “0000_0000” Table 200 - RX TDM Interrupt Enable Register 0 Address: 908h Label: monitor Reset Value: 0000h Label hdlc_pcm_channel_error Bit Position Type 9:0 Description RO Indicates the channel number, according to its position in the RX TDM control memory, on which the last underrun or underrun wrap error occurred RO Reserved. Always read as “0000_00” reserved 15:10 Table 201 - RX TDM Channel Number Monitor Register 170 Preliminary Datasheet 4.0 4.1 MT90502 Electrical Specification DC Characteristics Absolute Maximum Ratings Parameter Supply Voltage - 3.3 Volt Rail Voltage on 3.3V Input pins Voltage on 3.3V Output pins Storage Temperature Symbol VDD VI VO TS Min -0.5 -0.5 -0.5 -40.0 Max 5.0 VDD+0.5 VDD+0.5 +125.0 Units V V V °C * Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (V SS) unless otherwise stated. Long-term exposure to absolute maximum ratings may affect device reliability, and permanent damage may occur if operate exceeding the rating. The device should be operated under recommended operating condition. Recommended Operating Conditions Characteristics Operating Temperature Supply Voltage, 3.3 Volt Rail Sym TOP VDD Min 0.0 3.135 Typa 25.0 3.3 Max 70.0 3.465 Unit s °C V Test Conditions a. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Voltage measurements are with respect to ground (V SS) unless otherwise stated. DC Characteristics Characteristics Supply Current - 3.3 V supply Continuous current at digital inputs Continuous current at digital outputs Device Power Dissipation Sym IDD Min Typa 1.19 Max Unit s A Test Conditions b 60.0 MHz, Nominal output loads, 1023 Channels II IO PDDS 2.31 3.04 3.927 mA mA W 60.0 MHz, Nominal output loads, 1023 Channels Input High Voltage Input Low Voltage Output HIGH Voltage Output LOW Voltage Schmitt Trigger Positive Threshold Schmitt Trigger Neg. Threshold Input Leakage Current Inputs with gated pull-up Inputs with gated pull-down VIH VIL VOH VOL Vt+ VtII IIH IIL 0.7VDD 0.3VDD 2.4 0.4 1.6 1.2 -1.0 -30.0 30.0 1.0 -70.0 70.0 V V V V V µA µA µA VIN = VDDx or Vss VIN = VDD VIN = Vss 171 MT90502 DC Characteristics (continued) Characteristics Input Pin Capacitance Output Pin Capacitance Output High Impedance Leakage 3.3V output HIGH current (6 mA buffer) 3.3V output LOW current (6 mA buffer) 3.3V output HIGH current (12 mA buffer) 3.3V output LOW current (12 mA buffer) 3.3V output HIGH current (24 mA buffer) 3.3V output LOW current (24 mA buffer) Junction-to-Ambient Thermal Resistance Sym CI CO IOZ IOH IOL IOH IOL IOH IOL Min Typa 5.0 5.0 1.0 6.0 6.0 12.0 12.0 24.0 24.0 14.0 Max Preliminary Datasheet Unit s pF pF uA mA mA mA mA mA mA °C/W Test Conditions b VO = VSS or VDD θJ-A 0 cfm air flow (natural convection airflow only) a. Typical figures are at 25 ° C and are for design aid only; not guaranteed and not subject to production testing. b. TOP = 0°C to 70° C; 3.135V < VDD < 3.465V Voltage measurements are with respect to ground (V SS) unless otherwise stated. 172 Preliminary Datasheet 4.2 4.3 AC Characteristics Intel/Motorola Interface MT90502 write_access_active (when both CS and WR are low) t1_non_muxed t2_non_muxed cpu_a[14:0]/cpu_a_das cpu_d[15:0] t1_writes t4 t5 cpu_rdy_ndtack t2_writes2 t6 t2_writes1 Figure 71 - Non-Multiplexed CPU Interface - Intel Mode - Write Access Symbol Description Min Typical Max 2 * upclk - 4 ns Unit t1_non_muxed write_access_active falling edge to cpu_a valid cpu_a_das valid t1_writes write_access_active falling edge to cpu_d valid 0 2 * upclk - 4 ns ns t2_non_muxed cpu_rdy_ndtack rising edge to cpu_a invalid cpu_a_das invalid t2_writes1 t2_writes2 t4 t5 t6 cpu_rdy_ndtack rising edge to write_access_active rising edge cpu_rdy_ndtack rising edge to cpu_d invalid write_access_active falling edge to cpu_rdy_ndtack falling edge Write Access Time write_access_active rising edge to cpu_rdy_ndtack tri-state 0 0 0 12 740 0 10 ns ns ns ns ns Table 202 - Non-Multiplexed CPU Interface - Intel Mode - Write Access 173 MT90502 Preliminary Datasheet read_access_active (when both CS and RD are low) t1 cpu_a[14:0]/cpu_a_das t8 cpu_d[15:0] t4 t5 t13 cpu_rdy_ndtack t6 t2_reads t2_non_muxed Figure 72 - Non-Multiplexed CPU Interface - Intel Mode - Read Access Symbol t1 t2_reads Description read_access_active falling edge to cpu_a valid cpu_a_das valid cpu_rdy_ndtack rising edge to read_access_active rising edge (reads) 0 Min Typical Max 2 * upclk - 4 Unit ns ns ns t2_non_muxed cpu_rdy_ndtack rising edge to cpu_a invalid (non-multiplexed) cpu_a_das invalid (non-multiplexed) t4 t5 read_access_active falling edge to cpu_rdy_ndtack falling edge Read Access Time 0 12 See Table 205, “t5 Read Access Times,” on page 177. 0 3 * upclk - 4 upclk - 4 10 ns t6 t8 t13 read_access_active rising edge to cpu_rdy_ndtack tri-state read_access_active falling edge to cpu_d driven cpu_d valid to cpu_rdy_ndtack rising edge ns ns ns Table 203 - Non-Multiplexed CPU Interface - Intel Mode - Read Access 174 Preliminary Datasheet MT90502 inmo_cs inmo_rd_ds t11 R/W t5 t7 t6 t12 t4 inmo_rdy_ndtack t1 inmo_a[14:0] t1 inmo_d[15:0] t1 inmo_a_das t3 Address Valid t3 Data Valid t3 Figure 73 - Non-Multiplexed CPU Interface - Motorola Mode - Write Access inmo_cs inmo_rd_ds t11 R/W t5 t4 inmo_rdy_ndtack t12 t7 t9 t6 t1 Address Valid t3 inmo_a[14:0] t3 t1 inmo_a_das t10 inmo_d[15:0] Data Valid Figure 74 - Non-Multiplexed CPU Interface - Motorola Mode - Read Access 175 MT90502 Sym t1 Description Write Access Address & Data Setup -- cpu_cs and cpu_rd_ds asserted to cpu_a[14:0] and cpu_d[15:0] and cpu_a_das valid Address & Data Hold -- cpu_rdy_ndtack low to cpu_a[14:0] and cpu_d[15:0] and cpu_a_das invalid 0 Min Preliminary Datasheet Typ Max 2*upclk - 4 Unit ns t3 t4 t5 t6 t7 t11 t12 ns 12 740 ns ns ns ns ns ns cpu_rdy_ndtack high -- cpu_cs and cpu_rd_ds asserted 0 to cpu_rdy_ndtack driving one cpu_rdy_ndtack delay -- cpu_cs and cpu_rd_ds asserted to cpu_rdy_ndtack driving zero cpu_rdy_ndtack hold -- cpu_cs and cpu_rd_ds de-asserted to cpu_rdy_ndtack driving one cpu_rdy_ndtack high impedance -- cpu_rdy_ndtack driving one to cpu_rdy_ndtack high impedance cpu_r/w low to both cpu_cs and cpu_ds asserted cpu_cs or cpu_ds high to cpu_r/w high 0 2 0 0 10 8 Note: t1, t4, and t5 are dependent upon the last of cpu_cs and cpu_rd_ds to be asserted. t6 is dependent on the first of cpu_cs and cpu_rd_ds to be de-asserted. Sym t1 t3 t4 t5 Description Read Access Address Setup -- cpu_cs and cpu_rd_ds asserted to cpu_a[14:0] and cpu_a_das valid Address Hold -- cpu_rdy_ndtack low to cpu_a[14:0] and 0 cpu_a_das invalid cpu_rdy_ndtack high -- cpu_cs and cpu_rd_ds asserted 0 to cpu_rdy_ndtack driving one cpu_rdy_ndtack delay -- cpu_cs and cpu_rd_ds asserted to cpu_rdy_ndtack asserted 12 Min Typ Max 2*upclk - 4 Unit ns ns ns See Table 205, ns “t5 Read Access Times,” on page 177. 0 2 upclk - 4 10 10 8 ns ns ns ns ns ns t6 t7 t9 t10 t11 t12 cpu_rdy_ndtack hold -- cpu_cs or cpu_rd_ds de-asserted to cpu_rdy_ndtack driving one cpu_rdy_ndtack high impedance -- cpu_rdy_ndtack driving one to cpu_rdy_ndtack high-impedance Data to cpu_rdy_ndtack delay -- cpu_d[15:0] valid to cpu_rdy_ndtack asserted Data output hold -- cpu_cs or cpu_rd_ds de-asserted to 0 cpu_d[15:0] invalid cpu_r/w high to both cpu_cs and cpu_ds asserted cpu_cs or cpu_ds high to cpu_r/w low 0 0 Table 204 - Non-Multiplexed CPU Interface - Motorola Mode 176 Preliminary Datasheet Symbol t5 t5 t5 t5 t5 t5 t5 Description Register and internal memory access SSRAM SSRAM SSRAM SDRAM SDRAM SDRAM Burst Length (read only) 1-word 1-word 8-words 128-words 1-word 8-words 128-words Table 205 - t5 Read Access Times Max 740 1.07 1.44 8.78 1.16 2.32 24.9 MT90502 Unit ns µs µs µs µs µs µs write_access_active (when both CS and WR are low) t15 t1_muxed t2_muxed cpu_ale t17 t16 t1_writes cpu_d[15:0] addr data t2_writes2 t5 t4 cpu_rdy_ndtack t2_writes1 t6 Figure 75 - Multiplexed CPU Interface - Intel Mode - Write Access 177 MT90502 Symbol Description Preliminary Datasheet Min Typical Max Unit t1_muxed write_access_active falling edge to cpu_ale fall t1_writes write_access_active falling edge to cpu_d valid t2_muxed cpu_rdy_ndtack rising edge to cpu_ale rising edge t2_writes1 cpu_rdy_ndtack rising edge to write_access_active rising edge t2_writes2 cpu_rdy_ndtack rising edge to cpu_d invalid t4 t5 t6 t15 t16 t17 write_access_active falling edge to cpu_rdy_ndtack falling edge Write Access Time write_access_active rising edge to cpu_rdy_ndtack tri-state cpu_ale high pulse width cpu_d valid to cpu_ale falling edge cpu_ale falling edge to cpu_d invalid 0 5 5 5 0 0 0 0 2 * upclk - 4 ns 2 * upclk - 4 ns ns ns ns 12 740 10 ns ns ns ns ns ns Table 206 - Multiplexed CPU Interface - Intel Mode - Write Access read_access_active (when both CS and RD are low) t15 t1 cpu_ale t17 t16 t8 cpu_d[15:0] t5 t4 cpu_rdy_ndtack t13 t2_reads t6 t2_muxed Figure 76 - Multiplexed CPU Interface - Intel Mode - Read Access Symbol t1 Description read_access_active falling edge to cpu_ale fall 0 0 0 12 see Table 205 Min Typical Max Unit 2 * upclk - 4 ns ns ns ns t2_muxed cpu_rdy_ndtack rising edge to cpu_ale rising edge t2_reads cpu_rdy_ndtack rising edge to read_access_active rising edge t4 t5 read_access_active falling edge to cpu_rdy_ndtack falling edge Read Access Time Table 207 - Multiplexed CPU Interface - Intel Mode - Read Access 178 Preliminary Datasheet t6 t8 t13 t15 t16 t17 read_access_active rising edge to cpu_rdy_ndtack tri-state read_access_active falling edge to cpu_d driven cpu_d valid to cpu_rdy_ndtack rising edge cpu_ale high pulse width cpu_d valid to cpu_ale falling edge cpu_ale falling edge to cpu_d invalid 0 3 * upclk - 4 upclk - 4 5 5 5 MT90502 10 ns ns ns ns ns ns Table 207 - Multiplexed CPU Interface - Intel Mode - Read Access (continued) write_access_active (when all CS, R/W and DS are low) t15 t1_muxed cpu_ale t17 t16 t1_writes cpu_d[15:0] t11 t3_writes2 t9 cpu_rdy_ndtack t5 t3_writes1 t10 t3_muxed Figure 77 - Multiplexed CPU Interface - Motorola Mode - Write Access Symbol Description Min Typical Max Unit t1_muxed write_access_active falling edge to cpu_ale fall t1_writes write_access_active falling edge to cpu_d valid t3_muxed cpu_rdy_ndtack falling edge to cpu_ale rising edge t3_writes1 cpu_rdy_ndtack falling edge to write_access_active rising edge t3_writes2 cpu_rdy_ndtack falling edge to cpu_d invalid t5 t9 t10 t11 t15 t16 t17 Write Access Time write_access_active falling edge to cpu_rdy_ndtack driven high write_access_active rising edge to cpu_rdy_ndtack rising edge cpu_rdy_ndtack rising edge to cpu_rdy_ndtack tri-state cpu_ale high pulse width cpu_d valid to cpu_ale falling edge cpu_ale falling edge to cpu_d invalid 0 0 2 5 5 5 0 0 0 2 * upclk - 4 ns 2 * upclk - 4 ns ns ns ns 740 12 10 8 ns ns ns ns ns ns ns Table 208 - Multiplexed CPU Interface - Motorola Mode - Write Access 179 MT90502 read_access_active (when both CS, DS are low and R/W is high) cpu_ale t17 t16 t8 cpu_d[15:0] t5 t9 cpu_rdy_ndtack t14 t3_reads Preliminary Datasheet t15 t1 t3_muxed t12 t11 t10 Figure 78 - Multiplexed CPU Interface - Motorola Mode - Read Access Symbol t1 Description read_access_active falling edge to cpu_ale fall 0 0 see Table 205 3 * upclk - 4 0 0 2 5 5 5 12 10 8 ns ns ns ns ns ns ns Min Typical Max 2 * upclk - 4 Unit ns ns ns t3_muxed cpu_rdy_ndtack falling edge to cpu_ale rising edge t3_reads cpu_rdy_ndtack falling edge to read_access_active rising edge t5 t8 t9 t10 t11 t15 t16 t17 Read Access Time read_access_active falling edge to cpu_d driven read_access_active falling edge to cpu_rdy_ndtack driven high read_access_active rising edge to cpu_rdy_ndtack rising edge cpu_rdy_ndtack rising edge to cpu_rdy_ndtack tri-state cpu_ale high pulse width cpu_d valid to cpu_ale falling edge cpu_ale falling edge to cpu_d invalid Table 209 - Multiplexed CPU Interface - Motorola Mode - Read Access 180 Preliminary Datasheet 4.3.1 UTOPIA Interface MT90502 UTOPIA Timing {tx,rx}{a,b,c}_ clk t1 input t3 t5 output t4 t6 t2 Figure 79 - UTOPIA Timing Symbol t1 t2 t3 t4 t5 t6 Characteristics Input setup time Input hold time Clock to data valid Clock to data change Clock rising to signal driven Clock rising to signal tri-state Min 4 1 Type Max Units ns ns 12 2 1 1 20 ns ns ns ns Table 210 - UTOPIA Timing 4.3.2 External Memory Interface mem_clk t1 mem_*(input) t3 t5 mem_*(output) t4 t6 t2 Figure 80 - External Memory Timing (both SSRAM and SDRAM) 181 MT90502 Symbol t1 t2 t3 t4 t5 t6 Characteristics Input setup time Input hold time Clock to data valid Clock to data change Clock rising to signal driven Clock rising to signal tri-state 2 2 10 Min 2 0 8.30 Type Max Preliminary Datasheet Units ns ns ns ns ns ns 50 pF 50 pF Load Table 211 - External Memory Timing 4.3.3 H.100/H.110 Interface ct_c8 t4 t3 cd_d(1/2_cycle) t2 t1 cd_d(3/4_cycle) t5 cd_d(4/4_cycle) t6 Figure 81 - H.100/H.110 Timing - H.100 Input Sampling Symbol t1 t2 t3 t4 t5 t6 Description ct_c8 rise to ct_d valid ct_c8 rise to ct_d invalid ct_d valid to ct_c8 fall ct_c8 fall to ct_d invalid ct_d valid to ct_c8 rise ct_c8 rise to ct_d invalid Min Typical Max 69 Unit ns ns ns ns ns ns 102 3 1 5 0 Table 212 - H.100/H.110 Timing - H.100 Input Sampling 182 Preliminary Datasheet MT90502 ct_c8 t10 cd_d(valid data to early tri-state) t11 t14 cd_d(valid data to valid data) t12 cd_d(tri-state to valid data) t13 Figure 82 - H.100/H.110 Timing - H.100 Output Symbol t10 t11 t12 t13 t14 Description ct_c8 rise to ct_d tri-state ct_c8 rise to ct_d invalid ct_c8 rise to ct_d invalid ct_c8 rise to ct_d driven ct_c8 rise to ct_d valid Min Typical Max 122 Unit ns ns ns ns Load 200 pf 200 pf 200 pf 200 pf 200 pf 102 2 2 22 ns Table 213 - H.100/H.110 Timing - H.100 Output ct_c8 t20 ct_frame t21 Figure 83 - H.100/H.110 Timing - H.100 Frame Sampling Symbol t20 t21 Description ct_frame valid to ct_c8 rise ct_c8 rise to ct_frame invalid Min 5 5 Typical Max Unit ns ns Table 214 - H.100/H.110 Timing - H.100 Frame Sampling 183 MT90502 t30 ct_c8 ct_frame mc_clock H.100 Message Channel Clock t40 mc_tx ct_mc H.100 Message Transmission Delay t50 ct_mc t41 t31 Preliminary Datasheet mc_rx H.100 Message Reception Delay Figure 84 - H.100/H.110 Message Timing Symbol t30 t31 t40 t41 t50 Description ct_c8 rise to mc_clock rise ct_c8 fall to mc_clock fall mc_tx fall to ct_mc low mc_tx rise to ct_mc tri-state ct_mc fall to mc_rx fall Min Typical Max 15 15 Unit ns ns ns ns ns Load 3 3 3 15 15 15 200 pf 200 pf Table 215 - H.100/H.110 Message Timing 184 Preliminary Datasheet MT90502 H.100 Clock Skew (when chip is Master) t60 ct_c8_a ct_c8_b ct_frame_a ct_frame_b c2 c4 sclk sclkx2 frcomp c16+ c16- Figure 85 - H.100/H.110 Clock Skew Symbol t60 Description maximum skew when signals generated by MT90502 Min Typical Max 5 Unit ns Load 200 pF Table 216 - H.100/H.110 Clock Skew Table 185 MT90502 5.0 5.1 Preliminary Datasheet Glossary of Terminology Standard Terms and Abbreviations AAL0: ATM Adaptation Layer 0. AAL0 is a straight packaging of 48 bytes of data within an ATM cell. AAL0 can be used to treat either data cells (managed by CPU) or CBR cells (managed by TX SAR and RX SAR). AAL2: ATM Adaptation Layer 2. AAL2 is used to transport constant bit rate (CBR) and variable bit rate (VBR) data on ATM. AAL2 cells are made up of AAL2 CPS-Packets of different lengths containing different kinds of data. ADPCM: Adaptive Differential Pulse Code Modulation. ADPCM is a compression standard that allows the encoding of PCM data at rates of 40, 32, 24 and 16 kbps. CBR: Constant Bit Rate. CBR data means that cells on that particular channel are sent out at a regular rate. CBR is applicable to voice channels. CRC: Cyclic Redundancy Check. The CRC is a method of error detection and correction that is applied to a certain field of data. CRC is an efficient method of error detection because the odds of erroneously detecting a correct payload are low. FIFO: First In, First Out. A FIFO memory is one in which the first byte to have been written into the memory is the first one to be read from the read port. GFC: Generic Flow Control. The GFC field is kept in the 4 highest bits of an ATM cell’s header and is used for local functions (not carried end-to-end). The default value is “0000”, meaning that GFC protocol is not enforced. H.100/H.110: A TDM bus standard developed by ECTF to provide backward compatibility to existing TDM busses with more bandwidth and potential for development. HDLC: High-level Data Link Control. An encapsulation protocol that defines specific bit patterns as de-limiters and thus allows transmission of data over a serial link. In the MT90502, HDLC is used to carry variable-length packets on the H.100/H.110 bus. OC-3: Optical Carrier level-3. A SONET channel that carries a bandwidth of 155.55 Mbps. PCM: Pulse Code Modulation. PCM is the basic method of encoding an analog voice signal into digital form. PHY: PHYsical layer. The bottom layer of the ATM Reference Model, it provides ATM cell transmission over the physical interfaces that interconnect the various ATM devices. PLL: Phase Lock Loop. A phase lock loop is a component that generates an output clock by synchronizing itself to an input clock. PLLs are often used to multiply the frequency of clocks. RAM: Random Access Memory. RAM is the main memory in the computer. It is called “random” because any random address can be accessed in an equal amount of time. SAR: Segmentation And Reassembly. Method of partitioning, at the source, frames into ATM cells and reassembling, at the destination, these cells back into information frames. SAR is the lower sub-layer of the AAL which inserts data from the information frames into cells and then add the required header, trailer, and/or padding bytes to create 48-byte payloads to be transmitted to the ATM layer. TDM: Time Division Multiplexing. TDM busses carry voice data divided according to frames. In a single 125 us frame, the TDM bus will have carried one byte from each channel it contains. UTOPIA: Universal Test and Operations PHY Interface for ATM. A PHY-level interface to provide connectivity between ATM components. VC: Virtual Circuit. VCs define a point-to-point connection between two nodes in a network. A single ATM cell carries data that belongs to a single VC. VCI: Virtual Channel Identifier. This is the label given to an ATM VC to identify it and determine its destination. The VCI is a 16-bit number that is included in the header of an ATM cell. VPI: Virtual Path Identifier. A virtual path determines the way an ATM cell should be routed. The VPI is an 8-bit (in UNI) or 12-bit (in NNI) number that is included in the header of an ATM cell. 186 Preliminary Datasheet 5.2 Terms specific to AAL2 MT90502 CID: Channel IDentifier. The CID is an 8-bit field that identifies an AAL2 CPS-Packet and determines which of the 255 AAL2 channels on this VC it belongs to. The value of 00h is illegal for the CID, values 01h to 07h are denoted as reserved for use by the AAL type 2. EDU: Encoding Data Unit. A group of 8 PCM bytes or 8 ADPCM samples that represent 1 ms of voice traffic. The size of every PCM or ADPCM CPS-Packet sent on AAL2 is an integer number of EDUs. LI: Length Indicator. The LI is a 6-bit field encoded with a value that is one less than the number of octets in the CPS-Packet Payload portion of a CPS-Packet. SID: Silent Insertion Descriptor. A SID CPS-Packet is an AAL2 CPS-Packet containing a single byte of payload that is inserted when a valid CPS-Packet has been suppressed because it was silent. The payload byte indicates the energy level of the voice that was suppressed. UUI: User-to-User Indication. The UUI is a 5-bit field contained within the AAL2 header that is used to indicate the type of an AAL2 CPS-Packet. When indicating voice data, the UUI is often used as a 4-bit sequence number. 5.3 Terms specific to this specification AAL2 Channel: Any sub-channel carried by an AAL2 VC. An AAL2 channel is uniquely identified by its CID and the VPI/VCI of the VC it belongs to. AAL2 CPS-Packet: A CPS-Packet contained within one or many AAL2 cells. AAL2 CPS-Packets contain 3 bytes of overhead (including CID, LI, UUI and HEC) and from 1 to 64 bytes of payload. Because of this 64-byte maximum, they can straddle many cells. Also known as CPS-packet. HDLC Stream: A group of HDLC channels that are carried over the same time slots. HDLC CPS-Packets in streams have an address byte that indicates to which HDLC channel they belong. Usually, HDLC streams carry a series of channels communicating to and from the same agent (e.g. a DSP). HDLC Streams must be carried over a single H.100 stream and over one or multiple consecutive time slots on that stream. HDLC channel: An HDLC channel carries CPS-Packets destined to the same AAL2 channel. All CPS-Packets of an HDLC channel are carried by the same HDLC stream. PDV: Packet Delay Variation. AAL2 CPS-Packets arrive with a certain delay with respect to when they were sent. PDV is a measure of how much that delay varies on an AAL2 channel. PDV measures the peak-to-peak packet delay throughout the network. PDV is only relevant on CBR connections. Time Slot: In this document, the term time slot is often used to define a combination of a time slot and a stream on the H.100 bus. Thus a time slot would represent a single 8-bit slot every 125 us on the TDM bus. 5.4 Register types CNT: Counter. Events in the MT90502 will cause the counter to increment. CRL: Counter Roll-Over: This bit indicates its respect counter has wrapped. IE: Interrupt Enable. This is a register bit that enables a status event to generate an interrupt. This bit is always active-high. PC: Process Control bit. This is a register bit type that is written to ‘1’ to initiate a hardware process. When the process completes, the hardware clears the bit. PUL: Pulse. This bit is used to set an event. Setting this bit, creates a pulse in the MT90502 of 1 clock period. The hardware then clears this bit. 187 MT90502 Preliminary Datasheet RO: Read Only. This serves to define registers that cannot be written to by the CPU. ROL: Read Only Latch. This defines status bits. Status bits cannot be written to ‘1’ by the CPU; however, once the status bit is set, the CPU can clear it by writing a ‘1’ over it. RW: Read Write. This type of register bit will be readable and writable by the CPU. TS: Test Status. This type is for test purposes only and should not be written by the user. WO: Write Only. This type of register bit is writable by the CPU. The value read back by the CPU may not reflect the true value of the bit. 5.5 Units and Conventions All numbers in this document are decimal unless otherwise specified. Hexadecimal numbers can be identified by the ‘h’ suffix (e.g. 00A5h). Binary numbers are either in double quotes for multiple bits or in single quotes for individual bits (e.g. “1001”, ‘0’). All addresses are specified in hexadecimal and point to bytes. Addresses are converted from bytes to words to double words using the little endian format, unless otherwise specified. 188 Preliminary Datasheet 6.0 Mechanical Drawing D MT90502 A1 Corner D1 A1 Ball Pad Indicator E1 E Top View A2 A1 A Side View Seating Plane A1 Corner Dimension A A1 A2 D D1 E E1 I J b e N Min 1.92 (2.12) 0.50 1.12 Max 2.32 (2.54) 0.70 1.22 e 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF J 35.00 BSC 30.00 30.70 35.00 BSC 30.00 30.70 1.625 REF 1.625 REF b 0.60 0.90 1.27 BSC 456 e 2 Layers (4 Layers) I BOTTOM VIEW Figure 86 - MT90502 Package Outline Drawing (456 PBGA) 189 MT90502 Preliminary Datasheet 190 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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