MT91L62

ISO2 MT91L62 - CMOS 3 Volt Single Rail Codec Data Sheet Features • • • • • • • • • Single 2.7-3.6 volt supply Programmable µ−law/A-law Codec and filters Fully differential to output driver SSI digital interface Individual transmit and receive mute controls 0 dB gain in receive path 6 dB gain in transmit path Low power operation ITU-T G.714 compliant Ordering Information MT91L62AE MT91L62AS MT91L62AN July 2004 20 Pin Plastic DIP (300 mil) 20 Pin SOIC 20 Pin SSOP -40°C to +85 °C Description The MT91L62 3 V single rail Codec incorporates a built-in Filter/Codec, transmit anti-alias filter, a reference voltage and bias source. The device supports both A-law and µ-law requirements. The MT91L62 is a true 3 V device employing a fully differential architecture to ensure wide dynamic range. An analog output driver is provided, capable of driving a 20 k ohm load. The MT91L62 is fabricated in Zarlink's ISO2-CMOS technology ensuring low power consumption and high reliability. Applications • • • • Cellular radio sets Local area communications stations Line cards Battery operated equipment FILTER/CODEC GAIN VDD VSSA VBias VRef AIN+ ENCODER DECODER 6dB 0 dB Analog Interface AIN- AOUT + AOUT - Din Dout STB CLOCKin PCM Serial Interface Timing Control PWRST IC A/µ CSL0 CSL1 CSL2 RXMute TXMute Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2004, Zarlink Semiconductor Inc. All Rights Reserved. MT91L62 Data Sheet VBias VRef PWRST IC A/µ RXMute TXMute CSL0 CSL1 CSL2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AIN+ AINVSS AOUT + AOUT VDD CLOCKin STB Din Dout 20 PIN PDIP/SOIC/SSOP Figure 2 - Pin Connections Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 Name VBias VRef Description Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µ F capacitor to VSS. Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.1] volts. Used internally. Connect 0.1 µ F capacitor to VSS. Internal Connection. Tie externally to VSS for normal operation. A/µ Law Selection. CMOS level compatable input pin governs the companding law used by the device. A-law selected when pin tied to VDD or µ-law selected when pin tied to VSS. PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low). IC A/µ RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation. CMOS level compatable input. TXMute Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation. CMOS level compatable input. CSL0 CSL1 CSL2 Dout Clock Speed Select. These pins are used to program the speed of the SSI mode as well as the conversion rate between the externally supplied MCL clock and the 512 KHz clock required by a filter/codec. Refer to Table 2 for details. CMOS level compatable input. Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1 device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot defined by STB. Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the falling edge of BCL during the timeslot defined by STB. CMOS level compatable input. Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatable input. 12 13 Din STB 14 CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions. Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin when the bit clock is 128 kHz or 256 kHz. CMOS level compatable input. VDD AOUTAOUT+ VSS Positive Power Supply. Nominally 3 volts. Inverting Analog Output. (balanced). Non-Inverting Analog Output. (balanced). Ground. Nominally 0 volts. 15 16 17 18 2 Zarlink Semiconductor Inc. MT91L62 Pin Description (continued) Pin # 19 20 Name AinAin+ Description Inverting Analog Input. No external anti-aliasing is required. Data Sheet Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required. Overview The 3 V Single-Rail Codec features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/Codec) and an analog interface to a standard analog transmitter and receiver (analog Interface). The receiver amplifier is capable of driving a 20 k ohm load. Functional Description Filter/Codec The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion. The Filter/Codec block also implements a transmit audio path gain in the analog domain. Figure 3 depicts the nominal half-channel for the MT91L62. The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 3 volt supply design. This fully differential architecture is continued into the Analog Interface section to provide full chip realization of these capabilities for the external functions. A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it may be used for biasing external gain setting amplifiers. A 0.1 µF capacitor must be connected from VBias to analog ground at all times. Likewise, although VRef may only be used internally, a 0.1 µF capacitor from the VRef pin to ground is required at all times. The analog ground reference point for these two capacitors must be physically the same point. To facilitate this the VRef and VBias pins are situated on adjacent pins. The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a second order lowpass implementation with a corner frequency at 25 kHz. The receive filter is designed to meet ITU-T G.714 specifications. Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate. Companding law selection for the Filter/Codec is provided by the A/µ companding control pin. Table 1 illustrates these choices. ITU-T (G.711) µ-Law 1000 0000 1111 1111 0111 1111 0000 0000 Code + Full Scale + Zero -Zero (quiet code) - Full Scale A-Law 1010 1010 1101 0101 0101 0101 0010 1010 Table 1 - Law Selection 3 Zarlink Semiconductor Inc. MT91L62 Analog Interfaces Standard interfaces are provided by the MT91L62. These are: • • Data Sheet The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 2.123 Vpp µ−law across AIN+/AIN- and 2.2 Vpp A-law across these pins. The analog outputs (receiver), pins AOUT+/AOUT-. This internally compensated fully differential output driver is capable of driving a load of 20 k ohms. PCM Serial Interface A serial link is required to transport data between the MT91L62 and an external digital transmission device. The MT91L62 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly referred to as Simple Serial Interface (SSI). The bit clock rate is selected by setting the CSL2-0 control pins as shown in Figure 2. Quiet Code The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the TxMute pin is high. When either of these pins are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet code definition. External Clock Bit Rate (kHz) 128 256 512 1536 2048 4096 CLOCKin (kHz) 4096 4096 512 1536 2048 4096 CSL2 1 1 0 0 0 0 CSL1 0 0 0 0 1 1 CSL0 0 1 0 1 0 1 Table 2 - Bit Clock Rate Selection SSI Mode The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6. In SSI mode the MT91L62 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel data are always in the channel defined by the STB input. The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This is an active high signal with an 8 kHz repetition rate. SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is 512 kHz or greater then it is used directly by the internal MT91L62 functions allowing synchronous operation. If the available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal MT91L62 functions. 4 Zarlink Semiconductor Inc. MT91L62 Data Sheet Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT91L62 will re-align its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control pins CSL2, CSL1 and CSL0 are used to program the bit rates. For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input. Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation. For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation since the bit cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the PCM serial circuit for asynchronous operation. Refer to the specifications of Figures 5 & 6 for both synchronous and asynchronous SSI timing. PWRST While the MT91L62 is held in PWRST no device control or functionality is possible. Serial Port Filter/Codec and Analog Interface Default Bypass Aout + Decoder Receive Filter Gain 0 dB 0 dB Receiver Driver 20kΩ PCM Din Aout- PCM Dout Transmit Gain Encoder 6 dB AIN+ AIN- Analog Input Internal To Device External To Device F igure 3 - Audio Gain Partitioning 5 Zarlink Semiconductor Inc. MT91L62 Applications Figure 4 shows an application of the MT91L62 in a line card. VBias Data Sheet 0.1 µF Input from Subscriber Line Interface 0.1 µF 0.1 µF 100k 100k 1k 100k 1k 100k 1k 100k CS0 1k 100k CS1 1k 100k 1k CS2 Din Dout Timing Frame Pulse Block Clock A/µ RxMUTE TxMUTE 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 +3V Output to Subscriber Line Interface +3V MT91L62 Figure 4 - Line Card Application 6 Zarlink Semiconductor Inc. MT91L62 Absolute Maximum Ratings† Parameter 1 2 3 4 Supply Voltage Voltage on any I/O pin Current on any I/O pin (transducers excluded) Storage Temperature Symbol VDD - VSS VI/VO II/IO TS - 65 Min. - 0.3 VSS - 0.3 Max. 5 Data Sheet Units V V mA °C mW VDD + 0.3 ± 20 + 150 750 5 Power Dissipation (package) PD † Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 2 3 4 Supply Voltage CMOS Input Voltage (high) CMOS Input Voltage (low) Operating Temperature Voltages are with respect to VSS unless otherwise stated. Sym. VDD VIHC VILC TA Min. 2.7 0.9*VDD VSS - 40 Typ. 3 Max. 3.6 VDD 0.1*VDD + 85 Units V V V °C Test Conditions Power Characteristics Characteristics 1 2 Static Supply Current (clock disabled) Dynamic Supply Current: Total all functions enabled Sym. IDDC1 IDDFT Min. Typ. 2 6 Max. 20 10 Units µA mA Test Conditions Outputs unloaded, Input signals static, not loaded See Note 1. Note 1: Power delivered to the load is in addition to the bias current requirements. 7 Zarlink Semiconductor Inc. MT91L62 DC Electrical Characteristics† - Voltages are with respect to ground (VSS) Characteristics 1 2 3 4 5 6 Input HIGH Voltage CMOS inputs Input LOW Voltage CMOS inputs VBias Voltage Output VRef Output Voltage Input Leakage Current Positive Going Threshold Voltage (PWRST only) Negative Going Threshold Voltage (PWRST only) Hysteresis Output HIGH Current Output LOW Current Output Leakage Current Output Capacitance Input Capacitance Sym. VIHC VILC VBias VRef IIZ VT+ VT0.65 IOH IOL IOZ Co Ci 1.0 2.5 0.01 15 10 10 2.2 0.7 VDD/2 VDD/2-1.1 unless otherwise stated. Data Sheet Min. 0.7*Vdd Typ.‡ Max. Units V Test Conditions 0.3*Vdd V V V µA V V V mA mA µA pF pF VOH = 0.9*VDD See Note 1 VOL = 0.1*VDD See Note 1 VOUT = VDD and VSS Max. Load = 10 kΩ No load VIN=VDD to VSS Vdd=3V 0.1 10 7 8 9 10 11 † DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note 1 - Magnitude measurement, ignore signs. Clockin Tolerance Characteristics† Characteristics 1 CLOCKin Frequency (Asynchronous Mode) Min. 4095.6 Typ.‡ 4096 Max. 4096.4 Units. kHz Test Conditions (i.e., 100 ppm) † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 8 Zarlink Semiconductor Inc. MT91L62 Data Sheet AC Characteristics† for A/D (Transmit) Path - 0 dBm0 = ALo3.17 - 3.17 dB = 1.027 Vrms for µ-Law and 0 dBm0 = ALo3.14 - 3.14 dB =1.06 7Vrms for A-Law, at the Codec. (VRef=0.4 volts and VBias=1.5 volts.) Characteristics 1 Analog input equivalent to overload decision Absolute half-channel gain M ± to Dout 3 Gain tracking vs. input level ITU-T G.714 Method 2 Signal to total Distortion vs. input level. ITU-T G.714 Method 2 Transmit Idle Channel Noise Gain relative to gain at 1020 Hz 4600 Hz Absolute Delay Group Delay relative to DAX GAX1 GTX 5.4 -0.3 -0.6 -1.6 35 29 24 13 -70.5 16 -69 -25 -30 0.0 0.25 0.25 0.25 0.25 -12.5 -25 -25 6.0 6.6 0.3 0.6 1.6 dB dB dB dB dB dB dB dBrnC0 dBm0p dB dB dB dB dB dB dB dB dB dB µs µs µs µs µs at frequency of minimum delay 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz ±100mV peak signal on VDD µ-law Sym. ALi3.17 ALi3.14 Min. Typ.‡ 4.246 4.4 Max. Units Vp-p Vp-p Test Conditions µ-Law A-Law Both at Codec Transmit filter gain=0dB setting. @1020Hz 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0 µ-Law A-Law 2 4 DQX 5 6 NCX NPX GRX -45 -0.25 -0.9 -0.9 -1.2 -0.2 -0.6 -23 -41 360 750 380 130 750 7 8 DAX DDX 9 Power Supply Rejection f=1020 Hz PSSR 30 50 dB † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 9 Zarlink Semiconductor Inc. MT91L62 Data Sheet AC Characteristics† for D/A (Receive) Path - 0 dBm0 = ALo3.17 - 3.17 dB = 1.027 Vrms for µ-Law and 0 dBm0 = ALo3.14 - 3.14 dB =1.067 Vrms for A-Law, at the Codec. (VRef=0.4 volts and VBias=1.5 volts.) Characteristics 1 1 2 3 Analog output at the Codec full scale Analog output at the CODEC full scale. Absolute half-channel gain. Din to HSPKR± Gain tracking vs. input level ITU-T G.714 Method 2 Signal to total distortion vs. input level. ITU-T G.714 Method 2 Receive Idle Channel Noise Gain relative to gain at 1020 Hz 200 Hz 300 - 3000 Hz 3000 - 3300 Hz 3300 Hz 3400 Hz 4000 Hz 4600 Hz >4600 Hz Absolute Delay Group Delay relative to DAR Sym. ALo3.17 ALo3.14 ALo3.17 ALo3.14 GAR1 GTR -0.6 -0.3 -0.6 -1.6 35 29 24 11.5 -80 14 -77 0.25 0.25 0.25 0.25 0.25 -12.5 -25 -25 Min. Typ.‡ 4.183 4.331 4.183 4.331 0 0.6 0.3 0.6 1.6 Max. Units Vp-p Vp-p Vp-p Vp-p dB dB dB dB dB dB dB dBrnC0 dBm0p dB dB dB dB dB dB dB dB µs µs µs µs µs -74 -80 dB dB at frequency of min. delay 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz G.714.16 ITU-T Test Conditions µ-Law A-Law µ-Law A-Law @1020Hz 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0 µ-Law A-Law 4 GQR 5 6 NCR NPR GRR -0.25 -0.90 -0.9 -0.9 -0.1 -0.5 -23 -41 240 750 380 130 750 -90 -90 7 8 DAR DDR 9 Crosstalk D/A to A/D A/D to D/A CTRT CTTR † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Electrical Characteristics† for Analog Outputs Characteristics 1 2 Output load impedance Allowable output capacitive load Sym. EZL ECL Min. 20k 20 Typ.‡ Max. Units ohms pF Test Conditions across AOUT± each pin: AOUT+, AOUT- † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 10 Zarlink Semiconductor Inc. MT91L62 Electrical Characteristics† for Analog Inputs Characteristics 1 Maximum input voltage without overloading Codec across AOUT+/AOUTVIOLH 2.128 2.20 Vp-p Vp-p A/µ = 0 A/µ = 1 Sym. Min. Typ.‡ Max. Units Data Sheet Test Conditions 2 Input Impedance ZI 50 kΩ Ain+/Ain† Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. to VSS AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 5) Characteristics 1 BCL Clock Period 2 BCL Pulse Width High 3 BCL Pulse Width Low 4 BCL Rise/Fall Time 5 Strobe Pulse Width 6 Strobe setup time before BCL falling 7 Strobe hold time after BCL falling 8 Dout High Impedance to Active Low from Strobe rising 9 Dout High Impedance to Active High from Strobe rising 10 Dout Active Low to High Impedance from Strobe falling 11 Dout Active High to High Impedance from Strobe falling 12 Dout Delay (high and low) from BCL rising 13 Din Setup time before BCL falling 14 Din Hold Time from BCL falling Sym. tBCL tBCLH tBCLL tR/tF tENW tSSS tSSH tDOZL tDOZH tDOLZ tDOHZ tDD tDIS tDIH 10 50 70 80 Min. 244 115 122 122 20 8 x tBCL tBCL-80 tBCL-80 55 55 90 90 80 Typ.‡ Max. 1953 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL=50 pF, RL=1K CL=50 pF, RL=1K CL=50 pF, RL=1K CL=50 pF, RL=1K CL=50 pF, RL=1K Test Conditions BCL=4096 kHz to 512 kHz BCL=4096 kHz BCL=4096 kHz Note 1 Note 1 † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. NOTE 1: Not production tested, guaranteed by design. 11 Zarlink Semiconductor Inc. MT91L62 tBCL tF Data Sheet tBCLH tR CLOCKin 70% (BCL) 30% tBCLL tDIS Din 70% 30% tDOZL Dout 70% 30% tDOZH tSSS STB 70% 30% NOTE: Levels refer to % VDD (CMOS I/O) tENW tSSH tDOLZ tDOHZ tDD tDIH Figure 5 - SSI Synchronous Timing Diagram AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 6) Characteristics 1 Bit Cell Period 2 Frame Jitter 3 Bit 1 Dout Delay from STB going high 4 Bit 2 Dout Delay from STB going high 5 Bit n Dout Delay from STB going high Sym. TDATA Tj tdda1 tdda2 tddan 600+ TDATA-Tj 600 + (n-1) x TDATA-Tj TDATA-Tj TDATA\2 +500ns-Tj +(n-1) x TDATA TDATA\2 +500ns+Tj +(n-1) x TDATA 600+ TDATA 600 + (n-1) x TDATA Min. Typ.‡ 7812 3906 600 Tj+600 600 + TDATA+Tj 600 + (n-1) x TDATA+Tj TDATA+Tj Max. Units ns ns ns ns ns ns CL=50 pF, RL=1K CL=50 pF, RL=1K CL=50 pF, RL=1K n=3 to 8 Test Conditions BCL=128 kHz BCL=256 kHz 6 Bit 1 Data Boundary 7 Din Bit n Data Setup time from STB rising TDATA1 tSU ns ns n=1-8 8 Din Data Hold time from STB rising tho ns † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. NOTE 1:Not production tested, guaranteed by design. 12 Zarlink Semiconductor Inc. MT91L62 Data Sheet Tj STB 70% 30% tdda2 tdha1 tdda1 70% 30% Bit 1 TDATA1 tho tsu Bit 2 Bit 3 TDATA Dout Din 70% 30% TDATA/2 D1 TDATA D2 TDATA D3 NOTE: Levels refer to % VDD (CMOS I/O) Figure 6 - SSI Asynchronous Timing Diagram 3 2 1 E1 E n-2 n-1 n D A2 L A C eA B1 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) e B α Plastic Dual-In-Line Packages (PDIP) - E Suffix 13 Zarlink Semiconductor Inc. MT91L62 8-Pin DIM Min A A2 B B1 C D D1 E E1 e e1 eA L S α NOTE: ( ) Millimeters Pin 1 Data Sheet 18-Pin Plastic 20-Pin Plastic Max 0.210 (5.33) 0.115 (2.93) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 0.845 (21.47) 0.005 (0.13) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 0.925 (23.49) 0.115 (2.93) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 0.925 (23.49) 0.005 (0.13) 0.330 (8.38) 0.280 (7.11) 0.290 (7.37) 0.240 (6.10) 0.330 (8.38) 0.280 (7.11) 16-Pin Plastic Max Min Max 0.210 (5.33) 0.115 (2.93) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 0.745 (18.93) 0.005 (0.13) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 0.840 (21.33) Plastic Min Min Max 0.210 (5.33) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 1.060 (26.9) 0.210 (5.33) 0.115 (2.93) 0.014 (0.356) 0.045 (1.15) 0.008 (0.204) 0.348 (8.84) 0.005 (0.13) 0.290 (7.37) 0.240 (6.10) 0.330 (8.38) 0.280 (7.11) 0.195 (4.95) 0.022 (0.558) 0.070 (1.77) 0.015 (0.381) 0.430 (10.92) 0.290 (7.37) 0.240 (6.10) 0.330 (8.38) 0.280 (7.11) 0.290 (7.37) 0.240 (6.10) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.300 BSC (7.62) 0.115 (2.93) 0.160 (4.06) 0.300 BSC (7.62) 0.115 (2.93) 0.160 (4.06) 0.300 BSC (7.62) 0.115 (2.93) 0.160 (4.06) 0.300 BSC (7.62) 0.115 (2.93) 0.160 (4.06) 15° 15° 15° 15° F E A C L H e D G 4 mils (lead coplanarity) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) O1 & O2 are SYMMETRY dimensions 5) A & B Maximum dimensions include allowable mold flash L A1 B 14 Zarlink Semiconductor Inc. MT91L62 16-Pin Min 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.398 (10.1) 0.291 (7.40) Data Sheet DIM A A1 B C D E e F G H L 18-Pin Min 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.447 (11.35) 0.291 (7.40) 20-Pin Min 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.496 (12.60) 0.291 (7.40) 24-Pin Min 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.598 (15.2) 0.291 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.614 (15.6) 0.305 (7.75) Min 28-Pin Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.712 (18.1) 0.305 (7.75) Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.413 (10.5) 0.305 (7.75) Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.469 (11.90) 0.305 (7.75) Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.518 (13.00) 0.305 (7.75) 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.697 (17.7) 0.291 (7.40) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) 0.064 (1.625) 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) 0.064 (1.625) 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) 0.064 (1.625) 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) 0.064 (1.625) 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) 0.064 (1.625) 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) Lead SOIC Package - S Suffix 15 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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