MV1442DPAS

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ MV1442 HDB3 Encoder/Decoder/Clock Regenerator DS3077 ISSUE 4.0 July 2001 The MV1442, along with other devices in the Zarlink 2Mbit PCM signalling series comprise a group of circuits which will perform the common channel signalling and error detection functions for a 2.048Mbit PCM transmission link operating in accordance with the appropriate CCITT recommendations. The circuits are fabricated in CMOS and operate from a single +5V supply with all inputs and outputs being TTL compatible. The MV1442 is an encoder/decoder for the HDB3 pseudoternary transmission code, described in Annex A of CCITT Recommendation G.703. The device encodes and decodes simultaneously and asynchronously. Error monitoring functions are provided to detect violations of the HDB3 coding, all ones detection and loss of input (all zeros detection) In addition a loop back function is provided for terminal testing. The MV1442 may be selected to function in either internal or external clock recovery modes. Internal clock recovery mode may be selected tor either 1.544MHz or 2.048MHz operation and in this mode an external 16.384MHz crystal (12.352MHz for 1.544MHz operation) is required. External clock recovery mode may be selected for 1.544MHz, 2.048MHz or 8.448MHz operation. Ordering Information MV1442/IG/DPAS DIL plastic package MV1442/IG/MPES Miniature plastic package MV1442/IG/MPEG Miniature plastic (tape and reel) NRZ DATA IN ENCODER CLOCK LOSS OF INPUT NRZ DATA OUT DECODER CLOCK RESET AIS AIS MODE GND 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD TXD2 TXD1 RXD2 LOOP TEST ENABLE RXD1 CRYSTAL OUT/CDR DOUBLE VIOLATION CRYSTAL IN DP18 Features • On-chip Digital Clock Regenerator • HDB3 Encoding and Decoding to CCITT Recommendation G.703 • Asynchronous Operation • Simultaneous Encoding and Decoding • Clock Recovery Signal allows Off-chip Clock Regeneration • Loop Back Control • HDB3 Error Monitor • ‘All Ones’ Error Monitor • Loss of Input Alarm • Low Power Operation • 2.048MHz or 1.544MHz Operation in External or Internal Clock Recovery mode • 8.448MHz Operation in External Clock Recovery mode NRZ DATA IN ENCODER CLOCK LOSS OF INPUT NRZ DATA OUT DECODER CLOCK RESET AIS AIS MODE GND 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD TXD2 TXD1 RXD2 LOOP TEST ENABLE RXD1 CRYSTAL OUT/CDR DOUBLE VIOLATION CRYSTAL IN MP18 (WIDE BODY) Figure 1 - Pin connections – top view Absolute Maximum Ratings VDD Inputs Outputs Storage temperature -0.5V to +7V VDD -0.5V to GND -0.5V VDD -0.5V to GND -0.5V -55°C to +125°C MV1442 NRZ DATA IN ENCODER CLOCK MODE CRYSTAL CRYSTAL IN OUT/CDR ENCODER CLOCK REGENERATOR DECODER CLOCK RXD 1 LOOP TEST ENABLE RXD 2 COUNTER DECODER ERROR CIRCUIT AIS CIRCUIT LOSS OF INPUT NRZ DATA OUT AIS TXD 1 TXD 2 DOUBLE VIOLATION RESET AIS Figure 2 - Block diagram Functional Descriptions High Density Bipolar 3 (HDB3) is a pseudo-ternary transmission code in which the number of consecutive zeros which may occur is restricted to three to allow adequate clock recovery at the receiver. In any sequence of four consecutive binary zeros the last zero is substituted by a mark of the same polarity as the previous mark, thus breaking the Alternate Mark Inversion (AMI) code. This mark is termed a violation. In addition, the first zero may also be substituted by a mark if the last mark and last violation are of the same polarity. This mark does not violate the AMI code and ensures that successive violations alternate in polarity and as such introduce no DC component to the HDB3 signal. The MV1442 consists of three main blocks: the HDB3 Encoder, the HDB3 Decoder and the Clock Regenerator. The function of each block is now described separately. and as such this alarm can be used as an ‘all ones’ detector. The decoding process and all the alarm circuitry is synchronised to the clock signal being input to this block on the DECODER CLOCK pin. This clock signal may be asynchronous with the ENCODER CLOCK signal. The timing diagrams of the HDB3 Decoder and alarm circuitry are shown in Figures 4 to 7. In addition to the normal mode of operation, a loop test mode is available for terminal testing. This mode is selected by taking the LOOP TEST ENABLE input high. In this mode the HDB3 encoded pseudo-ternary data outputs of the Encoder block are fed back as the inputs to the Decoder block, which in turn decodes this data and outputs it in NRZ form. Clock Regenerator HDB3 Encoder The HDB3 Encoder is responsible for converting the incoming NRZ data into pseudo-ternary form for transmission over a PCM link. This conversion is carried out in accordance with the HDB3 coding laws specified in CCITT Recommendation G. 703 The data to be encoded is input on the NRZ DATA IN pin and the encoding process is synchronised to the clock signal being input on the ENCODER CLOCK pin. The two TXD outputs TXD1 and TXD2. represent the HDB3 data in pseudo-ternary form. If a mark is to be transmitted, the output goes high after the rising edge of the clock. The length of the pulse is set by the positive clock pulse width. The timing diagram of the HDB3 Encoder is shown in Figure 3. The Clock Regenerator block has two possible modes of operation. With the MODE pin high, internal crystal controlled clock regeneration is selected, whereas with the MODE pin low external clock regeneration is selected using, for example, a tuned circuit. In external clock regeneration mode, a logically ORed version of the HDB3 data, from the RXD inputs, is output to the external clock regeneration circuitry on the CRYSTAL OUT/CDR pin. The regenerated clock is then fed back into the MV1442 on the DECODER CLOCK pin External clock regeneration may be used for operation with data rates of 1.544Mbits, 2.048Mbits or 8.448Mbits. In internal clock regeneration mode, the logically ORed data is input to a digital regenerator which constantly resynchronises a divide-by-8 counter to the incoming data stream. The clock thus regenerated is output to the decoder circuitry and to any external circuitry on the DECODER CLOCK pin. A crystal of frequency 8 times the required data rate must be connected between the CRYSTAL IN and CRYSTAL OUT/CDR pins. Thus, the crystal frequency needs to be 16.384MHz or 12.352MHz for data rates of 2.048Mbits or 1.544Mbits respectively. Internal clock regeneration may not be used for operation at a data rate of 8.448Mbits. The MV1442 is capable of withstanding up to 0.25UI of peak to peak input jitter at a jitter frequency of 2.048MHz without introducing errors into the decoded data. At lower jitter frequencies the MV1442 is capable of withstanding much larger values to peak to peak input jitter. In the HDB3 Decoder The HDB3 Decoder is responsible for decoding the HDB3 pseudo-ternary data on its inputs RXD1 and RXD2 into NRZ form to be output on the NRZ DATA OUT pin. In addition to this, the decoder circuit provides three alarm outputs. The first of these alarms is DOUBLE VIOLATION. As its name suggests, a logic high on this output denotes that two successive violations have been received with the same polarity, thus violating the HDB3 coding laws. The second alarm, LOSS OF INPUT, is used to denote that 11 consecutive zeros have been received on the RXD inputs. The final alarm output is AIS (all ones) This alarm goes high if less than 3 decoded zeros have been detected in the preceding RESET AIS = 1 period (i.e. between RESET AIS = 0 pulses) 2 MV1442 absence of input jitter the MV1442 will produce an output jitter waveform in the form of a sawtooth ramping between 0UI and 0.125UI. The period of this waveform will be dependent upon the difference in frequencies between the remote transmitter’s clock and the crystal controlled clock of the MV1442. The MV1442 was originally designed as a pin compatible replacement for the MV1441 with a much improved internal clock recovery circuit and allowing operation at 8.448MHz with external clock recovery selected. ENCODER CLOCK NRZ DATA IN 4·5 CLOCK PERIODS TXD1 B B B V TXD2 B B V NOTES 1. The encoded HDB3 outputs, TXD1 and TXD2. are delayed dy 4·5 clock periods with respect to NRZ DATA IN. 2. B is an HDB3 mark, V is an HDB3 violation. Figure 3 - Encoder waveforms RXD1 B B V B B B RXD2 B B B B CDR DECODER CLOCK 5 CLOCK PERIODS NRZ DATA OUT NOTES 1. The decoded NRZ output is delayed by 5 clock periods with respect to the HDB3 inputs. 2. The diagram assumes the last violation occured on RXD2. 3. B is an HDB3 mark, V is an HDB3 violation. Figure 4 - Decoder waveforms RXD1 B B V B V V RXD2 DECODER CLOCK DOUBLE VIOLATION B B B 1 CLOCK PERIOD NOTES 1. There is a single clock period delay from detection of an error and the rising edge of DOUBLE VIOLATION 2. The diagram assumes the last violation occured on RXD2. 3. B is an HDB3 mark, V is an HDB3 violation. Figure 5 - HDB3 double violation waveforms 3 MV1442 RXD1 RXD2 DECODER CLOCK LOSS OF INPUT 1 2 3 4 5 6 7 8 9 10 11 1 CLOCK PERIOD NOTE The LOSS OF INPUT output is delayed by one clock period with respect to the incoming HDB3 waveform Figure 6 - Loss of input waveforms DECODER CLOCK NRZ DATA OUT RESET AIS AIS Figure 7 - AIS and RESET AIS waveforms Pin 1 2 3 Signal name NRZ DATA IN ENCODER CLOCK LOSS OF INPUT Description Input pin for data to be encoded into pseudo-ternary HDB3 form. This data is clocked into the Encoder block by the falling edge of ENCODER CLOCK. Clock input for the encoding of data on pin 1. Output from the loss of input circuit This output goes high one clock period after the detection of eleven consecutive zeros on the decoder inputs. Any logic ‘1’ at the input (RXD1 or RXD2=0) resets this count after a single clock period delay. NRZ data output obtained from the decoding of the pseudo-ternary inputs to the Decoder block. Clock input to the Decoder block for decoding data on RXD1 and RXD2 or TXD1 and TXD2 in loop test mode. In internal clock regeneration mode, this pin is used to output the regenerated clock to external circuitry. In external clock regeneration, mode this pin is used to input the externally regenerated clock signal direct to the Decoder block. Reset input to the decoded zero counter A logic ‘0’ on this input resets a decoded zero counter. It will also reset the AIS output to ‘0’ provided 3 or more zeros have been decoded in the preceding RESET AIS = 1 period or set AIS to 1 if less than 3 zeros have been decoded in the preceding RESET AIS = 1 period This may be used to indicate loss of timeslot zero. A logic ‘1’ on this pin enables the decoded zero counter. Output from AIS circuit (see description for pin 6). Input pin for selection of clock regeneration mode. A logic high on this input selects internal crystal controlled clock regeneration while a logic low selects external clock regeneration. Digital ground 0V. Table 1 - Pin descriptions Contd… 4 5 NRZ DATA OUT DECODER CLOCK 6 RESET AIS 7 8 9 AIS MODE GND 4 MV1442 Pin 10 Signal name CRYSTAL IN Description Input to crystal oscillator amplifier when in internal clock regeneration mode with the crystal connected between pins 10 and 12. Alternatively this pin may be used as the 16384/ 12.352MHz input to the internal clock regeneration circuitry if one oscillator is shared between several decoders. This pin has no function when external clock regeneration is selected and should in that case be tied to GND. Output from the error detector circuit. This output goes high for one period of Decoder clock one period after the detection of an HDB3 violation of the same polarity as the previous HDB3 violation. In external clock regeneration mode, this pin is used to output the OR function of the two HDB3 inputs RXD1 and RXD2 (or TXD1 and TXD2) if loop test mode is selected; to an external clock regeneration circuit in internal clock regeneration mode. This is the output which forms the crystal oscillator with pin 10. HDB3 input to Decoder block. This input asynchronously latches the incoming HDB3 encoded data and is falling edge sensitive. Input pin for selection of normal or loop back operation. A logic ‘0’ on this pin selects normal operation with encoder and decoder being independent and asynchronous. A logic ‘1’ on this pin internally connects TXD1 to RXD1 and TXD2 to RXD2. Note that in loop back mode a decoder clock must be supplied (or regenerated from pin 12 along with the encoder clock. HDB3 input 2 to Decoder block. See pin 13 description. HDB3 encoded output from Encoder block. This output goes high after the rising edge of clock if a mark is to be transmitted. The length of the pulse is set by the positive clock puIse width. HDB3 encoded output 2. See pin 16 description. Digital supply voltage. 5V±10%. Table 1 - Pin descriptions (continued) 11 DOUBLE VIOLATION 12 CRYSTAL OUT/CDR 13 14 RXD1 LOOP TEST ENABLE 15 16 RXD2 TXD1 17 18 TXD2 VDD Electrical Characteristics TAMB = -40°C to +85°C, VDD = +5V±0·5V These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Static Characteristics Characteristic Symbol Min. Low level input voltage High level input voltage Low level output voltage High level output voltage VIL VIH VOL VOHT VOHC Input leakage current Supply current (note 1) IIN IDD 2·4 VDD21 -10 +200 15 5 15 Input capacitance Output capacitance CIN COUT 5 5 0 2 Value Typ. Max. 0·8 VDD 0·4 V V V V V µA mA mA mA pF pF ISINK = 2mA ISOURCE = 2mA ISOURCE = 1mA VIN = VDD or GND 1.544/2.048MHz, with internal clock regeneration 1.544/2.048MHz, with external clock regeneration 8.448MHz operation All inputs All outputs Units Conditions NOTES 1. All supply currents are specified with outputs unloaded. These currents are not tested but are guaranteed by characterisation and a static current test. 5 MV1442 Electrical Characteristics TAMB = 0°C to +70°C, VDD = +5V±0·5V These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Dynamic Characteristics Characteristic Clock period Clock rise/fall time Clock high/low time Encoder data setup time Encoder data hold time TXD1/TXD2 output propagation delay CDR propagation delay RXD1/RXD2 data setup time RXD1/RXD2 pulse width Decoder output propagation delay RESET AIS hold off time RESET AIS pulse width RESET AIS setup time AIS output propagation delay Symbol Min. tCPF tCR/tCF tCH/tCL tEDS tEDH tEPDR/tEPDF tCPDR/tCPDF tRS tRW tOPD tRAHO tRAW tEDH tAPO 10 15 10 45 15 20 45 30 10 10 45 40 100 20 Value Typ. Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 8 9 9 9 10 10 10 10 10 10 10 10 2 2, 3 2 2 Units Figure Note TAMB = -40°C to +85°C, VDD = +5V±0·5V These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Dynamic Characteristics Characteristic Clock period Clock rise/fall time Clock high/low time Encoder data setup time Encoder data hold time TXD1/TXD2 output propagation delay CDR propagation delay RXD1/RXD2 data setup time RXD1/RXD2 pulse width Decoder output propagation delay RESET AIS hold off time RESET AIS pulse width RESET AIS setup time AIS output propagation delay Symbol Min. tCPF tCR/tCF tCH/tCL tEDS tEDH tEPDR/tEPDF tCPDR/tCPDF tRS tRW tOPD tRAHO tRAW tEDH tAPO 15 20 15 55 20 25 50 35 20 20 50 45 100 20 Value Typ. Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 8 9 9 9 10 10 10 10 10 10 10 10 2 2,3 2 2 Units Figure Note Electrical Characteristics NOTES 2. All propagation delays are measured with the relevant output loaded with a 50pF capacitor. 3. tOPD applies to outputs NRZ DATA OUT, LOSS OF INPUT and DOUBLE VIOLATION but does not apply to AIS. 6 MV1442 tCH ENCODER/DECODER CLOCK tCR VIH VIL tCL tCF tCP Figure 8 - Clock timing parameters ENCODER CLOCK tEDH NRZ DATA IN tEDS TXD1/TXD2 tEPDR tEPDF VIH VIL VIH VIL VOHT VOL Figure 9 - Encoder timing parameters tRW RXD1/RXD2 tCPDR CDR tRS DECODER CLOCK tOPD NRZ DATA OUT/ LOSS OF INPUT/ DOUBLE VIOLATION RESET AIS tAPD AIS VOHT VOL VOHT VOL VIH VIL VIH VIL tCPDF VOHT VOL tRAHO tRAW tRAS VIH VIL Figure 10 - Decoder timing parameters 7 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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