MV6001B0DG

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ MV6001 ADVANCE INFORMATION DS3138-2.1 MV6001 HDLC/DMA CONTROLLER The MV6001 is a combined HDLC transceiver and DMA controller capable of providing serial communications at rates up to 128K bits/second, and handling direct memory access clock rates up to 8MHz. GND A0 A1 A2 A3 A4 A5 A6 A7 GND TST A8/D0 A9/D1 A10/D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 VCC MRD MWR MR BRQ BAK CS DMACK RD WR MODE TXOP TCK RCK RXIP AEN ASB RINT TINT TOP2 FEATURES s s s s s s s Data Rates up to 128K Bits/s DMA Rate up to 8MHz Low Power CMOS Simple Interfacing to Popular 8-Bit Processors Frame Length up to 2K Bytes Low Host-Processor Overhead Conforms to ECMA40 and Related Standards (CCITT X25, X75, 1.440, ISO3309, ANSI X3.66, FED-STD 1003, FIPS71) MV6001 31 30 29 28 27 26 25 24 23 22 21 APPLICATIONS s ISDN Terminals s LANs s X25 p.s.s. Networks A11/D3 A12/D4 A13/D5 A14/D6 A15/D7 ORDERING INFORMATION MV6001 B0 DP (Commercial Plastic DIP) MV6001 B0 DG (Commercial Ceramic DIP) GND DP40 DG40 Figure 1: Pin connections - top view OP TOP2 TINT TCK RINT RXIP RCK TX DMA RX REGISTERS ADDRESS/ DATA BUS ADDRESS BUS BRQ ASB MRD CS MODE MWR AEN BAK TFL TA S C RFL RMFL RA A8/D0, A15/D7 A0, A7 WR RD MR TST Figure 2: Block diagram 1 MV6001 PIN DESCRIPTION Pin No. 1,10,20 2-9 11 12-19 21 22 Name GND A0 - A7 TST A8/D0- A15/D7 TOP2 TINT I/O I I/O O O I/O Function 0V supply. All 3 pins must be connected. Address Bus. Output for memory A0 - A7 addressing. Input for register addresses A0- A3. Test Enable. Tie to GND for normal operation. Data Bus/High Order Address. Multiplexed data and address bus. Transmitter Out. Alternative output to TXOP. This output is not affected by loop back (see Operating Notes - LOOPBACK). Transmitter Interrupt. An interrupt is generated whenever transmission of a frame is ended, either following the last FCS byte of a complete frame of when an abort sequence is transmitted. The interrupt is reset by the control register. Receiver Interrupt. An interrupt is generated whenever a frame is received. The interrupt is reset by the counter register. Address Strobe. Strobes the Address High byte from the Data/Address Bus into an external latch. Address Enable. Enables the external address latch. Receiver Input. Serial HDLC data input, clocked in by RCK. Receiver Data Clock. Provides clock to the receiver section, frequency should be at the required data rate, this need not necessarily the the same as the transmit data rate. Transmitter Data Clock. This input provides a clock signal for the transmitter section and should be set to the desired transmit data rate. Transmitter output. Main transmitter output for serial data. Bus Control Mode Select. Controls the polarity of BAK and BRQ. MODE = VCC gives active LOW, MODE = GND gives active HIGH. Write Register. Loads data from data bus into register addressed by A0- A3. Read Register. Reads addressed register onto data bus DMA Clock. This input provides clock to the DMA section. The DMA clock rate should be at least ten times the sum of the transmit and receive data rates. Chip Select. Enables RD and WR inputs. Bus Acknowledge. Input from processor relinquishing control of bus. See pin 30, Bus Mode Select. Bus Request. Output to processor requesting the bus for a DMA cycle. See pin 30, Bus Mode Select. Master Reset. Resets everything. Memory Write. This is a three-state output to write data into memory during DMA cycles. Memory Read. 3-state output to read data from memory during DMA cycles. ±5V ±10% supply. 23 24 25 26 27 RINT ASB AEN RXIP RCK O O O I I 28 29 30 31 32 33 34 35 36 37 38 39 40 TCK TXOP MODE WR RD DMACK CS BAK BRQ MR MWR MRD VCC I O I I I I I I O I O O 2 MV6001 USER FIELDS ≤2047 BYTES 01111110 FLAG START ADDRESS 1 OR N* BYTES CONTROL 1 OR 2 BYTES DATA FRAME CHECK SEQUENCE 2 BYTES 01111110 FLAG FINISH MV6001 GENERATED *N is any integer Figure 3 Fig.3 shows the construction of an HDLC frame. The start and finish of the frame are determined by FLAGS (the binary pattern 01111110). To prevent spurious recognition of flags in the user fields, the transmitter automatically inserts a ‘0’ after five successive ‘1 ‘s. The inserted ‘0’s are removed by the receiver, and hence are not seen by the user. Each HDLC frame contains a 2 byte frame check sequence produced by a cyclic redundancy generator in the transmitter. This sequence is checked by the receiver to validate the frame. There are two other sequences which have specific meanings - IDLE and ABORT. The IDLE state is the transmission of at least 15 continuous ‘1’s without inserted zeros. ABORT is 7 to 14 consecutive ‘1’s without inserted zeros sandwiched between two zeros. at any time to start transmission. Once a transmission has been started, the only way it can by stopped is to set the abort bit (D1). The transmitter will then transmit the abort sequence followed by flags. Transmitter reset (D2) resets the transmitter interrupt TINT, clears the TA and TFL registers and bits D0 and D1 of the status register. Transmitter reset is disabled during a transmission. INTERRUPT A transmitter interrupt (TINT) is generated whenever a transmission ceases, the status register can then be read to check if the frame was aborted or not. The interrupt is reset by writing a transmitter reset to the control register. NB. The status register must be read before a transmitter reset as this will alter the contents of the status register. STATUS The transmitter has two status bits - transmitting data (Do) and abort (D1) The transmitting data bit should always be low after TINT signifying that transmission is ended. The abort bit will be high whenever a frame is aborted either by an abort instruction to the control register, or internally due to an underrun . RECEPTION The receiver accepts serlal data, removes inserted zeros and checks the frame check sequence. For each byte of data received, the receiver section generates a DMA request to transfer the data to memory. If the DMA controller fails to make the transfer before the next request from the receiver, then the receiver will drop out and give a receiver. interrupt with the code in the status register for overrun. If the number of bytes received reaches the number in the receive maximum frame length registerthe receiverwilldropoutand give an interrupt with the code in the status register for frame too long. INITIALISATION The RA register (2 bytes) is loaded with the address where the first received byte of data is to be stored. The RMFL register (11 bits) is loaded with the maximum number of bytes in the user fields plus 3 bytes ( +2 bytes for the FCS, +1 byte because an interrupt will occur when the frame length is equal to the length set by the number in the register) . FUNCTIONAL DESCRIPTION The MV6001 consists of four main sections; transmitter, receiver, DMA unit and register bank. Each of the transminer~ receiver and DMA unit have their own clocks running at the required data rates. There are no restrictions on the relative timing between transmit and receive clocks, the DMA clock rate should be greater than ten times the sum of the transmit and receive clock rates. TRANSMISSION In its steady state the transmitter produces a continuous stream of FLAGS until the control register is loaded with a transmit instruction. The transmitter then, at intervals, requests the DMA unit to fetch a byte of data. This is then transferred from the system memory via the data bus to the transmitter. (If the DMA unit should fail to fetch a byte of data by the time the next request arrives then an under-run will occur and the transmitter will transmit an ABORT sequence). Data is converted into a serial stream with inserted zeros after five ones, and the 16-bit frame check sequence is appended at the end of each frame. As soon as the last bit of the FCS has been clocked out, the TINT OUtPUt goes low to inform the processor that transmission has ended. INITIALISATION To start transmission, two items of information are required - the start address for the data to be transmitted, and the length of the user fields are loaded into the TA and TFL registers respectively, after which the transmit enable bit (D0) can be set 3 MV6001 CONTROL The receiver has two control bits in the control register, receive enable (D3) and receive reset (D4). Once the RA and RMFL registers have been loaded, the receive enable bit can be set at any time to allow the receiver to receive a frame. Once set, the receive enable bit cannot be overwritten and receive reset is disabled until a frame has been received. Receiver reset will reset the RlNT interrupt bit, registers RFL, RMFL, RA and bits D2 - D7 of the status register. INTERRUPT A receive interrupt (RINT) is generated whenever a frame is received. The status register can then be read to check the status of the received frame. The interrupt is reset by writing a receiver reset to the control register. Since the reset will clear the receiver bits in the status register, the register must be read before writing the reset to the control register. STATUS The receiver uses bits D2 - D7 of the status register (see Figs. 5 and 6). A valid frame is indicated by both ‘overrun’ (D6) and ‘frame too long’ (D7) bits being high. Following RINT the ‘free to receive’ bit (D2) should be low, indicating that a frame has been received. The abort, overrun and long frame bits will be set according to the state of the frame received. The flag (D4) and idle (D3) bits monitor the incoming signal continuously even when the receiver is disabled. 2 FCS bytes in the count. The reqister should be read before a receiver reset. LOOPBACK Bit D7 of the control register, the loopback bit is provided for testing purposes. When the bit is set high an internal connection is made between the transmitter output and receiver input. The main transmitter output (TXOP) transmits IDLE (transmitted data is always available on TOP2). The receiver is clocked from TCK. The loopback bit will respond to every write to the control register. DIRECT MEMORY ACCESS (FIG.11) All data transfers to or from memory are carried out by the DMA controller. Each time it receives a request from the transmitter or receiver it will carry out one DMA cycle, i.e. only one byte is transferred at a time. Clashes between transmitter and receiver are resolved in favour of the receiver, otherwise operation is on a first come, first served basis. REGISTERS Fig.7 shows the addresses for the various instruction and status registers. All registers are readable from and writable to except for S, C and RFL. The S and C registers have the same address, which one is accessed is determined by whether a read (status) or write (control) operation is carried out. Transmitter registers should not be written to when transmitting (except to ABORT a frame), likewise receiver registers should not be written to when receiving. The TA and RA registers update continuously during transmission and reception respectively, giving the next address to be read from or written to. FRAME LENGTH REGISTER Having received a frame and read the status reqister, the received frame length can be read from the RFL register. The frame length is given as an eleven bit number and includes the D7 LOOPBACK ENABLE D6 DON'T CARE D5 DON'T CARE D4 RECEIVE RESET D3 RECEIVE ENABLE D2 TRANSMIT RESET D1 TRANSMIT ABORT D0 TRANSMIT ENABLE Figure 4: Control register D7 RECEIVED FRAME TOO LONG D6 RECEIVED OVERRUN FRAME D5 RECEIVED ABORT D4 RECEIVING FLAGS D3 RECEIVING IDLE D2 FREE TO RECEIVE D1 TRANSMISSION ABORTED D0 TRANSMITTING DATA RECEIVE BITS TRANSMIT BITS Figure 5: Status register 4 MV6001 Status Register D7 X X X X X X X 0 0 1 1 D6 D5 D4 D3 X X X X X X X 0 1 0 1 X X X X X X X 1 0 0 0 X X X X 0 0 1 X X X X X X X X 0 1 0 X X X X D2 X X X 1 X X X 0 0 0 0 D1 0 0 1 X X X X X X X X D0 1 0 0 X X X X X X X X Condition Currently transmitting data Transmitter disabled, transmission COMPLETE (status read after an interrupt) Transmitter disabled, transmission ABORTED (status read after an interrupt) Receiver enabled, free to receive Currently receiving data Receiving IDLE Receiving FLAGS Receiver disabled, ABORTED frame received (status read after an interrupt) Receiver disabled, OVERRUN frame received (status read after an interrupt) Receiver disabled, TOO LONG frame received (status read after an interrupt) Receiver disabled, VALID frame received (status read after an interrupt) Figure 6: Status interrupt Regisler Function Length (Bits) 8 3 8 8 8 8 8 3 8 3 8 8 Address (Hex) 2 3 6 7 9 9 A B C D E F A3 A2 A1 A0 R/W TFL Transmitter Frame Length LS Byte Transmitter Frame Length MS Byte Transmitter Address LS Byte Transmitter Address MS Byte Status Control Receiver Frame Length LS Byte Receiver Frame Length MS Byte Receiver Maximum Frame Length LS Byte Receiver Maximum Frame Length MS Byte Receiver Address LS Byte Receiver Address MS Byte 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 1 0 1 0 1 0 1 R/W R/W R/W R/W R W R R R/W R/W R/W R/W TA S C RFL RMFL RA Figure 7: Register addresses 5 MV6001 trs MR 2V Figure 8(a) Figure 6(a) tsu th DATA STABLE 2V 0.8V 2V CLOCK Figure 6(b) Figure 8(b) DATA td 2V 0.8V th CLOCK 2V 0.8V Figure 8(c) Figure 6(c) DATA td 2V 0.8V th CLOCK 2V 0.8V Figure 6(d) Figure 8(d) Figure 8: Timing diagram 6 MV6001 INPUT OF DATA 2V 0.8V tsu th D0-7 WR 2V Figure 7(a) Figure 9(a) D0-7 td 2V 0.8V th RD 2V Figure 9(b)7(b) Figure Figure 9: Register timing 2V DATA ADDRESS td STABLE 0.8V DMA CLOCK 2V Figure 10: DMA timing 7 MV6001 DMACK BRQ BAK A0-A7 D0-D7 ASB AEN *MRD *MWR A8-A15 A0-A7 D0-D7 } SHOWN IN ACTIVE LOW MODE Figure 11: DMA cycle timing *During a read cycle, MWR stays high and similarly during a write cycle MRD stays high. All other external signals are the same for both cycles. ABSOLUTE MAXIMUM RATINGS Supply voltage VCC Input voltage VIN Output voltage VOUT Clamp diode current per pin IK (See Note 2) Static discharge voltage Storage temperature Ts Ambient temperature with power applied Tamb -0.3V to 7.0V -0.3V to VCC +0.3V -0.3V to VCC +0.3V ±18mA -65°C to +150°C -40°C to +85°C NOTES 1. Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied 2. Maximum dissipation of 1 second should not be exceeded, only one output to be tested at any one time ELECTRICAL CHARACTERISTICS These characteristics are guaranteed over the following conditions (unless othetwise stated): Tamb = -40°C to +85°C, VCC = 5.0V ±10%, Ground = 0V STATIC CHARACTERISTICS Value Typ Characterislic Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current VCC current Output leakage current Output S/C current Symbol VOH VOL VIH VIL IL I CC lOZ lOS Mln. VCC-2 Max. Unlts V V V V µA mA µA mA Conditions IOH = 0.8mA I OL = 1 .6mA 0.4 2.2 -10 -50 15 0.8 +10 1 +50 80 GND ≤ VIN ≤ VCC Tamb = -40°C to +85 °C GND ≤ VOUT ≤ VCC VCC = Max 8 MV6001 SWITCHING CHARACTERISTICS Value Characteristic Maximum DMA clock frequency Maximum TX clock frequency Maximum RX clock frequency Minimum MR duration RXIP to RCK set-up time RXIP to RCK hold time BAK to DMACK set-up time BAK to DMACK hold time Delay DMA clock to MRD Delay DMA clock to MWR Delay RCK ⇓ to RINT Delay, TCK to TINT Delay, TCK ⇑ or RCK ⇓ to BRQ Delay, DMACK to AEN Delay, DMACK to ASB Delay, TCK to TXoP Delay, TCK to ToP2 Hold, DMACK to MRD Hold, DMACK to MWR Hold, DMACK to BRQ Hold, DMACK to AEN Hold, DMACK to ASB Data to WR set-up WR to data hold RD to data delay RD to data hold DMACK to data/address delay SymboI FDMACK FTCK FRCK trs tsu th tsu th td td td td td td td td td th th th th th tsu th td th td 60 50 0 90 0 25 40 40 50 60 70 40 40 70 60 90 50 60 30 40 55 55 55 55 110 90 90 55 55 115 115 130 75 Min. 8 128 128 Typ. Max. Units MHz kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Fig.8(a) Fig.8(b) Fig.8(b) Fig.8(b) Fig.8(b) Fig.8(c) Fig.8(c) Fig.8(d) Fig.8(c) Fig.8(c) & (d) Fig.8(c) Fig.8(c) Fig.8(c) Fig.8(c) Fig.8(d) Fig.8(d) Fig.8(d) Fig.8(d) Fig.8(d) Fig.9(a) Fig.9(a) Fig.9(b) Fig.9(b) Fig.10 Conditions 9 MV6001 HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O.Box 660017, 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel (408) 438 2900 Fax: (408) 438 5576 CUSTOMER SERVICE CENTRES • FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07 • GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 • ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 • JAPAN Tokyo Tel: (3) 5276-5501 Fax: (3) 5276-5510 • NORTH AMERICA Integrated Circuits and Microwave Products, Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061. • SOUTH EAST ASIA Singapore Tel: 2919291 Fax: 2916455 • SWEDEN Johanneshov Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 • UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. © GEC Plessey Semiconductors 1993 Publication No. DS 3138 Issue No. 2.1 September 1993 This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. 10 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE