PX5410

PX5410 Multi-Rate VCSEL Driver Product Brief January 2004 Description 4 PX5 10 Features • • • • • • • • Up to 4.25 Gb/s serial VCSEL driver Single +3.3 V supply Average power control (APC) provides constant output optical power Digital diagnostics provided with bias, photodiode, and temperature monitors Independent temperature compensation for VCSEL bias and modulation current VCSEL fault protection limits output optical power for laser safety Differential CML compatible inputs with on-chip termination 4 mm x 4 mm QFN package The growing use of the Internet and the increasing demand for storage area network (SAN) solutions has created the need for next generation physical layer ICs. In addition the introduction of 4 G Fiber Channel (4GFC) has introduced the need for next generation ICs to be backwards compatible with 1 G and 2 G Fiber Channel. The Zarlink PX5410 provides a multi-rate VCSEL driver solution for 1, 2, and 4GFC. The Zarlink PX5410 Multi-Rate VCSEL Driver is designed for various applications up to 4.25 Gb/s. It consists of a DC-coupled amplifier with adjustable modulation and bias currents optimized for driving commercially available VCSEL-based transmit optical sub assemblies (TOSAs) from a single +3.3 V supply. VCSEL modulation and bias currents can be programmed by a variety of means including external resistors, programmable potentiometers, SFF-8472 controllers, or microcontroller DAC outputs. Selectable temperature compensation and closed-loop average power control deliver optimized optical output power and extinction ratio over temperature. Applications • • • SFP, SFF form factors 4GFC, 2GFC, 1GFC, OC-48, Gigabit Ethernet Proprietary intra-system optics 1 Zarlink Semiconductor Inc. PX5410 Product Brief Figure 1: Filtered 4.25 Gb/s optical output with a PRBS7 data pattern Interrupt +3.3V Temp Sensor Figure 2: Typical APC closed-loop configuration using TOSA monitor photo diode to provide constant VCSEL output power. Modulation current temperature compensation also enabled to improve extinction ratio across operating temperatures. * Disable Tx_Flt Tx_Dis VCC VCC VCC TC_Mod TC_Bias VTherm GND Tx_Bias Tx_Out Tx_Bias GND Monitor Transmission Line TOSA VCSEL Anode VCSEL Cathode Data_P Data_N Tx_In_P Tx_In_N GND Bias_Mon PD Cathode Pwr_Mon RSafe RMod RBias RPower Comp TOSA PD monitor Interrupt +3.3V Temp Sensor Figure 3: Typical open-loop configuration with internal temperature compensation enabled for bias and modulation currents. * Disable Tx_Flt Tx_Dis VCC VCC VCC TC_Mod TC_Bias VTherm Tx_Bias Transmission Line GND TOSA VCSEL Anode VCSEL Cathode Data_P Data_N Tx_In_P Tx_In_N GND Tx_Out Tx_Bias GND Monitor Bias_Mon VCSEL bias monitor PD Cathode Pwr_Mon RSafe RMod RBias RPower Comp * See Table 2 for temperature compensation configurations 2 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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