SL1935NP1Q

SL1935 Single Chip Synthesized Zero IF Tuner April 2004 Features • • • • • • • • • Single chip synthesised tuner solution for quadrature down conversion, L-band to Zero IF. DVB compliant, operating dynamic range -70 to -20dBm. Compatible with DSS and DVB variable symbol rate applications. Selectable baseband path, programmable through I2C bus. Excellent quadrature balance up to 30MHz baseband Excellent immunity to spurious second harmonic (RF and LO) mixing effects. Low oscillator phase noise and reradiation. High output referred linearity for low distortion and multi channel application. Integral fast mode compliant I2C bus controlled PLL frequency synthesiser, designed for high comparison frequencies and low phase noise performance. Buffered crystal output for clocking QPSK demodulator. ESD protection (Normal ESD handling procedures should be observed). Ordering Information SL1935D/KG/NP1P (Tubes) 36 pin SSOP SL1935D/KG/NP1Q (Tape and Reel) 36 pin SSOP Description The SL1935 is a complete single chip I2C bus controlled Zero IF tuner and operates from 950 to 2150MHz. It includes an on-board low phase noise PLL frequency synthesiser and low noise LNA/AGC. The SL1935 is intended primarily for application in digital satellite Network Interface Modules and performs the complete tuner function. The device contains all elements necessary, with the exception of local oscillator tuning network and crystal reference, to produce a high performance I(n-phase) & Q(uadrature) downconversion tuner function. Due to the high signal handling design the device does not require any front end tracking filters. The SL1935 includes selectable baseband signal paths, allowing application with two externally definable filter bandwidths, facilitating application in variable symbol rate and simulcast systems. The SL1935 is optimised to interface with the VP310 (ADC/QPSK/FEC) Satellite Channel Decoder, available from Zarlink Semiconductor and offers a full front end solution. • • Applications • • Satellite receiver systems. Data communications systems. XTALCAP XTAL SDA SCL BUFREF VCCD VCC RF RFB VCC IFIA IFIB VCC OFIA OFIB VEE IOUT ADD 1 36 18 19 PUMP DRIVE PORT P0 VEE TANKS TANKSB VEE TANKV TANKVB VEE IFQA IFQB VCC OFQA OFQB VEE QOUT AGCCONT Figure 1. Pin connections 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003 - 2004, Zarlink Semiconductor Inc. All Rights Reserved. SL1935 RFB RF 8 9 AGCCONT 19 23 OFQA AGC Sender 22 OFQB 26 IFQA 25 IFQB 20 QOUT 90deg BS 17 IOUT RF Section VCC 7,10,13,24 VCCD 6 VEE 16,21,27,30,33 TANKV 29 TANKVB 28 VCOV TANKS 32 TANKSB 31 VCOS 15 bit Programmab le Divider Fpd Charge Pump Divide by 2 RF section PLL section Frequency Agile Phase Splitter 11 IFIA 12 IFIB 0deg 14 OFIA 15 OFIB 36 PUMP 35 DRIVE PLL Section VS BS SDA 3 SCL 4 ADD 18 REF OSC I2C Bus Interface 34 POR T P0 Fpd/2 Reference Divider 5 BUFREF Fcomp XTAL 2 XTALCAP 1 Figure 2. Block diagram 2 SL1935 Table 1. Quick Reference Data Characteristic Value Units MHz dBm dB dB dB dBm dBm dBm V dB deg dB dBc/Hz dBm dBc dBc MHz dBc/Hz 950 to 2150 Operating range -75 to -15 Input dynamic range 10 VSWR with input match Input NF 10 @ -70dBm operating sensitivity 15 @ -60dBm operating sensitivity +5 IPIP3 @ -20dBm operating sensitivity +20 IPIP2@ -20dBm operating sensitivity -5 IPP1dB@ -20dBm operating sensitivity 2.0 Baseband output limit voltage 0.2 Gain match up to 22MHz 0.7 Phase match up to 22MHz 1 Gain flatness up to 30MHz Local oscillator phase noise -80 SSB at 10kHz offset 4.25V 10 0 0 0.5 1 1.5 2 2.5 3 AGCCONT Voltage (V) 3.5 4 4.5 5 Figure 4. AGC characteristic (typical) 120 System input referred IP3 (dBuV) 110 100 90 80 70 60 20 25 30 35 40 45 50 55 60 65 70 System gain (dB) assuming 6dB interstage filter loss Figure 5. Variation in IIP3 with system gain (typical) 170 System input referred IP2 (dBuV) 160 Baseband dominated IP2 150 140 130 LNA dominated IP2 120 110 100 20 25 30 35 40 45 50 55 System gain (dB) assuming 6dB interstage filter loss 60 65 70 Figure 6. Variation in IIP2 with system gain (typical) 8 SL1935 110 Converter input referred P1dB (dBuV) 105 100 95 90 85 80 75 70 65 60 -10 -5 25 10 0 5 30 35 15 20 Converter gain seting (dB) from RF inputs OFIA/OFQA or OFIB/OFQB outputs 40 45 Figure 7. Variation in P1dB with converter gain (typical) 60 50 Noise figure (dB) 40 30 20 10 0 20 25 30 35 40 45 50 55 60 System gain (dB) assuming 6dB interstage filter loss 65 70 75 80 Figure 8. Variation in NF with system gain (typical) BB837 1kΩ BB837 4mm STRIPLINE 6 Tanks "vcos" 2kΩ 4mm STRIPLINE 7 Tanksb Vcnt BB831 10mm STRIPLINE 9 Tankv "vcov" 10 NOTE: Stripline width = 0.44mm (dimensions are approximate) 2kΩ 1kΩ BB831 10mm STRIPLINE Tankvb Figure 9. Local oscillator application circuit 9 SL1935 LO Frequency (MHz) 900 -70 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 -72 Phase noise @ 10kHz offset (dBc/Hz) vcos enabled -74 vcov enabled -76 -78 -80 -82 -84 -86 -88 Conditions: Loop filter as per standard application shown in Figure 21 Charge pump = 130uA Fcomp = 65.5kHz or 125kHz -90 Figure 10. Local oscillator phase noise variation with frequency (typical) +j1 +j0.5 +j2 3 +j0.2 x x 4 +j5 2x 0 0.2 1 0.5 x 1 2 5 Marker 1 2 3 4 —j5 Freq (MHz) 1 10 20 30 Z real Ω 17 18 22 33 Z imag Ω 0 19 38 60 —j0.2 —j0.5 —j2 —j1 START 1MHz Normalised to 50Ω STOP 30MHz Figure 11. Converter output impedance; OFIA, OFIB, OFQA, OFQB (typical) +j1 +j0.5 +j2 +j0.2 +j5 X4 0 0.2 X3 X2 X1 0.5 1 2 5 X Marker 1 2 3 4 —j5 Freq (MHz) 0.1 10 20 30 Z real Ω 9.5 10.0 10.6 12.6 Z imag Ω -2.0 1.3 3.3 5.5 —j0.2 —j0.5 —j2 —j1 START 100kHz Normalised to 50Ω STOP 30MHz Figure 12. Baseband output impedance; IOUT, QOUT (typical) 10 SL1935 100nF OFIA/OFIB OFQA/OFQB 1k Ω 100nF IFIA/IFIB IFQA/IFQB 1k Ω 3.9pF Figure 13. Example baseband interstage filter for 30MS/s 220nF 100 Ω 1k Ω 15pF Figure 14. Nominal baseband output load test condition 1 XTALCAP 150pF 82pF 4MHz 2 XTAL Figure 15. Crystal oscillator application (typical) 11 SL1935 1pF 33 Ω RFIN 100pF 8 RF 2.2pF 100pF 9 RFB Figure 16. Input matching network Table 10. Electrical Characteristics Test conditions (unless otherwise stated); Tamb = -20o to +80o Vee= 0V, Vcc =Vccd = 5V+-5%. C, These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Supply current RF input operating frequency SYSTEM System noise figure DSB Variation in system NF with gain adjust System input referred IP2 Variation in system input referred IP2 with operating sensitivity System input referred IP3 Variation in system input referred IP3 with operating sensitivity Pin Min 6,7,10 13,24 8,9 Value Typ 130 950 Max 175 2150 mA MHz All system specification items should be read in conjunction with Note 2 dB At -70dBm operating sensitivity dB At -60dBm operating sensitivity dB/dB Above –60dBm operating sensitivity, (Fig.7) dBµV At –20dBm operating sensitivity, see Notes 3 and 4 (Fig.6) dBµV At -20dBm operating sensitivity, see Note 5 (Fig.5) VCCD (PLL) and VCC Units Conditions 10 15 12 17 -1 121 140 112 SL1935 Continued 12 SL1935 Table 10. Electrical Characteristics (Continued) Characteristic System dynamic range -70 -20 System gain roll off System gain variation with temperature System I Q gain match System I Q phase balance System I and Q channel in band ripple System baseband path gain match LO second harmonic interference level LNA second harmonic interference level Synthesiser and other spurii on I and Q outputs In band leakage to RF input CONVERTER Converter input impedance Converter input return loss System input referred P1dB 3 2 17,20 17,20 17,20 -1 -3 +1 +3 1 +1 -50 -35 17,20 76 dBm dBm dB dB dB deg dB dB dBc dBc Note 8. Note 9. Pin Min Value Typ Max Note 6 AGCCONT = 0.75V AGCCONT = 4.25V Within RF band 950-2150MHz -20˚C to +80˚C Interstage filter (Fig.13) Interstage filter (Fig.13) Interstage filter (Fig.13) Units Conditions -1 8,9 -60 dBµV Within 0-100MHz band under all gain settings, RF input set to deliver 108dBµV on output dBm Within RF band 950-2150MHz. Note 11. Ω dB With input matching (Fig.16) dBµV Converter gain =-5dBm (to OFIA/ OPQA, OFIB/OPQB outputs. Fig.7) Ω 0.1 to 30MHz (Fig.11) dBc Relative to selected output 8,9 8,9 75 8 102 25 -26 50 Converter output impedance, OFIA, 14,15 OFIB, OPQA and OPQB. 22,23 Conver ter output leakage to unselected output, OFIA, OFIB, OPQA and OPQB. Oscillator VCOS operating range 31,32 Oscillator VCOV operating range Local oscillator SSB phase noise 28,29 1900 1450 -78 3000 AGCONT input current BASEBAND AMPLIFIERS Baseband input impedance, IFIA, IFIB, IFQA And IFQB. Resistance Capacitance Baseband unselected input leakage to output Baseband amplifier output impedance Baseband output limiting Baseband bandwidth 1dB Baseband output roll-off 19 -150 Giving LO = 950 to 1500MHz (Application as in Fig.9) 2150 MHz (Application as in Fig.9) dBc/Hz @10kHz offset, PLL loop bw < 1kHz Application is measured at baseband output frequency of 10MHz (Fig.10). 150 µA The baseband inputs must be externally ac coupled 0.1- 30MHz bandwidth MHz 11,12 25,26 10 17,20 17,20 17,20 17,20 2.0 40 6 5 -40 20 kΩ pF dBc Ω Relative to selected input. Vp-p Level at hard clipping (load as Fig.14) MHz (Load as Fig.14) dB/oct Above 3dB point, no load Continued 13 SL1935 Table 10. Electrical Characteristics (Continued) Characteristic SYNTHESISER SDA,SCL Input high voltage Input low voltage Input high current Input low current Leakage current Hysterysis SDA output voltage SCL clock rate Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency Recommended crystal series resistance External reference input frequency External reference drive level Phase detector comparison frequency Equivalent phase noise at phase detector Local oscillator programmable divider division ratio Reference division ratio Output port P0 Sink current Leakage current BUFREF output Output amplitude Output impedance Address select Input high curent Input low current Notes to Table 10 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. All power levels are referred to 75Ω, and 0dBm = 109dBµV. System specifications refer to total cascaded system of converter/AGC stage and baseband amplifier stagewith nominal 6dB pad as interstage filter and load impedance as detailed in Figure 14. Baseband dominated IP2. AGC set for 20dB system gain with two tones for intermodulation test at fc+146and fc+155MHz at 100dBµV generating output intermodulation spur at 9MHz. 30MHz 3dB bandwidthinterstage filter included. LNA dominated IP2. AGC set for 20dB system gain with two tones for intermodulation test at fc+146 and2*fc+155 MHz at 100dBµV generating output intermodulation spur at 9MHz. 30MHz 3dB bandwidthinterstage filter included. AGC set for 20dB system gain with two tones for intermodulation test at fc+110 and fc+211MHz at 100dBµVgenerating output intermodulation spur at 9MHz. 30MHz 3dB bandwidth interstage filter included. Dynamic range assuming termination as detailed in Figure 14, and including 6 dB interstage filter insertion loss, delivering 700mVp-p at baseband outputs (pins 17,20). AGC monotonic from Vee to Vcc (Fig.4). Port powers up in high impedance state. The level of 2.01GHz downconverted to baseband relative to 1.01GHz with the oscillator tuned to 1GHz,measured with no input pre-filtering. The level of second harmonic of 1.01GHz input at –25dBm downconverted to baseband relative to 2.01GHz at–40 dBm with the oscillator tuned to 2GHz, measured with no input pre-filtering. If the BUFREF output is not used it should be left open circuit or connected to Vccd, and disabled by settingRE = ‘0’. This parameter is very application dependant. With good RF isolation