SP5654-KG-MPAD

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS FEBRUARY 1994 ADVANCE INFORMATION D.S. 3931 1.5 SP5654 2.7GHz 3–WIRE BUS CONTROLLED SYNTHESISER The SP5654 is a single chip frequency synthesiser designed for satellite TV tuning systems. It is a programming variant of the SP5655 allowing the design of one tuner with either I2C bus or a 3–wire bus format depending on which device is inserted. The device when used with a varicap tuner, forms a complete phase locked loop tuning system. The circuit consists of a divide–by–16 prescaler with its own preamplifier and a 14/15 bit programmable divider controlled by a serially loaded data register. Four independently programmable open collector outputs are included. The device contains five modes of operation each compatible with Toshiba 18 and 19 bit software. The comparison frequencies are obtained from a crystal controlled on–chip oscillator typically operating at 4MHz. The comparator has a charge pump output amplifier stage around which feedback may be applied. Only one external transistor is required for varicap line driving. CHARGE PUMP CRYSTAL MODE SELECT DATA CLOCK PORT P3 PORT P2 PORT P1 1 16 DRIVE OUTPUT VEE S P 5 6 5 4 RF INPUT RF INPUT VCC LOCK ENABLE PORT P0 FEATURES J Complete 2.7GHz Single Chip System J High Sensitivity RF Input J Low power Consumption (5V, 30mA) J On–Chip Oscillator with 1kW negative resistance J On chip oscillator start–up circuit J Programming Compatible with Toshiba TD6380, TD6381 and TD6382# J Pin compatible with SP5655# J 5 Modes of Operation with different step sizes, see Table 1; each selectable with 18 or 19 bit transmission length. J Single Port 18/19 Bit Serial Data Entry J Auto select for Data transmission length, 18 or 19 J Low Radiation J Phase Lock Detector J Varactor Drive Amp Disable J Charge Pump Disable J Four Controllable Outputs J ESD Protection [ # See notes on pin and programming compatibility [ Normal ESD handling procedures should be observed. MP16 Fig. 1 Pin connections – top view APPLICATIONS J Satellite TV J High IF Cable Tuning Systems ORDERING INFORMATION SP5654/KG/MPAS (Tubes) SP5654/KG/MPAD (Tape and Reel) SP5654 Tamb= –20°C to )80°C, VCC=)4.5V to )5.5V. Reference frequency =4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristics Supply current Prescaler Input Voltage ELECTRICAL CHARACTERISTICS Symbol ICC Pin 12 13, 14 Min 12.5 40 Typ 30 Max 40 300 300 Units mA mVrms mVrms W pF Conditions Typical applies to VCC = 5V 300MHz to 2GHz sinewave. 120MHz & 2.7GHz See Fig.6. Prescaler Input Impedance Input Capacitance Data Clock and Enable High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Hysteresis Clock Rate Timing Information Data Setup Time Data Hold Time Enable Setup time Enable Hold Time Clock–to–Enable Time Clock Low Period Clock High Period Mode Select High Level Input Current Low Level Input Current Charge Pump Output Current Charge Pump Output Current Charge Pump Output Leakage Current Charge Pump Drive Output Current Charge Pump Amplifier Gain Oscillator Temperature Stability Oscillator Stability with Supply Voltage Recommended Crystal Series Resistance Crystal Oscillator Drive Level Crystal Oscillator Negative Resistance Reference Crystal Frequency External Reference input Frequency External Reference input Amplitude tSU tHD tES tEH tCE tLO tHI 13, 14 50 2 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 5 4 4 10 10 10 5 5 3 0 VCC 1.5 10 –10 0.8 500 V V mA mA V kHz ns ns ns ns ns ns ns mA mA mA mA See Fig.4 See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4 VIN=5.5V VCC=5.5V VIN=0V VCC=5.5V 300 600 300 600 300 600 600 3 3 1 1 1 16 1 6400 150 50 700 –700 VIN=5.5V VCC=5.5V VIN=0V VCC=5.5V V pin 1 = 2.0V, device ‘out of lock’ V pin 1 = 2.0V, device ‘locked’ V pin 1 = 2.0V, charge pump disabled V pin 16 = 0.7V Pin 18 Current = 100mA 5 nA mA 2 2 10 200 ppm/°C ppm/V W ‘‘Parallel resonant crystal.” Figure quoted is under all conditions including start up. Includes temperature and process tolerances AC coupled sinewave AC coupled sinewave 2 2 2 2 2 750 4 2 400 80 mV p–p W 8 16 1000 MHz MHz mVp–p 2 SP5654 ELECTRICAL CHARACTERISTICS (cont.) Tamb= –20°C to )80°C, VCC=)4.5V to )5.5V. Reference frequency =4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristics Ports and Lock output Sink Current Lock Leakage Current Port Leakage Current Varactor Drive Amp Disable Charge Pump Disable Test Mode Enable 6–9, 11 11 6–9 10 4 5 –50 –50 –50 10 10 10 mA mA mA mA mA mA Vout=0.7V Vout=VCC Vout=13.2V Vpin 10 < 0V. Current sourced from device Vpin 4 < 0V. Current sourced from device Vpin 5 < 0V. Current sourced from device. See Table 2 Symbol Pin Min Typ Max Units Conditions ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE=0V Value Parameter Parameter Supply voltage Prescaler input voltage Prescaler DC offset Port voltage Pin Pin Min 12 13, 14 13, 14 6–9 –0.3 –0.3 –0.3 Total port output current Loop amplifier DC offset Crystal oscillator DC offset 3–wire bus inputs Mode select input Lock output voltage Lock output current Storage temperature Junction temperature MP16 thermal resistance, chip–to–ambient MP16 thermal resistance, chip–to–case Power consumption ESD protection All 4 6–9 1, 16 2 4, 5, 10 3 11 11 –55 –0.3 –0.3 –0.7 –0.3 –0.3 –0.3 Max 7 2.5 VCC+0.3 14 6 50 VCC+0.3 VCC+0.3 6 VCC+0.3 VCC+0.3 15 +150 +150 111 41 220 V Vp–p V V V mA V V V V V mA °C °C °C/W °C/W mW kV All ports off MIL STD 883 TM 3015 Port in off state Port in on state Units Units Conditions Conditions 3 SP5654 +j1 +j0.5 +j2 +j0.2 +j5 0 0.2 2.6GHz 0.5 1 2 5 X X X X X –j5 –j0.2 –j0.5 –j2 –j1 FREQUENCY MARKER STEP = 500MHz S11:Z0 = 50W NORMALISED TO 50W Fig. 2 Typical input impedance 13 RF INPUTS 14 PRE AMP PRESCALER 16 FPD 14/15 BIT PROGRAMMABLE DIVIDER PHASE COMP F REFERENCE DIVIDER FCOMP 512/640/1024 /1280/2048 OSC 12 VCC 2 CRYSTAL 1 5 CLOCK CHARGE PUMP DATA 18/19 LATCH CHARGE PUMP AMP DRIVE/ VARICAP OUTPUT 16 4 DATA DATA INPUT INTERFACE CLOCK 10 ENABLE MODE 3 MODE SELECT SELECT CONTROL OUTPUT BUFFER LOCK DETECT CP DIS VA DIS 15 VEE 6 78 9 P3 P2 P1 P0 11 LOCK Fig. 3 Block diagram 4 SP5654 FUNCTIONAL DESCRIPTION The SP5654 contains all the elements necessary, with the exception of reference crystal, loop filter and external high voltage transistor, to control a voltage controlled local oscillator, so forming a PLL frequency synthesised source. The system is controlled by a microprocessor via a standard data, clock and enable three–wire bus. The data load consists of a single word, which contains the frequency and port information, and is only transferred to the internal data shift register during an enable high period. The clock is disabled during low periods. New data words are only accepted by the internal data buffers from the shift register on a negative transition of the enable, so giving improved fine tuning facility for digital AFC etc. The device has 5 modes of operation, as defined in Table 1, and each of these modes can accept either 18–bit or 19–bit data entry. The format of the data entry is shown in Fig. 4, and consists of 4–bits for port switching, plus 14/15 bits to control the 15–bit programmable divider. For 18–bit data entry (4+14), the MSB of the 15–bit programmable divider is internally set to logic ‘0’ effectively making the divider 14–bits. The device recognises the data entry as 18–bit when a falling edge at the enable input occurs during the 18th clock period. The device associates falling enable edges during the 19th clock period with 19–bit data entry. A falling edge at the enable input before the 18th clock period constitutes invalid data entry to the device. The frequency is set by first selecting the required mode of operation as detailed in Table 1, and then by loading the programmable divider with the required 14/15–bit divisor word. The output of this divider, FPD, is fed to the phase comparator where it is compared in phase and frequency to the internally generated comparison frequency, FCOMP. The comparison frequency FCOMP is obtained by dividing the output of the on–chip crystal controlled oscillator. The crystal frequency generally used is 4MHz, giving an FCOMP of 7.8125kHz in mode 4, which when multiplied back up to the LO gives a minimum step size of 125kHz. The programmable divider is preceded by an input RF preamplifier and high speed low radiation prescaler. The preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The input impedance and sensitivity are shown in Fig. 2 and 6 respectively. The device contains a lock detect circuit which generates a flag when the loop has attained lock. The ‘in lock’ condition is indicated by a high impedance state. The charge pump current is initially set to 150mA. When the device attains frequency lock, the charge pump current is switched to 50mA, so improving the local oscillator short term jitter. The device also contains four general purpose open collector output ports P0–P3. These outputs are each capable of sinking a minimum of 10mA, when the appropriate bits P0–P3 of the programming data, see Fig. 4 are set to a logic ‘1’. PIN and PROGRAMMING COMPATIBILITY The SP5654 may be used in SP5655 applications which require 3–wire bus as opposed to I2C bus data format. In SP5655 applications where the reference crystal is grounded to pin 3, a small modification is required to ground the crystal as shown in Fig. 5. Appropriate connections must also be to the mode select input (see Table 1). For each mode of operation, the SP5654 is programming and step size compatible with Toshiba devices as shown in Table 3. TEST FEATURES Charge pump disable The charge pump may be disabled by sourcing current from the data input, i.e. by forcing a negative input voltage. Varactor line disable The charge pump amplifier drive output may be disabled by sourcing current from the enable input, i.e. by forcing a negative voltage. Device test mode Further test modes can be invoked by sourcing current from the clock input, i.e. by forcing a negative input voltage. These test modes when invoked are determined by the data held in the P1, P2 and P3 internal registers as detailed in Table 2. MODE ‘MODE SELECT’ INPUT VOLTAGE PROGRAMMABLE DIVIDER BIT LENGTH 14/15 14/15 14/15 14/15 14/15 REFERENCE DIVIDER RATIO *FREQUENCY STEP SIZE (kHz) 125 50 62.5 31.25 100 *MAXIMUM OPERATING FREQUENCY (GHz) 14 bit 15 bit 2.7000 1.6383 2.0479 1.0239 2.7000 2.0479 0.8191 1.0239 0.5119 1.6383 4 3 2 1 0 0.85 VCC – VCC 0.65 VCC – 0.75VCC # OPEN CIRCUIT 0.25 VCC – 0.35VCC [ 0 – 0.15 VCC 512 1280 1024 2048 640 *When used with a 4MHz crystal # Selected by connecting a 15kW resistor to VCC [ Selected by connecting a 15kW resistor to VEE Table 1. Modes of operation 5 SP5654 Test Mode 0 1 2 3 4 P1 0 0 1 1 d P2 0 0 0 0 1 P3 0 1 0 1 0 Test Mode Description Charge pump down 170mA Charge pump up 170mA Charge pump down 50mA Charge pump up 50mA FCOMP to P2; FPD/2 to P3; Lock output switched to out of lock condition Lock output switched to inlock condition 5 d 1 1 These test modes are invoked by taking the clock input below VEE d=don‘t care Table 2 Test mode options MODE 18 Bit Data entry 4 3 2 1 0 COMPATIBILITY 19 Bit Data entry TD6382 plus 4 prescaler TD6381 TD6382 plus 2 prescaler TD6382 TD6381 plus 2 prescaler TD6380 plus 2 prescaler None TD6380 None None Table 3. Programming compatibilities CLOCK ENABLE 18–BIT DATA ENTRY MSB 217 P0 216 P1 215 P2 214 P3 FREQUENCY DATA 19–BIT DATA ENTRY MSB 218 P0 217 P1 216 P2 215 P3 FREQUENCY DATA tCE tES 3V 1.5V t ES t SU t HD t CE t EH t LO t Hi =Enable set up time =Data set up time =Data hold time =Clock–to–enable time =Enable hold time =Clock low period =Clock high period tLO tHi tEH 214 213 22 21 20 LSB MSB IS TRANSMITTED FIRST 213 212 22 21 20 LSB CLOCK ENABLE 3V 1.5V DATA 3V 1.5V tSU tHD Fig. 4 Data format and timing 6 SP5654 +30V 47n 180n 22k 4MHz CRYSTAL 18p 2N3904 1 16 +5V +12V 22k 10k 47k VARICAP INPUT 10n 1n 1n OSCILLATOR OUTPUT 2 3 4 5 P3 CONTROL MICRO 6 7 8 15 S P 5 6 5 4 14 13 12 11 10 9 SATELLITE TUNER P0 P1 P2 TUNER SWITCHING FUNCTIONS Fig. 5 Typical application (step size = 100kHz) 300 100 VIN (mV RMS INTO 50W) 50 40 25 12.5 OPERATING WINDOW 120 300 1000 2000 2700 3000 3500 FREQUENCY (MHz) Fig. 6 Typical input sensitivity 7 SP5654 vREF 400 400 vCC CHARGE PUMP RF INPUTS 170 VADIS (o/p disable) DRIVE OUTPUT RF inputs Loop amplifier vCC 20k VCC 67k I/P I/P 3k 20k 3k Mode select input Data, Clock, Enable inputs VCC VCC OUTPUT CRYSTAL Reference oscillator Output ports P0–P3 and lock output Fig. 7. Input/Output interface circuits 8 SP5654 9 SP5654 10 SP5654 11 SP5654 PACKAGE DETAILS Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre. 9.80/.01 (0.386/0.394) 0.18/0.25 (0.007/0.010) 0.25/0.51 5.80/6.20 (0.010/0.020) 3.80/4.00 345 (0.150/0.157) (0.228/0.244) O 16 SPOT REF CHAMFER REF PIN 1 0–8 0.35/0.49 (0.014/0.0019) NOTES 0.69 (0.027) MAX 16 LEADS AT 1.27 (0.050) NOM SPACING 0.10/0.25 1.35/1.91 (0.004/0.010) (0.053/0.075) O 0.41/1.27 (0.016/0.050) 1. Controlling dimensions are inches. 2. This package outline diagram is for guidance only. Please contact your GPS Customer Service Center for further information. MINIATURE PLASTIC DIL – MP16 HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire United Kingdom SN2 2QW. Tel: (01793) 518000 Fax: (01793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067–0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 CUSTOMER SERVICE CENTRES F FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07 F GERMANY Munich Tel: (089) 3609 06 0 Fax: (089) 3609 06 55 F ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 F JAPAN Tokyo Tel: (03) 5276–5501 Fax: (03) 5276–5510 F NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023 F SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 F SWEDEN Stockholm Tel: 46 8 7029770 Fax: 46 8 6404736 F TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260 F UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 518510 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world–wide. E GEC Plessey Semiconductors 1995 Publication No. D.S. 3931 Issue No. 1.5 February 1995 TECHNICAL DOCUMENTATION – NOT FOR RESALE. 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No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE