SP5730

SP5730 1.3 GHz Low Phase Noise Frequency Synthesiser Data Sheet November 2004 Features • Complete 1·3 GHz Single Chip System for Digital Terrestrial Television Applications • Selectable Reference Division Ratio, Compatible with DTT Requirements • Optimised for Low Phase Noise, with Comparison Frequencies up to 4 MHz • No RF Prescaler • Selectable Reference/Comparison Frequency Output • Four Selectable I2C Addresses • I2C Fast Mode Compliant with 3·3V and 5V Logic Levels • Four Switching Ports • Functional Replacement for SP5659 (except ADC) • Pin Compatible with SP5655 • Power Consumption 120mW with VCC = 5·5V, all Ports off • ESD Protection 2kV min., MIL-STD-883B Method 3015 Cat.1 (Normal ESD handling procedures should be observed) Ordering Information SP5730A/KG/QP1T 16 Pin QSOP SP5730A/KG/QP1S 16 Pin QSOP SP5730A/KG/MP1S 16 Pin SOIC SP5730A/KG/MP2S 16 Pin SOIC* SP5730A/KG/QP2T 16 Pin QSOP* SP5730A/KG/MP1T 16 Pin SOIC SP5730A/KG/MP2T 16 Pin SOIC* SP5730A/KG/QP2S 16 Pin QSOP* *Pb Free Matte Tin Tape & Reel Tubes Tubes Tubes Tape & Reel Tape & Reel Tape & Reel Tubes prescaler phase noise degradation over the full RF operating range. The comparison frequency is obtained either from an on-chip crystal controlled oscillator, or from an external source. The oscillator frequency, fREF, or phase comparator frequency, fCOMP, can be switched to the REF/ COMP output providing a reference for a second frequency synthesiser. The synthesiser is controlled via an 12C bus and is fast mode compliant. It can be hard wired to respond to one of four addresses to enable two or more synthesisers to be used on a common bus. The device contains four switching ports P0 - P3. Applications • Digital Satellite, Cable and Terrestrial Tuning Systems • Communications Systems Absolute Maximum Ratings All voltages are referred to VEE = 0V Supply voltage, VCC -0·3V to +7V RF differential input voltage 2·5Vp-p All I/O port DC offsets -0·3 to VCC +0·3V SDA and SCL DC offset -0·3 to 6V Storage temperature -55°C to +150°C Junction temperature +150°C QP16 thermal resistance Chip to ambient, θJA 80°C/W Chip to case, θJC 20°C/W Description The SP5730 is a single chip frequency synthesiser designed for tuning systems up to 1·3GHz and is optimised for digital terrestrial applications. The RF preamplifier interfaces direct with the RF programmable divider, which is of MN1A construction so giving a step size equal to the loop comparison frequency and no 11 2 13 REF/COMP CRYSTAL CAP CRYSTAL CHARGE PUMP DRIVE RF INPUT 12-BIT COUNT REFERENCE DIVIDER ENABLE/ SELECT 3 14 48/9 3-BIT COUNT LOCK fPD/2 1 16 PUMP CP MODE DISABLE 15-BIT LATCH ADDRESS SDA SCL 10 4 5 2 BIT 5 BIT 2 BIT 2 BIT I2C BUS TRANSCEIVER 4-BIT LATCH AND PORT INTERFACE 6 7 8 9 fPD/2 SELECT P3 P2 P1 P0 Figure 1 - SP5730 block diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2004, Zarlink Semiconductor Inc. All Rights Reserved. SP5730 Datasheet CHARGE PUMP CRYSTAL CAP CRYSTAL SDA SCL PORT P3/LOGLEV PORT P2 PORT P1 1 2 3 4 5 6 7 8 16 15 14 SP 5730 13 12 11 10 9 DRIVE VEE RF INPUT RFINPUT VCC REF/COMP ADDRESS PORTP0 CHARGE PUMP CRYSTAL CAP CRYSTAL SDA SCL PORT P3/LOGLEV PORT P2 PORT P1 1 2 3 4 5 6 7 8 16 15 14 SP 5730 13 12 11 10 9 DRIVE VEE RF INPUT RFINPUT VCC REF/COMP ADDRESS PORTP0 MP16 Figure 2 - Pin connections - top view QP16 Test Conditions: TAMB = -40°C to +85°C, VCC = 4·5V to 5·5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Supply current RF input Input voltage Input impedance SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Input hysteresis SDA output voltage SCL clock rate Charge pump Output current Output leakage Drive output current Crystal Frequency External reference Input frequency Drive level Buffered REF/COMP Output amplitude Output impedance Phase Detector Comparison frequency Equivalent phase noise at phase detector RF division ratio Reference division ratio Pin 12 13,14 12·5 40 4,5 3 2·3 0 0 5·5 3·5 1·5 1 10 -10 10 0·4 0·6 400 ±3 ±10 Table 1 - Electrical Characteristics Min. Typ. 16 Max. 22 300 300 Units mA Conditions mVrms 100MHz to 1·3GHz, see Figure 3 mVrms 50MHz to 100MHz, see Figure 3 See Figure 4 V V V V µA µA µA V V V kHz 5V I2C logic selected 3·3V I2C logic selected 5V I2C logic selected 3·3V I2C logic selected Input voltage = VCC Input voltage = VEE VCC = VEE ISINK = 3mA ISINK = 6mA 0·4 4 5 1 1 16 2,3 3 2 0·2 11 0.35 250 4 -152 -158 56 32767 20 0·5 0·5 2 20 nA mA MHz MHz Vp-p Vp-p Ω See Table 7, VPIN1 = 2V VPIN1 = 2V, VCC = 15·0V, TAMB = 25°C VPIN16 = 0·7V See Figure 5 for application Sinewave coupled via 10nF blocking capacitor Sinewave coupled via 10nF blocking capacitor AC coupled, see Note 2 0·5 to 20MHz Enabled by bit RE = 1 MHz dBc/Hz fCOMP = 2MHz, SSB, See Note 4 dBc/Hz fCOMP = 125kHz, SSB, See Note 4 See Table 2 cont… 2 Datasheet Table 1 - Electrical Characteristics (continued) Value Characteristic Output Ports P3 - P0 Sink current Leakage current Address select Input high current Input low current Logic level select Input high level Input low level Input current Pin 6-9 2 10 10 1 -0·5 SP5730 Min. Typ. Max. Units Conditions mA µA mA µA V V µA 6 3 0 -10 VCC 1·5 10 VPORT = 0·7V VPORT = VCC See Note 1 See Table 5 VIN = VCC VIN = VEE See Note 3 5V I2C logic level selected 3·3V I2C logic level selected VIN = VEE to VCC NOTES 1. Output ports high impedance on power-up, with SDA and SCL at logic ‘0’. 2. If the REF/COMP output is not used, the output should be left open circuit or connected to VCC and disabled by setting RE = ‘0’. 3. Bi-dectional port. When used as an output, the input logic state is ignored. When used as an input, the port should be switched into high impedance (off) state. 4. Figures measured at 2kHz deviation, SSB (within loop bandwidth). Functional Description The SP5730 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varactor tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. It can also be operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial television (DTT) receivers. The RF input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces with the 15-bit fully programmable divider which is of MN1A architecture, where the dual modulus prescaler is 48/9, the A counter is 3 bits, and the M counter is 12 bits. The output of the programmable divider is applied to the phase comparator where it is compared in both phase and frequency domains with the comparison frequency. This frequency is derived either from the on-chip crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed inTable 2. The output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. The programmable divider output fPD/2 can be switched to port P0 by programming the device into test mode. The test modes are described inTable 6. Programming The SP5730 is controlled by an I2C data bus and is compatible with both standard and fast mode formats and with I2C data generated from nominal 3·3V and 5V sources. The I2C logic level is selected by the bi-directional port P3/ LOGLEV. 5V logic levels are selected by connecting P3/ LOGLEV to VCC or leaving it open circuit; 3·3V logic levels are set by connecting P3/LOGLEV to ground. If this port is used as an input the P3 data should be programmed to high impedance. If used as an output only 5V logic levels can be used, in which case the logic state imposed by the port on the input is ignored. Data and clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format . The synthesiser can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tables 3 and 4 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C bus system. Table 5 shows how the address is selected by applying a voltage to the address input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must be pulled low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. 3 SP5730 R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Datasheet 4, a logic ‘0’ indicating byte 2, and a logic ‘1’ indicating byte 4. Having interpreted this byte as either byte 2 or 4, the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without readdressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte; if, however, it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. Read mode When the device is in read mode, the status byte read from the device takes the form shown in Table 4. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic ‘1’ if the VCC supply to the device has dropped below 3V (at 25°C ), e.g. when the device is initially turned on. The POR is reset to ‘0’ when the read sequence is terminated by a STOP command. When POR is set high this indicates the programmed information may be corrupted and the device reset to power up condition. Bit 2 (FL) indicates whether the device is phase locked, a logic’1’is present if the device is locked, and a logic ‘0’ if it is not. Table 2 - Reference division ratios R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Division ratio 2 4 8 16 32 64 128 256 Illegal state 5 10 20 40 80 160 320 Illegal state 6 12 24 48 96 192 384 Illegal state 7 14 28 56 112 224 448 Programable features • RF programmable divider Function as described above. • Reference programmable divider Function as described above. • Charge pump current The charge pump current can be programmed by bits C1 and C0 within data byte 5, as defined in Table 7. • Test mode The test modes are invoked by setting bits RE, RS, T1 and T0 as described in Table 6. • Reference/Comparison frequency output The reference frequency f REF or comparison frequency fCOMP can be switched to the REF/COMP output, function as defined in Table 8. RE and RS default to logic’1’during device power up, thus enabling the comparison frequency fCOMP at the REF/COMP output. Write mode With reference to Table 3, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Bytes 4 and 5 control the reference divider ratio (see Table 2), charge pump setting (see Table 7), REF/COMP output (see Table 8), output ports and test modes (see Table 6). After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4 Datasheet Table 3 - Write data format (MSB transmitted first) Address Programmable divider Programmable divider Control data Control data MSB 1 0 27 1 C1 1 214 26 T1 C0 0 213 25 T0 RE 0 212 24 R4 RS 0 211 23 R3 P3 MA1 210 22 R2 P2 MA0 29 21 R1 P1 LSB 0 28 20 R0 P0 SP5730 A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Key to Table 3. A Acknowledge bit MA1, MA0 Variable address bits (see Table 5) 214-20 Programmable division ratio control bits R4-R0 Reference division ratio select (see Table 2) C1, C0 Charge pump current select (see Table 7) RE Reference oscillator output enable RS REF/COMP output select when RE=1 (see Table 8) T1-T0 Test mode control bits (see Table 6) P3-P0 P3, P2, P1 and P0 port output states Table 4 - Read data format (MSB transmitted first) Address Status byte MSB 1 POR 1 FL 0 0 0 0 0 0 MA1 0 MA0 0 LSB 1 0 A A Byte 1 Byte 2 Key to table 4, A Acknowledge bit MA1, MA0 Variable address bits (see Table 5) POR Power On Reset indicator FL Phase lock flag Table 5 - Address selection MA1 0 0 1 1 MA0 0 1 0 1 Address input voltage level 0 to 0·1VCC Open circuit 0·4VCC to 0·6VCC * 0·9VCC to VCC Table 6 - Test modes RE•RS T1 0 1 X X X 0 0 0 1 1 T0 0 0 1 0 1 Test mode description Normal operation Normal operation, P0 = fPD/2 Charge pump sink*, FL = ‘0’ Charge pump source*, FL = ‘0’ Charge pump disabled*, FL = ‘1’ * Programmed by connecting a 15kΩ resistor from pin 10 to VCC Table 7 - Charge pump current Current (µA) C1 0 0 1 1 C0 Min. 0 1 0 1 ±116 ±247 ±517 ±1087 Typ. ±155 ±330 ±690 ±1450 Max. ±194 ±412 ±862 ±1812 * Clocks need to be present on crystal and RF inputs to enable charge pump test modes and to toggle Status byte bit FL. X = don’t care Table 8 - REF/COMP output RE RS 0 1 1 X 0 1 REF/COMP output High impedance fREF selected fCOMP selected X = don’t care 5 SP5730 Datasheet VIN (mVRMS INTO 50Ω) 300 40 25 12.5 OPERATING WINDOW 50 100 500 1000 FREQUENCY (MHz) 1300 Figure 3 - Typical RF input sensitivity j1 j0.5 j2 j0.2 j5 0 0.2 0.5 1 2 5 50MHz 500MHz 2j5 2j0.2 1GHz 1·3GHz 2j0.5 2j1 2j2 S11: ZO = 50Ω Normalised to 50Ω Figure 4 - RF input impedance 2 18p 39p 3 SP5730 Figure 5 - Crystal oscillator application 6 J1 POWER CONNECTOR 15V VCC C7 130V C9 RF2 EXT REF 18V 130V C3 C2 C6 C1 VCC X1 J5 SDA5 5V 3 4 5 1 16 15 14 2 3 4 5 1 C16 2 3 C8 C23 4 5 C22 Figure 6 - SP5730 evaluation board R8 R9 T1 R10 C14 R11 VCC C10 ADD CON1 R14 R12 C20 R13 RF INPUT 18V RF1 C19 VCO tuning range = 500MHz to 900MHz C21 RF OUT VT R7 J2 VARACTOR 2 1 VCO C18 C5 C4 SP 5730 13 12 11 10 9 18V SCL5 6 LED1 LED2 R1 R4 R5 R6 S1 6 7 8 C15 C13 C12 LED3 LED4 C24 Datasheet C17 LK1 J4 RF3 COMP OUTPUT 43 2 1 PORT OUTPUTS SP5730 7 SP5730 Datasheet Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 Value/type 18pF 2·2nF 68pF 1nF 1nF 10nF 100nF 4·7µF 100nF 100pF 1nF 100pF 100pF 4·7nF 100pF 4·7µF 10nF 39pF 100pF 1nF 1nF Component C22 C23 C24 LED 1 LED 2 R1 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 S1 T1 VCO X1 Value/type 100pF 4·7µF 1nF HLMPK-150 HLMPK-150 4·7kΩ 4·7kΩ 4·7kΩ 4·7kΩ 13·3kΩ 22kΩ 1kΩ 0Ω 16Ω 16Ω 16Ω 68Ω SW DIP-2 BCW31 POS_900 4MHz Table 9 - Component values for Figure 6 8 Datasheet SP5730 Top view Bottom view Figure 7 - SP5730 evaluation board layout 9 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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