SP8400

SP8400 Very Low Phase Noise Synthesiser Divider September 2005 The SP8400 is a very low phase noise programmable divider which is based on a divide by 8/9 dual modulus prescaler and a 12 stage control counter. This gives a minimum division ratio of 56 (64 for fractional - N synthesis applications), and a maximum division ratio of 4103. Special circuit techniques have been used to reduce the phase noise considerably below that produced by standard dividers.The data inputs are CMOS or TTL compatible. The SP8400 is packaged in a 28 pin plastic SO package. Ordering Information SP8400/KG/MPES SP8400/KG/MPFP 28 Pin SOIC 28 Pin SOIC* Tubes Tubes *Pb Free Matte Tin FEATURES I Very low Phase Noise (Typically -156dBc/Hz at 1kHz offset) I Supply Voltage 5V M2 M1 M0 VCC +5V GND CLOCK INPUT CLOCK INPUT CLOCK INPUT CLOCK INPUT GND VCC +5V VCC +5V GND A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 M3 M4 M5 M6 M7 M8 N/C OUTPUT OUTPUT N/C VCC +5V N/C A2 A1 ABSOLUTE MAXIMUM RATINGS Supply Voltage Output Current Storage Temperature Range Maximum Clock Input Voltage 6.5V 20mA -55°C to +125°C 2.5V p-p MP28 Fig.1 Pin connections - top view 0 –10 –20 –30 –40 –50 (f) (dBc/Hz) –3dB –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k Frequency (Hz) 10k 100k Fig.2 Typical single sideband phase noise measured at 300MHz 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved. SP8400 ELECTRICAL CHARACTERISTICS Guaranteed over: Supply voltage V CC = +4.75V to +5.25V Temperature Tamb = -10°C to +75° C Tested at +4.75V and +5.25V at T amb = +25°C Characteristic Supply current Output voltage swing Input sensitivity 200MHz to 1.5GHz Pin Min. 4, 11, 12, 18 20, 21 7, 8 122 320 Value Typ. Max. 137 410 152 mA mV mV dBm Output loaded with 300R See Fig.4 p-p @ 1.5GHz input ÷ 71 mode See Fig.4 RMS Sine wave into 50 Ohms (dBm equivalent) See Fig.3 Units Conditions 140 (-4) Data Inputs Logic high voltage Low low voltage Input current 2.2 0.8 180 V V µA 5V Data input voltage 600 500 400 V in mV rms 355mV 300 OPERATING WINDOW 200 140mV 100 0 200 400 600 800 1000 1200 1400 1600 FREQUENCY MHz Fig.3 Typical input sensitivity 2 SP8400 VCC TTL/CMOS MODULUS CONTROL 1 2 3 4 5 28 27 26 25 24 23 1nF 50R RF SIGNAL GENERATOR 6 7 8 9 10 11 12 13 SP8400 22 21 20 19 18 17 16 15 OUTPUT 220nF TTL/CMOS MODULUS CONTROL 14 1nF 10nF 1nF 2x330R 10nF 50R Fig.4 Test circuit APPLICATIONS INFORMATION Circuit description, synthesiser divider The divider is based on a divide by 8/9 modulus prescaler, and a 12 stage control counter. This gives minimum fractional – N division ratio of 64 (56 for general division), and a maximum division ratio of 4103. The inputs to the control counter are TTL/CMOS compatible. There is a fixed offset of 8 between the number on the data lines and the actual division ratio. The output is one transition only per divide cycle. This eliminates the problem of where to put the redundant edge when the divider is used in a fractional–N system, and also avoids the problem of how to define the output pulse width. This means that the overall division ratio conventionally defined in terms of the rate of edges of the same polarity is twice the selected division ratio. Equations for division The M and A data inputs form a 12 bit number with A0 being the least significant bit and M8 being the most significant bit. Definition 1: Division ratio – (input frequency to out put edges, positive or negative). = Number loaded + 8 Definition 2: Division ratio – (input frequency to out put frequency). = (Number loaded + 8) x 2 3 SP8400 Available division ratio All division ratios of 64 to 4103 (Definition 1) will return the divider to the same internal state at the end of the count and hence these are the only divisional ratios to be used for fractional–N synthesiser application. All division ratios of 56 to 4103 are available for general division purposes. Additional division ratios available for general division are:8,9 16, 17, 18 24, 25, 26, 27 32, 33, 34, 35, 36 40, 41, 42, 43, 44, 45 48, 49, 50, 51, 52, 53, 54 +5V M INPUTS 1 2 3 4 5 28 27 26 25 24 23 +15V 1k 2 x BF569 (or similar) 1nF CLOCK INPUT 50R 6 7 8 9 10 11 12 13 14 SP8400 22 21 20 19 18 17 16 15 10nF A INPUTS 330R 1nF 10nF 1nF 2x330R 10nF Fig.5 Typical application combining output to increase signal and retain low phase noise 4 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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