SP8402KG

SP8402 Very Low Phase Noise Divider by 2N September 2005 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise considerably below that produced by standard dividers. The data inputs are CMOS or TTL compatible. The SP8402 is packaged in a 28 pin plastic SO package to be compatible with the SP8400 and SP8401 devices. Ordering Information SP8402/KG/MPES SP8402/KG/MPFP SP8402/KG/MP1T 28 Pin SOIC 28 Pin SOIC* 28 Pin SOIC Tubes Tubes Tape & Reel *Pb Free Matte Tin FEATURES I Very low Phase Noise (Typically -155 to 160dBc/Hz at 1kHz offset) I Supply Voltage 5V N/C N/C N/C VCC +5V GND CLOCK INPUT CLOCK INPUT CLOCK INPUT CLOCK INPUT GND VCC +5V VCC +5V N/C S0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 N/C N/C N/C N/C N/C N/C N/C OUTPUT OUTPUT N/C VCC +5V N/C S2 S1 ABSOLUTE MAXIMUM RATINGS Supply Voltage Output Current Storage Temperature Range Maximum Clock Input Voltage 6.5V 20mA -55°C to +125°C 2.5V p-p MP28 Fig.1 Pin connections - top view 0 –10 –20 –30 –40 –50 (f) (dBc/Hz) –3dB –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k Frequency (Hz) 10k 100k Fig.2 Typical single sideband phase noise measured at 768MHz 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1994-2005, Zarlink Semiconductor Inc. All Rights Reserved. SP8402 ELECTRICAL CHARACTERISTICS Guaranteed over: Supply voltage V CC = +4.75V to +5.25V Temperature Tamb = -10°C to +75° C Tested at +4.75V and +5.25V at T amb = +25°C Characteristic Supply current Output voltage swing Input sensitivity 200MHz to 1.5GHz Pin Min. 4, 11, 12, 18 20, 21 7, 8 82 320 Value Typ. Max. 92 410 102 mA mV mV dBm Output loaded with 300R See Fig.5 p-p @ 1.4GHz input ÷ 256 mode outputs loaded with 330R See Fig.5 RMS Sine wave into 50 Ohms (dBm equivalent) See Fig.3 Units Conditions 140 (-4) Data Inputs Logic high voltage Low low voltage Input current 2.2 0.8 180 V V µA 5V Data input voltage 600 500 400 V in mV rms 300 OPERATING WINDOW 200 140mV 100 355mV 0 200 400 600 800 1000 FREQUENCY MHz 1200 1400 1600 Fig.3 Typical input sensitivity S0 L H L H L H L H S1 L L H H L L H H S2 L L L L H H H H DIVISION RATIO 2 4 8 16 32 64 128 256 Fig.4 Truth table 2 SP8402 VCC 1 2 3 4 5 28 27 26 25 24 23 22 1nF 50R RF SIGNAL GENERATOR 6 7 8 9 10 11 12 13 SP8402 21 20 19 18 17 16 15 220nF OUTPUT TTL/CMOS MODULUS CONTROL 14 50R 1nF 10nF 1nF 2x330R 10nF Fig.5 Test circuit 3 SP8402 +5V 10 F 1 2 3 4 5 28 27 26 25 24 23 22 CLOCK INPUT 1nF 50R 6 7 8 9 10 11 12 13 OUTPUT SP8402 21 20 19 18 17 16 15 S0 S1 S2 1nF 10nF 1nF 14 10nF 10nF 2x330R Fig.5 Typical application combining output to increase signal and retain low phase noise 4 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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