SP8660

ADVANCE INFORMATION DS3668-1·1 SP8660 150MHz410 The SP8660 is a low power ECL counter with an open collector output capable of driving TTL or CMOS. It has internally biased inputs. FEATURES s AC Coupled Inputs CLOCK INPUT VCC NC OUTPUT 1 2 8 7 CLOCK INPUT NC NC VEE (0V) s Low Power Consumption s CMOS/TTL Compatible Open Collector Output QUICK REFERENCE DATA s Supply Voltage: 5·0V SP8660 3 4 6 5 DP8 Fig. 1 Pin connections - top view s Power Consumption: 50mW s Temperature Range: 230°C to 170°C s 8-Lead Plastic Package ABSOLUTE MAXIMUM RATINGS Supply voltage Open collector output voltage Storage temperature range Max. junction temperature Max. clock input voltage Output sink current 8V 12V 255°C to 1150°C 1150°C 2·5V p-p 10mA ORDERING INFORMATION SP8660 DP VCC 2 D Q REF D Q D Q D Q 4 OUTPUT STAGE OUTPUT CLOCK INPUT CLOCK INPUT 1 8 D Q CK CK Q CK CK D Q CK CK D Q CK CK 5 VEE (0V) Fig. 2 Functional diagram SP8660 ELECTRICAL CHARACTERISTICS Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range Supply voltage, VCC = 5·0V± 0·25V, VEE = 0V Temperature, TAMB = 230°C to 170°C Value Characteristic Maximum frequency (sinewave input) Minimum frequency (sinewave input) Power supply current Output high voltage Output low voltage Symbol fMAX fMIN ICC VOH VOL Min. 150 40 13 9 400 Max. Units MHz MHz mA V mV Conditions Input = 200-1000mV p-p Input = 400-1000mV p-p VCC = 5·25V VCC = 5V, pin 4 = 1·5kΩ to 10V, see note 3 VCC = 5V, pin 4 = 1·5kΩ to 10V, see note 3 NOTES 1. The test configuration for dynamic testing is shown in Fig.5. 2. All characteristics above are tested at 25°C only. 3. CLOAD ∂ 5pF. 1600 1400 TAMB = 230°C TO 170°C INPUT AMPLITUDE (mV p-p) 1200 1000 800 600 400 200 0 0 50 100 INPUT FREQUENCY (MHz) 150 200 GUARANTEED * OPERATING WINDOW * Tested as specified in table of Electrical Characteristics Fig. 3 Typical input characteristic j1 j 0.5 j2 j 0.2 j5 0 0.2 0.5 1 2 5 50 100 2j 5 2j 0.2 150 2j 0.5 2j 1 2j 2 Fig. 4 Typical input impedance. Test conditions: supply voltage = 5·0V, ambient temperature = 25°C, frequencies in MHz, Impedances normalised to 50Ω 2 SP8660 OPERATING NOTES 1.The clock inputs (pins 1 and 8) should be capacitively coupled to the signal source. When driven single ended, the input signal path is completed by a capacitor from the unused input to ground. 2. In the absence of a signal the devices will self-oscillate. This can be prevented by connecting a 39kΩ resistor from either input to ground. If the device is driven single ended, it is recommended that the pull-down resistor be connected to the decoupled unused input. There will be a loss in sensitivity of approximately 200mV. 3. The device will operate down to DC but input slew rate must be better than 100V/µs. 4. The open collector output will drive three TTL loads, and therefore requires a a suitable resistor to VCC to maintain noise immunity. In order to maintain noise immunity on transitions, this resistor should not exceed 4·7kΩ. For interfacing to CMOS, the open collector may be restored to a 110V line via a 3·3kΩ resistor. The output sink current must not exceed 10mA and the use of too low a value of resistor may lead to a loss of noise immunity, especially at low temperatures. 5. Input impedance varies as a function of frequency; see Fig. 4. 6. The rise time of the open collector output waveform is directly proportional to the load capacitance and load resistor value. Therefore, the load capacitance should be minimised and the load resistor kept to a minimum compatible with system power requirements. In the test configuration of Fig. 5, the output rise time is approximately 20ns and the fall time is typically 10ns. VCC FROM GENERATOR TO SAMPLING SCOPE 10n 1n 1 8 5 1n 2 110V 3·3k 4 1k 100n SAMPLING SCOPE INPUT DUT 7p Fig. 5 Test circuit 15V 1n 2 1n INPUT 1 15V/110V (DEPENDING ON CMOS SUPPLY VOLTAGE) 3·3k 8 DIVIDE BY 10 1·6k 1·6k 4 CMOS 39k 1n BIAS 5 Fig. 6. Typical application circuit showing interfacing 15V 2 2·2k 4 SP8660 TTL Fig. 7. Interfacing to TTL. Load not to exceed 3 TTL unit loads 3 SP8660 PACKAGE DETAILS Dimensions are shown thus: mm (in). 1·14/1·65 (0·045/0·065) 1 7·11 (0·28) MAX 8 10·16 (0·40) MAX 5·08/(0·20) MAX SEATING PLANE PIN 1 REF NOTCH 7·62 (0·30) NOM CTRS 0·23/0·41 (0·009/0·016) 0·51 (0·02) 3·05 (0·120) MIN MIN NOTES 1. Controlling dimensions are inches. 2. This package outline diagram is for guidance only. Please contact your GPS Customer Service Centre for further information. 0·38/0·61 (0·015/0·024) 8 LEADS AT 2·54 (0·10) NOM. SPACING 8-LEAD PLASTIC DIL – DP8 HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, CA95067-0017 United States of America. Tel (408) 438 2900 Fax: (408) 438 5576 CUSTOMER SERVICE CENTRES q FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07 q GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 q ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 q JAPAN Tokyo Tel: (3) 5276-5501 Fax: (3) 5276-5510 q NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023. q SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 q SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 q UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (0793) 518510 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. © GEC Plessey Semiconductors 1994 Publication No. DS3668 Issue No. 1.1 March 1994 This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. 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