SP8795

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS DS 3295 - 1 SP8795 225MHz ÷ 32/33 TWO MODULUS DIVIDER The SP8789 is a low power programmable ÷32/33 counter.lt divides by 32, when the control input is in the high state and by 33 when in the low state. An internal voltage regulator allows operation from a wide range of supply voltages. CONTROL INPUT OUTPUT Vcc 2 OUTPUT VEE (0V) 1 2 8 7 Vcc 1 REF DECOUPLING INTERNAL BIAS DECOUPLING INPUT SP8795 3 4 6 5 FEATURES Very Low Power Control Input and Output CMOS/TTL Compatible AC Coupled Input Operation up to 9.5V using Internal Regulator Figure 1 Pin connections - top view DP8, MP8 ABSOLUTE MAXIMUM RATINGS QUICK REFERENCE DATA Supply Voltage 5.2V or 6.8V to 9.5V Power consumption: 26mW Typical Temperature range: -40°C to +85°C Supply voltage Supply voltage Storage temperature range Max. Junction temperature Max. clock input voltage Vcc2 6.0V pins 7 & 8 tied 13.5V pin 8, pin 7 decoupled -55°C to +125°C +175°C 2.5V p-p Max. 10V VCC1 100n VCC2 2 8 1n CLOCK INPUT INTERNAL BIAS DECOUPLING 5 VOLTAGE REGULATOR DIVIDE BY 20/21 6 1n 16k 4 1 CONTROL INPUT 3 OUTPUT 7 REF DECOUPLING VEE (0V) Figure 2 : Functional diagram SP8789 SP8795 ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated):] Supply voltage : Vcc 1 & 2 = 5.2 ± 0.25V or 6.8V to 9.5V (see Operating Note 7): VEE = 0V; Temperature Tamb = -40°C to +85°C Value Characteristics Maximum frequency (sinewave input)) Minimum frequency (sinewave input) Power supply current Control input high voltage Control input low voltage Output high voltage Output low voltage Set up time Release time Clock to output propagation time IEE VINH VINL VOH VOL ts tr tp 14 20 45 2.4 0.5 4 2 7 mA V V V V ns ns ns Note 4 Note 4 Note 4 Note 4 Note 4 Note 3 Note 3 Note 3 Pins 2, 7 and 8 linked Vcc = 4.95V IOH = 100µA Pin 2 linked to 8 and 7 IOL = 1.6mA 25°C 25°C 25°C fmin 20 MHz Note 4 Input = 400-800mV p-p Symbol fmax Min. 225 Max. MHz Units Notes Note 4 Conditions Input = 200-800mV p-p NOTES 1. Unless otherwise stated the electrical characteristics are guaranteed over full specified supply, frequency and temperature range. 2. The test configuration for dynamic testing is shown in Fig.6. 3. Guaranteed but not tested. 4. Tested onlt at 25°C TRUTH TABLE FOR CONTROL INPUTS Control input 0 1 33 32 Division Ratio Figure 3 : Timing diagramSP8785 NOTES The set-up time ts is defined as the minimum time that can elapse between a L ¡ H transition of the control input and the next L ¡ H clock pulse transition to ensure that the ÷ 32 mode is selected. The release time tr is defined as the minimum time that can elapse between a H ¡ L transition of the control input and the next L ¡ H clock pulse transition to ensure that the ÷ 33 mode is selected. 1600 1400 INPUT AMPLITUDE (mV p-p) 1200 1000 800 600 400 200 0 50 100 200 INPUT FREQUENCY (MHz) 300 Vcc 4.95V to 5.45V PINS 7 AND 8 CONNECTED TOGETHER. Tamb -40°C to +85°C *Tested as specified in table of Electrical Characteristics GUARANTEED * OPERATING WINDOW Figure 4 : Input sensitivity SP8785 SP8795 OPERATING NOTES 1. The clock input (Pin 5) should be capacitively coupled to the signal source. The input signal path is completed by coupling a capacitor from the internal bias decoupling, Pin 6 to ground. 2. The output stage which is normally open collector (Pin 2 open circuit) can be interfaced to CMOS. The open collector can be returned to a +10V line via a 5k resistor but the output sink current should not exceed 2mA. If interfacing to TTL is required then Pins 2 and 7 should be connected together to give a fan-out = 1. This will increase supply current by approximately 2mA. 3. The circuit will operate down to DC but a slew rate of better than 20V/~s is required. 4. The mark space ratio of the output is approximately 1.2:1 at 200MHz. 5. Input impedance is a function of frequency. See Fig.5. 6. If no signal is present the device will self-oscillate. If this is undesirable it may be prevented by connecting a 150k between unused input and ground. This reduces the input sensitivity by typically 50-100mV p-p. 7. The internal regulator has its input connected to Pin 8, while the internal reference voltage appears at Pin 7 and should be decoupled. For use from a 5.2V supply, Pins 7 and 8 should be connected together, and 5.2V applied to these pins. For operation from supply voltages in the range +6.8V to +9.5V, Pins 7 and 8 should be separately decoupled, and the supply voltage applied to Pin 8. Figure 5 : Typical impedance. Test conditions: supply voltage 5.2V, ambient temperature 25°C, frequencies in MHz, impedance normalised to 50 ohms. VCC OF MODULUS CONTROL DEVICE CONTROL INPUT 1 2 8 7 VCC1 50 MONITOR 1n 50 SIGNAL SOURCE SP8795 OUTPUT 3 4 6 5 1n 100n Figure 6 : Toggle frequency test circuit For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. 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