SP8852EKGHCAR

SP8852E 2·7GHz Parallel Load Professional Synthesiser Preliminary Information Supersedes January 1996 version, DS4237 - 1.2 DS4237 - 2.0 June 1998 The SP8852E is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a PLL synthesis loop. Other parts in the series are the SP8854E which has hard wired reference counter programming and requires only a single 16-bit programming word, and the SP8855E which is fully programmable using hard wired links or switches. The SP8852E is programmed using a 16-bit parallel data bus. Data can be stored in one of two internal buffers, selected by a single address bit on the input interface. In order to fully program the device, two 16-bit words are required, one to select the RF division ratio (A and M counters) and phase detector gain, and one to set the 10-bit reference divider count, phase detector state and sense. Once the reference divide ratio has been set, frequency changes can be made by a single 16-bit data load entry to the RF divider chain. B4 B3 B2 B1 B0 0V (PRESCALER) RF INPUT RF INPUT VCC (PRESCALER) VEE LOCK DETECT B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 1 44 SP8852E STROBE ADDRESS NC NC NC NC NC NC NC NC NC FEATURES s 2·7 GHz Operating Frequency s Single 5V Supply s Low Power Consumption 2. See note 1 Units Conditions Supply current RF input sensitivity RF division ratio Reference division ratio Comparison frequency Reference input frequency Reference input voltage FREF/FPD output voltage high FREF/FPD output voltage low LOCK DETECT output voltage CHARGE PUMP current 18, 26 13,14 13,14, 24 28, 25 28, 24, 25 28 28 24, 25 24, 25 17 19, 20, 21 mA dBm 100MHz to 2·7GHz. See note 3. NOTES 1. Lower frequencies may be used provided that slew rates are maintained. 2. Pin 19 current3multiplication factor must be less than 5mA if charge pump accuracy is to be maintained. 3. Guranteed but not tested. 4 SP8852E 120 TYPICAL OVERLOAD RF INPUT TO PIN 13 (dBm) 110 17 0 25 210 GUARANTEED OPERATING WINDOW 220 TYPICAL SENSITIVITY 230 100MHz 1GHz 2GHz 2·7GHz 10GHz FREQUENCY Fig. 3 Input sensitivity j1 j 0.5 j2 ZO = 50Ω j 0.2 j5 0 1·1GHz 0.2 0.5 1 2 5 50MHz 2·5GHz 2j 5 2j 0.2 2j 0.5 2j 1 2j 2 Fig. 4 RF input impedance 5 SP8852E ADDRESS STROBE CONTROL MICRO 15V 1k 7 8 9 10 11 12 13 15V 1n 14 15 16 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 SP8852E 34 33 32 31 30 17 29 18 19 20 21 22 23 24 25 26 27 28 1n SP8852E 27 28 1n 100p 2·2k LOOP FILTER 1n REF IN FREF 15V FPD 33p 100p 10MHZ * * 130V * − 1µ 10n Application using crystal reference VCO OP27 ETC + * VALUES DEPEND ON APPLICATION Fig. 5 Typical application diagram DESCRIPTION Prescaler and AM counter The programmable divider chain is of A and M counter construction and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which performs the bulk multi-modulus division. A programmable divider of this construction has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21), where N is the prescaler value. STROBE is low, the inputs are isolated and the data can be changed without affecting the programmed state. The data is loaded into the RF buffer when the address input is high and into the reference buffer when low. When the STROBE input is taken high, the A and M and reference counters are reset and the input data is applied to the internal storage register. When STROBE is again taken low, the data on the input bus is stored in the selected register and the counters released. The STROBE input is level triggered so that if the data is changed whilst the input is high, the final value before STROBE goes low will be stored. In order to prevent disturbances on the VCO control voltage when frequency changes are made, the STROBE input disables Data Entry and Storage Data is loaded from the 16-bit bus into one of the internal buffers by applying a positive pulse to the STROBE input. The input bus can be driven from TTL or CMOS logic levels. When 6 SP8852E the charge pump outputs when high. During this period the VCO control voltage will be maintained by the loop filter components around the loop amplifier, but due to the combined effects of the amplifier input current and charge pump leakage a gradual change will occur. In order to reduce the change, the duration of the strobe pulse should be minimised. Selection of a loop amplifier with low input current will reduce the VCO voltage droop during the strobe pulse and result in minimum reference sidebands from the synthesiser. Output for RF phase lag Sense bit (bit 12) 1 0 Pin 20 Current source Current sink Reference Input The reference source can be either driven from an external sine or square wave source of up to 100MHz or a crystal can be connected as shown in Fig. 5. Phase Comparator and Charge Pump The SP8852E has a digital phase/frequency comparator driving a charge pump with programmable current output. The charge pump current level at the minimum gain setting is approximately equal to the current fed into the RSET input, pin 19, and can be increased by programming the bus according to Table 2 by up to 4 times. Bit 15 Bit 14 0 0 1 1 0 1 0 1 Current multiplication factor 1·0 1·5 2·5 4·0 Table 3 The FPD and FREF signals to the phase detector are available on pins 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. These outputs may be programmed by bits 10 and 11 of word 0 according to Table 4. State 3, where the outputs are disabled by the lock detect circuit, is useful where the user wishes to use an external phase detector. The internal phase/frequency detector may be used to pull the loop into lock and an automatic switch-over to the external phase detector made. When the FPD and FREF outputs are to be used at high frequencies, an external pull down resistor of minimum value 330Ω may be connected to ground to reduce the fall time of the output pulse. Bit 11 Bit 10 0 0 1 1 0 1 0 1 Phase detector state Enabled, FPD and FREF off Enabled, FPD and FREF on Disabled by lock detect, FPD and FREF on Disabled, FPD and FREF on Table 2 Pin 19 current = VCC21·6V RSET IPIN19 (mA)3multiplication factor mA/rad 2p Phase detector gain = To allow for control direction changes introduced by the design of the PLL, bit 12 on the input bus address 0 can be programmed to reverse the sense of the phase detector by transposing the FPD and FREF connections. In order that any external phase detector will also be reversed by this programming bit, the FPD and FREF outputs are also interchanged by bit 12 as shown in Table 3. PIN 40 BIT 15 Table 4 The charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. The matching of the charge pump up and down currents will only be maintained if the charge pump output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. The lock detect circuit can drive an LED to give visual indication of phase lock or provide an indication to the control system if a pullup resistor is used in place of the LED. A small capacitor connected form the C-LOCK DETECTOR pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. PIN 11 BIT 0 0 29 28 27 26 25 24 23 22 21 20    NOT USED PHASE DETECTOR SENSE CONTROL (SEE TABLE 3) ADDRESS PHASE DETECTOR STATE CONTROL (SEE TABLE 4) Fig. 6a Reference word bit allocation PIN 40 BIT 15 PIN 11 BIT 0 1 ADDRESS 213 212 211 210 29 PHASE DETECTOR GAIN CONTROL (SEE TABLE 2) M COUNTER Fig. 6b RF division ratio bit allocation Fig. 6 Programming data format    3-BIT A COUNTER                                     10-BIT REFERENCE COUNTER 28 27 26 25 24 23 22 21 20 7 SP8852E VCC 40k INPUT VCC 4k 325 325 40k 5k 5k 500 13 500 RF INPUT 14 RF INPUT 50µA 0V 3mA 3k 0V Fig. 7a 16-bit input bus, strobe and address Fig. 7b RF inputs C-LOCK DETECT (HIGH WHEN LOCKED) VCC 2·5k VCC 3k 3k VREF 4·7V LOCK DETECT OUTPUT (LOW WHEN LOCKED) 3k 3k 17 2·5k 18 20µA 100µA 0V 400µA 100 100 1k 1k 0V Fig. 7c Lock detect decouple Fig. 7d Lock detect output VCC RSET 19 VCC 450 450 f UP CHARGE PUMP CURRENT SOURCES f UP VCC 83 83 20 21 OUTPUT REFERENCE f DN 130 0V f DN 2mA 0V Fig. 7e RSET pin Fig. 7f Charge pump circuit Fig 7 Interface circuit diagrams 8 SP8852E VCC 296 296 40k 3k 3k VCC 40k 296 28 24, 25 FPD, FREF OUTPUTS CRYSTAL CAPACITOR 27 60k 50µA 3·3mA 0V 100µA 100µA 100µA 50µA 60k 0V Fig. 7g FPD and FREF outputs Fig. 7h Reference oscillator Fig. 7 Interface circuit diagrams (continued) APPLICATIONS RF Layout The SP8852E can operate with input frequencies up to 2·7GHz but to obtain optimum performance, good RF layout practices should be used. A suitable layout technique is to use double sided printed circuit board with through plated holes. Wherever possible the top surface on which the SP8852E is mounted should be left as a continuous sheet of copper to form a low impedance ground plane. The ground pins 12 and 16 should be connected directly to the ground plane. Pins such as VCC and the unused RF input should be decoupled with chip capacitors mounted as close to the device pin as possible, with a direct connection to the ground plane; suitable values are 10nF for the power supplies and