SP8854EIGHCAR

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ SP8854E 2.7GHz Parallel Load Professional Synthesiser Preliminary Information DS4238 ISSUE 2.0 June 1998 The SP8854E is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a PLL synthesis loop. Other parts in the series are the SP8852E which is fully programmable, requiring tw0 16bit words to set the RF and reference counters and the SP8855E which is fully programmable using hard wired links or switches. The SP8854E is programmed using a 16-bit parallel data bus. Data is stored in an internal buffer. The 10-bit programmable reference divider is programmed by connecting the 10 programming pins either to ground or 1 5V. The device can therefore be programmed with a single transfer from the control microprocessor. Hard wired inputs can also control the FPD and FREF outputs and the control sense of the loop. Ordering Information SP8854E KG HCAR Non-standard temperature range, 255°C to 1100 °C, standard product screening SP8854E IG HCAR Industrial temperature range, 240° C to 185°C, standard product screening Features • 2·7 GHz Operating Frequency • Single 5V Supply • Low Power Consumption FREF or when the RF phase leads the reference phase. When pin 23 is low, the relationship is reversed (see Table 3). RF divider output pulses. FPD = RF input frequency/(M.N1A). Pulse width = 8 RF input cycles (1 cycle of the divide by 8 prescaler output). Reference divider output pulses. FREF = reference input frequency/R. Pulse width = high period of Ref input. Leave open circuit if an external reference is used. See Fig. 5 for typical connection for use as an onboard crystal oscillator. This pin is the input buffer amplifier for an external reference signal. This amplifier provides the active element if an onboard crystal oscillator is used. These pins set the reference divider ratio R. High is open circuit. When pin 39 is high the A, M, and R counters are held in the reset state and the charge pump output is disabled. When pin 39 is low the data on the RF data and PD gain pins is fixed in the buffers, the buffers are loaded into the RF counters and the PD gain control, all the counters are active, and the charge pump is enabled. High is open circuit. These pins set the charhe pump current multiplication factor (see Table 2). The data is transparent into the buffers when pin 39 is high and frozen when pin 39 is low. High is open circuit. Table 1 - Pin Descriptions 24 25 FPD if pin 23 is high FREF if pin 23 is low FPD if pin 23 is low FREF if pin 23 is high 27 (Ref. oscillator capacitor) 28 (REF IN/XTAL) 29-38 39 (STROBE) 40, 41 (PD gain) 3 SP8854E Preliminary Information Electrical Characteristics The Electrical Characteristics are guaranteed over the following range of operating conditions unless otherwise stated TAMB = 2 55° C to 1100°C (KG parts), 2 40°C to 185° C (IG parts); VCC = 4·75V to 5·25V Value Characteristic Pin Min. 18, 26 13,14 13,14, 24 28, 25 28, 24, 25 28 28 24, 25 24, 25 17 19, 20, 21 61·4 10 0 16 20·8 21·4 300 61·5 500 61·7 25 56 1 Typ. 180 Max. 240 17 16383 1023 50 100 110 MHz MHz dBm V V mV mA WRT VCC, 2·2kΩ to 0V WRT VCC, 2·2kΩ to 0V IOUT = 3mA VPIN20 = VPIN21, IPIN19 = 1·6mA, multiplication factor = 1 62·0 62·3 62·5 mA VPIN20 = VPIN21, IPIN19 = 1·6mA, multiplication factor = 1·5 63·4 63·8 64·1 mA VPIN20 = VPIN21, IPIN19 = 1·6mA, multiplication factor = 2·5 65·4 66·1 66·5 mA VPIN20 = VPIN21, IPIN19 = 1·6mA, multiplication factor = 4·0 Input bus logic level high 1-11, 22, 23, 29, 44 Input bus logic level low 1-11, 22, 23, 29, 44 Input bus current source 1-11, 22, 23, 29, 44 Input bus current sink 1-11, 22, 23, 29, 44 Up/down current matching CHARGE PUMP REFERENCE voltage 20 21 65 VCC20·5 % V VPIN20 = VPIN21, IPIN19 = 1·6mA IPIN19 = 1·6mA, current multiplication factor = 1·0 VCC21·6 19 19 18 50 100 2 1·6 110 V IPIN19 = 1·6mA, current multiplication factor = 4·0 RSET current RSET voltage C-LOCK DETECT current STROBE pulse width Data setup time 0·5 mA V µA ns ns Note 2 IPIN19 = 1·6mA VPIN18 = 4·7V Note 3 Note 3 10 µA VIN = VCC 2200 µA VIN = 0V 1 V 3·5 V Ref division ratio >2. See note 1 Units Conditions Supply current RF input sensitivity RF division ratio Reference division ratio Comparison frequency Reference input frequency Reference input voltage FREF/FPD output voltage high FREF/FPD output voltage low LOCK DETECT output voltage CHARGE PUMP current mA dBm 100MHz to 2·7GHz. See note 3. NOTES 1. Lower frequencies may be used provided that slew rates are maintained. 2. Pin 19 current3 multiplication factor must be less than 5mA if charge pump accuracy is to be maintained. 3. Guranteed but not tested. 4 Preliminary Information SP8854E 120 TYPICAL OVERLOAD RF INPUT TO PIN 13 (dBm) 110 17 0 25 210 GUARANTEED OPERATING WINDOW 220 TYPICAL SENSITIVITY 230 100MHz 1GHz 2GHz 2·7GHz 10GHz FREQUENCY Figure 3 - Input sensitivity j1 j 0.5 j2 ZO = 50Ω j 0.2 j5 0 1·1GHz 0.2 0.5 1 2 5 50MHz 2·5GHz 2j 5 2j 0.2 2j 0.5 2j 1 2j 2 Figure 4 - RF input impedance 5 SP8854E Preliminary Information STROBE CONTROL MICRO 15V 1k 7 8 9 10 11 12 13 15V 1n 14 15 16 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 15V SP8854E 34 33 32 31 30 17 29 18 19 20 21 22 23 24 25 26 27 28 1n SP8854E 27 28 1n 100p LOOP FILTER 1n REF IN FREF 15V FPD 33p 100p 10MHZ * * 130V * − 2·2k 1µ 10n Application using crystal reference VCO OP27 ETC + * VALUES DEPEND ON APPLICATION Figure 5 - Typical application diagram Description Prescaler and AM counter The programmable divider chain is of A and M counter construction and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which performs the bulk multi-modulus division. A programmable divider of this construction has a division ratio of MN1A and a minimum integer steppable division ratio of N(N21), where N is the prescaler value. data can be changed without affecting the programmed state. When STROBE input is taken high, the A and M counters are reset and the input data is applied to the internal storage register. When the STROBE input is again taken low, the data on the input bus is stored in the internal storage register and the A and M counters released. The STROBE input is level triggered so that if the data is changed whilst the input is high, the final value before STROBE goes low will be stored. In order to prevent disturbances on the VCO control voltage when frequency changes are made, the STROBE input disables Data Entry and Storage Data is loaded from the 16-bit bus into one of the internal buffers by applying a positive pulse to the STROBE input. The input bus can be driven from TTL or CMOS logic levels. When STROBE is low, the inputs are isolated and the 6 Preliminary Information the charge pump outputs when high. During this period the VCO control voltage will be maintained by the loop filter components around the loop amplifier but due to the combined effects of the amplifier input current and charge pump leakage a gradual change will occur. In order to reduce the change, the duration of the strobe pulse should be minimised. Selection of a loop amplifier with low input current will reduce the VCO voltage droop during the strobe pulse and result in minimum reference sidebands from the synthesiser. SP8854E To allow for control direction changes introduced by the design of the PLL, pin 23 is used to reverse the sense of the phase detector by transposing the F PD and F REF connections. In order that any external phase detector will also be reversed, programming bit, the FPD and F REF outputs are also interchanged by pin 23 as shown in Table 3. Output for RF phase lag Control direction (pin 23) 1 0 Table 3 The FPD and FREF signals to the phase detector are available on pins 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. The outputs are disabled by taking pin 22 low. When the FPD and FREF outputs are to be used at high frequencies, an external pull down resistor of minimum value 330 Ω may be connected to ground to reduce the fall time of the output pulse. The charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. The matching of the charge pump up and down currents will only be maintained if the charge pump output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. The lock detect circuit can drive an LED to give visual indication of phase lock or provide an indication to the control system if a pullup resistor is used in place of the LED. A small capacitor connected form the C-LOCK DETECTOR pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. Pin 20 Current source Current sink Reference Input The reference source can be either driven from an external sine or square wave source of up to 100MHz or a crystal can be connected as shown in Fig. 5. Phase Comparator and Charge Pump The SP8854E has a digital phase/frequency comparator driving a charge pump with programmable current output. The charge pump current level at the minimum gain setting is approximately equal to the current fed into the R SET input, pin 19, and can be increased by programming the bus according to Table 2 by up to 4 times. Bit 15 Bit 14 0 0 1 1 0 1 0 1 Table 2 VCC 21·6V Pin 19 current = RSET Phase detector gain = IPIN19 (mA) 3multiplication factor mA/rad 2p Current multiplication factor 1·0 1·5 2·5 4·0 PIN 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 213 PHASE DETECTOR GAIN CONTROL (SEE TABLE 2) 212 211 210 29 28 27 26 25 24 23 22 21 20 M COUNTER Figure 6 - Programming data format    3-BIT A COUNTER                   7 SP8854E Preliminary Information VCC 40k INPUT VCC 4k 325 325 40k 5k 5k 500 13 500 RF INPUT 14 RF INPUT 50µA 0V 3mA 3k 0V Fig. 7a 16-bit input bus, FPD/FREF enable, control direction, reference divider inputs and strobe Fig. 7b RF inputs C-LOCK DETECT (HIGH WHEN LOCKED) VCC 2·5k VCC 3k 3k VREF 4·7V LOCK DETECT OUTPUT (LOW WHEN LOCKED) 3k 3k 17 2·5k 18 20µA 100µA 0V 400µA 100 100 1k 1k 0V Fig. 7c Lock detect decouple Fig. 7d Lock detect output VCC RSET 19 VCC 450 450 f UP CHARGE PUMP CURRENT SOURCES f UP VCC 83 83 20 21 OUTPUT REFERENCE f DN 130 0V f DN 2mA 0V Fig. 7e RSET pin Fig. 7f Charge pump circuit Figure 7 - Interface circuit diagrams 8 Preliminary Information SP8854E VCC 296 296 40k 3k 3k VCC 40k 296 28 24, 25 FPD, FREF OUTPUTS CRYSTAL CAPACITOR 27 60k 50µA 3·3mA 0V 100µA 100µA 100µA 50µA 60k 0V Fig. 7g FPD and FREF outputs Fig. 7h Reference oscillator Figure 7 - Interface circuit diagrams (continued) Applications RF Layout The SP8854E can operate with input frequencies up to 2·7GHz but to obtain optimum performance, good RF layout practices should be used. A suitable layout technique is to use double sided printed circuit board with through plated holes. Wherever possible the top surface on which the SP8854E is mounted should be left as a continuous sheet of copper to form a low impedance ground plane. The ground pins 12 and 16 should be connected directly to the ground plane. Pins such as VCC and the unused RF input should be decoupled with chip capacitors mounted as close to the device pin as possible, with a direct connection to the ground plane; suitable values are 10nF for the power supplies and