SP8855DKGHCAR

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ SP8855D PACKAGE DETAILS Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre. 17.27/17.78 (0.680/0.700) 16.33/16.81 (0.643/0.662) 12.45/12.95 (0.490/0.510) 0.51 (0.02) NOM AT 45° INDEX CORNER 16.33/16.81 (0.643/0.662) 17.27/17.78 (0.680/0.700) 0.76MM(0.030 ″) 0.43MM(0.017 ″) 1.27/(0.050) NOM  45° AT 3 PLACES 1.02MM/(0.040 I )NOM 0.89(0.035) 03.05/3.43 (0.120/0.135) HC44 MULTILAYER CERAMIC J LEADED CHIP CARRIER HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire United Kingdom SN2 2QW. Tel: (01793) 518000 Fax: (01793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067–0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 E GEC Plessey Semiconductors 1995 CUSTOMER SERVICE CENTRES F FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 69 18 90 00 F GERMANY Munich Tel: (089) 3609 06 0 Fax: (089) 3609 06 55 F ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 F JAPAN Tokyo Tel: (03) 5276–5501 Fax: (03) 5276–5510 F NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023 F SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 F SWEDEN Stockholm Tel: 46 8 7029770 Fax: 46 8 6404736 F TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260 F UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 518527/518566 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world–wide. Publication No. D.S. 3702 Issue No. 2.6 October 1995 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM This publication is issued to provide information only, which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design, or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company’s conditions of sale, which are available on request. 15.49/16.51 (0.610/0.650) 12.45/12.95 (0.490/0.510) SP8855D From equation 3: C1 FROM CHARGE PUMP OUTPUT FROM CHARGE PUMP REFERENCE C2 t TO VCO 3 – + R2 t + 659 3 . 4142 + * tan 45° ) cos 45° + 0628319 100kHz 2p 1 1 0 *9 From equation 2: 2 t + (100kHz t + 3 . 844 2 1 2p)2 1 0 *6 2p 659 1 0 *9 Fig. 8 Third order loop filter circuit diagram Using these values in equation 1: t 1+ Loop Filter Design Generally the third order filter configuration shown in Fig.7 gives better results than the more commonly used second order because the reference sidebands are reduced. Three equations are required to determine values for the three constants where; 1 x 10 100 *3 (2p 10MHz V [ A] 100kHz)2 ½ 1 1 )w )w Where A is : t 2 nt n 2 2 2 2 3 ) + 1 )(2pp (2 1 62832 39 . 48 100kHz) 2 2 (3 . 844 x 10 *6) (659 x 10 ½ 2 100kHz) *9) 2 t1 = C 1 t2 = R2 (C1 + C2) t3 = C2 R2 The equations are; 1 2 t1 + t2 2 t3 2 6 . 833 10 12 1 . 1714 t1 + Nf 20 w KK n 1 1 )w )w n n 2 2 ½ Now t2 + w 12t n3 t3 + 3 * tan F ) cosF 1 0 t1 + 1 . 59 10*9 x 2 . 415 t1 + 3 . 84 10*9 t1 + C1 N C1 + 3 . 84nF t2 + R2 (C1 ) C2) t3 + C 2 R 2 wn 0 Where; Kf is the phase detector gain factor in mA/radian K0 is the VCO gain factor in radian/second/Volt N is the total division ratio from VCO to reference frequency wn is the natural loop bandwidth F0 is the phase margin normally set to 45° Since the phase detector is linear over a range of 2p radian, Kf can be calculated from Kf = Phase comparator current setting/2p mA/radian Substituting for C2 t2 + R2 2 R2 C1 )t 3 R2 N t +R C )t 2 2 1 10 3 R2 N + t *t + + 829 W 3 3 . 844 * 6 C1 9 . 61 * 659 10 * 10 * 9 9 .4 These values can now be substituted in equation 1 to obtain a value for C1 and equation 2 and 3 used to determine values for C2 and R2 C2 + 0 . 794 t 3 + C2 R 2 nF N +t + C2 3 659 10 * 9 R2 829 . 4 EXAMPLE Calculate values for a loop with the following parameters Frequency to be synthesised: Reference frequency Division ratio wn natural loop frequency K0 VCO gain factor F0 phase margin Phase comparator current 1000MHz 10MHz 1000MHz/10MHz = 100 100kHz 2p x 10MHz/Volt 45° 6.3mA The phase detector gain factor Kf = 6.3mA /2p = 1mA/radian SP8855D gain can be modified when new frequency data is entered to compensate for change in the VCO gain characteristic over its frequency band. The charge pump pulse current is determined by the current fed into pin 19 and is approximately equal to pin 19 current when the programmed multiplication ratio is one. The circuit diagram Fig. 7e shows the internal components on pin 19 which mirror the input current into the charge pump. The voltage at pin 19 will be approximately 1.6V above ground due to two Vbe drops in the current mirror. this voltage will exhibit a negative temperature coefficient, causing the charge pump current to change with chip temperature by up to 10% over the full military temperature range if the current programming resistor is connected to VCC as shown in the application diagram Fig. 5. In critical applications where this change in charge pump current would be too large the resistor to pin 19 could be increased in value and connected to a higher supply to reduce the effect of Vbe variation on the current level. A suitable resistor connected to a 30V supply would reduce the variation in pin 19 current due to temperature to less than 1.5%. Alternatively a stable current source could be used to set pin 19 current. The charge pump output on pin 20 will only produce symmetrical up and down currents if the voltage is equal to that on the voltage reference pin 21. In order to ensure that this voltage relationship is maintained, an operational amplifier must be used as shown in the typical application Fig. 5. Using this configuration pin 20 voltage will be forced to be equal to that on pin 21 since the operational amplifier differential input voltage will be no more than a few millivolts (the input offset voltage of the amplifier). When the synthesiser is first switched on or when a frequency outside the VCO range is programmed the amplifier output will limit, allowing pin 20 voltage to differ from that on pin 21. As soon as an achievable frequency value is programmed and the amplifier output starts to slew the correct voltage relationship between pin 20 and 21 will be restored. Because of the importance of voltage equality between the charge pump reference and output pins, a resistor should never be connected in series with the operational amplifier inverting input and pin 20 as is the case with a phase detector giving voltage outputs. Any current drawn from the charge pump reference pin should be limited to the few micro amps input current of a typical operational amplifier. A resistor between the charge pump reference and the non inverting input could be added to provide isolation but the value should not be so high that more than a few millivolts drop are produced by the amplifier input current. When selecting a suitable amplifer for the loop filter, a number of parameters are important; input offset voltage in most designs is only a few milivolts and an offset of 5mV will produce a mismatch in the up and down currents of about 4% with the charge pump multiplication factor set at 1. The mismatch in up down currents caused by input offset voltage will be reduced in proportion to the charge pump multiplication factor in use. If the linearity of the phase detector about the normal phase locked operating point is critical, the input offset voltage of most amplifiers can be adjusted to near zero by means of a potentiometer. The charge pump reference voltage on pin 21 is about 1.3V below the positive supply and will change with temperature and with the programmed charge pump multiplication factor. In many cases it is convenient to operate the amplifier with the negative power supply pin connected to 0V as this removes the need for an additional power supply. The amplifier selected must have a common mode range to within 3.4V (minimum charge pump reference voltage) of the negative supply pin to operate correctly without a negative supply. Most popular amplifiers can be operated from a 30V positive supply to give a wide VCO voltage drive range and have adequate common mode range to operate with inputs at +3.4V with respect to the negative supply. Input bias and offset current levels to most operational amplifiers are unlikely to be high enough to significantly affect the accuracy of the charge pump circuit currents but the bias current can be important in reducing reference side bands and local oscillator drift during frequency changes. When the loop is locked, the charge pump produces only very narrow pulses of sufficient width to make up for any charge lost from the loop filter components during the reference cycle. The charge lost will be due to leakage from the charge pump output pin and to the amplifier input bias current, the latter usually being more significant. The result of the lost charge is a sawtooth ripple on the VCO control line which frequency modulates the phase locked oscillator at the reference frequency and its harmonics. It is possible to disable the charge pump by taking pin 39 low. In this case any leakage current will cause the oscillator to drift off frequency. This feature may be useful where having acheived lock an external phase detector of the user’s choice can be employed to suit a specific application. Fpd and Fref outputs These outputs provide access to the outputs from the RF and reference dividers and are provided for monitoring purposes during product development or test, and for connection of an external phase detector if required. the output circuit is of ECL type, the circuit diagram being shown in Fig.7g. The outputs can be enabled or disabled under software control by the address 0 control word but are best left in the disabled state when not required as the fast edge speeds on the output can increase the level of reference sidebands on the synthesised oscillator. The emitter follower outputs have no internal pull down resistor to save current and if the outputs are required an external pull down resistor should be fitted.The value should be kept as high as possible to reduce supply current, about 2.2k being suitable for monitoring with a high impedance oscilloscope probe or for driving an AC coupled 50ohm load. A minimum value for the pull down resistor is 330ohms. When the Fpd and Fref outputs are disabled the output level will be at the logic low level of about 3.5V so that the additional supply current due to the load resistors will be present even when the outputs are disabled. Reference input The reference input circuit functions as an input amplifier or crystal oscillator. When an external reference signal is used this is simply AC coupled to pin 28, the base of the input emitter follower. When a low phase noise synthesiser is required the reference signal is critical since any noise present here will be multiplied by the loop. To obtain the lowest possible phase noise from the SP8855D it is best to use the highest possible reference input frequency and to divide this down internally to obtain the required frequency at the phase detector. The amplitude of the reference input is also important, and a level close to the maximum will give the lowest noise. When the use of a low reference input frequency say 4–10MHz is essential some advantage may be gained by using a limiting amplifier such as a CMOS gate to square up the reference input. In cases where a suitable reference signal is not available, it may be more convenient to use the input buffer as a crystal oscillator in this case the emitter follower input transistor is connected as a colpitts oscillator with the crystal connected from the base to ground and with the feedback necessary for oscillation provided by a capacitor tap at the emitter. The arrangement is shown inset in Fig. 5. SP8855D VCC 296 296 40k 296 24, 25 Fpd, Fref OUTPUTS OSCILLATOR OSCILLATOR CAPACITOR CRYSTAL 3k 3k VCC 40k 28 27 60k 60k 50mA 100mA 100mA 50mA 100mA 0V 3.3mA 0V Fig. 7g Fpd and Fref outputs Fig. 7 Interface circuit diagrams (cont) Fig. 7h Reference oscillator APPLICATIONS RF layout The SP8855D can operate with input frequencies up to 1.7GHz but to obtain optimum performance, good RF layout practices should be used. A suitable layout technique is to use double sided printed board with through plated holes. Wherever possible the top surface on which the SP8855D is mounted should be left as a continuous sheet of copper to form a low impedance earth plane. The ground pins 12 and 16 should be connected directly to the earth plane. Pins such as VCC and the unused RF input should be decoupled with chip capacitors mounted as close to the device pin as possible with a direct connection to the earth plane, suitable values are 10nF for the power supplies and