SP8855E

SP8855E 2.8GHz Parallel Load Professional Synthesiser Advance Information DS4239 ISSUE 3.0 PIN 1 March 1999 The SP8855E is one of a family of parallel load synthesisers containing all the elements apart from the loop amplifier to fabricate a PLL synthesis loop. Other devices in the series are the SP8852E which is a fully programmable device requiring two 16 bit words to set the RF and reference counters, and the SP8854E which has hard wired reference counter programming and requires a single bit word to program the RF divider. The SP8855E replaces the existing SP8855D. The SP8855E is intended for applications where a fixed synthesiser frequency is required although it can also be used where frequency selection is set by switches. In general the device will be programmed by connecting the programming pins to either VCC or ground. Additional hard wired inputs can be used to control the Fpd and Fref outputs set the control direction of the loop and select the phase detector gain. Another input may be used to disable the phase detector output. The device is available in both plastic (HP) and ceramic (HC) J-leaded 44-lead chip carrier. Ambient temperature ranges available are shown in the ordering information. HC44 OPTIONAL PIN 1 REFERENCE Features • • • • • • • • • • 2.8GHz Operating Frequency (IG GRADE) Single 5V Supply Operation High Comparison Frequency 50MHz High Gain Phase Detector 1mA/rad Programmable Phase Detector Gain Zero "Dead Band" Phase Detector Wide range of RF and Reference Divide Ratios Programming by Hard Wired Inputs Low cost plastic package option GPS HI-REL level a screened option Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Description Input bus bit 10 Input bus bit 9 Input bus bit 8 Input bus bit 7 Input bus bit 6 Input bus bit 5 Input bus bit 4 Input bus bit 3 Input bus bit 2 Input bus bit 1 Input bus bit 0 0V (prescaler) RF input RF input VCC + 5V (prescaler) VEE 0V Lock detect output C-lock detect Rset Charge pump output Charge pump ref. Fref/Fpd enable Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 HP44 Description Control Direction Fpd* Fref* +5V Ref. osc capacitor Ref in/XTAL Reference bit 9 Reference bit 8 Reference bit 7 Reference bit 6 Reference bit 5 Reference bit 4 Reference bit 3 Reference bit 2 Reference bit 1 Reference bit 0 Phase Detect Enable Phase Detect Gain 1 Phase Detect Gain 0 Input bus bit 13 Input bus bit 12 Input bus bit 11 Absolute Maximum Ratings Supply voltage Storage temperature Operating temperature Prescaler & reference Input Voltage Data Inputs Junction temperature -0.3V to 6V -65 °C to +150°C -55°C to +100°C 2.5V p-p VCC +0.3V VEE -0.3V + 175°C (HC package) + 150°C (HP package) *Fpd and Fref outputs are reversed using the Control Direction input. The table above is correct when pin 23 is high. Figure 1 - Pin connections - top view 26 +5V 26 VEE 0V PHASE DETECTOR 2 SP8855E RF DIVIDER PROGRAMMING B0 B2 B3 B13 7 6 54 3 2 Fpd 11 BIT M COUNTER 1 44 43 42 9 8 10 MODULS CONTROL 11 3 BIT A COUNTER Vcc + 5V PRESCALER RF INPUT ÷ 8/9 0V PRESCALER 20 21 17 19 18 24 25 22 23 40 41 10 BIT REFERENCE DIVIDER Fref CHARGE PUMP OUTPUT CHARGE PUMP REFERENCE LOCK DET O/P R set C - LOCK DETECT Fpd * Fref * Fpd / Fref ENABLE CONTROL DIRECTION PHASE DETECTOR GAIN 1 PHASE DETECTOR GAIN 0 PHASE DETECTOR ENABLE Advance Information 39 27 28 REFERENCE REFERENCE CRYSTAL CAPACITOR 38 37 36 35 34 33 32 31 30 29 BIT 0 BIT 9 REFERENCE DIVIDER PROGRAMMING * Fpd and Fref outputs are reversed using the Control Direction input. Diagram is correct when pin 23 is high. Figure 2 - SP8855E block diagram Advance Information PIN Description PIN 1,2,3,4,5,6,7,8,9,10,11,42,43,44 Description SP8855E These pins are the data inputs used to set the RF divider ratio (M.N+A). Open circuit = 1 (high) on these pins. Inputs are transparent into the data buffers. Balanced inputs to the RF pre-amplifier. For single ended operation the signal is AC coupled into pin 13 with pin 14 AC decoupled to ground (or vice -versa). Pins 13 and 14 are internally DC biased. A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give an external indication of phase lock. A capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indicator. An external resistor from Pin 19 to V CC sets the charge pump output current The phase detector output is a single ended charge pump sourcing or sinking current to the inverting input of an external loop filter. Connected to the non-inverting input of the loop filter to set the optimum DC bias. Part of the data input bus. When this pin is logic HI the F ref and Fpd outputs are enabled. Open circuit = HI This pin controls charge pump output direction. For Pin 23 HI the output sinks current when F pd > Fref or when the RF phase leads Ref phase. For Pin 23 LO the relationship is reversed. (see table 2). Changing the state of pin 23 reverses the pins on which Fref and Fpd output occur. See pin 24 and Pin 25 below for details. Open circuit = HI. RF divider output pulses. Fpd = RF input frequency /(M.N+A). Pulse width = 8 RF input cycles (1 cycle of the divide by 8 prescaler output). Reference divider output pulses. Fref = Reference input frequency/R. Pulse width = high period of Ref input. Leave open circuit if an external reference is used. See fig. 5 for typical connection for use as an onboard crystal oscillator. This pin is the input buffer amplifier for an external reference signal. This amplifier provides the active element if an onboard crystal oscillator is used. These pins set the Reference divider ratio R. Open circuit = HI. When this pin is HI the phase detector output is enable. Open circuit = HI. These pins set the charge pump current multiplication factor (see table 1). Open circuit = HI. 13, 14 (RF INPUT) 17 (LOCK DETECT INPUT) 18 (C-LOCK DETECT) 19 (Rset) 20 (CP OUTPUT) 21 (CP REF) 22 (Fref /Fpd ENABLE 23 (CONTROL DIRECTION) 24 = Fpd if Pin 23 is HI = Fref if Pin 23 is LO = Fref if Pin 223 is HI 25 27 (Reference Oscillator Capacitor) 28 (Ref IN/XTAL) 29,30,31,32,33,34,35,36,37,38 39 (Phase Detector ENABLE) 40, 41 (PD Gain) 3 SP8855E Advance Information Electrical Characteristics Guaranteed over the full temperature and supply voltage range (unless otherwise stated) Temperature Tamb for IG parts -40°C and +85°, Temperature Tcase for Temperature Tamb for KG parts -55°C and +100°C, MA part -55°C and +125° C Supply Voltage = 4.75V and 5.25V Characteristics Supply current15, 26 RF input sensitivity RF division ratio Reference division ratio Comparison frequency Reference input frequency 13, 14 13,14,24 28, 25 28,24,25 28 10 Pin Min 180 -5.0 56 1 Value Typ 240 Units Max mA +7.0 16383 1023 50 100 MHz MHz dBm Conditions 100MHz to 2.8/2.7GHz See Fig. 3 Reference division ratio ≥ 2 at frequencies >50MHz also see Note 1. Sine Wave 10-100MHz 2.2K to 0V 2.2K to 0V IOUT = 3mA Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Reference input voltage Fref/F pd output voltage high Fred/Fpd output voltage low Lock detect output voltage Charge pump current at multiplication factor = 1 Charge pump current at multiplication factor = 1.5 Charge pump current at multiplication factor = 2.5 Charge pump current at multiplication factor = 4.0 Input bus high logic level 28 24, 25 24, 25 17 19,20,21 630 1200 - 0.8 - 1.4 300 2000 mV p-p Vwrt VCC Vwrt VCC 500 ±1.7 ±2.5 ±4.6 ±6.5 mV mA ±1.4 ±2.0 ±3.4 ±5.4 3.5 ±1.5 ±2.3 ±3.8 ±6.1 19,20,21 mA 19,20,21 mA 19,20,21 mA 1-11, 22 23, 29-44 1-11, 22 23,29-44 1-11,22 23,29-44 1-11, 22 23,29-44 20 V Input bus low logic level 1 V µA µA Input bus current source -200 VIN = 0V VIN = VCC Vpin 20 = Vpin 21, Ipin 19 = 1.6mA Ipin 19 =1.6mA current multiplication factor = 1 Ipin 19 =1.6mA current Input bys current sink 10 ±5 VCC-0.5 VCC-1.6 Up down current matching % Charge pump reference voltage Charge pump reference voltage 21 V 21 V multiplication factor = 4 19 0.5 1.6 2 V mA See Note 2 Ipin 19 = 1.6mA Rset current Rset Voltage 19 Notes: 1. Lower reference frequencies may be used if slew rates are maintained. 2. Pin 19 current x multiplication factor must be less than 5mA if charge pump accuracy is to be maintained. 4 Advance Information SP8855E TYPICAL OVERLOAD +20 +10 +7 GUARANTEED OPERTAING WINDOW -5 OPERATING AREA FOR 'IG' PARTS ONLY -10 -20 TYPICAL SENSITIVITY -30 100MHz 1GHz 2.7GHz 2.8GHz 2GHz 10GHz INPUT DRIVE REQUIREMENTS Figure 3 - SP8855E +j1 +j0.5 +j2 Zo = 50Ω +j0.2 0 1.1GHz 0.2 0.5 1 50MHz 2.5GHz -j0.2 -j0.5 -j1 -j2 Figure 4 - R.F. input impedance 5 SP8855E Advance Information +5V VCC * VALUES DEPEND ON APPLICATION RF COUNTER PROGRAMMING 44 43 42 41 40 1k REFERENCE COUNTER PROGRAMMING 2 1 VCC 39 38 37 36 35 34 33 32 31 30 29 LOOP FILTER * * + OP27 ETC 100n * +30V 4 6 7 8 9 10 11 12 1n VCO APPLICATION USING CRYSTAL REFERENCE 13 14 15 16 17 SP8855 21 23 24 25 20 22 26 18 2k2 33p 10MHz CRYSTAL 19 Fpd Fref 100p 1n 10n *100n 1µ 27 28 1n Ref in 27 28 5 3 10n Figure 5 - Typical application diagram Description Prescaler and AM counter The programmable divider chain is of AM counter construction and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which performs the bulk multi-modulus division. A programmable divider of this construction has a division ratio of MN+A and a minimum integer steppable division ratio of N(N-1), where N is the prescaler ratio. Programming The device is programmed by connecting the programming pins to either VCC or ground. The programming inputs will go high if left open circuit but for best noise immunity a wired connection to VCC is preferable. The programming inputs can be driven from TTL or CMOS logic levels if required. Reference input The reference source can be either driven from an external sine or square wave source of up to 100MHz or a crystal can be connected as shown in Fig. 5. Phase Comparator and Charge pump The SP8855E has a digital phase/frequency comparator driving a charge pump with programmable current output. The charge pump current level at the minimum gain setting is approximately equal to the current fed into the Rset input pin 19 and can be increased by programming pins 40 and 41 according to Table 1 by up to 4 times. Pin 40 Pin 41 Current Multiplication Factor 1.0 1.5 2.5 4.0 0 0 1 1 0 1 0 1 Table 1 6 Advance Information Pin 19 current . VCC - 1.6V Rset SP8855E mA/radian 2π To allow for control direction changes introduced by the design of the PLL, pin 23 can be programmed to reverse the control direction of the loop by transposing the Fpd and Fref connections. In order that any external phase detector will also be reversed by this function, the Fpd and Fref outputs are also interchanged as shown in Table 2. Phase detector gain = Ipin 19 (mA) X multiplication factor The charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. The matching of the charge pump up and down currents will only be maintained if the charge pumps output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. The lock detect circuit can drive an LED to give visual indication of phase lock or provide an indication to the control system if a pull-up resistor is used in place of the LED. A small capacitor connected from the C-lock detector pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. The phase detector can be disabled by pulling pin 39 to logic low. Output for RF Phase Lag Control direction pin 23 pin 20 1 Current Source 0 Current Sink Table 2 The Fpd and Fref signals to the phase detector are available on pin 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. When the Fpd/Fref outputs are to be used at high frequencies, an external pull down resistor of minimum value 330Ω may be used connected to ground to reduce the fall time of the output pulse. 29 29 30 28 31 27 32 26 33 25 34 24 35 23 36 22 37 21 38 20 PIN TEN BIT REFERENCE COUNTER REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION 40 41 42 43 44 1 2 3 28 4 27 5 26 6 25 7 24 8 23 9 22 10 21 11 20 PIN 213 212 211 210 29 PHASE DETECTOR GAIN CONTROL see Table 1 M COUNTER 3 BIT A COUNTER REFERENCE DIVIDER PROGRAMMING PIN ALLOCATION RF Figure 6 - Programming data format 7 SP8855E Advance Information Vcc Vcc 40k 40k 5k 5k RF INPUT13 4k 325 325 500 INPUT 500 50µA 0V RF INPUT 14 3mA 3k 0V Figure 7a - RF and reference divider programming bits, Fpd/Fref enable, control direction and phase detector gain control inputs C-LOCK DETECT (HIGH WHEN LOCKED) 18 Vcc 3k 50k V REF 4.7V 3k Figure 7b - RF inputs Vcc 2k5 2k5 LOW WHEN LOCKED 3k 17 LOCK DETECT OUTPUT 3k 400µA 20µA 100µA 0V 100 100 1k 11 0V Figure 7c - Lock detect decouple Figure 7d - Lock detect output CHARGE PUMP R set 19 OUTPUT REFERENCE Vcc 20 21 450 450 Vcc CHARGE PUMP CURRENT SOURCES UP Vcc DOWN 83 83 130 2mA Figure 7e - Rset pin Figure 7f - Charge pump circuit Figure 7 - Interface circuit diagrams 8 Advance Information SP8855E Vcc Vcc 296 296 40k OSCILLATOR OSCILLATOR CAPACITOR CRYSTAL 3k 3k 40k 296 24, 25 Fpd, Fref, OUTPUTS 28 27 60k 50µA 100µA 50µA 100µA 100µA 60k 3.3mA 0V 0V Figure 7g - Fpd, and Fref outputs Figure 7h - Reference oscillator Applications RF Layout The SP8855E can operate with input frequencies up to 2.8GHz but to obtain optimum performance, good RF layout practices should be used. A suitable layout technique is to use double sided printed circuit board with through plated holes. Wherever possible the top surface on which the SP8855E is mounted should be left as a continuous sheet of copper to form a low impedance earth plane. The ground pins 12 and 16 should be connected directly to the earth plane. Pins such as Vcc and the unused RF input should be decoupled with chip capacitors mounted as close to the device pin as possible with a direct connection to the earth plane, suitable values are 10nF for the power supplies and