SP8858IGHPAS

SP8858 1·5GHz Professional Synthesiser Supersedes March 1997 version, DS3843 - 3.0 DS3843 - 4.1 July 1998 LOCK DETECT FEATURES s Low Residual Phase Noise (see Reference 1) s Operation to 1·5GHz over Full Temperature Range s High Input Sensitivity s Improved Linear Digital Phase Detector s Programmable Charge Pump Current: 10µA to 2 mA s On-chip 416/17 or 48/9 Dual Modulus Prescaler s Three-wire Serial Data Interface s 13-bit Reference Counter s 15-bit M Counter s Stores an Alternative Programming Word s Facility to Program A counter Only s Power Saving Standby Mode ABSOLUTE MAXIMUM RATINGS Supply voltage Storage temperature Operating temperature Prescaler input voltage 20·3V to 17V 265°C to 1150°C 255°C to 1125°C 2·5V p-p 4 3 2 1 28 27 26 25 24 23 FREF* POWER DOWN VEE4 VCC4 VCC1 RF INPUT RF INPUT 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CP REF FPD* VEE3 The SP8858 is a single chip synthesiser intended for PLL signal synthesis applications up to 1.5GHz and includes a dual modulus prescaler (4N/N11), programmable A, M and R dividers, digital phase detector, charge pump and lock detect circuits. The SP8858 is a development of the SP8853 synthesiser with low residual phase noise, increased dynamic range above 1GHz and an improved high gain phase detector design that eliminates the dead-band. The low prescaler modulus, programmable to either 16/17 or 8/9, together with the 15-bit M counter and 13-bit reference counter make this device ideal for a diverse range of high performance applications. The nominal phase detector gain is set by a reference current into pin 24 and the gain can be varied over a 4:1 range when the device is programmed. The dividers, the phase detector sense, the prescaler modulus and the data buffer control logic are also programmable using the three wire serial interface. An alternative 22-bit control word for the A and M dividers and phase detector gain can be stored so allowing fast frequency hopping and bandwidth switching by simply toggling the logic level on pin 13 (F1/F2). In addition, the A counter of the ‘active’ buffer can be programmed with only 6 bits, allowing fast hopping to adjacent channels. A simple exclusive - or lock detect circuit is also provided, the sensitivity of which is determined by an external capacitor. LOCK DETECT 4 3 2 1 28 27 26 25 24 23 FREF* POWER DOWN VEE4 VCC4 VCC1 RF INPUT RF INPUT CP REF FPD* VEE3 NC NC CD 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CP OUTPUT RPD VCC3 GROUND XTAL 1 XTAL2 VEE2 SP8858 22 21 20 19 DATA CLOCK ENABLE F1/F2 VEE1 NC VCC2 HC28 NC NC CD CP OUTPUT RPD VCC3 GROUND XTAL 1 XTAL2 VEE2 SP8858 22 21 20 19 DATA CLOCK ENABLE F1/F2 VEE1 NC VCC2 HP28 Fig. 1 Pin connections (top view) ORDERING INFORMATION SP8858 IG HCAR 240°C to 185°C (Industrial grade) SP8858 MG HCAR 255°C to 1125°C (Military grade) SP8858 IG HPAS 240°C to 185°C (Industrial grade) SP8858 Pin 4 Description FPD = M divider output pulses = RF input frequency 4(MN1A) when SENSE bit in the programming word = ‘0’. When SENSE bit = 1, this pin is FREF = R divider output pulses = reference input frequency 4R. (see Data Entry and Control description and Fig. 6). FREF = R divider output pulses when SENSE bit in the programming word = ‘0’. When SENSE bit = 1, this pin is FPD = M divider output pulses (see Data Entry and Control description and Fig. 6). With this pin held high the device is in the power saving standby mode. The serial interface shift register and data buffers remain active at all times so that the device can still be programmed in this mode. Balanced inputs to the RF preamplifier. For single ended operation the signal is AC coupled into pin 11 with pin 10 decoupled to ground or vice-versa. The logic level on this input determines which of the two words stored in the internal buffers is used to reload the A and M dividers at the end of the count cycle. With F1/F2 high the F1 buffer is selected. Serial data on this line is clocked into a shift register under control of CLOCK and ENABLE. Clocks the data into the shift register. Logic high on this pin allows data to be clocked into the shift register and the subsequent falling edge loads the buffer chosen by the LSBs of the programmed word. The clock input is ignored when ENABLE is low. This pin is the input to a buffer amplifier if an external reference signal is provided. Alternatively, the amplifier provides the active element for a reference oscillator if a quartz crystal is connected at this point (see Applications). Leave open circuit if an external reference is used or connect load capacitors for the chosen crystal (see Applications) An external resistor connected between this pin and VCC sets the charge pump output current. A multiplication factor can also be programmed into the device (see Table 3) The phase detector output is a single-ended charge pump sourcing or sinking current to the inverting input of an external loop filter. Connected to the non-inverting input of the loop filter to set the DC bias. A current sink into this pin is enabled when the lock detect circuit indicates lock. Used to give external indication of phase lock. A capacitor connected to this point determines the lock detect integrator time constant and can be used to vary the sensitivity of the phase lock indicator. Pre-amp and prescaler supply. Oscillator supply. Charge pump supply. ECL supply. 5 6 (POWER DOWN) 10, 11 (RF INPUT) 13 (F1/F2) 14 (DATA) 15 (CLOCK) 16 (ENABLE) 20 (XTAL 2) 21 (XTAL 1) 24 (RPD) 25 (CP OUTPUT) 26 (CP REF) 27 (LOCK DETECT) 28 (CD) 9 (VCC1), 12 (VEE1) 18 (VCC2), 19 (VEE2) 23 (VCC3), 2 (VEE3) 8 (VCC4), 7 (VEE4) Table 1 Pin descriptions 2 SP8858 MODULUS CONTROL 10 11 RF INPUT RF INPUT 16/17 OR 8/9 XFV M COUNTER A FV COUNTER RESET fPD 28 PD GAIN 2 BITS LOCK DETECT CD 15 BITS 4 BITS 27 LOCK DETECT F1/F2 13 F1/F2 22-BIT DATA BUFFER 3 BITS SELECT F1/F2 ACTIVE A C1 C2 LSB SELECT R 16-BIT REFERENCE BUFFER VREF SELECT MODULUS 13 BITS DECODE XFR R DIVIDER FR DISABLE PD1 PD2 BUFFER FV 24 XFV FR MSB XFR PD SENSE 4 5 FPD* FREF* PHASE CHARGE DETECTOR PUMP 25 25 RPD CP OUTPUT CP REF DATA 14 22 BITS CLOCK ENABLE 15 DATA INTERFACE 24-BIT SHIFT REGISTER 16 BITS 16 POWER 6 DOWN *FREF and FPD outputs are reversed by the phase detector sense bit in the F1/F2 programming word. The pin allocations shown are correct when the sense bit is low (see Fig. 6). 20 21 CRYSTAL Fig. 2 SP8858 block diagram 500 INPUT VOLTAGE (mV RMS) 400 GUARANTEED OPERATING WINDOW 48/9 MODE 300 200 GUARANTEED OPERATING WINDOW 416/17 MODE 100 50 0 0 80 500 750 1000 1500 TYPICAL SENSITIVITY FREQUENCY (MHz) Fig. 3 Typical input characteristics and input drive requirements 3 SP8858 ELECTRICAL CHARACTERISTICS These characteristics are guaranteed over the following range of operating conditions unless otherwise stated: Supply voltage VCC = 14·75V to 15·25V. TAMB = 255°C to 1125°C (Military), 240°C to 185°C (Industrial) Value Characteristic Pin Min. Typ. 95 35 Max. 110 45 50 400 240 56 Comparison frequency Reference oscillator input frequency External reference input voltage Reference division ratio Data clock repetition rate, tREP Minimum setup time, tS DATA input high DATA input low CLOCK input high CLOCK input low ENABLE high ENABLE low F1/F2 input high F1/F2 input low POWER DOWN input high POWER DOWN input low F1/F2 input current POWER DOWN input current Current into RPD Charge pump current Charge pump current accuracy Charge pump leakage LOCK DETECT output voltage when in lock FPD and FREF output voltage swing LOCK DETECT output resistor 4,5 20,21 20 20,5 15 14,15 14 14 15 15 16 16 13 13 6 6 13 6 24 25 25 25 27 27 0·9 kΩ 2 50 50 0·6VCC VEE 0·6VCC VEE 0·6VCC VEE 0·6VCC VEE 0·6VCC VEE VCC 0·3VCC VCC 0·3VCC VCC 0·3VCC VCC 0·3VCC 0·9VCC 0·3VCC 5 5 500 2 65 5 1 4 50 1 524287 262143 5 40 600 8191 200 ns ns V V V V V V V V V V µA µA µA mA % µA V Charge pump current = 2mA I pin 27 < 3mA VCC = 5V, external pulldown may be required 500µA34 V pin 13 = 5·0V V pin 6 = 4·5V F1 buffer selected F2 buffer selected See Fig. 4 See Fig. 4 MHz MHz mVrms See note 1 Units Conditions Supply current Supply current in power down mode Input sensitivity Input overload RF input division ratio 8,9,18,23 8 10,11 10,11 10,11,4 mA mA mVrms mVrms See Fig. 3 See Fig. 3 With 416/17 selected With 48/9 selected 27 50 NOTE 1. The reference frequency range when using a crystal oscillator is 4-20MHz. 4 SP8858 tS1tCH DATA FIRST DATA BIT LAST DATA BIT 2V tS CLOCK tCH tCL tREP 2V ENABLE 2V tS-EN tREP = tCH 1 tCL MIN tS = 50ns MIN tCH = 100ns MIN tCL = 100ns MIN tE = 50ns MIN tS-EN = [(31M)N1A]4RF INPUT (Hz)150ns OR 14REFERENCE (Hz)150ns WHICHEVER IS APPROPRIATE (SEE DATA ENTRY AND CONTROL) tE Fig. 4 DATA, CLOCK and ENABLE timing requirements MODULUS CONTROL RF INPUT PRESCALER 4N / N11 A COUNTER RESET M COUNTER RF INPUT 4(MN1A) Fig. 5 5 SP8858 DESCRIPTION Prescaler and Dividers The block diagram of a dual modulus divider arrangement is shown in Fig. 5. The N/N11 prescaler, together with the A and M dividers, divide the RF input frequency down to the comparison frequency at the phase detector input. The comparison frequency, FREF, sets the resolution of a single loop synthesiser; when A is incremented (or decremented) by one, the loop output frequency automatically increments (or decrements) by FREF Hz. When the dividers are reset, at the end of each count cycle, the modulus of the prescaler is set to N11 and the input frequency to the A and M dividers is then RFinput 4(N11) Hz. The output of the A counter controls the prescaler modulus, which is set to N when A reaches its programmed value. The M divider continues to count at the rate RFinput 4N until it reaches its programmed value, at which point the dividers are reset and the count cycle starts again. The division ratio of this arrangements is therefore A(N11) 1 (M2A)N = MN1A It is evident that for this arrangement to work M must always be programmed greater than or equal to A and A must be able to count to N21. These restrictions set a minimum count of N 22N; below this value some division ratios will not be available. The SP8858 prescaler can be set to 48/9 or 416/17 mode by setting the appropriate bit of the reference word. The A divider is a 4-bit counter, whilst the M divider is a 15-bit counter. The minimum division ratio, with the 8/9 prescaler, is 8228 = 56, whilst the maximum division ratio, with the 16/17 prescaler, is 16(21521)1(2421) = 524287. If the 8/9 prescaler is used the MSB of the A counter must be programmed to 0 and the maximum RF input frequency must be reduced to 750MHz. reference current into pin 24 (RPD). An external transimpedance amplifier is required to provide the voltage drive to the VCO. This requirement is usually performed by the loop filter operational amplifier which is designed to provide a type II third order control loop. Data Entry and Control The SP8858 is programmed using the serial data interface. Data is entered into the chip on the DATA pin and clocked into the internal shift register by the positive going edge of the CLOCK signal with the ENABLE pin held high. While ENABLE is high, changes to the shift register will not affect the current count cycle. On the falling edge of ENABLE the data held in the shift register is transferred to one of the three buffers (F1, F2 or reference). Fig. 4 shows the timing requirements for these three signals. The 2 LSBs of the 24-bit shift register, C1 and C2, determine which of the three buffers is loaded with the data held in the remaining 22 bits as shown in Table 2. 2-bit SR contents C2 0 1 0 1 C1 0 0 1 1 Buffer loaded F1 F2 Active A (only the A divider of the active buffer is changed) Reference Table 2 If the F1 buffer (C2 = 0, C1 = 0) is selected the 22 MSBs of the shift register are transferred to it. 19 bits of the buffer provide the data for the A and M dividers; the three remaining bits control the charge pump current multiplication factor and the sense of the phase detector. The F2 buffer performs the same function so that an alternative divider word and/or phase detector gain can be stored. The CP current can be multiplied by up to four times by programming bits G1 and G2 as shown in Table 3. The maximum charge pump output current is 62mA. The reference current can be set by resistor RPD connected between VCC and pin 24 so that: Ipin 24 = (VCC21·5)/RPD IOUT = G3Ipin 24 (G is multiplication factor) Phase detector gain, KPD = IOUT/2p A/rad See Applications, Loop Filter Design F1 or F2 word G2 0 1 0 1 G1 0 0 1 1 Charge pump 1 current (µA) 50 75 125 200 Charge pump 2 multiplier 1 1·5 2·5 4 Reference Source and Divider The reference source for the SP8858 is obtained from an on-chip oscillator, stabilised by an external quartz crystal. The oscillator circuit will also function as a buffer amplifier if an external reference is preferred. In the latter case the signal, should be AC coupled into pin 20 (see Fig. 12). The reference oscillator drives a divider stage, the output of which is the reference signal to the phase comparator. The PLL controls the input voltage to an external VCO so that the divided VCO signal is phased locked to this reference signal. The dynamics of the control loop are determined by the external loop filter. The 13-bit reference divider is fully programmable and can be set to any ratio between 1 and 8191. The programmed word is stored in the internal reference buffer. Phase Comparator and Charge Pump The digital phase detector is sensitive to frequency and phase errors. The basic circuit for a conventional digital phase/frequency detector is based on two D type flip-flops. Initially the flip-flops are reset, each one is then set by the respective pulses of the M and R divider outputs. When both flip-flops have been set they are immediately reset. In this way the output of one flip-flop is a pulse whose width is proportional to phase difference, whilst the second flip-flop is a narrow pulse determined by the time to reset. The phase detector outputs drive a charge pump amplifier. One output controls a constant current source, the other an identical current sink connected to the same node (CP output, pin 25). The SP8858 phase/frequency detector has been modified and improved to provide a linear characteristic, thus eliminating deadband effects. The phase detector gain is determined by the output current from the charge pump (±IOUT) which is set by a Table 3 Charge pump currents When the SENSE bit is set to 1 the inputs and clocks to the phase detector flip-flops are reversed. The bit should be set to 1 for a VCO with a positive frequency v. voltage characteristic. The sense bit also swaps the outputs FREF and FPD on pins 4 and 5. Fig. 1 shows the pin-out for SENSE = 0. The active buffer, i.e. the one that is currently used to update the dividers, is selected at pin 13 (F1/F2). A high on this pin selects F1. The F2 word can be updated while F1 is 6 SP8858 PHASE DETECTOR GAIN CONTROL (SEE TABLE 3)       G2 G1 218 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 MSB LSB C2 C1                       15-BIT PROGRAMMABLE COUNTER (M COUNTER) PHASE DETECTOR SENSE BIT      4-BIT PROGRAMMABLE COUNTER (A COUNTER) Fig. 6a F1 or F2 word, bit allocation with 416/17 selected PHASE DETECTOR GAIN CONTROL (SEE TABLE 3) MUST BE ZERO LSB MSB G2 G1 217 216 215 214 213 212 211 210 29 28 27 26 25 24 23 0 22 21 20                       15-BIT PROGRAMMABLE COUNTER (M COUNTER) PHASE DETECTOR SENSE BIT Fig. 6b F1 or F2 word, bit allocation with 48/9 selected DUAL MODULUS N RATIO SELECT 0 = 416/17 1 = 48/9 MSB LSB PD1 PD2 212 211 210 29 28 27 26 25 24 23 22 21 20    PHASE DETECTOR BISTABLE CONTROL (SEE TABLE 4) DATA 22 BITS CLOCK 22 CLOCKS ENABLE DATA LOADS ON FALLING EDGES                        13-BIT PROGRAMMABLE COUNTER (R COUNTER) CONTROL LOGIC (SEE TABLE 3) Fig. 6c Reference word bit allocation F1 WORD 00 F2 WORD 22 BITS 10 22 CLOCKS 16 CLOCKS Fig. 6d Data load sequence Fig. 6 Data formats      C2 C1 REF WORD 16 BITS 11 3-BIT CONTROL PROGRAMMABLE LOGIC COUNTER (SEE (A COUNTER) TABLE 3)       CONTROL LOGIC (SEE TABLE 3)       C2 C1 7 SP8858 controlling the dividers without disrupting the loop (and vice versa). This facility can be used to reduce synthesiser switching time by preparing the non-active buffer prior to the instant of switching and can also be used to modify the open loop gain. To ensure reliable data is loaded into the dividers the internal control circuits ensure that the buffer data can only be updated if the remaining M count is greater than 3. Given this restriction, the maximum time taken to update the buffer after the negative going ENABLE transition (or after F1/F2 has been toggled) is: [(31M) N1A]/RF input150ns where update time is in seconds and RF input is in Hz. The time taken to re-program the shift register (F1or F2) is determined by the clock rate and the number of bits required and is equal to: 243tREP1tS1tE (see Fig. 4) If the reference buffer is selected (C2 = 1, C1 = 1), only the 16 LSBs of the shift register are used. 13 bits provide the data for the Reference divider. Two bits, PD1 and PD2, control the charge pump and the divider output buffer as shown in Table 4. PD2 0 0 1 1 PD1 0 1 0 1 Result FREF and FPD outputs off, charge pump on FREF and FPD outputs on, charge pump on FREF and FPD outputs on, charge pump off FREF and FPD outputs on, charge pump disabled by lock detect APPLICATIONS Introduction This section provides the basic information required to implement a complete digital PLL synthesiser based on the SP8858. A typical circuit is shown in Fig. 12 and is available on a demonstration PCB, including a serial programmer. The demonstration board can be used to evaluate the SP8858 and can be readily adapted by the system/RF designer for a specific application to aid in rapid prototype development. Users of the SP8853 should consult Appendix A for details of the design changes that are required to replace the SP8853 with the SP8858. PLL Basics A system level specification for a stable radio signal will include measures of signal stability such as a single sideband phase noise specification and a spurious output specification. The power spectrum of the composite RF output signal is influenced by a number of factors: q q q q q q q q Residual phase noise of the dividers Active loop filter residual noise Feedback divider ratio Phase detector gain VCO signal phase noise and gain Reference signal phase noise The closed loop root locations (an under damped loop will cause a noise peak) Environmental influences such as EMI and power supply noise Table 4 The remaining bit of the Reference word is used to select the prescaler modulus. A ‘1’ in this position selects the 8/9 mode. Note that when the 8/9 mode is selected the A divider only requires 3 bits; the 4th bit must be set to ‘0’. To ensure reliable data is loaded into the dividers the internal control circuits ensure that the buffer data can only be updated if the remaining R count is greater than 1. Given this restriction, the maximum time taken to update the buffer after the negative going ENABLE transition (or after F1/F2 has been toggled) is: 1/FREF150ns Only 16 bits are required to program the reference buffer, therefore reference programming time tREF is: tREF =163tREP1tS1tE (see fig. 4) If the Active A mode is programmed (C2=0. C1=1) only the four A divider bits are updated at the end of the M count. The M divider data, multiplication factor and phase detector sense remain unchanged. This can be used to frequency hop to an adjacent channel with the programming time reduced to: Programming time (Active A) = 63tREP1tS1tE The programming details discussed above are summarised in Fig. 6. A single-loop synthesiser based around the SP8858 is suitable for the synthesis of highly stable, low phase noise signals provided each of the points above are carefully considered. The block diagram of a simple PLL is shown in Fig. 7. PHASE DETECTOR (mA/RAD) KPD LOOP FILTER (V/mA) F(s) VCO (RAD/SEC/V) KVCO s FO (Hz) fo(s) fi(s) FREF (Hz) FPD (Hz) DIVIDER 4N CLOSED LOOP RESPONSE = fo(s) fi(s) = F(s)3KVCO3KPD s1F(s)3KVCO3KPD / N OPEN LOOP DC GAIN = KVCO3KPD / N Fig. 7 The basic aim is to phase-lock the VCO signal to a stable reference signal, fi(s) and, ideally, set a relatively wide closed loop bandwidth and a high DC loop gain (KPD3KVCO/N). This combination will ensure that the freerunning VCO phase noise is attenuated and that both the long-term and the short-term stability of the output signal is determined by the properties of the reference signal. A wide loop bandwidth would also be consistent with the requirement of many synthesiser specifications to change frequency and regain phase lock within a specified time limit. In practice, the following considerations limit the closed loop bandwidth and the DC gain and, consequently, limit the extent to which the ideal system is achieved: Lock Detect A simple Exclusive-OR phase detector together with an integrator and comparator are used to indicate phase lock. Capacitor CD on pin 28 sets the integrator time constant and hence the sensitivity of the lock detect function. The comparator controls a current sink connected to pin 27 which can be used together with an external LED or resistor to indicate phase lock. The lock detect can also be used to disable the charge pump by programming PD1 and PD2 of the reference word (Table 4). 8 SP8858 q q The divider in the feedback path imposes limitations on the designer because it reduces the DC gain of the loop and also because it unavoidably introduces a measurement error. The contribution to fo(s) phase noise power of the fi(s) signal, at frequency offsets within the loop bandwidth, is multiplied by N2 (i.e. increases by 20logN dB); this may impose a specific loop bandwidth for optimum phase noise. Physical imperfections in the charge pump and active loop filter circuits force periodic corrections (at the rate of 1/FREF) when the loop is phase-locked. The resulting disturbance frequency modulates the VCO producing reference sidebands in the output signal spectrum. The closed-loop bandwidth must be much less than FREF for reasonable sideband suppression. individual application and to ensure that the minimum voltage swing at the RF input is within the guaranteed operating range over the full tuning range of the application. The SP8858 incorporates a pre-amplifier at the RF input and the dividers can be seen to operate well below the guaranteed operating range. Fig. 9 shows a typical sensitivity curve as measured on the demonstration board board driven by a 50Ω signal generator (sensitivity is the lowest power level at which the divider operates without mis-counting). The dividers could be more susceptible to spurious interference at low drive levels causing the dividers to mis-count. However, driving the RF input with relatively high levels will ensure greater immunity from interference signals. j1 j 0.5 j2 The design of the filter F(s), suitable for any given application, may require careful trade-offs between the requirement to meet the phase noise and the spurious output specification and the settling time specification: Example 1 In applications where high resolution is required (the resolution is FREF Hz) the imposed closed loop bandwidth (less than FREF Hz) could result in an unacceptably long time to acquire phase lock. Example 2 If a relatively high feedback division ratio is required the 20logN increase in reference phase noise power, seen at the output, could also impose a relatively narrow closed loop bandwidth and hence a long acquisition time. The roots of the characteristic equation in the closed loop transfer function, f o(s)/f i(s), are manipulated through changes to the DC loop gain and the selection of the pole(s) and zero(s) in F(s). Careful mathematical analysis is a prerequisite to successful PLL synthesiser design. If the analysis shows that the simple PLL as shown in Fig.12 is not suitable then there are numerous modifications that can be made to the basic loop and the texts listed in the References should be consulted for more information. The Mitel Application Note AN194 (Ref. 9) provides specific guidance on noise minimisation and loop filter design for the SP8858 user. The section Loop Filter Design below gives details of the formula that can be used to implement the loopfilter given that the desired second order characteristics are known, i.e. the desired natural loop frequency vn and damping factor z. j 0.2 j5 0 0.2 0.5 1 2 5 2j 5 2j 0.2 2j 0.5 2j 1 2j 2 NORMALISED TO 50Ω START 102MHz, STOP 2000MHz Fig. 8 Demonstration board input impedance 0 25 210 215 220 225 230 235 50 100 500 1000 1500 2000 2300 DESIGN IMPLEMENTATION RF inputs The availability of a suitable VCO should be considered early in a project because information on the tuning range, the tuning gain in Hz/V and the output noise spectrum is required for the initial mathematical analysis. Variation in the tuning gain over the tuning range should be minimised as this parameter feeds into the closed loop characteristic equation. There is also a trade-off between the requirement for a high tuning gain (which requires the use of a relatively low Q resonator) and phase noise. The VCO, whether bought in or designed for the application, must also be able to simultaneously drive the SP8858 RF input as well as the input of the next stage in the system. A power splitter and active buffer may be required in some applications. The example in Fig.12 includes a simple resistive power splitter. This type of buffer introduces a 6dB loss but is adequate if the VCO output power is sufficient and if the intention is simply to assess the SP8858 by monitoring the output signal using a 50Ω measurement system. The SP8858’s RF input frequency specification covers the range 80MHz to 1·5GHz and the input impedance varies with frequency; a typical Smith chart is shown in Fig. 8. It is advisable to consider transmission line effects for each RF INPUT FREQUENCY (MHz) Fig. 9 Typical sensitivity for demo. board at 25°C Reference Input When the loop is phase-locked the output signal, Qo(s), takes on the long term stability characteristics of the reference signal. In many applications a crystal stabilised oscillator is adequate as the reference source Qi(s). The VCO output signal is divided down and compared with the reference 9 SP8858 signal at the phase detector input. The multiplied reference signal phase noise can set the limit on the achievable closein phase noise. It is important then that the reference signal is a low phase noise source with good long term stability. The residual noise of the reference divider is also important because, at some offsets from the carrier, the dividers limit the phase noise reduction that is achievable when the reference signal is divided down to FREF. More detailed advice on phase noise optimisation is given in Ref. 1. amplifier should be chosen to maintain the match between the reference current into RPD (pin 24) and the actual output current. The simplest method of setting the reference current is to connect a resistor between RPD and the supply. The voltage at pin 24 is approximately 1·5V but this varies slightly with the magnitude of the current and a simple calculation of Ipin 24 = (VCC21·5)/RPD (see Description, Data Entry and Control) is approximate. The voltage at pin 24 will also vary with temperature and the impact of the phase detector gain variations on performance should be assessed in each individual application. If it is considered important to improve the accuracy of the phase detector gain then the use of a constant current source may be more appropriate. Charge Pump Output CP OUTPUT (pin 26) and CP REF (pin 5) are connected directly to the inverting and non-inverting input of the loop filter amplifier respectively as shown in Fig. 12. The CP OUTPUT pin will source/sink a current to/from the inverting input equal in magnitude to, or a multiple of, a current reference flowing into RPD (pin 24). The multiplication factor is programmed by two bits (G1 and G2) in the F1 or F2 word (see Data Entry and Control section). The CP OUTPUT has two stable states. The ON state sourcing or sinking a fixed current and an OFF state in which no current will flow from or into the CP output pin. The proportion of time the charge pump is ON depends on the frequency/phase relationship between the reference signal (divided by R) and the VCO signal (divided by N) at the phase detector input: q Miscellaneous I/Os The SP8858 includes simple lock-detect circuit. The output signals from the Reference and RF dividers are used to drive an EXOR type phase detector. The output of this type of detector is logic high if the inputs are at the same voltage level and low if the inputs are polarised. The EXOR gate drives a buffer stage with the output collector loaded with a single 50kΩ on-chip resistor and a capacitor connected externally at pin 28 (CD). The RC serves to integrate the output pulse train from the phase detector. The capacitor voltage must reach a fixed threshold to enable a constant current sink into pin 27. The inputs POWER DOWN and F1/F2 can either be fixed at the required logic level or controlled by some peripheral circuit. See Table 1 and Fig. 12. As with any RF design work care must be taken with the power supply layout to and the returns from the IC and the physical position of the PLL on the PCB in relation to potential interference sources. The VCC supply inputs should be connected to a well regulated 5V power supply and locally decoupled; noise on the supply can influence the noise power spectrum of the output signal. The programming inputs DATA, CLOCK and ENABLE are compatible with standard CMOS and TTL logic and are subject to the timing restrictions shown in Fig. 4. q The digital phase detector is sensitive to a frequency difference between the two input signals and will source or sink a constant current for frequency differences. When phase-lock is acquired the charge pump current ON/ OFF ratio is in direct proportion to the phase difference between the two signals at the phase detector input. Starting from the state ‘charge pump OFF’ the edge of the leading signal triggers the charge pump into the ON state. The edge of the lagging signal briefly triggers a current at the output which is opposite in sign and equal in magnitude to the current already present before the charge pump returns to the OFF state. When the phase difference reaches zero the input signals simultaneously trigger brief source and sink current pulses which cancel at the output so that zero phase error gives zero output and the deadband is eliminated. The pulse widths are determined by the time taken to reset the internal flip-flops. Loop Filter Design The linear model of the PLL, as shown in Fig.7, includes an external loop-filter F(s). A filter is required that will: q In practice, when the loop is phase locked and the charge pump is predominately in the OFF state there are two imperfections to consider: q q The loop filter capacitors discharge during the period of the reference signal. A small current leaks into CP OUTPUT in the OFF state at high charge-pump current settings. q A small correction is therefore required each cycle. The resulting disturbance is attenuated by the loop but any residual ripple on the VCO control frequency modulates the VCO causing the characteristic reference sidebands. The magnitude of the sidebands that can be tolerated depends entirely on the application and can be reduced by setting a loop bandwidth very much less than the phase detector comparison frequency (FREF) or by reducing the charge-pump current (the leakage current is negligible for low charge-pump currents). The charge-pump can be set to source or sink a current for any given phase difference and the SENSE bit in the F1 (or F2) programme word is used to set the appropriate sign for the application. The SENSE bit should be set to 1 for a VCO with a positive frequency versus control voltage characteristic to ensure phase lock. The actual bias voltage at the CP REF pin varies with the magnitude of the reference current and CP OUT is held at the same voltage by the operational amplifier. A low offset voltage Add a zero to the open-loop transfer function thus allowing the designer to manipulate the closed-loop root locations through the appropriate choice of filter components. Without the filter (F(s) = 1) the closed loop is first order with the root locus travelling along the negative real axis with increasing DC gain. In this situation the designer has very little control over the fo(s)/fi(s) transfer characteristic because the selection of the gain factor KPD KVCO/N may, in practice, be limited. Introduce a second pole at the origin in order to increase the type number of the loop to type II. This is required to ensure that the steady state error signal tends to zero for a ramp in phase. In addition, a suitable interface is required to provide the transimpedance function from the charge-pump output to the VCO thus converting the output signal, in the form of current pulses, to the voltage signal required at the VCO input. The required transfer function is therefore F(s) = (s+a)/s (zero at 2a) and the loop filter is implemented using the circuit and formula shown in Fig. 10a. The closed-loop transfer function becomes: fo(s)/fi(s) = (st111)KVCOKPD/(s21st1K/C11K/C1) where K = KVCOKPD/N t1 = C1R1 10 SP8858 The selection of C1 and R1 is often approached by using the standard representation for the second order characteristic equation: s2 12zv n1v n2 and selecting the natural-loop frequency and the damping factor z to give the desired response. The time constants are calculated using: 2zvn = t1K/C1 and vn2 = K/C1 so that C1 = K/vn2 and R1 = 2zvn/K Alternatively, the loop filter and formula shown in Fig. 10b can be used to introduce a pole in F(s) at 21/t2 which will provide additional roll-off in the closed loop transfer characteristic in order to attenuate the reference sidebands. The closed loop transfer function becomes: higher order loops to use CAD tools to assess stability. Popular analysis tools taken from control theory, such as root locus and Bode diagrams, are useful to aid the design of the closed loop PLL system. AN194 describes these tools in more detail and introduces a loop filter design methodolgy aimed at optimising the phase noise performance. Loop filter design example Use the demonstration board to generate a 1GHz signal with a resolution of 500kHz (N = 5000) and reference oscillator frequency of 40MHz. Set natural loop frequency, vn, to 2p3104 rad/s and damping factor to 0·7. The MQE001-1016 VCO gain, KVCO, is nominally 25MHz/V. Set the phase detector output current to 2mA so that KPD = 2 31023/2p A/rad. Using the above formula, calculate the loop filter R and Cs. K = 2p32531063231023/2p35000 = 10 C1 = 10/(2p3104)32 ≈ 2·531029 R1 = 230·732p3104/10 ≈ 8796 C2 = C1/10 ≈ 0·2531029 Realise the loop filter with C1 = 2·2nF, C2 = 220pF and R1 = 8·2kΩ The single sideband phase noise specturm for . this example is shown in Fig. 11. C2 C1 R1 fo(s) [s(t11t2)11]KVCOKPD = fi(s) [C1t2s31C1s21K(t11t2)s1K] Care must be taken when choosing C2 to ensure that the additional pole does not unduly affect the stability margins of the loop. In practice, a simple and useful rule of thumb is to set the desired second order response as above and then set C2 to be 1/10 of C1. It is advisable when designing third order or C1 R1 Ii(s) − + V o ( s) / Ii(s) = [s( t 1 1 1]/sC1 where t 1 = C1R1 Vo (s) Ii(s) − + Vo (s) V o ( s) / Ii(s) = [s(t 1 1 t 2) 1 1]/sC1(s t 2 1 1) where t 1 = C1R1 and t 2 = C2R1 Fig. 10a Fig. 10 Loop filters Fig. 10b 0 210 220 230 240 NOISE AMPLITUDE (dBc/Hz) 250 260 270 280 290 2100 2110 2120 2130 2140 2150 2160 2170 10Hz 100Hz 1kHz 10kHz 100kHz FREQUENCY Fig. 11 11 SP8858 FREF FPD C4 R1 1VOP C6 R12 R13 15V 15V R2 15V POWER DOWN 6 26 25 5 4 24 27 21 − OP27 + R10 2VOP CONTROL 33p 20 33p 10MHz MURATA MQE001-1016 VCO 15V F1/F2 13 SP8858 Alternative reference oscillator 100n R7 SMA R6 R5 SMA RF INPUT SMA C43 10 11 28 16 15 14 20 (INADVERTENTLY LABELED R9 ON BOARD) DATA CLOCK ENABLE 40MHz REFERENCE OSCILLATOR NOTES 1. PINS 1, 3, 17 AND 21 ARE NC 2. PINS 2, 7, 11, 12, 19, AND 22 = GND 3. PINS 8, 9, 18 AND 23 = 15V 4. DECOUPLING CAPACITORS NOT SHOWN LINK TO COMPLETE PLL C40 C32 6 LOGIC ‘1’ SEND 15V R4 R3 1 3 HC20 1 5 4 2 1 C14 1 2 2 D CLR HC08 3 3 HC74 4 Q 5 CLK PRE 4 5 7 11 5 3 11 LOGIC ‘1’ OSC 2 HC00 HC08 6 5 QD LOAD 12 UP HC193a CO ABCD 15 1 10 9 QA LOAD UP HC193b ABCD 15 1 10 9 1MHz CLK 9 10 HC00 8 2 10 1 2 9 10 1 2 9 10 1 TO SHIFT REGISTER d, e AND f 9 CLK SER SH / LD CLK SER SH / LD CLK SER SH / LD QH HC165c ABCDEFGH 11 12 13 14 3 4 5 QH HC165b ABCDEFGH 11 12 13 14 3 4 5 QH HC165a ABCDEFGH 11 12 13 14 3 4 5 6 15V 6 15V 6 15V SILc SILb SILa SWITCHc SWITCHb SWITCHa FROM SECOND PROGRAMMABLE SHIFT REGISTER d, e AND f CIRCUIT IN DOTTED LINES IS DUPLICATED Fig. 12 SP8858 demonstration board 12 SP8858 Integrated circuits SP8858 1·5GHz synthesiser OP27 Operational amplifier HC00 HC08 HC20 HC74 HC165 (6 off) HC193 (2 off) Leaded resistors and capacitors R1, C4 and C6: Application specific to define the loop filter characteristic (no components fitted) R2: 6·8kΩ C1, C2, C7 and C10: 10µF Tantalum C3, C5, C8 and C9: 0·1µF Ceramic Chip resistors (0805) R3, R12, and R13: 3·3kΩ R4:10k Ω R5, R6 and R7: 15Ω R8: 100Ω R10: 2·2kΩ R11: No component Chip capacitors (0805) C11 through C26, C28, C29, C33, C34, C36 through C39, C41 and C42: 0·1µF C14: 1nF C32: 220pF C40 and C43: 100pF C27, C30, C31 and C35: No components Miscellaneous Murata MQE001-106 VCO 40MHz crystal oscillator 1MHz clock oscillator for programmer logic PCB keyboard switch (SEND) Slide switches (3 off) (SELECT, F1/F2, POWER DOWN) 16-pin DIL switch (6 off) (SIL a, b, c, d, e and f) SMA PCB mounting socket (3 off) Table 5. Demonstration board parts list APPENDIX A: SP8853 TO SP8858 The SP8858 is not a drop-in replacement for the SP8853; minor modifications will be required to a SP8853-based design if the SP8858 is to be used in its place. The changes mainly affect the charge pump output pins as shown in Table 6 below. The SP8858 has only one charge pump output. In addition the modifications have: q Increased the operating frequency range for both the RF and reference input q Simplified the lock detect circuit q Increased the maximum charge-pump current specification to 2mA. Recalculate the loop filter components using formula in Application section. PIn No. 1 3 25 26 SP8853 Internally connected PD1 output PD2 output NC SP8858 NC NC CP OUTPUT CP REF REFERENCES 1. Knights P.J., Analysis and Design of a SP8858 Digital PLL Synthesiser for Low Phase Noise, Proceeding of RF Expo East 1994, Nov 1994. 2. Gardener F.M., Phaselock Technique, Wiley 1979. 3. Rohde U.L., Digital Frequency Synthesisers Theory and Design, Prentice Hall 1983. 4. Manassewitsch V., Frequency Synthesisers Theory and Design, Wiley 1980. 5. Philips C.L. and Harbur R.D., Feedback Control Systems, Prentice Hall 1991. 6. Scherer D., Learn About Low Noise Design, Microwave April 1979 p.116. 7. Robins W.P., Phase Noise in Signal Sources, Peter Peregrineus Ltd. (IEE) 1991. 8. Breed G.A. (ed.), Frequency Synthesis Handbook, A Collection from RF Design, Cardiff Publishing Co. May 1992. 9. AN194, The SP8858 Synthesiser: Design for Low Phase Noise, Mitel Semiconductor Table 6 13 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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