VP7610

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ AUGUST 1996 DS4585 - 1.6 VP7610 COLOUR DIGITAL VIDEO CAMERA DECODER IC The VP7610 iCamHost™ Processor chip can decode the signals from a variety of iVision™ compatible digital video cameras (such as Silicon Vision’s iCam™) and process them for use in a host computer system. Digital cameras can offer real cost and performance gains in applications which require a digital video input, and iVision technology realises both these benefits. In a typical analog camera the digitised output from the CCD imager is normally encoded into an analog composite video signal which then has to be redigitised at the input to the host system. By employing the iVision approach the output from the camera is maintained as a digital signal, but in a format which allows for a low cost 9wire connection to the host. Eliminating the unnecessary conversion to an analog signal and back again not only saves cost, but also avoids any possible degradation of image quality. Other benefits include direct control of the camera from the host and the ability to power the camera from the host system so saving the cost of a separate power supply. The VP7610 supports two software selectable CamPort™ interface ports, either of which can receive the digital video from an iVision™ compatible digital video camera. The output is a standard colour digital video signal, similar to standard composite analog-digital decoder chips such as the Philips SAA7110 and SAA7111. All iCamHost™ operating modes are controlled by the host PC via an I2C interface. Hardware I/O controls include output enable and I2C address offset. NOTE: iCamTM, CamPort™ and iCamHost™ are trademarks of Silicon Vision, Inc., Fremont, CA. FEATURES s Accommodates different camera configurations based on a variety of CCD imager resolutions s Requires only a small, low-cost 9 pin mini-DIN to connect to camera s Receives the image signal from the camera in digital form at a frame rate determined by the host s Decodes all necessary synchronization and clock signals from the digital data stream s Programmable gamma correction curve in RGB colourspace s Programmable colour-separation matrix s Collects image status data within user-defined rectangular gated zone of CCD sensor s Programmable horizontal and vertical aperture correction s Pin-strap selectable output format in 16 bit YUV 4:2:2 or 8 bit CCIR 656 YUV 4:2:2 s Test pattern generator for SMPTE colourbars s Bypass mode to output unprocessed 8 bit CCD pixel samples in the luminance channel s Dual iCamPort™ camera input ports, software selectable s Completely iVision™ Compatible 768 X8X2 6 SYNC & CLK 2H LINE DELAY FIFO RAM PORT A 5 5 PORT B DEMUX & SYNC RECOVERY RAM CONTROL C M Y G PIXEL SEPARATOR COLOUR MATRIX CONVERTER RG B ADDRESS OFFSET SERIAL BUS CONTROLLER 2 I2 C FIELD & COLOUR FLAGS GAMMA CORRECTION COLOUR SPACE CONVERSION UV CHROMINANCE SUB-SAMPLING & FILTERING OUTPUT FORMATTER CC IR6 01 or CC IR6 56 16 or 8 Y UV APERTURE CORRECTION CHROMINANCE & LUMINANCE METRICS Y OUTPUT ENABLE Fig.1 Functional Block Diagram VP7610 THEORY OF OPERATION General Overview The VP7610 iCamHost™ is a fully synchronous real-time pipeline pixel processor for converting digitized CCD photosite samples into co-sited, colour calibrated, gamma corrected and aperture corrected digital video in an industryconventional format similar to analog video decoders. The VP7610 supports the full iVision™ Command Set for control of camera head functions such as frame rate, resolution, exposure and colour depth via the CamPort™ Interface. 2 Access to all registers and functions is provided by an I C state machine. Demux and sync recovery The incoming CCD photosite bytes come in a single nibble at a time in a “bi-endian” fashion from one of two CamPort™s. These nibbles are clocked in via a separate pixel clock signal. The formatting signals such as start of active video, end of active video, and start of new frame are all encoded into the nibble stream. The output is an 8 bit byte of CCD sample for each pixel clock, as well as separate horizontal and vertical sync signals. RAM control & 2H line delay FIFO RAM Since the iCamHost™ assumes an interlaced scanning CCD with a CMYG colour mosaic format, the colour content is derived from different locations around where the output video pixel is desired. Specifically, the first line from the CCD contains “red-like” colour content, alternating with the following line containing “blue-like” colour content. The third line is real-time, and the first opportunity to output properly cosited luminance and chrominance as though the colour pixels were superimposed upon themselves, all on the second line. Pixel separator Since the colourspace converter requires the 3 most recent lines of CCD data, this block handles the shuffling of either the 2 red and 1 blue line, or 2 blue and 1 red line of data. Colour matrix converter The input to this converter is derived from the relative sums and differences of the above 3 lines of sample data, and processes them through a programmable 3x3 matrix multiplier. The output is colour-separated and calibrated RGB samples. Gamma corrector Since CRT monitors have a non-linear RGB intensity response to input signal, gamma correction must be performed in RGB space as well to prevent cross-coupling errors between luminance and chrominance. This block is a programmable 16 line-segment curve generator to provide not only gamma correction, but any arbitrary contiguous curve of positive slope, with end points at any level to adjust contrast and range. Colourspace converter Since the output of the processor is to be YUV and not RGB, a fixed-coefficient 3x3 matrix converter is used. Chrominance sub-sampling & filtering Spatial sub-sampling and filtering is performed since the output sampling format must be reduced from 4:4:4 to 4:2:2 because most video systems do not require more chrominance data for video camera input. Output formatter Devices taking digital video input such as capture, graphics and compression chips usually require the YUV to be formatted either in 16 bit (YU then YV) mode or 8 bit (U then Y then V then Y) mode. The output mode is pin-strap selectable. An output enable input signal may be used when sharing a data bus with other video decoders. Other useful signals such as field and colour flags are also provided. Aperture corrector Since both the luminance and chrominance are derived from spatially spread pixels and the ideal output would be as though all the pixels were superimposed upon one another, a programmable vertical and horizontal aperture correction can be applied to either “soften” or “sharpen” the image. Scene-sensing luminance and chrominance metrics There are no hard-wired closed-loop control circuits in the processor. To achieve great flexibility in control over the behavior of the camera head and processor system, a userdefined region of interest is programmed which provides statistical information about the field of video only within that region. Peak luminance, total luminance, total red chrominance and total blue chrominance are provided and updated after each field. Serial bus control To provide read-write control over the registers within the processor, a standard I2C state-machine is provided. Its address may be offset by 3 bits to preclude address conflicts. 2 VP7610 PERFORMANCE PARAMETER CCD Resolution Field Rate Video Sample Rate Video Sample Quantization Control Signals Configuration Inputs Gamma Correction Output Format Output Colourspace Output Signals Power Consumption MAXIMUM VALUE OR SPECIFICATION Up to 768 pixels per line Up to 60 fields per second 30 MHz. max. input clock rate, 15MHz. max. output clock rate 8 bit samples in 2 nibbles of 4 bits each Standard I2C protocol I2C address offset, output enable Programmable via 16 arbitrary connected line segments CCIR601 compliant 4:2:2 digital video, pixels per line=CCD pixels YCrCb luminance & chrominance 16 bit digital video, H & V sync, 1X & 2X clock, field ID, chroma ID 950mW STATUS REGISTERS FUNCTION Gated Luminance Sum Gated Luminance Peak Gate Red Chrominance Sum Gated Blue Chrominance Sum SIZE 32 bits 8 bits 32 bits 32 bits DESCRIPTION Sum of luminance values within gated zone Value of peak luminance pixel(s) within gated zone Sum of red chrominance values within gated zone Sum of blue chrominance values within gated zone CONTROL REGISTERS FUNCTION Colour Calibration Matrix Gating Zone Start Pixel Gating Zone End Pixel Gamma Correction Horiz. Aperture Correction Vert. Aperture Correction Processor bypass CamPortTM select Test pattern generator SIZE 78 bit 16 bits 16 bits 128 bit 4 bits 4 bits 2 bits 1 bit 1 bits DESCRIPTION 9x9 bit signed coefficients converting CMYG to RGB 8 bits for column # and for row #, in 4 pixel increments 8 bits for column # and for row #, in 4 pixel increments Locus of 16 points of 8 bits each forms many curves 00H = 0%, 40H = +100%, 70H = +175%, F0H= -175% 00H = 0%, 40H = + 50%, 70H = + 87%, F0H= - 87% 0=normal, 1=pass raw 8 bit samples to Y output pins 0=port A, 1=port B 0=live video, 1=colourbars 3 VP7610 SIGNALS & PINOUT Pin # 60 54 55 56 59 88 84 85 86 87 91 I/O In* In* In* In* In* In* In* In* In* In* Out Name CPCLK CPD3 CPD2 CPD1 CPD0 CPCKB CPDB3 CPDB2 CPDB1 CPDB0 CPSEL Description Clock - This input receives the clock from the CamPort™ camera on port A. CamPort™ Data Bit 3 - This bus receives the data from the CamPort™ camera on port A. CamPort™ Data Bit 2 - Port A CamPort™ Data Bit 1 - Port A CamPort™ Data Bit 0 - Port A CamPort™ B Clock - This input receives the clock from the CamPort™ camera on port B. CamPort™ B Data Bit 3 - This bus receives the data from the CamPort™ camera on port B. CamPort™ B Data Bit 2 CamPort™ B Data Bit 1 CamPort™ B Data Bit 0 CamPort™ Select Status - When this output is low, the data from CamPort™ A is being used, when this output is high, the data from CamPort™ B is being used. This pin is controlled by Bit 3 of the Configuration Register (sub-address = 0x00). Reset Not - When this Schmidtt trigger input is low, the chip is placed into a known state. When this input is high, the chip can operate. Luminance Out bit 7 - When CCSEL is low this bus carries the luminance data. When CCSEL is high this bus carries multiplexed luminance and chrominance data Luminance Out bit 6 Luminance Out bit 5 Luminance Out bit 4 Luminance Out bit 3 Luminance Out bit 2 Luminance Out bit 1 Luminance Out bit 0 Chrominance Out bit 7 - When CCSEL is low this bus carries the chrominance data. When CCSEL is high this bus carries a constant value of 0x80 (128). Chrominance Out bit 6 Chrominance Out bit 5 Chrominance Out bit 4 Chrominance Out bit 3 Chrominance Out bit 2 Chrominance Out bit 1 Chrominance Out bit 0 Clock Out 2X - This clock runs at twice the pixel rate Clock Out 1X - This clock runs at the pixel rate. Output Enable - When this input is high, the signals YY[7..0], UV[7..0], HSYNC, VSYNC, CLK2, CLK1, HACT, VACT, FIELD and BFLAG are driven. When this input is low, these signals are high-impedance. 44 11 10 9 6 5 4 3 2 23 22 21 20 17 16 15 14 24 27 34 In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out In RSTN YY7 YY6 YY5 YY4 YY3 YY2 YY1 YY0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 CLK2 CLK1 OUTEN * CamPort inputs are TTL levels. All other inputs are CMOS. See Static Electrical Characteristics table. 4 VP7610 12 Out VSYNC Vertical Sync - This signal goes low for 3 horizontal lines to mark the beginning of each field. In Odd fields, it starts and ends when HSYNC and HACT are low. In Even fields, it starts and ends when HSYNC and HACT are high. Horizontal Sync - This signal goes low and returns high in the horizontal blanking interval, to mark the beginning of each line. Horizontal Active - This signal is high when there is valid video data on the luminance and chrominance busses. Data is valid only when this signal and VACT are high. Vertical Active - This signal is high when there is valid video data on the luminance and chrominance busses. Data is valid only when this signal and HACT are high. Field Flag - This signal indicates the field. When it is low, the field is odd. When it is high, the field is even. Blue Flag - This signal indicates when Blue chrominance data is on the chrominance bus. CCIR 656 Select - When this input is high, the YY[7..0] bus carries multiplexed luminance and chrominance data in conformance with CCIR 656. When this signal is low, the YY[7..0] bus carries only luminance data. Register Clock - This input clocks the control circuitry in the chip and must be running in order to access the registers via the I2C bus. The frequency on this input should be between 10 and 20 MHz. Inverter In - This CMOS Schmidt trigger input controls the INVO output. This inverter can be used to form an RC oscillator to drive the input RCLK. It is typically connected through a resistor to INVO and through a capacitor to GND. This oscillator has a period roughly equal to the time constant R*C. Inverter Out - This signal outputs the opposite level from that applied to INVI. If this inverter is used to form an RC oscillator, this pin would be connected to RCLK. Oscillator Crystal Input - The crystal oscillator is another way to produce a clock for the input RCLK. A crystal is connected between this input and OSXO. Oscillator Crystal Output - A crystal is connected between this output and OSXI. Oscillator Output - If the crystal oscillator is used to produce the register clock, this CMOS output drives the RCLK input. I2C Address Select Bit 3 - The IAD[3..1] inputs select the I2C address that the chip will respond to. The address is 0x60 + 8 * IAD3 + 4 * IAD2 + 2 * IAD1. I2C Address Select Bit 2 I2C Address Select Bit 1 Serial Data In - This input is connected to the I2C Data line. It may be connected through a filter to reduce noise susceptibility. Serial Data Out - This open-drain output connects directly to the I2C Data line. Serial Data Monitor - This output is low when the SDAO output is driving low. This output is high when the SDAO output is high impedance. Serial Clock In - This input is connected to the I2C Clock line. It may be connected through a filter to reduce noise susceptibility. Serial Clock Out Port A - This output drives the level on the SCLI input when the CamPort™ A is selected. When the CamPort™ B is selected this output is driven high. This is not an open-drain output. Serial Clock Out Port B - This output drives the level on the SCLI input when the CamPort™ B is selected. When the CamPort™ A is selected this output is driven high. This is not an open-drain output. Test Pin - This pin should be tied low. 13 28 29 30 31 35 Out Out Out Out Out In HSYNC HACT VACT FIELD BFLAG CCSEL 36 In RCLK 38 In INVI 37 42 41 39 45 43 40 48 47 48 49 89 Out In Out Out In In In In Out Out In Out INVO OSXI OSXO OSCO IAD3 IAD2 IAD1 SDAI SDAO SDMN SCLI SCLOA 90 Out SCLOB 52 In TST0 5 VP7610 53 61 62 63 71 In In In In In TST1 TST2 TST3 TST4 TSTOE TOUT Test Pin - This pin should be tied low. Test Pin - This pin should be tied low. Test Pin - This pin should be tied low. Test Pin - This pin should be tied low. Test Output Enable - This pin should be tied high. Test Outputs - These pins should be unconnected. 64, 65, 66, Out 67, 70, 72, 73, 74, 77, 78, 79, 80, 81, 92, 93, 94, 95, 96, 97, 98, 99 1, 7, 19, 25, 32, 51, 57, 69, 75, 82, 8, 18, 26, 33, 50, 58, 68, 76, 83, 100 In GND Power In VDD Power REGISTER DESCRIPTIONS The VP7610 iCamHost™ processor station address is strap-configurable to any even location between 0x60 and 0x6E inclusive. Since most iCam cameras currently built use the Station Address 0x68, it is recommended that the iCamHost™ be strapped to a different address. The register addresses shown below are the sub-addresses written to the iCamHost™ immediately after the Station Address. The 7 LSBs of the sub-address must match the specified address. The MSB of the sub-address controls the auto-increment feature of the iCamHost™. If the MSB of the sub-address is a ‘1’, (sub-addresses 0x80 through 0xFF), the sub-address register in the iCamHost™ is incremented to the next address immediately after the data register is read or written. If the MSB of the sub-address is a ‘0’, (sub-addresses 0x00 through 0x7F), the sub-address register in the iCamHost™ remains constant regardless of any reads or writes to the data register. Address 0x00 Configuration Control Register Read/Write 7 0 6 0 Bits 7 - 4 Bit 3 5 0 4 0 3 Cfg3 2 Cfg2 1 Cfg1 0 Cfg0 Always read as ‘0’ Cfg3 - Camera Input Port Enable ‘1’ CamPort™ ‘B’ is source ‘0’ CamPort™ ‘A’ is source Cfg2 - Colour Bar Enable ‘1’ Colour Bar Test Pattern Output ‘0’ Normal Video Output Cfg1 - RGB to YUV Converter Bypass ‘1’ Green + BnR Pattern Output ‘0’ Normal YUV Output Cfg0 - Separator Bypass ‘1’ Sum = CCD Data, Diff = 0 ‘0’ Normal Separator Output Bit 2 Bit 1 Bit 0 6 VP7610 Address 0x01 RESERVED Address 0x02 Peak Luma Filter Control Register Read/Write 7 0 6 0 Bits 7 - 3 Bits 2 - 0 5 0 4 0 3 0 2 PLF2 1 PLF1 0 PLF0 Always read as ‘0’ Peak Luma Filter Control ‘000’ - PLF K = 1, No Luma Filter ‘001’ - PLF K = 1/2, Fast Luma Filter ‘010’ - PLF K = 1/4, Med Fast Luma Filter ‘011’ - PLF K = 1/8, Med Slow Luma Filter ‘1XX’ - PLF K = 1/16, Slow Luma Filter Address 0x01 RESERVED Address 0x04 Horizontal Start Register Read/Write 7 HStrt7 6 HStrt6 5 HStrt5 4 HStrt4 3 2 1 0 HStrt3 HStrt2 HStrt1 HStrt0 Bits 7 - 0 Horizontal Start Register Four times the value of this register is the Horizontal starting pixel for the Metrics window. Address 0x05 Horizontal Stop Register Read/Write 7 6 5 4 3 2 1 0 HStop7 HStop6 HStop5 HStop4 HStop3 HStop2 HStop1 HStop0 Bits 7 - 0 Horizontal Stop Register Four times the value of this register is the Horizontal ending pixel for the Metrics window. Read/Write Address 0x06 Vertical Start Register 7 VStrt7 6 VStrt6 5 VStrt5 4 VStrt4 3 VStrt3 2 VStrt2 1 VStrt1 0 VStrt0 Bits 7 - 0 Vertical Start Register Four times the value of this register is the Vertical starting line (in the frame) for the Metrics window (two times in the field). Read/Write Address 0x07 Vertical Stop Register 7 6 5 4 3 2 1 0 VStop7 VStop6 VStop5 VStop4 VStop3 VStop2 VStop1 VStop0 Bits 7 - 0 Vertical Stop Register Four times the value of this register is the Vertical ending line (in the frame) for the Metrics window (two times in the field). 7 VP7610 Address 0x08 Horizontal Aperture Control Register Read/Write 7 HApt7 6 HApt6 5 HApt5 4 HApt4 3 0 2 0 1 0 0 0 Bits 7 Horizontal Aperture Sign Bit ‘1’ Correction is negative (blurring) ‘0’ Correction is positive (sharpening) Horizontal Aperture Control Value ‘000’ - No Aperture Correction | ‘111’ - Maximum Aperture Correction Always read as ‘0’ Read/Write Bits 6 - 4 Bits 3 - 0 Address 0x09 Vertical Aperture Control Register 7 VApt7 6 VApt6 5 VApt5 4 VApt4 3 0 2 0 1 0 0 0 Bits 7 Vertical Aperture Sign Bit ‘1’ Correction is negative (blurring) ‘0’ Correction is positive (sharpening) Vertical Aperture Control Value ‘000’ - No Aperture Correction ‘111’ - Maximum Aperture Correction Always read as ‘0’ Read Only Bits 6 - 4 Bits 3 - 0 Address 0x0E Hardware Version Register 7 HVer7 6 HVer6 5 HVer5 4 HVer4 3 HVer3 2 HVer2 1 HVer1 0 HVer0 Bits 7 - 0 Hardware Version Register 0x01 - Zeus II Board Rev 0.1 0x10 - CHP-7600 Rev 1.0 0x11 - CHP-7610 Rev 1.1 Read Only Address 0x0F Timing Status Register 7 FCnt5 6 FCnt4 5 FCnt3 4 FCnt2 3 FCnt1 2 FCnt0 1 Fld 0 VBlk Bits 7 - 2 Field Count A number between 0 and 63 which increments at the beginning of every Vertical Blanking Interval Field Bit ‘1’ Even Field - Digital Field 2 ‘0’ Odd Field - Digital Field 1 Vertical Blanking ‘1’ Vertical Blanking Interval ‘0’ Vertical Active Interval Bit 1 Bit 0 8 VP7610 Address 0x10 Lower Byte Red Chroma Register Read Only This register contains Bits 07 - 00 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x11 Lower Middle Byte Red Chroma Register Read Only This register contains Bits 15 - 08 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x12 Upper Middle Byte Red Chroma Register Read Only This register contains Bits 23 - 16 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x13 Upper Byte Red Chroma Register Read Only This register contains Bits 31 - 24 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x14 Lower Byte Blue Chroma Register Read Only This register contains Bits 07 - 00 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x15 Lower Middle Byte Blue Chroma Register Read Only This register contains Bits 15 - 08 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x16 Upper Middle Byte Blue Chroma Register Read Only This register contains Bits 23 - 16 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x17 Upper Byte Blue Chroma Register Read Only This register contains Bits 31 - 24 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x18 Lower Byte Luminance Register This register contains Bits 07 - 00 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x19 Lower Middle Byte Luminance Register This register contains Bits 15 - 08 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1A Upper Middle Byte Luminance Register This register contains Bits 23 - 16 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1B Upper Byte Luminance Register This register contains Bits 31 - 24 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1C Peak Luminance Register This register contains the peak value of the filtered Luminance of the pixels within the Metrics window. Read Only Read Only Read Only Read Only Read Only Address 0x20 Sum to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the Sum signal. Address 0x21 AmB to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the AmB signal. Address 0x22 CmD to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the CmD signal. 9 VP7610 Address 0x23 Red Coefficients Sign Register Read/Write 7 0 Bit 1 Bit 0 6 0 5 0 4 0 3 0 2 0 1 0 RCmD RAmB Sign for CmD to Red Coefficient Sign for AmB to Red Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive Address 0x24 Sum to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the Sum signal. Address 0x25 AmB to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the AmB signal. Address 0x26 CmD to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the CmD signal. Address 0x27 Green Coefficients Sign Register Read/Write 7 0 Bit 1 Bit 0 6 0 5 0 4 0 3 0 2 0 1 0 GCmD GAmB Sign for CmD to Green Coefficient Sign for AmB to Green Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive Address 0x28 Sum to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the Sum signal. Address 0x29 AmB to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the AmB signal. Address 0x2A CmD to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the CmD signal. Address 0x2B Blue Coefficients Sign Register Read/Write 7 0 Bit 1 Bit 0 6 0 5 0 4 0 3 0 2 0 1 0 BCmD BAmB Sign for CmD to Blue Coefficient Sign for AmB to Blue Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive Addresses 0x30 - 0x3F Gamma Values Write Register Write The 16 values that are written to these 16 registers determine the breakpoints in the Gamma correction circuit. The breakpoint values should be written in ascending order starting at address 0x30. Addresses 0x30 - 0x3F Gamma Values Read Register Read The breakpoints in the Gamma correction circuit are read from these registers. 10 VP7610 TIMING REQUIREMENTS Name fCPX tCPX dcCPX tsuCPDX frequency CPCKA or CPCKB period CPCKA or CPCKB duty cycle CPCKA or CPCKB setup time, CPDA [3..0] to CPCKA or CPDB [3..0] to CPCKB thCPDX hold time, CPDA [3..0] to CPCKA or CPDB [3..0] to CPCKB fRCK twRSTN frequency RCLK pulse width of RSTN 4 10 100 40 ns MHz ns 8 ns Description 0 33 40 Value Min. Max. 30 60 MHz ns % Unit TIMING CHARACTERISTICS Name tcqRCLK tcpCPX tcqCK2f tcqCK2r tcpCK1f tcqCK1r tpdCK2 tpdINV tpdSCL Description Min. RCLK to output (CPSEL, SDAO, SDMN) rising edge of CPCKA or CPCKB to output (YY[7..0], UV[7..0], CLK1, VSYNC, HSYNC,VACT, HACT, BFLAG) falling edge of CLK2 to output (YY[7..0], UV[7..0], CLK1, VSYNC, HSYNC, VACT, HACT, BFLAG) rising edge of CLK2 to output (YY[7..0], UV[7..0], CLK1,VSYNC, HSYNC, VACT, HACT, BFLAG) falling edge of CLK1 to output (YY[7..0], UV[7..0],VSYNC, HSYNC, VACT, HACT, BFLAG) rising edge of CLK1 to output (YY[7..0], UV[7..0], VSYNC, HSYNC, VACT, HACT, BFLAG) propagation delay from CPCKA or CPCKB to CK2 propagation delay from INVI to INVO propagation delay from SCLI to SCLOA or SCLOB tCPX-3 tCPX+3 10 10 10 ns ns ns ns -3 3 ns (0.4*tCPX)-2 (0.6*tCPX)+5 ns -2 5 ns 20 ns Value Max. 20 Unit ns 11 VP7610 ABSOLUTE MAXIMUM RATINGS [See Notes] Supply voltage VDD -0.5V to 7.0V Input voltage VIN -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V Output voltage VOUT Clamp diode current per pin IK (see note 2) 18mA Static discharge voltage (HBM) 500V -55° C to 150°C Storage temperature TS Ambient temperature with power applied TAMB 0° C to 70°C Junction temperature 125°C Package power dissipation 1000mW NOTES ON MAXIMUM RATINGS 1. Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. 2. Maximum dissipation for 1 second should not be exceeded, only one output to be tested at any one time. 3. Exposure to absolute maximum ratings for extended periods may affect device reliablity. 4. Current is defined as negative into the device. STATIC ELECTRICAL CHARACTERISTICS Operating Conditions (unless otherwise stated) Tamb = 0°C to +70° C VDD = 5.0v ± 5% Value Characteristic Symbol Min. Output high voltage Output low voltage Input high voltage (CMOS input) Input low voltage (CMOS input) Input high voltage (TTL input) Input low voltage (TTL input) Input leakage current Input capacitance Output leakage current Output S/C current VOH VOL VIHC VILC VIHT VILT IIN CIN IOZ ISC 0.8VDD 0.7VDD 2.0 0.8 -1 10 -1 10 +1 300 Typ. Max. 0.4 0.2VDD +1 V V V V V V µA pF µA mA IOH = 4mA IOL = -4mA Units Conditions GND < VIN < VDD GND < VOUT < VDD VDD = Max ORDERING INFORMATION VP7610 CG FPIR (Note: Prior to full release to production device may be designated as VP7610 PR FPIR) 12 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE