WL600KG

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ WL600C 2.4 - 2.5GHz RF and IF Circuit Preliminary Information DS4581 ISSUE 2.1 August 1997 The WL600C is a 2.4-2.5GHz RF transmitter and receiver chip for use in digital radio, and operates from a supply voltage of 2.7 - 3.6V. It is designed to work with the Zarlink Semiconductor WL800 frequency synthesiser and the WL102 WLAN controller chip which together make up the DE6038 frequency hopping Wireless Local Area Network (WLAN) transceiver. The receiver circuit contains a low noise amplifier, image rejecting mixer, IF limiting strip with RSSI and a quadrature demodulator. There is also a power amplifier driver stage and ramp control facility for use in transmit. Ordering Information WL600C/KG/GP1R PIN 1 Features • • • • • • • Part of DE6038 chipset (WL800, WL102) High level of integration Low noise figure Low power consumption High data rates with comparator for 2 level FSK Minimal external components 48 lead LQFP package PIN 1 IDENT PIN 48 Absolute Maximum Ratings Supply voltage Vcc Transmit/Receive and standby input Current consumption Junction temperature Tj ESD protection 4V -0.5 to Vcc +0.5V TBD 150° 2KV Pin Description QUAD+ QUADGND_IF DEMOD_OUT+ DEMOD_OUTRSSI CLAMP_SET CCA_THRESHOLD VCC_IFSTRIP DECOUPLE_LOGDECOUPLE_LOG+ IF_IN+ IF_INCCAB GND_IF BUFFER_IN+ BUFFER_INVCC_DATA RXD RXDB GND_RF IF_OUTIF_OUT+ GND_PADDLE Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Description VCC_RF GND_RF VCC_LNA GND_RF RF_IN LNA_DEGEN LNA_DEGEN DRIVE VCC_PA GND_RF RAMP_CAP PA_ON STDBYB TX/RXB GND_LO LO_IN VCC_LO DATA_IN+ DATA_INBUFFER_OUTBUFFER_OUT+ CLAMPCLAMP+ GND_PADDLE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LQFP48 Figure 1 - Pin connections - top view Related Documents Datasheets WL800/102 DE6038 WL600C Preliminary Information 22 IMAGE REJECT MIXER PHASE SHIFT 23 46 47 7 42 43 DATA SLICE 19 20 29 LNA PHASE SHIFT ACTIVE CLAMP CIRCUIT BUFFER AMP X2 16 44 45 17 10 11 1 IMAGE REJECT MIXER PA DRIVE BUFFER 32 PHASE SHIFT IF STRIP 2 4 5 LO BUFFER DETECTORS COMPARATOR 14 35 40 12 13 6 8 Figure 2 - WL600C block diagram DEVICE PIN OUT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ref QUAD+ QUAD GND_IF DEMOD_OUT + DEMOD_OUT RSSI CLAMP_SET CCA_THRESHOLD VCC_IFSTRIP DECOUPLE_LOG DECOUPLE_LOG + IF_IN + IF_IN CCAB GND_IF BUFFER_IN + BUFFER_IN VCC_DATA RXD Type I/O I/O GND OUT OUT OUT IN IN VCC I/O I/O IN IN OUT GND IN IN VCC OUT Description Quadrature demodulator tank circuit connection Quadrature demodulator tank circuit connection Ground for IF strip circuitry Demodulator output Demodulator output RSSI detector analogue output Sets clamp knee voltage Sets level at which CCA comparator will switch Power supply for log amp, demod, and internal references Decoupling for log amp feedback network, AC couple Decoupling for log amp feedback network, AC couple Log amp input, AC couple Log amp input, AC couple CCA comparator output: signal = logic high, clear = logic low Ground for IF strip circuitry x 2 buffer input x 2 buffer input Power supply for clamp, data comparator and buffer amp Data comparator output 2 Preliminary Information Pin 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Ref RXDB GND_RF IF_OUTIF_OUT+ GND_PADDLE VCC_RF GND_RF VCC_LNA GND_RF RF_IN LNA_DEGEN LNA_DEGEN DRIVE VCC_PA GND_RF RAMP_CAP PA_ON STDBYB TX/RXB GND_LO LO_IN VCC_LO DATA_IN+ DATA_INBUFFER_OUTBUFFER_OUT+ CLAMP CLAMP + GND_PADDLE Type OUT GND OUT OUT GND VCC GND VCC GND IN I/O I/O OUT VCC GND I/O IN IN IN GND IN VCC IN IN OUT OUT I/O I/O GND Description Data comparator output WL600C Ground for LNA, mixer, IF summation, and PA driver circuits Downconverter output, requires external load and RFC Downconverter output, requires external load and RFC Ground for substrate and package paddle Power supply for mixer, summation, and PA ramp circuits Ground for LNA, mixer, IF summation, and PA driver circuits Power supply for LNA Ground for LNA, mixer, IF summation, and PA driver circuits LNA input, AC couple LNA degeneration, connect to ground LNA degeneration, connect to ground Power amplifier driver output, requires external load and RFC Power supply for power amplifier driver Ground for LNA, mixer, IF summation, and PA driver circuits PA ramp circuit timing capacitor connection PA ramp circuit control input: PA on = logic high, PA off = logic low Power down control input: active= logic high, standby = logic low Transmit/Receive control input: transmit = logic high, receive = logic low Ground for LO buffer, phaseshifter, and standby circuitry Local oscillator input, AC couple Power supply for LO buffer, phaseshifter, and standby circuitry Data comparator input Data comparator input x2 buffer output x2 buffer output Data clamp, knee voltage set by pin 7, AC couple Data clamp, knee voltage set by pin 7, AC couple Ground for substrate and package paddle 3 WL600C Preliminary Information Electrical Characteristics These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20°C to + 85° C VCC = 2.7V to 3.6V, Characteristic Min Supply current (transmit) Supply current (Receive) Supply current in standby PA DRIVER & RAMP CIRCUIT Logic low voltage Logic high voltage Logic Input current Ramp capacitor charge Current Ramp capacitor voltage swing Output power Output band Max to Min power out ratio RECEIVER LOW NOISE AMPLIFIER & MIXERS Conversion gain 3rd order intercept point 1dB input gain compression Noise figure Input impedance 2.4GHz 2.45GHz 2.5GHz Image frequency rejection Local oscillator input level Local oscillator input impedance IF output impedance 25 19 -10 -22 -2 2.4 20 0 Vcc-0.7 Value Typ 50 60 0.3 Max Unit mA mA mA Condition 0.8 Vcc 10 250 1 2 2.5 V V µA µA V dBm GHz dB Ramp down Ramp up 22 dB dBm dBm Differential into 600Ohms 7 13+j20 15+j30 20+j50 10 dB Ohms Matched to 50Ohms dB -16 15-j40 600 dBm Ohms Ohms With external 900Ω resistor TRANSMIT/RECEIVE INPUT Logic low voltage Logic high voltage Input current 0 Vcc-0.7 0.8 Vcc 10 V V µA Receive mode Transmit mode 4 Preliminary Information Electrical Characteristics (cont) These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20°C to + 85°C VCC = 2.7V to 3.6V, Characteristic Min LIMITING STRIP Maximum input frequency Noise figure Input resistance Capacitance Limiting strip gain Limiting point RSSI Rise time Non linearity Maximum output voltage Output voltage @ -70dBm input Output impedance CLEAR CHANNEL ASSESSMENT COMPARATOR Logic high voltage Logic low voltage Threshold input limits Input current DEMODULATOR Detect output voltage Detected signal bandwidth Output pull down current Output DC common mode CLAMP CIRCUIT Knee voltage range Clamp set range DC bias at inputs Slope resistance OUTPUT COMPARATOR Input offset voltage Input current Output rise/fall time Output voltage swing Input common mode range Output common mode 1 Vcc-0.85 11 15 400 Vcc-0.7 5 1 20 mV µA ns mV V V 0.1 1 Vcc-1 100 0.350 2 V V V Ohms 0.4 3 350 Vcc-1.5 Vp-p MHz µA V 1 2.2 0.5 2 1 V V V µA 1.9 1.3 6 100 ±3 ns dB V V kOhms Input = 0dBm 70 -78 -75 3.5 1200 0.5 50 6 MHz dB Ohms pF dB dBm Value Typ Max Unit Condition WL600C Set by external 1k8 resistor Differential. 150kHz deviation Quad circuit (2.2µH/40kΩ) Dependent on Quad circuit Inversely proportional to knee voltage For load capacitiance 0-10pF pk-pk differential 5 WL600C Preliminary Information Electrical Characteristics (cont) These characteristics are guaranteed over the following conditions (unless otherwise stated): TAMB = -20°C to + 85° C VCC = 2.7V to 3.6V, Characteristic Min BUFFER AMP Buffer amplifier gain Input common mode range Output common mode Max difference between inputs Output pull down current STANDBY INPUT Logic low voltage Logic high voltage Input current Standby to receive time 0 Vcc-0.7 100 0.8 Vcc V V µA µs 350 1.2 Vcc-1.5 450 2 Vcc-0.5 V V mV µA Chip must be in receive mode when switching to/from standby Circuit powered down Circuit powered up Amp will limit outside this range Value Typ Max Unit Condition Functional Description Receive The RF input stage of the WL600C receiver is a 2.5GHz low noise amplifier (LNA). The output of the single ended LNA is split and fed into the inputs of two mixers which form an image rejecting down converter. An external oscillator (2.357 → 2.457GHz)is fed through an RC phase shift network to provide the required quadrature local oscillator signal. The mixer outputs are fed through further phase shift networks and are combined to form a differential 43MHz IF signal which is used to drive the 43MHz SAW filter. The output of the SAW filter is fed into a differential limiting strip which provides the IF gain. The strip has a series of detectors whose output provides an analog voltage indicating receive signal strength (RSSI). Alternatively, for basic applications a comparator connected to the RSSI detectors can be used. When the RSSI signal is greater than a value set by the CCA_THRESHOLD input the clear channel assessment (CCAB) output goes high. A conventional quadrature demodulator (with external tuned circuit to supply the quadrature drive) provides the analogue data stream which is then AC coupled to a data slice comparator. A clamp circuit is connected between the comparator inputs to provide DC restoration of the AC coupled signal. The comparator output then goes to the data and clock recovery circuits on a CMOS integrated circuit (such as the WL102). Transmit The local oscillator signal is also used in transmit at a higher frequency (2.4 →2.5GHz) and is buffered and amplified on the WL600C. This provides the drive to the transmit power amplifier (also off chip). A ramp circuit is included to control the drive level to the power amplifier in a controlled manner. This is done at the start and end of a transmit sequence and should be used to prevent the generation of spectral “splash”. A single external capacitor controls the rate of increase and decrease of the power drive level. 6 Preliminary Information Control Waveforms WL600C TX/RXB PA_ON Ramp_Cap PA_Drive RF output Figure 3 - Transmit control waveforms Control Logic Control Line TX/RXB PA_ON STDBYB Logic ‘0’ Receive PA off Standby Logic ‘1’ Transmit PA on Active 7 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE