TRAC020LH

TOTALLY RE-CONFIGURABLE ANALOG CIRCUIT - TRAC® Issue 2 - MARCH 1999 DEVICE DESCRIPTION The TRAC020LH is a Micro-Power version of the existing TRAC products. It also offers significant improvements in bandwidth and function accuracy. The TRAC020LH is the latest addition to the TRAC family of Field Programmable Analog Devices (FPAD) which offers an integrated path from signal processing problems to working silicon solutions - in minutes! The Totally Reconfigurable Analog Circuit is a highly flexible single chip solution to the signal processing problems found in many markets. Introducing a Top-Down, Structured design discipline, TRAC enables rapid implementation, prototyping and product release. Rather than working at the component level, TRAC champions the Computational Approach, providing designers with benefits formerly associated with programmable digital devices. TRAC brings a truly integrated Signal Processing problem solving process and offers a path to Custom Silicon for high volume applications. TRAC020LH • • • • • • • • • • • • • • • • • • Log, Linear and Modern Filter Design Instrumentation Transducer Characteristic Correction Vector Analysis FEATURES AND BENEFITS Faster design and verification of signal processing solutions Instant working silicon Flexibility to react to changing requirements Stay thinking about analog problems mathematically - minimal circuit design Just as versatile as FPGA - and just as easy Complete more projects on time High level of integration and design secrecy Integration with other CAE systems Transparent design migration to semi-custom and future devices Less than 8 bytes to program Full industrial temperature range Standby mode for improved battery life Devices easily cascaded for more complex designs Combines silicon, software and support APPLICATIONS Many analog signal processing applications including:- • • • • • • • Analog Computation Analog Signal Processing (ASP) Classical & Modern Control Systems Audio Applications Sonar and Ultrasonic Systems Analog Correlation Echo Cancellation ORDERING INFORMATION PART NUMBER TRAC020LHQ36 PACKAGE QSOP36 PART MARK TRAC020LH For more information on Fast Analog Solutions and all our products see www.fas.co.uk 1 TRAC020LH ABSOLUTE MAXIMUM RATINGS Voltage on any pin = 7.0V (relative to VSS) Operating Temperature = -40 to 85°C Storage Temperature = -55 to 125°C GENERAL ELECTRICAL CHARACTERISTICS Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = -2.0V±0.10V PARAMETER General Characteristics Dynamic Range Noise Voltage Total Harmonic Distortion Intermodulation Distortion Supply Rejection Cell to cell crosstalk Input Range (all IO pins) Slew Rate Supply Current Operating Current IDD Operating Current ISS Shutdown Current IDD Cell Output Capability Sink Current Source Current 150µA 150µA PD=VSS Cells to NIP function PD=VDD 2.5mA -2.5mA 5.0mA -5.0mA 6.0mA -6.0mA 10µA 10Hz-100kHz 100mV peak-peak 1.0V peak-peak 80dB CONDITIONS MIN TYPICAL MAX 15nV/√  Hz 0.02% 0.08% < 0.1% 60dB -60dB VDD -2.0V, VSS +1.0V 4V/µS 2 TRAC020LH ELECTRICAL CHARACTERISTICS OF THE CELL Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V FUNCTION Non Inverting Pass Gain Input Resistance Offset Input Current Bandwidth (small signal) Bandwidth (large signal) Negate Gain Input Resistance Offset Bandwidth(small signal) Bandwidth(large signal) Add Gain Input Resistance Offset Bandwidth (small signal) Bandwidth (large signal) Log Output Voltage Vin=0mV 20mV peak-peak 500mV peak-peak Vin =±1.000V ±625 mV Vin=0mV 20mV peak-peak 500mV peak-peak VA=VB =±400mV -1.012 30kΩ -3.4mV 20mV peak-peak 500mV peak-peak Vin = ±800mV -1.010 30kΩ -2.4mV Vin=0mV -1.2mV PARAMETER CONDITIONS Vin = ±800mV MIN 0.996 TYPICAL 1.000 60MΩ 0mV 100nA 12MHz 3MHz -1.000 40kΩ 0mV 7MHz 3MHz -1.000 40kΩ 0mV 6MHz 3MHz ±685 mV ±60mV MAX 1.004 1.2mV 260nA -0.990 50kΩ 2.4mV -0.988 50kΩ 3.4mV ±745 mV Transfer Characteristic Vin =±10mV, (Change in output for a 10x ±100mV,±1000mV change in input voltage) Input Resistance Auxiliary Gain Input Current Offset RF = RS =20kΩ, RF = RS =20kΩ, Vin = 0 mV RF = RS =20kΩ, Vin = 0mV VDD-1.7V 700 3 TRAC020LH ELECTRICAL CHARACTERISTICS OF THE CELL (Continued) Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V FUNCTION Alog PARAMETER Output Voltage Transfer Characteristic (Multiplication of the output voltage for fixed steps in input voltage) CONDITIONS Vin = ±685mV Vin =±565mV, ±625mV, ±685mV steps Vin = −685mV Vin = 685mV Vin =−565mV, −625mV, −685mV steps Vin =±1.0V Vin= ±1.0V 20mV peak-peak 500mV peak-peak Vin= ±1.0V 20mV peak-peak 500mV peak-peak MIN ± 0.80V TYPICAL ±1.00V ±10 MAX ±1.2V Rectify Output Voltage Transfer Characteristic (Multiplication of the output voltage for fixed steps in input voltage) +0.80V -5.0mV +1.00V +1.2V 5.0mV +10 Off LOG/ALOG Attenuation Gain Bandwidth (small signal) Bandwidth (large signal) -60dB -80dB 1.00 6MHz 2MHz 1.00 6MHz 2MHz LOG/REC Gain Bandwidth (small signal) Bandwidth (large signal) ELECTRICAL CHARACTERISTICS OF THE LOGIC FUNCTIONS(VDD-VSS=5.0V±0.25V) FUNCTION (VOH (for output pins DOUT, CLCR ) VOL (for outputs DOUT, CLCR IIH (for inputs DATA CLOCK, RESET,PD ) IIL (for inputs DATA CLOCK, RESET,PD ) Max. CLOCK frequency CONDITIONS IOH=-4mA IOH=4mA VIH=5V (WRT VSS) VIL=0V (WRT VSS) MIN 4.0V (WRT VSS) 0.0V (WRT VSS) TYPICAL MAX 5.0V (WRT VSS) 0.4V (WRT VSS) 1.0µA -1.0µA 10MHz 4 TRAC020LH DESCRIPTION OF PIN FUNCTIONS DATA Serial programming data is input to the TRAC via this pin. Each TRAC cell contains a 3-bit shift register that allows each cell to be programmed to the required analog function. Active low - The pin resets all on-chip shift registers to the logic zero state, which sets all TRAC cells to the OFF function. The pin should be held high while the device is being programmed and when the analog functions are in use. Active low - The pin switches off the bias generators to the analog cells, which turns off the supply current to all the TRAC cells. This does not influence the programming of the cells so this feature can be used to reduce power consumption for applications that have a standby mode. The pin should be held high while the device is being programmed and when the analog functions are in use. This pin is permanently held high (VDD) on the TRAC development board. Used to clock in the serial data to program the TRAC device. The on-chip shift registers are positive edge triggered. This pin is the serial data output from cell 20 on the TRAC device. This is used for validation of programming of the TRAC device. This pin also allows two or more TRAC devices to be connected in a serial architecture. This is done by connecting the DOUT pin of the first TRAC device to the DATA pin of the second TRAC device, and connecting the CLOCK pins. Clock Clear. When the TRAC device is used in stand alone applications CLCR is used as a control pin. It allows the downloading circuitry to be switched off when the programming serial data from the EEPROM is complete. These are the analog inputs / outputs for cells 1 to 20. These are the analog inputs for cells 1 and 2. TRAC positive supply rail (+3V) Analog Ground TRAC negative supply rail (-2V) - this will also be the system ground RESET PD CLOCK DOUT CLCR IO3..IO22 IO1,IO2 VDD AGND VSS 5 TRAC020LH CELL FUNCTION DETAILS ADD (code 011) Can be represented as an operational amplifier with three resistors of equal value R. The virtual earth at the inverting input gives:Eo = -R(Ea/R + Eb/R) = - (Ea + Eb) The output is the inverted sum of the input voltages. NEGATE (code 010) The negate function is provided by an adder, but with only one input, therefore Eo=-Eb NON INVERTING PASS (code 100) Used for topological reasons. It provides a route through the cell with no modification. i.e. a unity gain amplifier LOG (code 110) Can be represented as an operational amplifier with a pair of back to back diodes in the negative feedback loop and an input resistor R. The virtual earth at the inverting input gives:Eo = -kT/q log (Ea/RIo + 1) where k = Boltzmann’s constant T = absolute temperature q = electron charge Io=saturation current ANTI - LOG (code 101) Similar to the log circuit except that the diodes and resistors are reversed. The output voltage is therfore given as :Eo = -RIo (exp qEa/KT - 1) When the signal is processed through both log and anti-log the magnitude of the saturation current and absolute temperature cancel. 6 TRAC020LH CELL FUNCTION DETAILS (Continued) RECTIFIER (code 111) Similar to the anti-log function except that one of the diodes is removed so that a positive input gives zero output. AUX (code 001) As for an operational amplifier external components are used to provide the following functions - external components are shown dotted Amplification Attenuation Differentiation Integration OFF (code 000) In the off condition there is no signal path through the cell. 7 TRAC020LH SCHEMATIC DIAGRAM TRAC020LH TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell Frequency Responses, Small Signal Amplitude 20mV Pk-Pk Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 3 0 -3 12 6 0 -6 -12 -18 -24 10 100 1000 10000 100000 10 100 1000 10000 100000 Gain (dB) -6 -9 -12 -15 Frequency (kHz) Gain (dB) Frequency (kHz) NIP Small Signal Bandwidth NEG Small Signal Bandwidth 12 12 6 0 -6 -12 -18 -24 10 100 1000 10000 100000 10 100 1000 10000 100000 6 Gain (dB) 0 -6 -12 -18 Frequency (kHz) Gain (dB) Frequency (kHz) ADD Small Signal Bandwidth (for both A and B inputs) 12 12 AUX Small Signal Bandwidth (RS=RF=20K, RS Shunts preceeding OFF cell) 6 6 Gain (dB) 0 Gain (dB) 0 -6 -6 -12 -12 -18 10 100 1000 10000 100000 -18 10 100 1000 10000 100000 Frequency (kHz) Frequency (kHz) LOG/ALOG Small Signal Bandwidth (26mV DC Biased) LOG/REC Small Signal Bandwidth (26mV DC Biased) 10 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell Phase Delay, Small Signal Amplitude 20mV Pk-Pk Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 45 225 Phase (Degrees) Phase (Degrees) 10 100 1000 10000 100000 0 180 -45 135 -90 90 -135 45 -180 0 10 100 1000 10000 100000 Frequency (kHz) Frequency (kHz) NIP Phase Shift V Frequency 225 NEG Phase Shift V Frequency 225 Phase (Degrees) Phase (Degrees) 10 100 1000 10000 100000 180 180 135 135 90 90 45 45 0 0 10 100 1000 10000 100000 Frequency (kHz) Frequency (kHz) ADD Phase Shift V Frequency (For both A and B inputs) 45 0 -45 -90 -135 -180 -225 -270 10 100 1000 10000 45 0 AUX Phase Shift V Frequency (RS=RF=20K, RS Shunts preceeding OFF Cell) Phase (Degrees) Phase (Degrees) -45 -90 -135 -180 -225 -270 10 100 1000 10000 Frequency (kHz) Frequency (kHz) LOG/ALOG Phase Shift V Frequency (26mV DC Biased) LOG/REC Phase Shift V Frequency (26mV DC Biased) 11 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell Offset Voltage against Temperature CharacteristicsTest Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 0.2 0.4 0 Offset Voltage (mV) -20 0 20 40 60 80 100 Offset Voltage (mV) 0.2 0 -0.2 -0.4 -0.6 -0.8 -40 -0.2 -0.4 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) NIP Offset Voltage V Temp. 0.2 NEG Offset Voltage V Temp. 0.1 Offset Voltage (mV) 0 Offset Voltage (mV) -20 0 20 40 60 80 100 0 -0.2 -0.1 -0.4 -0.2 -0.6 -40 -0.3 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) ADD Offset Voltage Vs Temp. 0.2 AUX Offset Voltage V Temp. 0.4 Offset Voltage (mV) 0.1 Offset Voltage (mV) -20 0 20 40 60 80 100 0.2 0 0 -0.1 -0.2 -0.2 -40 -0.4 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) LOG/ALOG Offset Voltage V Temp. LOG/REC Offset Voltage V Temp. 12 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell Voltage Gain against Temperature Characteristics Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 0.1 -0.1 0.09 Gain Error (%) 0.08 Gain Error (%) -20 0 20 40 60 80 100 -0.15 -0.2 0.07 0.06 -0.25 0.05 -40 -0.3 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (° C) NIP Gain Error V Temp. 0.1 1000 NEG Gain Error V Temp. Differential Gain -20 0 20 40 60 80 100 0.05 Gain Error (%) 900 0 800 -0.05 700 -0.1 -0.15 -40 600 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) ADD Gain Error V Temp. 3 2.5 2 AUX Open Loop Gain V Temp. 1.6 Gain Error (%) 2 1.5 1 0.5 0 -40 Gain Error (%) -20 0 20 40 60 80 100 1.2 0.8 0.4 0 -40 -20 0 20 40 60 80 100 Temperature (°C) Temperature (°C) LOG/ALOG Gain Error V Temp. LOG/REC Gain Error V Temp. 13 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Cell DC Transfer Characteristics Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 1000 750 500 1000 750 500 Vout (mV) 250 0 -250 -500 -750 -1000 -1000 Vout (mV) 0 250 0 -250 -500 -750 -1000 -1000 -500 500 1000 -500 0 500 1000 Vin (mV) Vin (mV) NIP DC Transfer Characteristics 800 600 400 NEG DC Transfer Characteristics 800 600 400 Vout (mV) 200 0 -200 -400 -600 -800 -400 Vout (mV) 0 200 0 -200 -400 -600 -800 -1000 -200 200 400 -100 -10 0 10 100 1000 Va = Vb (mV) Log Vin (mV) ADD DC Transfer Characteristics LOG DC Transfer Characteristics ≈ ≈ 1000 750 500 1000 750 500 Vout (mV) 250 0 -250 -500 -750 Vout (mV) 250 0 -250 -500 -750 ≈ ≈ -1000 -680 -620 -560 -500 500 560 620 680 -1000 -680 -620 -560 -500 500 560 620 680 Vin (mV) Vin (mV) ALOG DC Transfer Characteristics REC DC Transfer Characteristics 14 TRAC020LH TYPICAL ELECTRICAL CHARACTERISTICS Settling Performance for Power Down and Data Clocking Test Conditions: Temperature = 25 °C, VDD = 3.0V±0.15V, VSS = - 2.0V±0.10V 1.4 1.2 0.4 0.2 Output Voltage (v) Output Voltage (v) Input = +800mV PD = VDD PD = VSS 1.0 0.8 0.6 0.4 0.2 PD = VSS PD = VDD 0.0 -0.2 Input = -800mV -0.4 -0.6 -0.8 -1.0 0.0 0 100 200 300 400 500 600 0 50 100 150 200 250 Time (µS) Time (µS) NIP Power Down Response 1.2 0.8 0.4 0.0 -0.4 -0.8 -1.2 -0.5 NIP Power Down Response 0.4 Output Voltage (v) Output Voltage (v) 0 Vin = -800mV Switched to NIP @ t = 0 µS Vin = 800mV Switched to NIP @ t = 0uS -0.4 -0.8 -1.2 0 0.5 1.0 1.5 -1.6 -0.5 0 0.5 1.0 1.5 Time (µS) Time (µS) OFF Cell to NIP Cell Response 1.2 0.8 0.4 0.0 -0.4 -0.8 -1.2 -0.5 OFF Cell to NIP Cell Response 1.2 0.8 0.4 0.0 -0.4 -0.8 -1.2 -0.5 Output Voltage (v) Input = 800mV Switched to NEG @ t = 0uS Output Voltage (v) Input = -800mV Switched to NEG @ t = 0uS 0 0.5 1.0 1.5 0 0.5 1.0 1.5 Time (µS) Time (µS) NIP Cell to NEG Cell Response NIP Cell to NEG Cell Response 15 TRAC020LH CONNECTION DIAGRAM QSOP 36 Lead Note: For clarity the IO pin definition has been changed from previous issue TOP VIEW (NOT TO SCALE) PACKAGING INFORMATION A B C H D P IN N o. 1 E K J Fast Analog Solutions Ltd. Fields New Road, Chadderton, Oldham, OL9 8NP, United Kingdom. Tel: (+44) (0) 161 622 4567 Fax: (+44) (0) 161 622 4568 e-mail: trac@fas.co.uk Internet: http://www.fas.co.uk TRAC products are supported by agents and distributors in many countries of the world. Details can be found on our web site. A ZETEX GROUP COMPANY This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of any product or service. 16 0 .1 3(.005) F I