S3 Family 8-Bit Microcontrollers
S3F8S6B MCU
Product Specification
PS032408-0220
PRELIMINARY
Copyright ©2020 Zilog®, Inc. All rights reserved.
www.zilog.com
S3F8S6B MCU
Product Specification
ii
Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2020 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
S3 and Z8 are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the
property of their respective owners.
PS032408-0220
PRELIMINARY
S3F8S6B MCU
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in
the table below.
Revision
Level
Description
Page
Feb
2020
08
Updated to new Zilog logo.
All
Mar
2018
07
Replaced Figure 23-2 (64-LQFP Package Dimensions);
corrected typos in LCD Mode Control Register description
23-2;
4-19
Dec
2016
06
Updated LCD Mode Control Register; added Table 15.1; updated Figure 4-19; 15-4;
15-5; updated Table 22.10
15-6; 22-14
May
2015
05
Updated title and header/footer information
All
Feb
2015
04
Reduced PDF file size
All
Feb
2015
03
Corrected Figure Title in Figure 1-3
1-8
Jan
2015
02
Updated the Third Parties for Development Tools section.
25-7
Mar
2014
01
Original Zilog issue. Deleted Pin Circuit Type A diagram from Product
1-14; 6-5
Overview chapter; changed “First interrupt” to “Fast interrupt”, Figure 6-1.
Jan
2014
1.00
First release.
Jun
2013
0.00
First draft.
Date
PS032408-0220
PRELIMINARY
Revision History
S3F8S6B Product Specification
Table of Contents
Table of Contents
Table of Contents ....................................................................................................................................................... 4
List of Figures .......................................................................................................................................................... 13
List of Tables ............................................................................................................................................................ 17
List of Examples ....................................................................................................................................................... 19
1 Product Overview ................................................................................................................................................. 1-1
1.1 S3C8-Series Microcontrollers .................................................................................................................. 1-1
1.2 S3F8S6B Microcontroller ......................................................................................................................... 1-1
1.3 Features ................................................................................................................................................... 1-2
1.4 Block Diagram .......................................................................................................................................... 1-6
1.5 Pin Assignment ........................................................................................................................................ 1-7
1.6 Pin Descriptions ..................................................................................................................................... 1-10
1.7 Pin Circuits ............................................................................................................................................. 1-14
2 Address Spaces ................................................................................................................................................... 2-1
2.1 Overview .................................................................................................................................................. 2-1
2.2 Program Memory (ROM) .......................................................................................................................... 2-2
2.2.1 Smart Option ..................................................................................................................................... 2-3
2.3 Register Architecture ................................................................................................................................ 2-5
2.3.1 Register Page Pointer (PP) .............................................................................................................. 2-7
2.3.2 Register Set 1 ................................................................................................................................... 2-9
2.3.3 Register Set 2 ................................................................................................................................... 2-9
2.3.4 Prime Register Space ..................................................................................................................... 2-10
2.3.5 Working Registers........................................................................................................................... 2-11
2.3.6 Using the Register Points ............................................................................................................... 2-12
2.4 Register Addressing ............................................................................................................................... 2-14
2.4.1 Common Working Register Area (C0H−CFH) ................................................................................ 2-16
2.4.2 4-bit Working Register Addressing ................................................................................................. 2-17
2.4.3 8-bit Working Register Addressing ................................................................................................. 2-19
2.5 System and User Stack .......................................................................................................................... 2-21
2.5.1 Stack Operations ............................................................................................................................ 2-21
2.5.2 User-Defined Stacks ....................................................................................................................... 2-22
2.5.3 Stack Pointers (SPL, SPH) ............................................................................................................. 2-22
3 Addressing Modes ............................................................................................................................................... 3-1
3.1 Overview .................................................................................................................................................. 3-1
3.2 Register Addressing Mode ....................................................................................................................... 3-2
3.3 Indirect Register Addressing Mode (IR) ................................................................................................... 3-3
3.4 Indexed Addressing Mode (X).................................................................................................................. 3-7
3.5 Direct Address Mode (DA) ..................................................................................................................... 3-10
3.6 Indirect Address Mode (IA) .................................................................................................................... 3-12
3.7 Relative Address Mode (RA).................................................................................................................. 3-13
3.8 Immediate Mode (IM) ............................................................................................................................. 3-14
4 Control Registers ................................................................................................................................................. 4-1
4.1 Overview .................................................................................................................................................. 4-1
PS032408-0220
PRELIMINARY
iv
S3F8S6B Product Specification
Table of Contents
4.1.1 ADCON: A/D Converter Control Register (D2H, Set 1, Bank 0) ...................................................... 4-6
4.1.2 BTCON: Basic Timer Control Register (D3H, Set 1) ........................................................................ 4-7
4.1.3 CLKCON: System Clock Control Register (D4H, Set 1)................................................................... 4-8
4.1.4 FLAGS: System Flags Register (D5H, Set 1) ................................................................................... 4-9
4.1.5 FMCON: Flash Memory Control Register (F9H, Set 1, Bank 0) ..................................................... 4-10
4.1.6 FMSECH: Flash Memory Sector Address Register-High Byte (F6H, Set 1, Bank 0) ..................... 4-11
4.1.7 FMSECL: Flash Memory Sector Address Register-Low Byte (F7H, Set 1, Bank 0) ...................... 4-11
4.1.8 FMUSR: Flash Memory User Programming Enable Register (F8H, Set 1, Bank 0) ...................... 4-12
4.1.9 IMR: Interrupt Mask Register (DDH, Set 1) .................................................................................... 4-13
4.1.10 INTPND: Interrupt Pending Register (F4H, Set 1, Bank 0) .......................................................... 4-14
4.1.11 IPH: Instruction Pointer-High Byte (DAH, Set 1) .......................................................................... 4-15
4.1.12 IPL: Instruction Pointer-Low Byte (DBH, Set 1) ............................................................................ 4-15
4.1.13 IPR: Interrupt Priority Register (FFH, Set 1, Bank 0) .................................................................... 4-16
4.1.14 IRQ: Interrupt Request Register (DCH, Set 1) ............................................................................. 4-17
4.1.15 LCON: LCD Control Register (F0H, Set 1, Bank 0) ...................................................................... 4-18
4.1.16 LMOD: LCD Mode Control Register (F1H, Set 1, Bank 0) ........................................................... 4-19
4.1.17 OSCCON: Oscillator Control Register (FAH, Set 1, Bank 0) ....................................................... 4-20
4.1.18 P0CONH: Port 0 Control Register-High Byte (E0H, Set 1, Bank 1) ............................................. 4-21
4.1.19 P0CONL: Port 0 Control Register-Low Byte (E1H, Set 1, Bank 1) .............................................. 4-22
4.1.20 P1CONH: Port 1 Control Register-High Byte (E2H, Set 1, Bank 1) ............................................. 4-23
4.1.21 P1CONL: Port 1 Control Register-Low Byte (E3H, Set 1, Bank 1) .............................................. 4-24
4.1.22 P1PUR: Port 1 Pull-up Resistor Enable Register (E4H, Set 1, Bank 1) ....................................... 4-25
4.1.23 PNE1: Port 1 N-channel Open-drain Mode Register (E5H, Set 1, Bank 1) ................................. 4-27
4.1.24 P2CONH: Port 2 Control Register-High Byte (E6H, Set 1, Bank 1) ............................................. 4-28
4.1.25 P2CONL: Port 2 Control Register-Low Byte (E7H, Set 1, Bank 1) .............................................. 4-29
4.1.26 P2INTH: Port 2 Interrupt Control Register-High Byte (E8H, Set 1, Bank 1) ................................. 4-30
4.1.27 P2INTL: Port 2 Interrupt Control Register-Low Byte (E9H, Set 1, Bank 1) .................................. 4-31
4.1.28 P2PND: Port 2 Interrupt Pending Register (EAH, Set 1, Bank 1) ................................................ 4-32
4.1.29 P3CONH: Port 3 Control Register-High Byte (EBH, Set 1, Bank 1)............................................. 4-33
4.1.30 P3CONM: Port 3 Control Register-Middle Byte (ECH, Set 1, Bank 1) ......................................... 4-34
4.1.31 P3CONL: Port 3 Control Register-Low Byte (EDH, Set 1, Bank 1) .............................................. 4-35
4.1.32 P3PUR: Port 3 Pull-up Resistor Enable Register (EEH, Set 1, Bank 1) ...................................... 4-36
4.1.33 PNE3: Port 3 N-channel Open-drain Mode Register (EFH, Set 1, Bank 1) ................................. 4-38
4.1.34 P4CONH: Port 4 Control Register-High Byte (0CH, Page 8) ....................................................... 4-39
4.1.35 P4CONL: Port 4 Control Register-Low Byte (0DH, Page 8) ........................................................ 4-40
4.1.36 P4INTH: Port 4 Interrupt Control Register-High Byte (0EH, Page 8) ........................................... 4-41
4.1.37 P4INTL: Port 4 Interrupt Control Register-Low Byte (0FH, Page 8)............................................. 4-42
4.1.38 P4PND: Port 4 Interrupt Pending Register (10H, Page 8) ........................................................... 4-43
4.1.39 P5CONH: Port 5 Control Register-High Byte (F0H, Set 1, Bank 1) ............................................. 4-44
4.1.40 P5CONL: Port 5 Control Register-Low Byte (F1H, Set 1, Bank 1) ............................................... 4-45
4.1.41 P6CONH: Port 6 Control Register-High Byte (F2H, Set 1, Bank 1) ............................................. 4-46
4.1.42 P6CONL: Port 6 Control Register-Low Byte (F3H, Set 1, Bank 1) ............................................... 4-47
4.1.43 P6PUR: Port 6 Pull-up Resistor Enable Register (F4H, Set 1, Bank 1) ....................................... 4-48
4.1.44 PNE6: Port 6 N-channel Open-drain Mode Register (F5H, Set 1, Bank 1) .................................. 4-49
4.1.45 PGCON: Pattern Generation Module Control Register (D0H, Set 1, Bank 1) .............................. 4-50
4.1.46 PP: Register Page Pointer (DFH, Set 1) ...................................................................................... 4-51
4.1.47 RP0: Register Pointer 0 (D6H, Set 1) ........................................................................................... 4-52
4.1.48 RP1: Register Pointer 1 (D7H, Set 1) ........................................................................................... 4-53
4.1.49 SIOCON: SIO Control Register (E7H, Set 1, Bank 0) .................................................................. 4-54
4.1.50 SPH: Stack Pointer-High Byte (D8H, Set 1) ................................................................................. 4-55
4.1.51 SPL: Stack Pointer-Low Byte (D9H, Set 1) .................................................................................. 4-55
4.1.52 STPCON: Stop Control Register (F5H, Set 1, Bank 0) ................................................................ 4-56
4.1.53 SYM: System Mode Register (DEH, Set 1) .................................................................................. 4-57
4.1.54 TACON: Timer A Control Register (E2H, Set 1, Bank 0) ............................................................. 4-58
4.1.55 TBCON: Timer B Control Register (E3H, Set 1, Bank 0) ............................................................. 4-59
PS032408-0220
PRELIMINARY
v
S3F8S6B Product Specification
Table of Contents
4.1.56 TCCON: Timer C Control Register (ECH, Set 1, Bank 0) ............................................................ 4-60
4.1.57 TD0CON: Timer D0 Control Register (FAH, Set 1, Bank 1) ......................................................... 4-61
4.1.58 TD1CON: Timer D1 Control Register (FBH, Set 1, Bank 1) ......................................................... 4-62
4.1.59 UART0CONH: UART 0 Control Register-High Byte (14H, Page 8) ............................................. 4-63
4.1.60 UART0CONL: UART 0 Control Register-Low Byte (15H, Page 8) ................................................. 64
4.1.61 UART1CONH: UART 1 Control Register-High Byte (18H, Page 8) ............................................. 4-65
4.1.62 UART1CONL: UART 1 Control Register-Low Byte (19H, Page 8) ................................................. 66
4.1.63 WTCON: Watch Timer Control Register (E6H, Set 1, Bank 0) .................................................... 4-67
5 Interrupt Structure ................................................................................................................................................ 5-1
5.1 Overview .................................................................................................................................................. 5-1
5.2 Interrupt Types ......................................................................................................................................... 5-2
5.3 S3F8S6B Interrupt Structure .................................................................................................................... 5-3
5.4 Interrupt Vector Addresses ...................................................................................................................... 5-5
5.5 Enable/Disable Interrupt Instructions (EI, DI) ........................................................................................... 5-8
5.6 System-Level Interrupt Control Registers ................................................................................................ 5-8
5.7 Interrupt Processing Control Points ......................................................................................................... 5-9
5.8 Peripheral Interrupt Control Registers ................................................................................................... 5-10
5.9 System Mode Register (SYM) ................................................................................................................ 5-12
5.10 Interrupt Mask Register (IMR) .............................................................................................................. 5-13
5.11 Interrupt Priority Register (IPR) ............................................................................................................ 5-14
5.12 Interrupt Request Register (IRQ) ......................................................................................................... 5-16
5.13 Interrupt Pending Function Types ........................................................................................................ 5-17
5.13.1 Overview ....................................................................................................................................... 5-17
5.13.2 Pending Bits Cleared Automatically by Hardware ........................................................................ 5-17
5.13.3 Pending Bits Cleared by the Service Routine ............................................................................... 5-17
5.14 Interrupt Source Polling Sequence ...................................................................................................... 5-18
5.15 Interrupt Service Routines .................................................................................................................... 5-18
5.16 Generating interrupt Vector Addresses ................................................................................................ 5-19
5.17 Nesting of Vectored Interrupts ............................................................................................................. 5-19
5.18 Instruction Pointer (IP) ......................................................................................................................... 5-19
5.19 Fast Interrupt Processing ..................................................................................................................... 5-20
5.20 Procedure for Initiating Fast Interrupts ................................................................................................. 5-20
5.21 Fast Interrupt Service Routine ............................................................................................................. 5-20
5.22 Relationship to Interrupt Pending Bit Types ......................................................................................... 5-21
5.23 Programming Guidelines ...................................................................................................................... 5-21
6 Instruction Set ...................................................................................................................................................... 6-1
6.1 Overview .................................................................................................................................................. 6-1
6.1.1 Data Types ........................................................................................................................................ 6-1
6.1.2 Register Addressing ......................................................................................................................... 6-1
6.1.3 Addressing Modes ............................................................................................................................ 6-1
6.2 Flags Register (FLAGS) ........................................................................................................................... 6-5
6.2.1 Flag Descriptions .............................................................................................................................. 6-6
6.2.2 Instruction Set Notation .................................................................................................................... 6-7
6.2.3 Condition Codes ............................................................................................................................. 6-11
6.3 Instruction Descriptions .......................................................................................................................... 6-12
6.3.1 ADC - Add with carry ...................................................................................................................... 6-13
6.3.2 ADD - Add ....................................................................................................................................... 6-14
6.3.3 AND - Logical AND ......................................................................................................................... 6-15
6.3.4 BAND - Bit AND .............................................................................................................................. 6-16
6.3.5 BCP - Bit Compare ......................................................................................................................... 6-17
6.3.6 BITC - Bit Complement ................................................................................................................... 6-18
6.3.7 BITR - Bit Reset .............................................................................................................................. 6-19
PS032408-0220
PRELIMINARY
vi
S3F8S6B Product Specification
Table of Contents
6.3.8 BITS - Bit Set .................................................................................................................................. 6-20
6.3.9 BOR - Bit OR .................................................................................................................................. 6-21
6.3.10 BTJRF - Bit Test, Jump Relative on False ................................................................................... 6-22
6.3.11 BTJRT - Bit Test, Jump Relative on True ..................................................................................... 6-23
6.3.12 BXOR - Bit XOR............................................................................................................................ 6-24
6.3.13 CALL - Call Procedure .................................................................................................................. 6-25
6.3.14 CCF - Complement Carry Flag ..................................................................................................... 6-26
6.3.15 CLR - Clear ................................................................................................................................... 6-27
6.3.16 COM - Complement ...................................................................................................................... 6-28
6.3.17 CP - Compare ............................................................................................................................... 6-29
6.3.18 CPIJE - Compare, Increment, and Jump on Equal ...................................................................... 6-30
6.3.19 CPIJNE - Compare, Increment, and Jump on Non-Equal ............................................................ 6-31
6.3.20 DA - Decimal Adjust ...................................................................................................................... 6-32
6.3.21 DEC - Decrement.......................................................................................................................... 6-34
6.3.22 DECW - Decrement Word ............................................................................................................ 6-35
6.3.23 DI - Disable Interrupts ................................................................................................................... 6-36
6.3.24 DIV - Divide (Unsigned) ................................................................................................................ 6-37
6.3.25 DJNZ - Decrement and Jump if Non-Zero .................................................................................... 6-38
6.3.26 EI - Enable Interrupts .................................................................................................................... 6-39
6.3.27 ENTER - Enter .............................................................................................................................. 6-40
6.3.28 EXIT - Exit ..................................................................................................................................... 6-41
6.3.29 IDLE - Idle Operation .................................................................................................................... 6-42
6.3.30 INC - Increment............................................................................................................................. 6-43
6.3.31 INCW - Increment Word ............................................................................................................... 6-44
6.3.32 IRET - Interrupt Return ................................................................................................................. 6-45
6.3.33 JP - Jump ...................................................................................................................................... 6-46
6.3.34 JR - Jump Relative ....................................................................................................................... 6-47
6.3.35 LD - Load ...................................................................................................................................... 6-48
6.3.36 LDB - Load Bit............................................................................................................................... 6-50
6.3.37 LDC/LDE - Load Memory ............................................................................................................. 6-51
6.3.38 LDCD/LDED - Load Memory and Decrement .............................................................................. 6-53
6.3.39 LDCI/LDEI - Load Memory and Increment ................................................................................... 6-54
6.3.40 LDCPD/LDEPD - Load Memory with Pre-Decrement .................................................................. 6-55
6.3.41 LDCPI/LDEPI - Load Memory with Pre-Increment ....................................................................... 6-56
6.3.42 LDW - Load Word ......................................................................................................................... 6-57
6.3.43 MULT - Multiply (Unsigned) .......................................................................................................... 6-58
6.3.44 NEXT - Next .................................................................................................................................. 6-59
6.3.45 NOP - No Operation ..................................................................................................................... 6-60
6.3.46 OR - Logical OR............................................................................................................................ 6-61
6.3.47 POP - Pop from Stack .................................................................................................................. 6-62
6.3.48 POPUD - Pop User Stack (Decrementing) ................................................................................... 6-63
6.3.49 POPUI - Pop User Stack (Incrementing) ...................................................................................... 6-64
6.3.50 PUSH - Push To Stack ................................................................................................................. 6-65
6.3.51 PUSHUD - Push User Stack (Decrementing) ............................................................................... 6-66
6.3.52 PUSHUI - Push User Stack (Incrementing) .................................................................................. 6-67
6.3.53 RCF - Reset Carry Flag ................................................................................................................ 6-68
6.3.54 RET - Return ................................................................................................................................. 6-69
6.3.55 RL - Rotate Left............................................................................................................................. 6-70
6.3.56 RLC - Rotate Left Through Carry .................................................................................................. 6-71
6.3.57 RR - Rotate Right ......................................................................................................................... 6-72
6.3.58 RRC - Rotate Right Through Carry............................................................................................... 6-73
6.3.59 SB0 - Select Bank 0 ...................................................................................................................... 6-74
6.3.60 SB1 - Select Bank 1 ...................................................................................................................... 6-75
6.3.61 SBC - Subtract with Carry ............................................................................................................. 6-76
6.3.62 SCF - Set Carry Flag .................................................................................................................... 6-77
PS032408-0220
PRELIMINARY
vii
S3F8S6B Product Specification
Table of Contents
6.3.63 SRA - Shift Right Arithmetic .......................................................................................................... 6-78
6.3.64 SRP/SRP0/SRP1 - Set Register Pointer ...................................................................................... 6-79
6.3.65 STOP - Stop Operation ................................................................................................................. 6-80
6.3.66 SUB - Subtract .............................................................................................................................. 6-81
6.3.67 SWAP - Swap Nibbles .................................................................................................................. 6-82
6.3.68 TCM - Test Complement Under Mask .......................................................................................... 6-83
6.3.69 TM - Test Under Mask .................................................................................................................. 6-84
6.3.70 WFI - Wait for Interrupt ................................................................................................................. 6-85
6.3.71 XOR - Logical Exclusive OR ......................................................................................................... 6-86
7 Clock Circuit ......................................................................................................................................................... 7-1
7.1 Overview .................................................................................................................................................. 7-1
7.1.1 System Clock Circuit ......................................................................................................................... 7-1
7.1.2 CPU Clock Notation .......................................................................................................................... 7-1
7.2 Main Oscillator Circuits ............................................................................................................................ 7-2
7.3 Sub Oscillator Circuits .............................................................................................................................. 7-3
7.4 Clock Status During Power-Down Modes ................................................................................................ 7-4
7.5 System Clock Control Register (CLKCON) .............................................................................................. 7-5
7.6 Stop Control Register (STPCON) ............................................................................................................ 7-7
7.7 Switching the CPU Clock ......................................................................................................................... 7-8
8 RESET and Power-Down .................................................................................................................................... 8-1
8.1 System Reset ........................................................................................................................................... 8-1
8.1.1 Overview ........................................................................................................................................... 8-1
8.1.2 Normal Mode Reset Operation ......................................................................................................... 8-1
8.1.3 Hardware Reset Values .................................................................................................................... 8-2
8.2 Power-Down Modes ................................................................................................................................. 8-7
8.2.1 Stop Mode......................................................................................................................................... 8-7
8.2.2 Idle Mode .......................................................................................................................................... 8-8
9 I/O Port ................................................................................................................................................................. 9-1
9.1 Overview .................................................................................................................................................. 9-1
9.2 Port Data Registers .................................................................................................................................. 9-2
9.2.1 Port 0 ................................................................................................................................................ 9-3
9.2.2 Port 1 ................................................................................................................................................ 9-5
9.2.3 Port 2 ................................................................................................................................................ 9-8
9.2.4 Port 3 .............................................................................................................................................. 9-12
9.2.5 Port 4 .............................................................................................................................................. 9-16
9.2.6 Port 5 .............................................................................................................................................. 9-20
9.2.7 Port 6 .............................................................................................................................................. 9-22
10 Basic Timer ...................................................................................................................................................... 10-1
10.1 Overview .............................................................................................................................................. 10-1
10.1.1 Basic Timer (BT) ........................................................................................................................... 10-1
10.2 Basic Timer Control Register (BTCON) ............................................................................................... 10-2
10.3 Basic Timer Function Description ........................................................................................................ 10-3
10.3.1 Watchdog Timer Function ............................................................................................................. 10-3
10.3.2 Oscillation Stabilization Interval Timer Function ........................................................................... 10-3
11 8-Bit Timer A/B ................................................................................................................................................. 11-1
11.1 8-Bit Timer A ........................................................................................................................................ 11-1
11.1.1 Overview ....................................................................................................................................... 11-1
11.1.2 Timer A Control Register (TACON) .............................................................................................. 11-2
11.1.3 Timer A Function Description ....................................................................................................... 11-3
PS032408-0220
PRELIMINARY
viii
S3F8S6B Product Specification
Table of Contents
11.1.4 Block Diagram............................................................................................................................... 11-6
11.2 8-Bit Timer B ........................................................................................................................................ 11-7
11.2.1 Overview ....................................................................................................................................... 11-7
11.2.2 Block diagram ............................................................................................................................... 11-8
11.2.3 Timer b PULSE WIDTH CALCULATIONS ................................................................................... 11-9
12 8-Bit Timer C .................................................................................................................................................... 12-1
12.1 8-Bit Timer C ........................................................................................................................................ 12-1
12.1.1 Overview ....................................................................................................................................... 12-1
12.1.2 Timer c Control Register (TcCON) ............................................................................................... 12-2
12.1.3 Block Diagram............................................................................................................................... 12-3
13 16-Bit Timer D0/D1 .......................................................................................................................................... 13-1
13.1 16-Bit Timer D0 .................................................................................................................................... 13-1
13.1.1 Overview ....................................................................................................................................... 13-1
13.1.2 Timer D0 Control Register (TD0CON) .......................................................................................... 13-2
13.1.3 Timer D0 Function Description ..................................................................................................... 13-3
13.1.4 Block Diagram............................................................................................................................... 13-6
13.2 16-bit timer D1 ...................................................................................................................................... 13-7
13.2.1 Overview ....................................................................................................................................... 13-7
13.2.2 Timer D1 Control Register (TD1CON) .......................................................................................... 13-8
13.2.3 Timer D1 Function Description ..................................................................................................... 13-9
13.2.4 Block Diagram............................................................................................................................. 13-12
14 Watch Timer ..................................................................................................................................................... 14-1
14.1 Overview .............................................................................................................................................. 14-1
14.2 Watch Timer CONTROL Register (WTCON) ....................................................................................... 14-2
14.3 Watch Timer Circuit Diagram ............................................................................................................... 14-3
15 LCD Controller/Driver....................................................................................................................................... 15-1
15.1 Overview .............................................................................................................................................. 15-1
15.2 LCD Circuit Diagram ............................................................................................................................ 15-2
15.3 LCD RAM Address Area ...................................................................................................................... 15-3
15.4 LCD control register (lCON) ................................................................................................................. 15-4
15.5 LCD MODE Control Register (LMOD) ................................................................................................. 15-6
15.6 Internal Resistor Bias Pin Connection ................................................................................................. 15-7
15.7 External Resistor Bias Pin Connection ................................................................................................ 15-8
15.8 Capacitor Bias Pin Connection ............................................................................................................ 15-9
15.9 Common (COM) Signals .................................................................................................................... 15-10
15.10 Segment (SEG) Signals ................................................................................................................... 15-11
16 10-Bit Analog-To-Digital Converter .................................................................................................................. 16-1
16.1 Overview .............................................................................................................................................. 16-1
16.2 Function Description ............................................................................................................................ 16-2
16.3 Conversion Timing ............................................................................................................................... 16-3
16.4 A/D Converter Control Register (ADCON) ........................................................................................... 16-3
16.5 Internal Reference Voltage Levels ....................................................................................................... 16-4
16.6 Block Diagram ...................................................................................................................................... 16-5
17 Serial I/O Interface ........................................................................................................................................... 17-1
17.1 Overview .............................................................................................................................................. 17-1
17.2 Programming Procedure ...................................................................................................................... 17-1
17.3 SIO Control Register (SIOCON) .......................................................................................................... 17-2
PS032408-0220
PRELIMINARY
ix
S3F8S6B Product Specification
Table of Contents
17.4 SIO Pre-Scaler Register (SIOPS) ........................................................................................................ 17-3
17.5 Block Diagram ...................................................................................................................................... 17-4
17.6 Serial I/O Timing Diagram .................................................................................................................... 17-5
18 UART 0 ............................................................................................................................................................ 18-1
18.1 Overview .............................................................................................................................................. 18-1
18.2 Programming Procedure ...................................................................................................................... 18-2
18.3 UART 0 High-Byte Control Register (UART0CONh) ........................................................................... 18-2
18.4 UART 0 Low-Byte Control Register (UART0CONl) ............................................................................. 18-2
18.5 UART 0 Interrupt Pending bits ............................................................................................................. 18-5
18.6 UART 0 Data Register (UDATA0) ........................................................................................................ 18-5
18.7 UART 0 Baud Rate Data Register (BRDATA0) ................................................................................... 18-5
18.8 Baud Rate Calculations ........................................................................................................................ 18-6
18.8.1 Mode 0 Baud Rate Calculation ..................................................................................................... 18-6
18.8.2 Mode 2 Baud Rate Calculation ..................................................................................................... 18-6
18.8.3 Modes 1 and 3 Baud Rate Calculation ......................................................................................... 18-6
18.9 Block Diagram ...................................................................................................................................... 18-7
18.10 uart 0 Mode 0 Function Description ................................................................................................... 18-8
18.10.1 Mode 0 Transmit Procedure ....................................................................................................... 18-8
18.10.2 Mode 0 Receive Procedure ........................................................................................................ 18-8
18.11 Serial Port Mode 1 Function Description ........................................................................................... 18-9
18.11.1 Mode 1 Transmit Procedure ....................................................................................................... 18-9
18.11.2 Mode 1 Receive Procedure ........................................................................................................ 18-9
18.12 Serial Port Mode 2 Function Description ......................................................................................... 18-11
18.12.1 Mode 2 Transmit Procedure ..................................................................................................... 18-11
18.12.2 Mode 2 Receive Procedure ...................................................................................................... 18-11
18.13 Serial Port Mode 3 Function Description ......................................................................................... 18-13
18.13.1 Mode 3 Transmit Procedure ..................................................................................................... 18-13
18.13.2 Mode 3 Receive Procedure ...................................................................................................... 18-13
18.14 Serial Communication for Multiprocessor Configurations ................................................................ 18-15
18.14.1 Sample Protocol for Master/Slave Interaction .......................................................................... 18-15
18.14.2 Setup Procedure for Multiprocessor Communications ............................................................. 18-16
19 UART 1 ............................................................................................................................................................ 19-1
19.1 Overview .............................................................................................................................................. 19-1
19.2 Programming Procedure ...................................................................................................................... 19-2
19.3 UART 1 High-Byte Control Register (UART1CONh) ........................................................................... 19-2
19.4 UART 1 Low-Byte Control Register (UART1CONl) ............................................................................. 19-2
19.5 UART 1 Interrupt Pending Bits ............................................................................................................. 19-5
19.6 UART 1 Data Register (UDATA1) ........................................................................................................ 19-5
19.7 UART 1 Baud Rate Data Register (BRDATA1) ................................................................................... 19-5
19.8 Baud Rate Calculations ........................................................................................................................ 19-6
19.8.1 Mode 0 Baud Rate Calculation ..................................................................................................... 19-6
19.8.2 Mode 2 Baud Rate Calculation ..................................................................................................... 19-6
19.8.3 Modes 1 and 3 Baud Rate Calculation ......................................................................................... 19-6
19.9 Block Diagram ...................................................................................................................................... 19-7
19.10 UART 1 Mode 0 Function Description ............................................................................................... 19-8
19.10.1 Mode 0 Transmit Procedure ....................................................................................................... 19-8
19.10.2 Mode 0 Receive Procedure ........................................................................................................ 19-8
19.11 Serial Port Mode 1 Function Description ........................................................................................... 19-9
19.11.1 Mode 1 Transmit Procedure ....................................................................................................... 19-9
19.11.2 Mode 1 Receive Procedure ........................................................................................................ 19-9
19.12 Serial Port Mode 2 Function Description ......................................................................................... 19-11
19.12.1 Mode 2 Transmit Procedure ..................................................................................................... 19-11
PS032408-0220
PRELIMINARY
x
S3F8S6B Product Specification
Table of Contents
19.12.2 Mode 2 Receive Procedure ...................................................................................................... 19-11
19.13 Serial Port Mode 3 Function Description ......................................................................................... 19-13
19.13.1 Mode 3 Transmit Procedure ..................................................................................................... 19-13
19.13.2 Mode 3 Receive Procedure ...................................................................................................... 19-13
19.14 Serial Communication for Multiprocessor Configurations ................................................................ 19-15
19.14.1 Sample Protocol for Master/Slave Interaction .......................................................................... 19-15
19.14.2 Setup Procedure for Multiprocessor Communications ............................................................. 19-16
20 Pattern Generation Module .............................................................................................................................. 20-1
20.1 Overview .............................................................................................................................................. 20-1
20.1.1 PAttern Gneration Flow ................................................................................................................ 20-1
21 Embedded Flash Memory Interface ................................................................................................................. 21-1
21.1 Overview .............................................................................................................................................. 21-1
21.2 User Program Mode ............................................................................................................................. 21-2
21.2.1 Flash Memory Control Registers (User Program Mode) .............................................................. 21-3
21.3 ISPTM (On-Board Programming) Sector ............................................................................................... 21-6
21.3.1 ISP Reset Vector and ISP Sector Size ......................................................................................... 21-7
21.4 Sector Erase......................................................................................................................................... 21-8
21.5 Programming ...................................................................................................................................... 21-10
21.6 Reading .............................................................................................................................................. 21-12
21.7 Hard Lock Protection .......................................................................................................................... 21-13
22 Electrical Data .................................................................................................................................................. 22-1
22.1 Overview .............................................................................................................................................. 22-1
22.2 Absolute Maximum Ratings ................................................................................................................. 22-2
22.3 D.C. Electrical Characteristics .............................................................................................................. 22-3
22.4 A.C. Electrical Characteristics .............................................................................................................. 22-6
22.5 Input/Output Capacitance .................................................................................................................... 22-7
22.6 Data Retention Supply Voltage in Stop Mode ...................................................................................... 22-7
22.7 A/D Converter Electrical Characteristics .............................................................................................. 22-9
22.8 Low Voltage Reset Electrical Characteristics .................................................................................... 22-10
22.9 Synchronous SIO Electrical Characteristics ...................................................................................... 22-11
22.10 UART Timing Characteristics ........................................................................................................... 22-12
22.11 LCD Capacitor Bias Electrical Characteristics ................................................................................. 22-14
22.12 Main Oscillator Characteristics......................................................................................................... 22-15
22.13 Sub Oscillation Characteristics ........................................................................................................ 22-16
22.14 Main Oscillation Stabilization Time .................................................................................................. 22-17
22.15 Sub Oscillation Stabilization Time .................................................................................................... 22-18
22.16 Operating Voltage Range ................................................................................................................. 22-19
22.17 Internal Flash ROM Electrical Characteristics ................................................................................. 22-20
23 Mechanical Data .............................................................................................................................................. 23-1
23.1 Overview .............................................................................................................................................. 23-1
24 S3F8S6B Flash MCU ....................................................................................................................................... 24-1
24.1 Overview .............................................................................................................................................. 24-1
24.2 Pin Assignments .................................................................................................................................. 24-1
24.3 On Board Writing .................................................................................................................................. 24-5
24.3.1 Circuit Design Guide ..................................................................................................................... 24-5
24.3.2 Reference Table for Connection ................................................................................................... 24-6
PS032408-0220
PRELIMINARY
xi
S3F8S6B Product Specification
Table of Contents
25 Development Tools .......................................................................................................................................... 25-1
25.1 Overview .............................................................................................................................................. 25-1
25.1.1 Target Boards ............................................................................................................................... 25-1
25.1.2 Programming Socket Adapter ....................................................................................................... 25-1
25.2 TB8S6B Target Board .......................................................................................................................... 25-3
25.2.1 Third Parties for Development Tools ............................................................................................ 25-7
25.2.2 In-Circuit Emulators ...................................................................................................................... 25-7
25.2.3 OTP/MTP Programmers ............................................................................................................... 25-7
PS032408-0220
PRELIMINARY
xii
S3F8S6B Product Specification
List of Figures
List of Figures
Figure
Number
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 1-6
Figure 1-7
Figure 1-8
Figure 1-9
Figure 1-10
Figure 1-11
Figure 1-12
Figure 1-13
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Figure 2-13
Figure 2-14
Figure 2-15
Figure 2-16
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 4-1
Title
Page
Number
Block Diagram ................................................................................................................................... 1-6
S3F8S6B Pin Assignments (64-LQFP-1010) ................................................................................... 1-7
S3F8S6B Pin Assignments (64-QFP-1420F) ................................................................................... 1-8
S3F8S6B Pin Assignments (64-SDIP-750) ...................................................................................... 1-9
Pin Circuit Type B ........................................................................................................................... 1-14
Pin Circuit Type C ........................................................................................................................... 1-15
Pin Circuit Type D-2 (P5.6 – P5.7).................................................................................................. 1-15
Pin Circuit Type F-16 (P4) .............................................................................................................. 1-16
Pin Circuit Type F-17 (P5.0 - P5.5) ................................................................................................. 1-16
Pin Circuit Type H-39 .................................................................................................................... 1-17
Pin Circuit Type H-43 (P2) ............................................................................................................ 1-17
Pin Circuit Type H-44 (P0) ............................................................................................................ 1-18
Pin Circuit Type H-42 (P1, P3, P6) ............................................................................................... 1-18
Program Memory Address Space ..................................................................................................... 2-2
Smart Option ..................................................................................................................................... 2-3
Internal Register File Organization (S3F8S6B) ................................................................................ 2-6
Register Page Pointer (PP) ............................................................................................................... 2-7
Set 1, Set 2, Prime Area Register, and LCD Data Register Map ................................................... 2-10
8 byte Working Register Areas (Slices) .......................................................................................... 2-11
Contiguous 16 byte Working Register Block .................................................................................. 2-12
Non-Contiguous 16 byte Working Register Block........................................................................... 2-13
16-Bit Register Pair ......................................................................................................................... 2-14
Register File Addressing ............................................................................................................... 2-15
Common Working Register Area .................................................................................................. 2-16
4-bit Working Register Addressing ............................................................................................... 2-18
4-bit Working Register Addressing Example ................................................................................ 2-18
8-bit Working Register Addressing ............................................................................................... 2-19
8-bit Working Register Addressing Example ................................................................................ 2-20
Stack Operations .......................................................................................................................... 2-21
Register Addressing .......................................................................................................................... 3-2
Working Register Addressing ........................................................................................................... 3-2
Indirect Register Addressing to Register File ................................................................................... 3-3
Indirect Register Addressing to Program Memory ............................................................................ 3-4
Indirect Working Register Addressing to Register File ..................................................................... 3-5
Indirect Working Register Addressing to Program or Data Memory ................................................. 3-6
Indexed Addressing to Register File ................................................................................................. 3-7
Indexed Addressing to Program or Data Memory with Short Offset................................................. 3-8
Indexed Addressing to Program or Data Memory ............................................................................ 3-9
Direct Addressing for Load Instructions ........................................................................................ 3-10
Direct Addressing for Call and Jump Instructions ......................................................................... 3-11
Indirect Addressing ....................................................................................................................... 3-12
Relative Addressing ...................................................................................................................... 3-13
Immediate Addressing .................................................................................................................. 3-14
Register Description Format ............................................................................................................. 4-5
PS032408-0220
PRELIMINARY
xiii
S3F8S6B Product Specification
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 6-1
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 9-5
Figure 9-6
Figure 9-7
Figure 9-8
Figure 9-9
Figure 9-10
Figure 9-11
Figure 9-12
Figure 9-13
Figure 9-14
Figure 9-15
Figure 9-16
Figure 9-17
Figure 9-18
Figure 9-19
Figure 9-20
Figure 9-21
Figure 9-22
Figure 9-23
Figure 9-24
Figure 9-25
Figure 9-26
Figure 9-27
Figure 9-28
Figure 10-1
Figure 10-2
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Figure 11-5
Figure 11-6
List of Figures
S3C8-Series Interrupt Types ............................................................................................................ 5-2
S3F8S6B Interrupt Structure ............................................................................................................. 5-4
ROM Vector Address Area ............................................................................................................... 5-5
Interrupt Function Diagram ............................................................................................................... 5-9
System Mode Register (SYM) ........................................................................................................ 5-12
Interrupt Mask Register (IMR)......................................................................................................... 5-13
Interrupt Request Priority Groups ................................................................................................... 5-14
Interrupt Priority Register (IPR) ....................................................................................................... 5-15
Interrupt Request Register (IRQ) .................................................................................................... 5-16
System Flags Register (FLAGS)....................................................................................................... 6-5
Crystal/Ceramic Oscillator (fX) .......................................................................................................... 7-2
External Oscillator (fX) ...................................................................................................................... 7-2
RC Oscillator (fX) .............................................................................................................................. 7-2
Crystal Oscillator (fxt) ........................................................................................................................ 7-3
External Oscillator (fxt) ...................................................................................................................... 7-3
System Clock Circuit Diagram .......................................................................................................... 7-4
System Clock Control Register (CLKCON) ...................................................................................... 7-5
Oscillator Control Register (OSCCON) ............................................................................................. 7-6
STOP Control Register (STPCON) ................................................................................................... 7-7
S3F8S6B I/O Port Data Register Format .......................................................................................... 9-2
Port 0 High-Byte Control Register (P0CONH) .................................................................................. 9-3
Port 0 Low-Byte Control Register (P0CONL) ................................................................................... 9-4
Port 1 High-Byte Control Register (P1CONH) .................................................................................. 9-6
Port 1 Low-Byte Control Register (P1CONL) ................................................................................... 9-6
Port 1 Pull-up Resistor Enable Register (P1PUR) ............................................................................ 9-7
Port 1 N-Channel Open-drain Mode Register (PNE1) ...................................................................... 9-7
Port 2 High-Byte Control Register (P2CONH) .................................................................................. 9-9
Port 2 Low-Byte Control Register (P2CONL) ................................................................................... 9-9
Port 2 High-Byte Interrupt Control Register (P2INTH) .................................................................. 9-10
Port 2 Low-Byte Interrupt Control Register (P2INTL) ................................................................... 9-10
Port 2 Interrupt Pending Register (P2PND) .................................................................................. 9-11
Port 3 High-Byte Control Register (P3CONH) .............................................................................. 9-13
Port 3 Middle-Byte Control Register (P3CONM) .......................................................................... 9-13
Port 3 Low-Byte Control Register (P3CONL) ............................................................................... 9-14
Port 3 Pull-Up Resistor Enable Register (P3PUR) ....................................................................... 9-14
Port 3 N-Channel Open-Drain Mode Register (PNE3) ................................................................. 9-15
Port 4 High-Byte Control Register (P4CONH) .............................................................................. 9-17
Port 4 Low-Byte Control Register (P4CONL) ............................................................................... 9-17
Port 4 High-Byte Interrupt Control Register (P4INTH) .................................................................. 9-18
Port 4 Low-Byte Interrupt Control Register (P4INTL) ................................................................... 9-18
Port 4 Interrupt Pending Register (P4PND) .................................................................................. 9-19
Port 5 High-Byte Control Register (P5CONH) .............................................................................. 9-20
Port 5 Low-Byte Control Register (P5CONL) ............................................................................... 9-21
Port 6 High-Byte Control Register (P6CONH) .............................................................................. 9-23
Port 6 Low-Byte Control Register (P6CONL) ............................................................................... 9-23
Port 6 Pull-up Resistor Enable Register (P6PUR) ........................................................................ 9-24
Port 6 N-Channel Open-drain Mode Register (PNE6) .................................................................. 9-24
Basic Timer Control Register (BTCON) ........................................................................................ 10-2
Basic Timer Block Diagram ........................................................................................................... 10-4
Timer A Control Register (TACON) .............................................................................................. 11-2
Simplified Timer A Function Diagram: Interval Timer Mode ......................................................... 11-3
Simplified Timer A Function Diagram: PWM Mode ...................................................................... 11-4
Simplified Timer A Function Diagram: Capture Mode .................................................................. 11-5
Timer A Functional Block Diagram ............................................................................................... 11-6
Timer B Control Register .............................................................................................................. 11-7
PS032408-0220
PRELIMINARY
xiv
S3F8S6B Product Specification
Figure 11-7
Figure 11-8
Figure 12-1
Figure 12-2
Figure 13-1
Figure 13-2
Figure 13-3
Figure 13-4
Figure 13-5
Figure 13-6
Figure 13-7
Figure 13-8
Figure 13-9
Figure 13-10
Figure 14-1
Figure 14-2
Figure 15-1
Figure 15-2
Figure 15-3
Figure 15-4
Figure 15-5
Figure 15-6
Figure 15-7
Figure 15-8
Figure 15-9
Figure 15-10
Figure 15-11
Figure 15-12
Figure 15-13
Figure 15-14
Figure 16-1
Figure 16-2
Figure 16-3
Figure 16-4
Figure 17-1
Figure 17-2
Figure 17-3
Figure 17-4
Figure 17-5
Figure 18-1
Figure 18-2
Figure 18-3
Figure 18-4
Figure 18-5
Figure 18-6
Figure 18-7
Figure 18-8
Figure 18-9
Figure 18-10
Figure 19-1
Figure 19-2
Figure 19-3
Figure 19-4
Figure 19-5
Figure 19-6
PS032408-0220
List of Figures
Timer B Functional Block Diagram ............................................................................................... 11-8
Timer B Output Flip-Flop Waveforms in Repeat Mode ............................................................... 11-10
Timer C Control Register (TCCON) .............................................................................................. 12-2
Timer C Function Block Diagram .................................................................................................. 12-3
Timer D0 Control Register (TD0CON) .......................................................................................... 13-2
Simplified Timer D0 Function Diagram: Interval Timer Mode ....................................................... 13-3
Simplified Timer D0 Function Diagram: PWM Mode .................................................................... 13-4
Simplified Timer D0 Function Diagram: Capture Mode ................................................................ 13-5
Timer D0 Functional Block Diagram ............................................................................................. 13-6
Timer D1 Control Register (TD1CON) .......................................................................................... 13-8
Simplified Timer D1 Function Diagram: Interval Timer Mode ....................................................... 13-9
Simplified Timer D1 Function Diagram: PWM Mode .................................................................. 13-10
Simplified Timer D1 Function Diagram: Capture Mode .............................................................. 13-11
Timer D1 Functional Block Diagram ......................................................................................... 13-12
Watch Timer Control Register (WTCON) ..................................................................................... 14-2
Watch Timer Circuit Diagram ........................................................................................................ 14-3
LCD Function Diagram ................................................................................................................. 15-1
LCD Circuit Diagram ..................................................................................................................... 15-2
LCD Display Data RAM Organization ........................................................................................... 15-3
LCD Control Register (LCON) ...................................................................................................... 15-5
LCD Mode Control Register (LMOD) ............................................................................................ 15-6
Internal Resistor Bias Pin Connection .......................................................................................... 15-7
External Resistor Bias Pin Connection ......................................................................................... 15-8
Capacitor Bias Pin Connection ..................................................................................................... 15-9
Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode ...................................................... 15-11
Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode .................................................... 15-11
LCD Signal Waveforms (1/2 Duty, 1/2 Bias) ............................................................................. 15-12
LCD Signal Waveforms (1/3 Duty, 1/3 Bias) ........................................................................... 15-13
LCD Signal Waveforms (1/4 Duty, 1/3 Bias) ............................................................................. 15-14
LCD Signal Waveforms (1/8 Duty, 1/4 Bias) ............................................................................. 15-16
A/D Converter Control Register (ADCON) .................................................................................... 16-3
A/D Converter Data Register (ADDATAH/L) ................................................................................ 16-4
A/D Converter Functional Block Diagram ..................................................................................... 16-5
Recommended A/D Converter Circuit for Highest Absolute Accuracy ......................................... 16-6
Serial I/O Module Control Registers (SIOCON)............................................................................ 17-2
SIO Pre-scaler Register (SIOPS).................................................................................................. 17-3
SIO Functional Block Diagram ...................................................................................................... 17-4
Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) ................................. 17-5
Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) .................................. 17-5
UART 0 High Byte Control Register (UART0CONH) ................................................................... 18-3
UART 0 Low Byte Control Register (UART0CONL) ..................................................................... 18-4
UART 0 Data Register (UDATA0)................................................................................................. 18-5
UART 0 Baud Rate Data Register (BRDATA0) ............................................................................ 18-5
UART 0 Functional Block Diagram ............................................................................................... 18-7
Timing Diagram for Serial Port Mode 0 Operation........................................................................ 18-8
Timing Diagram for Serial Port Mode 1 Operation...................................................................... 18-10
Timing Diagram for Serial Port Mode 2 Operation...................................................................... 18-12
Timing Diagram for Serial Port Mode 3 Operation...................................................................... 18-14
Connection Example for Multiprocessor Serial Data Communications .................................... 18-16
UART 1 High Byte Control Register (UART1CONH) ................................................................... 19-3
UART 1 Low Byte Control Register (UART1CONL) ..................................................................... 19-4
UART 1 Data Register (UDATA1)................................................................................................. 19-5
UART 1 Baud Rate Data Register (BRDATA1) ............................................................................ 19-5
UART 1 Functional Block Diagram ............................................................................................... 19-7
Timing Diagram for Serial Port Mode 0 Operation........................................................................ 19-8
PRELIMINARY
xv
S3F8S6B Product Specification
Figure 19-7
Figure 19-8
Figure 19-9
Figure 19-10
Figure 20-1
Figure 20-2
Figure 20-3
Figure 21-1
Figure 21-2
Figure 21-3
Figure 21-4
Figure 21-5
Figure 21-6
Figure 22-1
Figure 22-2
Figure 22-3
Figure 22-4
Figure 22-5
Figure 22-6
Figure 22-7
Figure 22-8
Figure 22-9
Figure 22-10
Figure 22-11
Figure 23-1
Figure 23-2
Figure 23-3
Figure 24-1
Figure 24-2
Figure 24-3
Figure 24-4
Figure 24-5
Figure 25-1
Figure 25-2
Figure 25-3
Figure 25-4
PS032408-0220
List of Figures
Timing Diagram for Serial Port Mode 1 Operation...................................................................... 19-10
Timing Diagram for Serial Port Mode 2 Operation...................................................................... 19-12
Timing Diagram for Serial Port Mode 3 Operation...................................................................... 19-14
Connection Example for Multiprocessor Serial Data Communications .................................... 19-16
Pattern Generation Flow ............................................................................................................... 20-1
Pattern Generation Control Register (PGCON) ............................................................................ 20-2
Pattern Generation Circuit Diagram .............................................................................................. 20-2
Flash Memory Control Register (FMCON) ................................................................................... 21-3
Flash Memory User Programming Enable Register (FMUSR) ..................................................... 21-4
Flash Memory Sector Address Register High Byte (FMSECH) .................................................... 21-5
Flash Memory Sector Address Register Low Byte (FMSECL) ..................................................... 21-5
Program Memory Address Space ................................................................................................. 21-6
Sector Configurations in User Program Mode .............................................................................. 21-8
Input Timing for External Interrupts .............................................................................................. 22-6
Input Timing for nRESET .............................................................................................................. 22-6
Stop Mode Release Timing Initiated by nRESET ......................................................................... 22-8
Stop Mode Release Timing Initiated by Interrupts ........................................................................ 22-8
LVR (Low Voltage Reset) Timing ............................................................................................... 22-10
Serial Data Transfer Timing ........................................................................................................ 22-11
Waveform for UART Timing Characteristics ............................................................................... 22-12
Timing Waveform for the UART Module ..................................................................................... 22-13
Clock Timing Measurement at XIN .............................................................................................. 22-17
Clock Timing Measurement at XTIN .......................................................................................... 22-18
Operating Voltage Range ......................................................................................................... 22-19
Package Dimensions (64-QFP-1420F) ......................................................................................... 23-1
Package Dimensions (64-LQFP-1010) ......................................................................................... 23-2
Package Dimensions (64-SDIP-750) ............................................................................................ 23-3
S3F8S6B Pin Assignments (64-QFP-1420F) ............................................................................... 24-1
S3F8S6B Pin Assignments (64-LQFP-1010) ............................................................................... 24-2
S3F8S6B Pin Assignments (64-SDIP-750) .................................................................................. 24-3
RC Delay Circuit ........................................................................................................................... 24-4
PCB Design Guide for on Board Programming ............................................................................ 24-5
Emulator Product Configuration .................................................................................................... 25-2
TB8S6B Target Board Configuration ............................................................................................ 25-3
40-Pin Connectors (J101, J102) for TB8S6B ............................................................................... 25-5
S3E8S60 Cables for 64-QFP Package ......................................................................................... 25-6
PRELIMINARY
xvi
S3F8S6B Product Specification
List of Tables
List of Tables
Table
Number
Title
Page
Number
Table 1.1
S3F8S6B Pin Descriptions ............................................................................................................... 1-10
Table 2.1
S3F8S6B Register Type Summary .................................................................................................... 2-5
Table 4.1
Set 1 Registers ................................................................................................................................... 4-1
Table 4.2
Set 1, Bank 0 Registers ...................................................................................................................... 4-2
Table 4.3
Set 1, Bank 1 Registers ...................................................................................................................... 4-3
Table 4.4
Page 8 Registers ................................................................................................................................ 4-4
Table 5.1
Interrupt Vectors ................................................................................................................................. 5-6
Table 5.2
Interrupt Control Register Overview ................................................................................................... 5-8
Table 5.3
Interrupt Source Control and Data Registers ................................................................................... 5-10
Table 6.1
Instruction Group Summary ............................................................................................................... 6-2
Table 6.2
Flag Notation Conventions ................................................................................................................. 6-7
Table 6.3
Instruction Set Symbols ...................................................................................................................... 6-7
Table 6.4
Instruction Notation Conventions ....................................................................................................... 6-8
Table 6.5
Opcode Quick Reference ................................................................................................................... 6-9
Table 6.6
Condition Codes ............................................................................................................................... 6-11
Table 8.1
S3F8S6B Set 1 Register and Values After RESET ........................................................................... 8-2
Table 8.2
S3F8S6B Set 1, Bank 0 Register and Values after RESET .............................................................. 8-3
Table 8.3
S3F8S6B Set 1, Bank 1 Register and Values after RESET .............................................................. 8-4
Table 8.4
S3F8S6B Page 8 Register and Values After RESET ........................................................................ 8-6
Table 9.1
S3F8S6B Port Configuration Overview .............................................................................................. 9-1
Table 9.2
Port Data Register Summary ............................................................................................................. 9-2
Table 15.1. LCD Frame Rate ................................................................................................................................ 15-4
Table 18.1
Commonly Used Baud Rates Generated by BRDATA0 ................................................................ 18-6
Table 19.1
Commonly Used Baud Rates Generated by BRDATA1 ................................................................ 19-6
Table 21.1
ISP Sector Size .............................................................................................................................. 21-7
Table 21.2
Reset Vector Address .................................................................................................................... 21-7
Table 22.1
Absolute Maximum Ratings ............................................................................................................ 22-2
Table 22.2
D.C. Electrical Characteristics ........................................................................................................ 22-3
Table 22.3
A.C. Electrical Characteristics ........................................................................................................ 22-6
Table 22.4
Input/Output Capacitance ............................................................................................................... 22-7
Table 22.5
Data Retention Supply Voltage in Stop Mode ................................................................................ 22-7
Table 22.6
A/D Converter Electrical Characteristics ........................................................................................ 22-9
Table 22.7
Low Voltage Reset Electrical Characteristics............................................................................... 22-10
Table 22.8
Synchronous SIO Electrical Characteristics ................................................................................. 22-11
Table 22.9
UART Timing Characteristics in Mode 0 (12.0 MHz) ................................................................... 22-12
Table 22.10
LCD Capacitor Bias Electrical Characteristics (Normal and Idle Mode) .................................... 22-14
Table 22.11
Main Oscillator Characteristics ................................................................................................... 22-15
Table 22.12
Sub Oscillation Characteristics................................................................................................... 22-16
Table 22.13
Main Oscillation Stabilization Time ............................................................................................ 22-17
Table 22.14
Sub Oscillation Stabilization Time .............................................................................................. 22-18
Table 22.15
Internal Flash ROM Electrical Characteristics ............................................................................ 22-20
Table 24.1
Descriptions of Pins Used to Read/Write the Flash ROM .............................................................. 24-4
Table 24.2
Reference Table for Connection .................................................................................................... 24-6
Table 25.1
Components of TB8S6B ................................................................................................................. 25-4
PS032408-0220
PRELIMINARY
xvii
S3F8S6B Product Specification
Table 25.2
List of Tables
Setting of the Jumper in TB8S6B ................................................................................................... 25-4
PS032408-0220
PRELIMINARY
xviii
S3F8S6B Product Specification
List of Examples
List of Examples
Example
Number
Example 2-1
Example 2-2
Example 2-3
Example 2-4
Example 2-5
Example 5-1
Example 5-2
Example 7-1
Example 7-2
Example 11-1
Example 11-2
Example 15-1
Example 20-1
Example 21-1
Example 21-2
Example 21-3
Example 21-4
PS032408-0220
Title
Page
Number
Using the Page Pointer for RAM clear (Page 0, Page 1) .............................................................. 2-8
Setting the Register Pointers ...................................................................................................... 2-12
Using the RPs to Calculate the Sum of a Series of Registers .................................................... 2-13
Addressing the Common Working Register Area ....................................................................... 2-17
Standard Stack Operations Using PUSH and POP .................................................................... 2-22
How to Prevent the Unexpected External Interrupts ................................................................. 5-11
How to Clear an Interrupt Pending Bit ........................................................................................ 5-17
How to Use Stop Instruction.......................................................................................................... 7-7
Switching the CPU clock ............................................................................................................... 7-8
To Generate 38 kHz, 1/3 Duty Signal Through P3.0 .............................................................. 11-11
To Generate a One Pulse Signal Through P3.0 ..................................................................... 11-12
LCD Display on, After Capacitor Bias Selected ...................................................................... 15-17
Using the Pattern Generation.................................................................................................... 20-3
Sector Erase ............................................................................................................................. 21-9
Programming ........................................................................................................................... 21-11
Reading ................................................................................................................................... 21-12
Hard Lock Protection ............................................................................................................... 21-14
PRELIMINARY
xix
S3F8S6B Product Specification
1
Chapter 1. Product Overview
Product Overview
1.1 S3C8-Series Microcontrollers
Zilog's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of
integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:
•
Efficient register-oriented architecture
•
Selectable CPU clock sources
•
Idle and Stop power-down mode release by interrupts
•
Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to
specific interrupt levels.
1.2 S3F8S6B Microcontroller
The S3F8S6B single-chip CMOS microcontrollers are fabricated using the highly advanced CMOS process, based
on Zilog's newest CPU architecture.
The S3F8S6B is a microcontroller with a 64KB Flash ROM embedded respectively.
Using a proven modular design approach, Zilog engineers have successfully developed the
S3F8S6B by integrating the following peripheral modules with the powerful SAM8 core:
•
Seven programmable I/O ports, including six 8-bit ports, and one 6-bit port, for a total of 54 pins
•
Sixteen bit-programmable pins for external interrupts
•
One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset)
•
Three 8-bit timer/counter and two 16-bit timer/counter with selectable operating modes
•
Watch timer for real time
•
LCD Controller/driver
•
A/D converter with 8 selectable input pins
•
Synchronous SIO modules
•
Two asynchronous UART modules
•
Pattern generation module
They are currently available in 64-pin QFP and 64-pin SDIP package
PS032408-0220
PRELIMINARY
1-1
S3F8S6B Product Specification
Chapter 1. Product Overview
1.3 Features
CPU
•
SAM88 RC CPU core
Memory
•
•
Program Memory (ROM)
−
64K 8 bits program memory
−
Internal Flash memory (program memory)
o Sector size: 128 bytes
o
10 years data retention
o
Fast programming time
o
User program and sector erase available
o
Endurance: 10,000 erase/program cycles
o
External serial programming support
o
Expandable OBPTM (on board program) sector
Data Memory (RAM)
−
Including LCD display data memory
−
2,098 8 bits data memory
Instruction Set
•
78 instructions
•
Idle and stop instructions added for power-down modes
54 I/O Pins
•
I/O: 18 pins (Sharing with other signal pins)
•
I/O: 36 pins (Sharing with LCD signal outputs)
Interrupts
•
8 interrupt levels and 30 interrupt sources
•
Fast interrupt processing feature
8-Bit Basic Timer
•
Watchdog timer function
•
4 kinds of clock source
PS032408-0220
PRELIMINARY
1-2
S3F8S6B Product Specification
Chapter 1. Product Overview
8-Bit Timer/Counter A
•
Programmable 8-bit internal timer
•
External event counter function
•
PWM and capture function
8-Bit Timer/Counter B
•
Programmable 8-bit internal timer
•
Carrier frequency generator
Two 8-Bit Timer/Counter C
•
Programmable 8-bit internal timer
•
PWM function
Two 16-Bit Timer/Counter (D0/D1)
•
Programmable 16-bit internal timer
•
External event counter function
•
PWM and capture function
Watch Timer
•
Interval time: 1.995 mS, 0.125S, 0.25S, and 0.5S at 32.768 kHz
•
0.5/1/2/4 kHz Selectable buzzer output
LCD Controller/Driver
•
28 segments and 8 common terminals
•
1/2, 1/3, 1/4, and 1/8 duty selectable
•
Capacitor or resistor bias selectable
•
Regulator and booster circuit for LCD bias
Analog to Digital Converter
•
8-channel analog input
•
10-bit conversion resolution
•
25 s conversion time
Two Channels UART
•
Full-duplex serial I/O interface
•
Four programmable operating modes
•
Auto generating parity bit
PS032408-0220
PRELIMINARY
1-3
S3F8S6B Product Specification
Chapter 1. Product Overview
8-bit Serial I/O Interface
•
8-bit transmit/receive mode
•
8-bit receive mode
•
LSB-first or MSB-first transmission selectable
•
Internal or external clock source
Pattern Generation Module
•
Pattern generation module triggered by timer match signal and software
Low Voltage Reset (LVR)
•
Criteria voltage: 1.9 V,2.2 V
•
En/Disable by smart option (ROM address: 3FH)
Two Power-Down Modes
•
Idle: only CPU clock stops
•
Stop: selected system clock and CPU clock stop
Oscillation Sources
•
Crystal, ceramic, or RC for main clock
•
Main clock frequency: 0.4 MHz to 12.0 MHz
•
32.768 kHz crystal oscillation circuit for sub clock
Instruction Execution Times
•
333 ns at 12.0 MHz fx (Minimum)
•
122.1 s at 32.768 kHz fxt (Minimum)
Operating Voltage Range
•
1.8 V to 5.5 V at 0.4 to 4.2 MHz
•
2.2 V to 5.5 V at 0.4 to 12.0 MHz
Operating Temperature Range
•
– 40 C to + 85 C
Package Type
•
64-QFP-1420F, 64-LQFP-1010, 64-SDIP-750
PS032408-0220
PRELIMINARY
1-4
S3F8S6B Product Specification
Chapter 1. Product Overview
IVC
•
Internal Voltage Converter for 5 V operations
Smart Option
•
Low Voltage Reset (LVR) level and enable/disable are at your hardwired option (ROM address 3FH)
•
ISP related option selectable (ROM address 3EH)
PS032408-0220
PRELIMINARY
1-5
S3F8S6B Product Specification
Chapter 1. Product Overview
1.4 Block Diagram
XIN
Low Voltage
Reset
P5.7/
XTIN
XOUT
Main OSC
P5.6/
XTOUT
Sub OSC
Watch-dog
Timer
P0.0-P0.1/COM0-COM1
P0.2-P0.7/COM2-COM7
SEG0-SEG5
P1.2-P1.7/SEG6-SEG11
P2.0-P2.7/SEG12-SEG19
P3.0-P3.7/SEG20-SEG27
P6.0-P6.5/SEG28-SEG33
Basic Timer
LCD Driver/
Controller
P5.4/CA
P5.5/CB
P5.0-P5.3/VLC0-VLC3
Regulator
and
Booster
P1.7/TACLK
P1.6/TACAP
P1.6/TAOUT/TAPWM
8-bit Timer/
Counter A
P3.0/TBPWM
8-bit Timer/
Counter B
P3.1/TCOUT/TCPWM
8-bit Timer/
Counter C
P3.4/TD0CLK
P3.3/TD0CAP
P3.3/TD0OUT/TD0PWM
16-bit Timer/
Counter D0
P3.6/TD1CLK
P3.5/TD1CAP
P3.5/TD1OUT/TD1PWM
16-bit Timer/
Counter D1
P6.0/SCK
P6.1/SI
P6.2/SO
SEG20-SEG27/
PG0-PG7
SIO
I/O Port and Interrupt
Control
SAM88 RC
Core
64-Kbyte
ROM
TEST
nRESET IVCREF
Pattern
Generation
VDD
AVREF
Figure 1-1
PS032408-0220
2,098-byte
RAM
VSS1
VSS2
AVSS
Watch Timer
BUZ/P3.7
I/O Port 0
P0.0-P0.7
I/O Port 1
P1.0-P1.7
I/O Port 2
P2.0-P2.7
I/O Port 3
P3.0-P3.7
I/O Port 4
P4.0-P4.7
I/O Port 5
P5.0-P5.7
I/O Port 6
P6.0-P6.5
UART0
TXD0/P1.3
RXD0/P1.2
UART1
TXD1/P1.5
RXD1/P1.4
10-bit ADC
P4.0-P4.7/
AD0-AD7
INTERRUPT
P2.0-P2.7/
INT0-INT7
P4.0-P4.7/
INT8-INT15
Block Diagram
PRELIMINARY
1-6
S3F8S6B Product Specification
Chapter 1. Product Overview
1.5 Pin Assignment
P2.5/INT5/SEG17
P2.4/INT4/SEG16
P2.3/INT3/SEG15
P2.2/INT2/SEG14
P2.1/INT1/SEG13
P2.0/INT0/SEG12
P1.7/TACLK/SEG11
P1.6/TAOUT/TAPWM/TACAP/SEG10
P1.5/TXD1/SEG9
P1.4/RXD1/SEG8
P1.3/TXD0/SEG7
P1.2/RXD0/SEG6
P1.1
P1.0
AVSS
AVREF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P4.7/INT15/AD7
P4.6/INT14/AD6
P4.5/INT13/AD5
P4.4/INT12/AD4
P4.3/INT11/AD3
P4.2/INT10/AD2
P4.1/INT9/AD1
P4.0/INT8/AD0
VDD
VSS1
XOUT
XIN
TEST
P5.7/XTIN
P5.6/XTOUT
nRESET
1
2
3
4
5
6
7 (SDAT)
8 (SCLK)
9
10
11
12
13
14
15
16
S3F8S6B
64-LQFP-1010
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P2.6/INT6/SEG18
P2.7/INT7/SEG19
P3.0/PG0/TBPWM/SEG20
P3.1/PG1/TCOUT/TCPWM/SEG21
P3.2/PG2/SEG22
P3.3/PG3/TD0OUT/TD0PWM/TD0CAP/SEG23
IVCREF
VSS2
P3.4/PG4/TD0CLK/SEG24
P3.5/PG5/TD1OUT/TD1PWM/TD1CAP/SEG25
P3.6/PG6/TD1CLK/SEG26
P3.7/PG7/BUZ/SEG27
P6.0/SCK/SEG28
P6.1/SI/SEG29
P6.2/SO/SEG30
P6.3/SEG31
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P6.4/SEG32
P6.5/SEG33
P0.0/COM0
P0.1/COM1
P0.2/COM2/SEG0
P0.3/COM3/SEG1
P0.4/COM4/SEG2
P0.5/COM5/SEG3
P0.6/COM6/SEG4
P0.7/COM7/SEG5
P5.0/VLC0
P5.1/VLC1
P5.2/VLC2
P5.3/VLC3
P5.4/CA
P5.5/CB
Figure 1-2
PS032408-0220
S3F8S6B Pin Assignments (64-LQFP-1010)
PRELIMINARY
1-7
S3F8S6B Product Specification
Chapter 1. Product Overview
P2.2/INT2/SEG14
P2.1/INT1/SEG13
P2.0/INT0/SEG12
P1.7/TACLK/SEG11
P1.6/TAOUT/TAPWM/TACAP/SEG10
P1.5/TXD1/SEG9
P1.4/RXD1/SEG8
P1.3/TXD0/SEG7
P1.2/RXD0/SEG6
P1.1
P1.0
AVSS
AVREF
52
53
54
55
56
57
58
59
60
61
62
63
64
P4.7/INT15/AD7
P4.6/INT14/AD6
P4.5/INT13/AD5
P4.4/INT12/AD4
P4.3/INT11/AD3
P4.2/INT10/AD2
P4.1/INT9/AD1
P4.0/INT8/AD0
VDD
VSS1
XOUT
XIN
TEST
P5.7/XTIN
P5.6/XTOUT
nRESET
P5.5/CB
P5.4/CA
P5.3/VLC3
1
2
3
4
5
6
7 (SDAT)
8 (SCLK)
9
10
(64-QFP-1420F)
11
12
13
14
15
16
17
18
19
S3F8S6B
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG15/INT3/P2.3
SEG16/INT4/P2.4
SEG17/INT5/P2.5
SEG18/INT6/P2.6
SEG19/INT7/P2.7
SEG20/TBPWM/PG0/P3.0
SEG21/TCOUT/TCPWM/PG1/P3.1
SEG22/PG2/P3.2
SEG23/TD0OUT/TD0PWM/TD0CAP/PG3/P3.3
IVCREF
VSS2
SEG24/TD0CLK/PG4/P3.4
SEG25/TD1OUT/TD1PWM/TD1CAP/PG5/P3.5
SEG26/TD1CLK/PG6/P3.6
SEG27/BUZ/PG7/P3.7
SEG28/SCK/P6.0
SEG29/SI/P6.1
SEG30/SO/P6.2
SEG31/P6.3
32
31
30
29
28
27
26
25
24
23
22
21
20
SEG32/P6.4
SEG33/P6.5
COM0/P0.0
COM1/P0.1
COM2/SEG0/P0.2
COM3/SEG1/P0.3
COM4/SEG2/P0.4
COM5/SEG3/P0.5
COM6/SEG4/P0.6
COM7/SEG5/P0.7
VLC0/P5.0
VLC1/P5.1
VLC2/P5.2
Figure 1-3
PS032408-0220
S3F8S6B Pin Assignments (64-QFP-1420F)
PRELIMINARY
1-8
S3F8S6B Product Specification
P1.4/RXD1/SEG8
P1.3/TXD0/SEG7
P1.2/RXD0/SEG6
P1.1
P1.0
AVSS
AVREF
P4.7/INT15/AD7
P4.6/INT14/AD6
P4.5/INT13/AD5
P4.4/INT12/AD4
P4.3/INT11/AD3
P4.2/INT10/AD2
P4.1/INT9/AD1
P4.0/INT8/AD0
VDD
VSS1
XOUT
XIN
TEST
P5.7/XTIN
P5.6/XTOUT
nRESET
P5.5/CB
P5.4/CA
P5.3/VLC3
P5.2/VLC2
P5.1/VLC1
P5.0/VLC0
P0.7/SEG5/COM7
P0.6/SEG4/COM6
P0.5/SEG3/COM5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Figure 1-4
PS032408-0220
S3F8S6B
(64-SDIP-750)
Chapter 1. Product Overview
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
38
38
37
36
35
34
33
SEG9/TXD1/P1.5
SEG10/TAOUT/TAPWM/TACAP/P1.6
SEG11/TACLK/P1.7
SEG12/INT0/P2.0
SEG13/INT1/P2.1
SEG14/INT2/P2.2
SEG15/INT3/P2.3
SEG16/INT4/P2.4
SEG17/INT5/P2.5
SEG18/INT6/P2.6
SEG19/INT7/P2.7
SEG20/TBPWM/PG0/P3.0
SEG21/TCOUT/TCPWM/PG1/P3.1
SEG22/PG2/P3.2
SEG23/TD0OUT/TD0PWM/TD0CAP/PG3/P3.3
IVCREF
VSS2
SEG24/TD0CLK/PG4/P3.4
SEG25/TD1OUT/TD1PWM/TD1CAP/PG5/P3.5
SEG26/TD1CLK/PG6/P3.6
SEG27/BUZ/PG7/P3.7
SEG28/SCK/P6.0
SEG29/SI/P6.1
SEG30/SO/P6.2
SEG31/P6.3
SEG32P6.4
SEG33/P6.5
COM0/P0.0
COM1/P0.1
COM2/SEG0/P0.2
COM3/SEG1/P0.3
COM4/SEG2/P0.4
S3F8S6B Pin Assignments (64-SDIP-750)
PRELIMINARY
1-9
S3F8S6B Product Specification
Chapter 1. Product Overview
1.6 Pin Descriptions
Table 1.1
Pin
Names
P0.0
P0.1
P0.2−P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
Pin
Type
I/O
I/O
S3F8S6B Pin Descriptions
Pin Description
I/O port with bit-programmable pins;
Input or push-pull output and software
assignable pull-ups.
I/O port with bit-programmable pins;
Input or push-pull, open-drain output and
software assignable pull-ups.
Circuit
Type
Pin
Numbers (NOTE)
Share Pins
H-44
30(37)
29(36)
28−23
(35−30)
COM0
COM1
COM2−COM7/
SEG0−SEG5
H-42
P1.7
62(5)
61(4)
60(3)
59(2)Pin
58(1)
57(64)
56(63)
55(62)
P2.0−P2.7
I/O
I/O port with bit-programmable pins;
Schmitt trigger input or push-pull output
and software assignable pull-ups.
Alternately used for external interrupt
input (noise filters, interrupt enable and
pending control).
H-43
54−47
(61−54)
P3.0
46(53)
P3.1
45(52)
P3.2
P3.3
44(51)
43(50)
P3.4
I/O
I/O port with bit-programmable pins;
Input or push-pull, open-drain output and
software assignable pull-ups.
H-42
40(47)
P3.5
39(46)
P3.6
38(45)
P3.7
37(44)
P4.0−P4.7
I/O
The P4.2-P4.7 are the I/O port with bitprogrammable pins, but the P4.0/P4.1 are
the I/O port with two-bits-programmable
pins
Schmitt trigger input or push-pull output
and software assignable pull-ups.
P5.0−P5.3
I/O
I/O port with bit-programmable pins;
Input or push-pull output and software
PS032408-0220
PRELIMINARY
−
−
RxD0/SEG6
TxD0/SEG7
RxD1/SEG8
TxD1/SEG9
TAOUT/TAPW
M/TACAP/SEG
10
TACLK/SEG11
INT0−INT7/
SEG12−SEG19
TBPWM/PG0/
SEG20
TCOUT/TCPW
M/PG1/SEG21
PG2/SEG22
TD0OUT/
TD0PWM/
TD0CAP/
PG3/SEG23
TD0CLK/PG4/
SEG24
TD1OUT/
TD1PWM/
TD1CAP/
PG5/SEG25
TD1CLK/PG6/
SEG26
BUZ/PG7/
SEG27
F-16
8−1
(15−8)
AD0−AD7/
INT8−INT15
F-17
22−19
(29−26)
VLC0−VLC3
1-10
S3F8S6B Product Specification
Pin
Names
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3−P6.5
Pin
Type
Pin Description
Chapter 1. Product Overview
Circuit
Type
assignable pull-ups.
I/O
I/O port with bit-programmable pins;
Input or push-pull output and software
assignable pull-ups.
I/O
I/O port with bit-programmable pins;
Input or push-pull, open-drain output and
software assignable pull-ups.
XTOUT
XTIN
H-42
36(43)
35(42)
34(41)
33−31
(40−38)
SCK/SEG28
SI/SEG29
SO/SEG30
SEG31−SEG33
P0.2−P0.7/
SEG0−SEG5
P0.2−P0.7/
COM2−COM7
I/O
LCD common signal output.
H-44
30−29
(37−36)
28−23
(35−30)
I/O
LCD segment signal output.
H-44
28−23
(35−30)
I/O
LCD segment signal output.
H-42
SEG11
SEG12−S
EG19
60(3)
59(2)
58(1)
57(64)
56(63)
55(62)
I/O
LCD segment signal output.
H-43
54−47
(61−54)
SEG20
46(53)
SEG21
45(52)
SEG22
SEG23
44(51)
43(50)
I/O
LCD segment signal output.
H-42
SEG24
SEG25
40(47)
39(46)
SEG26
SEG27
38(45)
37(44)
SEG28
SEG29
PS032408-0220
I/O
LCD segment signal output.
PRELIMINARY
CA
CB
15(22)
14(21)
COM2−C
OM7
SEG6
SEG7
SEG8
SEG9
SEG10
Share Pins
D-2
COM0−C
OM1
SEG0–
SEG5
Pin
Numbers (NOTE)
18(25)
17(24)
H-42
36(43)
35(42)
P0.0−P0.1
P1.2/RxD0
P1.3/TxD0
P1.4/RxD1
P1.5/TxD1
P1.6/TAOUT/
TAPWM/TACA
P
P1.7/TACLK
P2.0−P2.7/
INT0−INT7
P3.0/ PG0/
TBPWM
P3.1/PG1/
TCOUT/TCPW
M
P3.2/PG2
P3.3/PG3/
TD0OUT/
TD0PWM/
TD0CAP
P3.4/PG4/TD0
CLK
P3.5/PG5/
TD1OUT/
TD1PWM/
TD1CAP
P3.6/PG6/TD1
CLK
P3.7/PG7/BUZ
P6.0/SCK
P6.1/SI
1-11
S3F8S6B Product Specification
Pin
Names
SEG30
SEG31−S
EG33
Pin
Type
Pin Description
Chapter 1. Product Overview
Circuit
Type
Pin
Numbers (NOTE)
34(41)
33−31
(40−38)
Share Pins
P6.2/SO
P6.3−P6.5
VLC0−
VLC3
I/O
LCD power supply pins.
F-17
22−19
(29−26)
P5.0−P5.3
CA
CB
I/O
Capacitor terminal for voltage booster.
F-17
18(25)
17(24)
P5.4
P5.5
AD0−AD7
I/O
A/D converter analog input channels.
F-16
8–1
(15–8)
P4.0−P4.7/
INT8−INT15
AVREF
−
A/D converter reference voltage.
−
64(7)
−
AVSS
−
A/D converter ground.
−
63(6)
−
P3.0−P3.3/
SEG20−SEG23
P3.4−P3.7/
SEG24−SEG27
I/O
Pattern generation output.
H-42
46−43
(53−50)
40−37
(47−44)
TxD0
RxD0
I/O
UART 0 data output, input.
H-42
59(2)
60(3)
P1.3/SEG7
P1.2/SEG6
TxD1
RxD1
I/O
UART 1 data output, input.
H-42
57(64)
58(1)
P1.5/SEG9
P1.4/SEG8
TAOUT/
TAPWM
I/O
Timer A clock output and PWM output.
H-42
56(63)
P1.6/SEG10/
TACAP
TACAP
I/O
Timer A capture input.
H-42
56(63)
P1.6/SEG10/
TAOUT/TAPW
M
TACLK
I/O
Timer A external clock input.
H-42
55(62)
P1.7/SEG11
TBPWM
I/O
Timer B carrier frequency output.
H-42
46(53)
P3.0/SEG20/
PG0
TCOUT/
TCPWM
I/O
Timer C clock output and PWM output.
H-42
45(52)
P3.1/SEG21/
PG1
TD0OUT/
TD0PWM
I/O
Timer D0 clock output and PWM output.
H-42
43(50)
P3.3/SEG23/
PG3/TD0CAP
TD0CAP
I/O
Timer D0 capture input.
H-42
43(50)
P3.3/SEG23/
PG3/TD0OUT/
TD0PWM
TD0CLK
I/O
Timer D0 external clock input.
H-42
40(47)
P3.4/SEG24/
PG4
TD1OUT/
TD1PWM
I/O
Timer D1 clock output and PWM output.
H-42
39(46)
P3.5/SEG25/
PG5/TD1CAP
TD1CAP
I/O
Timer D1 capture input.
H-42
39(46)
P3.5/SEG25/
PG5/TD1OUT/
TD1PWM
TD1CLK
I/O
Timer D1 external clock input.
H-42
38(45)
P3.6/SEG26/
PG6
PG0−PG3
PG4−PG7
PS032408-0220
PRELIMINARY
1-12
S3F8S6B Product Specification
Pin
Names
Pin
Type
Pin Description
Chapter 1. Product Overview
Circuit
Type
Pin
Numbers (NOTE)
Share Pins
BUZ
I/O
Output pin for buzzer signal.
H-42
37(44)
P3.7/SEG27/
PG7
SCK
I/O
Serial interface clock.
H-42
36(43)
P6.0/SEG28
SI
I/O
Serial interface data input.
H-42
35(42)
P6.1/SEG29
SO
I/O
Serial interface data output.
H-42
34(41)
P6.2/SEG30
I/O
External interrupts input pins.
H-43
54−47
(61−54)
P2.0−P2.7/
SEG12−SEG19
I/O
External interrupts input pins.
F-16
1−8
(8−15)
P4.0−P4.7/
AD0−AD7
INT0−INT7
INT8−INT1
5
nRESET
I
System reset pin
B
16(23)
−
XIN
XOUT
−
Main oscillator pins.
−
12(19)
11(18)
−
XTIN
XTOUT
−
Crystal oscillator pins for sub clock.
−
14(21)
15(22)
P5.7
P5.6
TEST
I
Test input: it must be connected to VSS
−
13(20)
−
VDD
−
Power supply input pins.
−
9(16)
−
VSS1
VSS2
−
Ground pins.
−
10(17)
41(48)
−
IVCREF
−
Internal voltage controller reference input
pin. A capacitor (0.1uF) must be
connected between IVCREF and VSS.
−
42(49)
−
NOTE: Parentheses indicate pin number for 64-SDIP-750 package.
PS032408-0220
PRELIMINARY
1-13
S3F8S6B Product Specification
Chapter 1. Product Overview
1.7 Pin Circuits
VDD
Pull-up
Resistor
In
Schmitt Trigger
Figure 1-5
PS032408-0220
Pin Circuit Type B
PRELIMINARY
1-14
S3F8S6B Product Specification
Chapter 1. Product Overview
VDD
P-Channel
Data
Out
N-Channel
Output
Disable
Figure 1-6
Pin Circuit Type C
VDD
Pull-up
Resistor
Pull-up
Enable
Data
Output
Disable
Pin Circuit
Type C
I/O
Data
XTI
XTO
Figure 1-7
PS032408-0220
Pin Circuit Type D-2 (P5.6 – P5.7)
PRELIMINARY
1-15
S3F8S6B Product Specification
Chapter 1. Product Overview
VDD
Pull-up
Enable
Data
Output
Disable
Circuit
Type C
I/O
ADCEN
ADC Select
Data
To ADC
Figure 1-8
Pin Circuit Type F-16 (P4)
VDD
Pull-up
Enable
Data
Output
Disable
Circuit
Type C
I/O
VLC/CA/CB
Select
Data
To LCD
Block
Figure 1-9
PS032408-0220
Pin Circuit Type F-17 (P5.0 - P5.5)
PRELIMINARY
1-16
S3F8S6B Product Specification
Chapter 1. Product Overview
VLC0
VLC1/2
COM/SEG
Out
Output
Disable
VLC2/3
Figure 1-10
Pin Circuit Type H-39
VDD
Pull-up
Resistor
Resistor
Enable
COM/SEG
Circuit
Type H-39
Output
Disable
I/O
Data
Figure 1-11
PS032408-0220
Pin Circuit Type H-43 (P2)
PRELIMINARY
1-17
S3F8S6B Product Specification
Chapter 1. Product Overview
VDD
Pull-up
Resistor
Resistor
Enable
COM/SEG
Circuit
Type H-39
Output
Disable
I/O
Data
Figure 1-12
Pin Circuit Type H-44 (P0)
VDD
VDD
Pull-up
Resistor
Resistor
Enable
Open-drain
P-CH
Data
I/O
N-CH
Output
Disable1
COM/SEG
Circuit
Type H-39
Output
Disable2
Data
Figure 1-13
PS032408-0220
Pin Circuit Type H-42 (P1, P3, P6)
PRELIMINARY
1-18
S3F8S6B Product Specification
2
Chapter 2. Address Spaces
Address Spaces
2.1 Overview
The S3F8S6B microcontroller has two types of address space:
•
Internal program memory (ROM)
•
Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The S3F8S6B has an internal 64KB Flash ROM.
The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes.
A 34 byte LCD display register file is implemented.
PS032408-0220
PRELIMINARY
2-1
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.2 Program Memory (ROM)
Program memory (ROM) stores program codes or table data. The S3F8S6B has 64KB internal Flash program
memory.
The first 256 bytes of the ROM (0H−0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you use the vector address area to store a program
code, be careful not to overwrite the vector addresses stored in these locations.
The ROM address at which a program execution starts after a reset is 0100H in the S3F8S6B.
The reset address of ROM can be changed by a smart option in the S3F8S6B (Full-Flash Device). Refer to the
chapter 21. Embedded Flash Memory Interface for more detail contents.
(HEX)
FFFFH
(Decimal)
65535
64K- bytes
Internal
Program
Memory Area
8FFH
Available
ISP Sector
255
Interrupt Vector Area
Smart option Area
0
FFH
3FH
3CH
00H
Byte
Figure 2-1
PS032408-0220
Program Memory Address Space
PRELIMINARY
2-2
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.2.1 Smart Option
ROM Address: 003EH
MSB
.7
.6
.5
.4
.3
.2
Not used
.1
.0
LSB
ISP protection size selection bits: (4)(5)
00 = 256 bytes
01 = 512 bytes
10 = 1024 bytes
11 = 2048 bytes
ISP reset vector change
selection bit: (1)
0 = OBP reset vector address
1 = Normal vector (address 0100H)
ISP reset vector address selection bits: (2)
00 = 200H(ISP area size: 256 byte)
01 = 300H(ISP area size: 512 byte)
10 = 500H(ISP area size: 1024 byte)
11 = 900H(ISP area size: 2048 byte)
ISP protection enable/disable bit: (3)
0 = Enable (not erasable by LDC)
1 = Disable (Erasable by LDC)
ROM Address: 003FH
MSB
.7
.6
.5
.4
.3
.2
.1
Not used
.0
LSB
LVR enable/disable bit
0 = Disable LVR
1 = Enable LVR
LVR Criteria Voltage Selection bit
0 = 1.9 V
1 = 2.2 V
ROM Address: 003CH
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
.1
.0
LSB
Not used
ROM Address: 003DH
MSB
.7
.6
.5
.4
.3
.2
Not used
NOTES:
1. By setting ISP reset vector change selection bit (3EH.7) to '0', user can have the available ISP area.
If ISP reset vector change selection bit (3EH.7) is '1', 3EH.6 and 3EH.5 are meaningless.
2. If ISP reset vector change selection bit (3EH.7) is '0', user must change ISP reset vector address from
0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).
If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes).
If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can
be assigned from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be assigned from 0100H
to 08FFH (2048bytes).
3. If ISP protection enable/disable bit is '0', user can't erase or program the ISP area selected by 3EH.1
and 3EH.0 in flash memory.
4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP protection enable/disable bit
(3EH.2) is '1', 3EH.1 and 3EH.0 are meaningless.
5. After selecting ISP reset vector address in selecting ISP protection size, don't select upper than ISP
area size.
Figure 2-2
PS032408-0220
Smart Option
PRELIMINARY
2-3
S3F8S6B Product Specification
Chapter 2. Address Spaces
Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from
003CH to 003FH. The S3F8S6B only use 003EH to 003FH.
When any values are written in the Smart Option area (003CH-003FH) by LDC instruction, the data of the area
may be changed but the Smart Option is not affected. The data for Smart Option should be written in the Smart
Option area (003CH-003FH) by OTP/MTP programmer (Writer tools)
PS032408-0220
PRELIMINARY
2-4
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.3 Register Architecture
In the S3F8S6B implementation, the upper 64 byte area of register files is expanded two 64 byte areas, called set
1 and set 2. The upper 32 byte area of set 1 is further expanded two 32 byte register banks (bank 0 and bank 1),
and the lower 32 byte area is a single 32 byte common area.
In case of S3F8S6B the total number of addressable 8-bit registers is 2,192. Of these 2,192 registers, 13 bytes are
for CPU and system control registers, 34 bytes are for LCD data registers, 81 bytes are for peripheral control and
data registers, 16 bytes are used as a shared working registers, and 2,048 registers are for general-purpose use,
page 0-page 7.
You can always address set 1 register locations, regardless of which of the ten register pages is currently
selected. Set 1 locations, however, can only be addressed using register addressing modes.
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by
various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer
(PP).
Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2.1.
Table 2.1
S3F8S6B Register Type Summary
Register Type
Number of Bytes
General-purpose registers (including the 16 byte common working register area,
eight 192 byte prime register area, and eight 64 byte set 2 area)
LCD data registers
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers
2,064
Total Addressable Bytes
2,192
PS032408-0220
PRELIMINARY
34
13
81
2-5
S3F8S6B Product Specification
Set1
Bank 1
FFH
32
Bytes
E0H
64
Bytes
DFH
D0H
CFH
Bank
0 and
System
Peripheral Control
System
and
Registers
Peripheral Control
Registers
(Register Addressing Mode)
Chapter 2. Address Spaces
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
FFH
Page 1
FFH
Page 0
Set 2
General-Purpose
Data Registers
System Registers
(Register Addressing Mode)
(Indirect Register,
Indexed Mode, and
Stack Operations)
General Purpose Register
(Register Addressing Mode)
C0H
51H
34
Bytes
C0H
BFH
Page 8
~
~
~
192
Bytes
~
Prime
Data Registers
~
~~
~
~
~
~~
(All Addressing
Modes)
Peripheral Control Register
(All addressing modes)
00H
00H
Figure 2-3
PS032408-0220
Page 0
Prime
Data Registers
(All addressing modes)
LCD Display Reigster
30H
2FH
48
Bytes
256
Bytes
Internal Register File Organization (S3F8S6B)
PRELIMINARY
2-6
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.3.1 Register Page Pointer (PP)
The S3C8-series architecture supports the logical expansion of the physical 256 byte internal register file (using an
8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the
register page pointer (PP, DFH). In the S3F8S6B microcontroller, a paged register file expansion is implemented
for LCD data registers, and the register page pointer must be changed to address other pages.
After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
"0000", automatically selecting page 0 as the source and destination page for register addressing.
Register Page Pointer (PP)
DFH ,Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Destination register page selection bits:
Source register page selection bits:
0000
0001
0010
0011
0100
0101
0110
0111
1000
Others
0000
0001
0010
0011
0100
0101
0110
0111
1000
Others
Destination: Page 0
Destination: Page 1
Destination: Page 2
Destination: Page 3
Destination: Page 4
Destination: Page 5
Destination: Page 6
Destination: Page 7
Destination: Page 8
Not used for the S3F8S6B
Source: page 0
Source: page 1
Source: page 2
Source: page 3
Source: page 4
Source: page 5
Source: page 6
Source: page 7
Source: page 8
Not used for the S3F8S6B
NOTES:
1. In the S3F8S6B microcontroller, the internal register file is configured as nine pages (Pages 0-7, 8).
The pages 0-7 are used for general purpose register file.
2. The page 8 of S3F8S6B is used for LCD data register (30H~51H) and system register (00H~2FH).
Figure 2-4
PS032408-0220
Register Page Pointer (PP)
PRELIMINARY
2-7
S3F8S6B Product Specification
Example 2-1
RAMCL0
RAMCL1
Using the Page Pointer for RAM clear (Page 0, Page 1)
;
Destination 0, Source 0
R0,#0FFH
@R0
R0,RAMCL0
@R0
;
;
Page 0 RAM clear starts
LD
PP,#10H ;
Destination 1, Source 0
LD
CLR
DJNZ
CLR
R0,#0FFH
@R0
R0,RAMCL1
@R0
;
;
LD
PP, #00H
SRP
#0C0H
LD
CLR
DJNZ
CLR
Chapter 2. Address Spaces
R0 = 00H
Page 1 RAM clear starts
R0 = 00H
NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.
PS032408-0220
PRELIMINARY
2-8
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.3.2 Register Set 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H−FFH.
The upper 32 byte area of this 64 byte space (E0H−FFH) is expanded two 32 byte register banks, bank 0 and
bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware
reset operation always selects bank 0 addressing.
The upper two 32 byte areas (bank 0 and bank 1) of set 1 (E0H−FFH) contains 56 mapped system and peripheral
control registers. The lower 32 byte area contains 16 system registers (D0H−DFH) and a 16 byte common working
register area (C0H−CFH). You can use the common working register area as a "scratch" area for data operations
being performed in other areas of the register file.
Registers in set 1 location are directly accessible at all times using Register addressing mode. The 16 byte
working register area can only be accessed using working register addressing (For more information about
working register addressing, please refer to Chapter 3, "Addressing Modes.")
2.3.3 Register Set 2
The same 64 byte physical space that is used for set 1 location C0H–FFH is logically duplicated to add another 64
bytes of register space. This expanded area of the register file is called set 2. For the S3F8S6B, the set 2 address
range (C0H–FFH) is accessible on pages 0-7.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 location. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.
The set 2 register area of page 0 is commonly used for stack operations.
PS032408-0220
PRELIMINARY
2-9
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.3.4 Prime Register Space
The lower 192 bytes (00H−BFH) of the S3F8S6B's eight/four/two 256 byte register pages is called prime register
area. Prime registers can be accessed using any of the seven addressing modes
(Refer to Chapter 3, "Addressing Modes.")
The prime register area on page 0 is immediately addressable following a reset. In order to address prime
registers on pages 0, 1, 2, 3, 4, 5, 6, 7, or 8 you must set the register page pointer (PP) to the appropriate source
and destination values.
Set 1
Bank 0
Bank 1
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
Page 1
FFH
Page 0
FFH
Set 2
FCH
E0H
D0H
C0H
BFH
C0H
Page 0
51H
Page 8
Prime
Space
CPU and system control
30H
2FH
General-purpose
LCD Data
Registr Area
Peripheral and I/O
LCD data register
Figure 2-5
PS032408-0220
00H
00H
Set 1, Set 2, Prime Area Register, and LCD Data Register Map
PRELIMINARY
2-10
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.3.5 Working Registers
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256 byte register file can be seen by the programmer as one
that consists of 32 8 byte register groups or "slices." Each slice comprises of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16 byte working register block. Using the register pointers, you can move this 16 byte register block
anywhere in the addressable register file, except the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
•
One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)
•
One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)
All the registers in an 8 byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The
base addresses for the two selected 8 byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16 byte common area in set 1 (C0H−CFH).
FFH
F8H
F7H
F0H
Slice 32
Slice 31
1 1 1 1 1 X X X
Set 1
Only
RP1 (Registers R8-R15)
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.
CFH
C0H
~
~
0 0 0 0 0 X X X
RP0 (Registers R0-R7)
Slice 2
Slice 1
Figure 2-6
PS032408-0220
10H
FH
8H
7H
0H
8 byte Working Register Areas (Slices)
PRELIMINARY
2-11
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.3.6 Using the Register Points
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8
byte working register slices in the register file. After a reset, they point to the working register common area: RP0
points to addresses C0H−C7H, and RP1 points to addresses C8H−CFH.
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.
(see Figure 2-7 and Figure 2-8).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H−FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing
modes.
The selected 16 byte working register block usually consists of two contiguous 8 byte slices. As a general
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice
(see Figure 2-7). In some cases, it may be necessary to define working register areas in different (non-contiguous)
areas of the register file. In Figure 2-8, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to either of the two 8 byte slices in the working register block, you can flexibly
define the working register area to support program requirements.
Example 2-2
Setting the Register Pointers
SRP
#70H
;
RP0 70H, RP1
78H
SRP1
#48H
;
RP0 no change, RP1
48H,
SRP0
#0A0H
;
RP0 A0H, RP1
no change
CLR
RP0
;
RP0 00H, RP1
no change
LD
RP1,#0F8H
;
RP0 no change, RP1
0F8H
Register File
Contains 32
8-Byte Slices
0 0 0 0 1 X X X
FH (R15)
8-Byte Slice
RP1
8H
7H
0 0 0 0 0 X X X
8-Byte Slice
0H (R0)
16-Byte
Contiguous
Working
Register block
RP0
Figure 2-7
PS032408-0220
Contiguous 16 byte Working Register Block
PRELIMINARY
2-12
S3F8S6B Product Specification
Chapter 2. Address Spaces
F7H (R7)
8-Byte Slice
F0H (R0)
1 1 1 1 0
X X X
Register File
Contains 32
8-Byte Slices
X X X
8-Byte Slice
16-Byte
Contiguous
working
Register block
RP0
7H (R15)
0 0 0 0 0
0H (R0)
RP1
Figure 2-8
Example 2-3
Non-Contiguous 16 byte Working Register Block
Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H−85H using the register pointer. The register addresses from 80H through 85H contain
the values 10H, 11H, 12H, 13H, 14H, and 15H, respectively:
SRP0
#80H
;
RP0 80H
ADD
R0,R1
;
R0 R0 + R1
ADC
R0,R2
;
R0 R0 + R2 + C
ADC
R0,R3
;
R0 R0 + R3 + C
ADC
R0,R4
;
R0 R0 + R4 + C
ADC
R0,R5
;
R0 R0 + R5 + C
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12
bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these
registers, the following instruction sequence would have to be used:
ADD
80H,81H
;
80H (80H) + (81H)
ADC
80H,82H
;
80H (80H) + (82H) + C
ADC
80H,83H
;
80H (80H) + (83H) + C
ADC
80H,84H
;
80H (80H) + (84H) + C
ADC
80H,85H ;
80H (80H) + (85H) + C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction
code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
PS032408-0220
PRELIMINARY
2-13
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.4 Register Addressing
The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair,
you can access any location in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8 byte working register space in the register file and an 8-bit register within that
space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and
the least significant byte is always stored in the next (+1) odd-numbered register.
Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8
byte working register space in the internal register file and a specific 8-bit register within that space.
MSB
LSB
Rn
Rn+1
Figure 2-9
PS032408-0220
n = Even address
16-Bit Register Pair
PRELIMINARY
2-14
S3F8S6B Product Specification
Special-Purpose Registers
Bank 1
Chapter 2. Address Spaces
General-Purpose Register
Bank 0
FFH
FFH
Control
Registers
E0H
Set 2
System
Registers
D0H
CFH
C0H
C0H
BFH
RP1
Register
Pointers
RP0
Each register pointer (RP) can independently point
to one of the 24 8-byte "slices" of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).
NOTE:
Prime
Registers
LCD Data
Registers
In the S3F8S6B microcontroller, pages 0-7, 8 are
Pages 0-7, 8 contain all of the addressable
registers in the internal register file.
System
Registers
00H
Page 0
Register Addressing Only
All
Addressing
Modes
Can be Pointed by Register Pointer
Figure 2-10
PS032408-0220
Page 0
Indirect Register,
All
Indexed
Addressing
Addressing
Modes
Modes
Can be Pointed to
By register Pointer
Register File Addressing
PRELIMINARY
2-15
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.4.1 Common Working Register Area (C0H−CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8 byte register slices in set 1, locations C0H–
CFH, as the active 16 byte working register block:
•
RP0 → C0H–C7H
•
RP1 → C8H–CFH
This 16 byte address range is called common area. That is, locations in this area can be used as working registers
by operations that address any location on any page in the register file. Typically, these working registers serve as
temporary buffers for data operations between different pages.
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
Page 1
FFH
Page 0
Set 1
FFH
FCH
Set 2
E0H
D0H
C0H
BFH
C0H
~
~
Page 0
~
~
~
~
Following a hardware reset, register
pointers RP0 and RP1 point to the
common working register area,
locations C0H-CFH.
RP0 =
1100
0000
RP1 =
1100
1000
~
~
30H
2FH
Page 8
LCD Data
Register Area
System
Register Area
00H
Figure 2-11
PS032408-0220
Prime
Space
51H
00H
Common Working Register Area
PRELIMINARY
2-16
S3F8S6B Product Specification
Example 2-4
Chapter 2. Address Spaces
Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H−CFH, using
working register addressing mode only.
1.
LD
0C2H,40H
;
Invalid addressing mode!
Use working register addressing instead:
2.
SRP
#0C0H
LD
R2,40H
;
R2 (C2H)
ADD
0C3H,#45H
;
Invalid addressing mode!
the value in location 40H
Use working register addressing instead:
SRP
#0C0H
ADD
R3,#45H
;
R3 (C3H)
R3 + 45H
2.4.2 4-bit Working Register Addressing
Each register pointer defines a movable 8 byte slice of working register space. The address information stored in a
register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
•
The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).
•
The five high-order bits in the register pointer select an 8 byte slice of the register space.
•
The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-12, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8 byte register slice.
Figure 2-13 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction "INC
R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three
low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
PS032408-0220
PRELIMINARY
2-17
S3F8S6B Product Specification
Chapter 2. Address Spaces
RP0
RP1
Selects
RP0 or RP1
Address
OPCODE
4-bit address
provides three
low-order bits
Register pointer
provides five
high-order bits
Together they create an
8-bit register address
Figure 2-12
4-bit Working Register Addressing
RP0
0 1 1 1 0
RP1
0 0 0
0 1 1 1 1
0 0 0
Selects RP0
0 1 1 1 0
1 1 0
Figure 2-13
PS032408-0220
Register
address
(76H)
R6
OPCODE
0 1 1 0
1 1 1 0
Instruction
'INC R6'
4-bit Working Register Addressing Example
PRELIMINARY
2-18
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.4.3 8-bit Working Register Addressing
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.
As shown in Figure 2-14, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.
Figure 2-15 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address, 0ABH
(10101011B).
RP0
RP1
Selects
RP0 or RP1
Address
Thes e addres s
bits indicate 8-bit
working register
addressing
1
1
0
0
Register pointer
provides five
high-order bits
8-bit logical
address
Three low-order bits
8-bit phys ical addres s
Figure 2-14
PS032408-0220
8-bit Working Register Addressing
PRELIMINARY
2-19
S3F8S6B Product Specification
Chapter 2. Address Spaces
RP0
0 1 1 0 0
RP1
0 0 0
1 0 1 0 1
0 0 0
1 0 1 0 1
0 1 1
Selects RP1
R11
1 1 0 0
1
0 1 1
8-bit address
form instruction
'LD R11, R2'
Register
address
(0ABH)
Specifies working
register addressing
Figure 2-15
PS032408-0220
8-bit Working Register Addressing Example
PRELIMINARY
2-20
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.5 System and User Stack
The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH
and POP instructions are used to control system stack operations. The S3F8S6B architecture supports stack
operations in the internal register file.
2.5.1 Stack Operations
Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-16.
High Address
PCL
PCL
Top of
stack
PCH
PCH
Top of
stack
Stack contents
after a call
instruction
Flags
Stack contents
after an
interrupt
Low Address
Figure 2-16
PS032408-0220
Stack Operations
PRELIMINARY
2-21
S3F8S6B Product Specification
Chapter 2. Address Spaces
2.5.2 User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
2.5.3 Stack Pointers (SPL, SPH)
Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.
The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least
significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.
Because only internal memory space is implemented in the S3F8S6B, the SPL must be initialized to an 8-bit value
in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if
necessary.
When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the
register file), you can use the SPH register as a general-purpose data register. However, if an overflow or
underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register
during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,
overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can
initialize the SPL value to "FFH" instead of "00H".
Example 2-5
Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and POP
instructions:
SPL,#0FFH
;
;
;
SPL FFH
(Normally, the SPL is set to 0FFH by the initialization
routine)
PUSH
PP
;
Stack address 0FEH PP
PUSH
RP0
;
Stack address 0FDH RP0
PUSH
RP1
;
Stack address 0FCH RP1
PUSH
R3
;
Stack address 0FBH R3
POP
R3
;
R3 Stack address 0FBH
POP
RP1
;
RP1 Stack address 0FCH
POP
RP0
;
RP0 Stack address 0FDH
POP
PP
;
PP Stack address 0FEH
LD
•
•
•
•
•
•
PS032408-0220
PRELIMINARY
2-22
S3F8S6B Product Specification
3
Chapter 3. Addressing Modes
Addressing Modes
3.1 Overview
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction. The seven addressing modes and their symbols are:
•
Register (R)
•
Indirect Register (IR)
•
Indexed (X)
•
Direct Address (DA)
•
Indirect Address (IA)
•
Relative Address (RA)
•
Immediate (IM)
PS032408-0220
PRELIMINARY
3-1
S3F8S6B Product Specification
Chapter 3. Addressing Modes
3.2 Register Addressing Mode
In Register addressing mode (R), the operand value is the content of a specified register or register pair
(see Figure 3-1).
Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory
8-bit Register
File Address
dst
OPCODE
Register File
OPERAND
Point to One
Register in Register
File
One-Operand
Instruction
(Example)
Value used in
Instruction Execution
Sample Instruction:
DEC
CNTR
;
Where CNTR is the label of an 8-bit register address
Figure 3-1
Register Addressing
Regis ter File
MSB Point to
RP0 ot RP1
RP0 or RP1
Selected
RP points
to s tart
of working
regis ter
block
Program Mem ory
4-bit
Working Register
dst
3 LSBs
s rc
Point to the
Working Register
(1 of 8)
OPCODE
Two-Operand
Ins truction
(Example)
OPERAND
Sample Ins truction:
ADD
R1, R2
;
Figure 3-2
PS032408-0220
Where R1 and R2 are regis ters in the currently
selected working register area.
Working Register Addressing
PRELIMINARY
3-2
S3F8S6B Product Specification
Chapter 3. Addressing Modes
3.3 Indirect Register Addressing Mode (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figure 3-3, Figure 3-4, Figure 3-5 and Figure 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Please note, however, that you cannot access locations C0H−FFH in
set 1 using the Indirect Register addressing mode.
Regis ter File
Program Mem ory
8-bit Regis ter
File Addres s
dst
OPCODE
One-Operand
Ins truction
(Exam ple)
Point to One
Regis ter in Register
File
ADDRESS
Addres s of Operand
used by Instruction
Value us ed in
Ins truction Execution
OPERAND
Sample Instruction:
RL
@SHIFT
Figure 3-3
PS032408-0220
;
Where SHIFT is the label of an 8-bit register addres s
Indirect Register Addressing to Register File
PRELIMINARY
3-3
S3F8S6B Product Specification
Chapter 3. Addressing Modes
Regis ter File
Program Mem ory
Example
Ins truction
References
Program
Memory
dst
OPCODE
REGISTER
PAIR
Points to
Regis ter Pair
Program Mem ory
Sample Ins tructions:
CALL
JP
@RR2
@RR2
Figure 3-4
PS032408-0220
Value us ed in
Ins truction
16-Bit
Address
Points to
Program
Memory
OPERAND
Indirect Register Addressing to Program Memory
PRELIMINARY
3-4
S3F8S6B Product Specification
Chapter 3. Addressing Modes
Regis ter File
MSB Points to
RP0 or RP1
RP0 or RP1
Program Mem ory
4-bit
Working
Regis ter
Addres s
ds t
src
OPCODE
~
~
3 LSBs
Point to the
Working Register
(1 of 8)
ADDRESS
~
~
Sam ple Instruction:
OR
R3, @R6
Figure 3-5
PS032408-0220
Selected
RP points
to s tart fo
working regis ter
block
Value used in
Instruction
OPERAND
Indirect Working Register Addressing to Register File
PRELIMINARY
3-5
S3F8S6B Product Specification
Chapter 3. Addressing Modes
Regis ter File
MSB Points to
RP0 or RP1
RP0 or RP1
Selected
RP points
to s tart of
working
regis ter
block
Program Mem ory
4-bit Working
Regis ter Address
Example Instruction
References either
Program Mem ory or
Data Memory
dst
s rc
OPCODE
Next 2-bit Point
to Working
Regis ter Pair
(1 of 4)
LSB Selects
Value us ed in
Ins truction
Regis ter
Pair
Program Mem ory
or
Data Memory
16-Bit
address
points to
program
m em ory
or data
m em ory
OPERAND
Sample Ins tructions:
LCD
LDE
LDE
Figure 3-6
PS032408-0220
R5,@RR6
R3,@RR14
@RR4, R8
; Program m em ory acces s
; External data mem ory acces s
; External data mem ory acces s
Indirect Working Register Addressing to Program or Data Memory
PRELIMINARY
3-6
S3F8S6B Product Specification
Chapter 3. Addressing Modes
3.4 Indexed Addressing Mode (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory. Please note, however, that you cannot access locations
C0H–FFH in set 1 using Indexed addressing mode.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range – 128
to + 127. This applies to external memory accesses only (see Figure 3-8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory, when implemented.
Regis ter File
RP0 or RP1
~
Value us ed in
Ins truction
+
Program Mem ory
Two-Operand
Ins truction
Exam ple
Base Address
dst/s rc
x
3 LSBs
Point to One of the
Woking Regis ter
(1 of 8)
OPCODE
~
Selected RP
points to
s tart of
working
regis ter
block
OPERAND
~
~
INDEX
Sample Instruction:
LD
R0, #BASE[R1]
Figure 3-7
PS032408-0220
;
Where BASE is an 8-bit im mediate value
Indexed Addressing to Register File
PRELIMINARY
3-7
S3F8S6B Product Specification
Chapter 3. Addressing Modes
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
~
~
Program Mem ory
4-bit Working
Register Address
OFFSET
ds t/src
x
OPCODE
Selected
RP points
to s tart of
working
regis ter
block
NEXT 2 Bits
Point to Working
Register Pair
(1 of 4)
LSB Selects
+
8-Bits
Register
Pair
Program Mem ory
or
Data Mem ory
16-Bit
addres s
added to
offs et
16-Bits
16-Bits
OPERAND
Value used in
Instruction
Sam ple Instructions:
LDC
R4, #04H[RR2]
LDE
R4,#04H[RR2]
Figure 3-8
PS032408-0220
; The values in the program address (RR2 + 04H)
are loaded into register R4.
; Identical operation to LDC exam ple, except that
external program m em ory is acces sed.
Indexed Addressing to Program or Data Memory with Short Offset
PRELIMINARY
3-8
S3F8S6B Product Specification
Chapter 3. Addressing Modes
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
Program Mem ory
~
~
OFFSET
4-bit Working
Register Address
OFFSET
ds t/src
src
NEXT 2 Bits
Point to Working
Register Pair
OPCODE
Selected
RP points
to s tart of
working
regis ter
block
LSB Selects
+
8-Bits
Register
Pair
Program Mem ory
or
Data Mem ory
16-Bit
addres s
added to
offs et
16-Bits
16-Bits
OPERAND
Value used in
Instruction
Sam ple Instructions:
LDC
R4, #1000H[RR2]
LDE
R4,#1000H[RR2]
Figure 3-9
PS032408-0220
; The values in the program address (RR2 + 1000H)
are loaded into regis ter R4.
; Identical operation to LDC exam ple, except that
external program m em ory is acces sed.
Indexed Addressing to Program or Data Memory
PRELIMINARY
3-9
S3F8S6B Product Specification
Chapter 3. Addressing Modes
3.5 Direct Address Mode (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load
operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Program Mem ory
Memory
Address
Us ed
Upper Address Byte
Lower Address Byte
dst/src "0" or "1"
OPCODE
LSB Selects Program
Memory or Data Mem ory:
"0" = Program Mem ory
"1" = Data Memory
Sample Ins tructions:
LDC
R5,1234H
;
LDE
R5,1234H
;
Figure 3-10
PS032408-0220
The values in the program addres s (1234H)
are loaded into regis ter R5.
Identical operation to LDC exam ple, except that
external program mem ory is access ed.
Direct Addressing for Load Instructions
PRELIMINARY
3-10
S3F8S6B Product Specification
Chapter 3. Addressing Modes
Program Mem ory
Next OPCODE
Mem ory
Addres s
Us ed
Upper Addres s Byte
Lower Addres s Byte
OPCODE
Sample Instructions :
JP
CALL
C,JOB1
DISPLAY
Figure 3-11
PS032408-0220
;
;
Where JOB1 is a 16-bit im mediate addres s
Where DISPLAY is a 16-bit im m ediate address
Direct Addressing for Call and Jump Instructions
PRELIMINARY
3-11
S3F8S6B Product Specification
Chapter 3. Addressing Modes
3.6 Indirect Address Mode (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.
Program Mem ory
Next Ins truction
LSB Mus t be Zero
Current
Ins truction
dst
OPCODE
Lower Addres s Byte
Upper Addres s Byte
Program Mem ory
Locations 0-255
Sample Instruction:
CALL
#40H
; The 16-bit value in program mem ory addres s es 40H
and 41H is the s ubroutine start addres s.
Figure 3-12
PS032408-0220
Indirect Addressing
PRELIMINARY
3-12
S3F8S6B Product Specification
Chapter 3. Addressing Modes
3.7 Relative Address Mode (RA)
In Relative Address (RA) mode, a twos-complement signed displacement between − 128 and + 127 is specified in
the instruction. The displacement value is then added to the current PC value. The result is the address of the next
instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately
following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions
that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
Program Mem ory
Next OPCODE
Program Mem ory
Address Us ed
Current
PC Value
Dis placement
OPCODE
Current Ins truction
+
Signed
Dis placement Value
Sample Ins tructions:
JR
ULT,$+OFFSET
; Where OFFSET is a value in the range +127 to -128
Figure 3-13
PS032408-0220
Relative Addressing
PRELIMINARY
3-13
S3F8S6B Product Specification
Chapter 3. Addressing Modes
3.8 Immediate Mode (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand
field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate
addressing mode is useful for loading constant values into registers.
Program Mem ory
OPERAND
OPCODE
(The Operand value is in the ins truction)
Sample Instruction:
LD
Figure 3-14
PS032408-0220
R0,#0AAH
Immediate Addressing
PRELIMINARY
3-14
S3F8S6B Product Specification
4
Chapter 4. Control Registers
Control Registers
4.1 Overview
In this chapter, detailed descriptions of the S3F8S6B control registers are presented in an easy-to-read format.
You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the
important features of the standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.
Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
The locations and read/write characteristics of all mapped registers in the S3F8S6B register file are listed in Table
4.1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and Power-Down."
Table 4.1
Register Name
Set 1 Registers
Mnemonic
Decimal
Hex
RW
BTCON
211
D3H
RW
CLKCON
212
D4H
RW
FLAGS
213
D5H
RW
Register Pointer 0
RP0
214
D6H
RW
Register Pointer 1
RP1
215
D7H
RW
Stack Pointer (High Byte)
SPH
216
D8H
RW
Stack Pointer (Low Byte)
SPL
217
D9H
RW
Instruction Pointer (High Byte)
IPH
218
DAH
RW
Instruction Pointer (Low Byte)
IPL
219
DBH
RW
Interrupt Request Register
IRQ
220
DCH
R
Interrupt Mask Register
IMR
221
DDH
RW
System Mode Register
SYM
222
DEH
RW
Register Page Pointer
PP
223
DFH
RW
Basic Timer Control Register
System Clock Control Register
System Flags Register
PS032408-0220
PRELIMINARY
4-1
S3F8S6B Product Specification
Table 4.2
Chapter 4. Control Registers
Set 1, Bank 0 Registers
Register Name
Mnemonic
Decimal
Hex
RW
A/D Converter Data Register (High Byte)
ADDATAH
208
D0H
R
A/D Converter Data Register (Low Byte)
ADDATAL
209
D1H
R
A/D Converter Control Register
ADCON
210
D2H
RW
Timer A Counter Register
TACNT
224
E0H
R
Timer A Data Register
TADATA
225
E1H
RW
Timer A Control Register
TACON
226
E2H
RW
Timer B Control Register
TBCON
227
E3H
RW
Timer B Data Register (High Byte)
TBDATAH
228
E4H
RW
Timer B Data Register (Low Byte)
TBDATAL
229
E5H
RW
Watch Timer Control Register
WTCON
230
E6H
RW
SIO Control Register
SIOCON
231
E7H
RW
SIO Data Register
SIODATA
232
E8H
RW
SIO Pre-Scaler Register
SIOPS
233
E9H
RW
Timer C Counter Register
TCCNT
234
EAH
R
Timer C Data Register
TCDATA
235
EBH
RW
Timer C Control Register
TCCON
236
ECH
RW
LCD Control Register
LCON
240
F0H
RW
LCD Mode Register
LMOD
241
F1H
RW
Interrupt Pending Register
INTPND
244
F4H
RW
STOP Control Register
STPCON
245
F5H
RW
Flash Memory Sector Address Register (High Byte)
FMSECH
246
F6H
RW
Flash Memory Sector Address Register (Low Byte)
FMSECL
247
F7H
RW
Flash Memory User Programming Enable Register
FMUSR
248
F8H
RW
Flash Memory Control Register
FMCON
249
F9H
RW
OSCCON
250
FAH
RW
BTCNT
253
FDH
R
IPR
255
FFH
RW
Locations EDH−EFH are not mapped.
Locations F2H−F3H are not mapped.
Oscillator Control Register
Locations FBH−FCH are not mapped.
Basic Timer Counter
Location FEH is not mapped.
Interrupt Priority Register
PS032408-0220
PRELIMINARY
4-2
S3F8S6B Product Specification
Table 4.3
Register Name
Chapter 4. Control Registers
Set 1, Bank 1 Registers
Mnemonic
Decimal
Hex
RW
Pattern Generation Control Register
PGCON
208
D0H
RW
Pattern Generation Data Register
PGDATA
209
D1H
RW
Port 0 Control Register (High Byte)
P0CONH
224
E0H
RW
Port 0 Control Register (Low Byte)
P0CONL
225
E1H
RW
Port 1 Control Register (High Byte)
P1CONH
226
E2H
RW
Port 1 Control Register (Low Byte)
P1CONL
227
E3H
RW
P1PUR
228
E4H
RW
PNE1
229
E5H
RW
Port 2 Control Register (High Byte)
P2CONH
230
E6H
RW
Port 2 Control Register (Low Byte)
P2CONL
231
E7H
RW
Port 2 Interrupt Control Register (High Byte)
P2INTH
232
E8H
RW
Port 2 Interrupt Control Register (Low Byte)
P2INTL
233
E9H
RW
Port 2 Interrupt Pending Register
P2PND
234
EAH
RW
Port 3 Interrupt Control Register (High Byte)
P3CONH
235
EBH
RW
Port 3 Interrupt Control Register (Middle Byte)
P3CONM
236
ECH
RW
Port 3 Interrupt Control Register (Low Byte)
P3CONL
237
EDH
RW
P3PUR
238
EEH
RW
PNE3
239
EFH
RW
Port 5 Control Register (High Byte)
P5CONH
240
F0H
RW
Port 5 Control Register (Low Byte)
P5CONL
241
F1H
RW
Port 6 Control Register (High Byte)
P6CONH
242
F2H
RW
Port 6 Control Register (Low Byte)
P6CONL
243
F3H
RW
P6PUR
244
F4H
RW
PNE6
245
F5H
RW
Timer D0 Counter Register (High Byte)
TD0CNTH
246
F6H
R
Timer D0 Counter Register (Low Byte)
TD0CNTL
247
F7H
R
Timer D0 Data Register (High Byte)
TD0DATAH
248
F8H
RW
Timer D0 Data Register (Low Byte)
TD0DATAL
249
F9H
RW
Timer D0 Control Register
TD0CON
250
FAH
RW
Timer D1 Control Register
TD1CON
251
FBH
RW
Timer D1 Counter Register (High Byte)
TD1CNTH
252
FCH
R
Timer D1 Counter Register (Low Byte)
TD1CNTL
253
FDH
R
Timer D1 Data Register (High Byte)
TD1DATAH
254
FEH
RW
Timer D1 Data Register (Low Byte)
TD1DATAL
255
FFH
RW
Location D2H is not mapped.
Port 1 Pull-up Resistor Enable Register
Port 1 N-Channel Open-drain Mode Register
Port 3 Pull-up Resistor Enable Register
Port 3 N-Channel Open-drain Mode Register
Port 6 Pull-up Resistor Enable Register
Port 6 N-Channel Open-drain Mode Register
PS032408-0220
PRELIMINARY
4-3
S3F8S6B Product Specification
Table 4.4
Register Name
Chapter 4. Control Registers
Page 8 Registers
Mnemonic
Decimal
Hex
RW
Port 0 Data Register
P0
0
00H
RW
Port 1 Data Register
P1
1
01H
RW
Port 2 Data Register
P2
2
02H
RW
Port 3 Data Register
P3
3
03H
RW
Port 4 Data Register
P4
4
04H
RW
Port 5 Data Register
P5
5
05H
RW
Port 6 Data Register
P6
6
06H
RW
Port 4 Control Register (High Byte)
P4CONH
12
0CH
RW
Port 4 Control Register (Low Byte)
P4CONL
13
0DH
RW
Port 4 Interrupt Control Register (High Byte)
P4INTH
14
0EH
RW
Port 4 Interrupt Control Register (Low Byte)
P4INTL
15
0FH
RW
Port 4 Interrupt Pending Register
P4PND
16
10H
RW
UART 0 Control Register (High Byte)
UART0CONH
20
14H
RW
UART 0 Control Register (Low Byte)
UART0CONL
21
15H
RW
UDATA0
22
16H
RW
BRDATA0
23
17H
RW
UART 1 Control Register (High Byte)
UART1CONH
24
18H
RW
UART 1 Control Register (Low Byte)
UART1CONL
25
19H
RW
UDATA1
26
1AH
RW
BRDATA1
27
1BH
RW
Locations 07H−0BH are not mapped.
Locations 11H−13H are not mapped.
UART 0 Data Register
UART 0 Baud Rate Data Register
UART 1 Data Register
UART 1 Baud Rate Data Register
Locations 1CH−2FH are not mapped.
PS032408-0220
PRELIMINARY
4-4
S3F8S6B Product Specification
Bit number(s) that is/are appended to
the register name for bit addressing
Register ID
Chapter 4. Control Registers
Name of individual
bit or related bits
Register location
in the internal
register file
Register address
(hexadecimal)
Full Register name
FLAGS - System Flags Register
D5H
Set 1
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
x
x
x
x
x
x
x
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
Bit Addressing
Register addressing mode only
Mode
.7
Carry Flag (C)
.6
0
Operation does not generate a carry or borrow condition
1
Operation generates carry-out or borrow into high-order bit 7
Zero Flag (Z)
0
Operation result is a non-zero value
1
Operation result is zero
.5
Sign Flag (S)
0
Operation generates positive number (MSB = "0")
1
Operation generates negative number (MSB = "1")
R = Read-only
W = Write-only
R/W = Read/write
'-' = Not used
Description of the
effect of specific
bit settings
Type of addressing
that must be used to
address the bit
(1-bit, 4-bit, or 8-bit)
RESET value notation:
'-' = Not used
'x' = Undetermined value
'0' = Logic zero
'1' = Logic one
Figure 4-1
PS032408-0220
Bit number:
MSB = Bit 7
LSB = Bit 0
Register Description Format
PRELIMINARY
4-5
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.1 ADCON: A/D Converter Control Register (D2H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
–
0
0
0
0
0
0
0
Read/Write
–
RW
RW
RW
R
RW
RW
RW
Addressing Mode
Register addressing mode only
.7
Not used for the S3F8S6B
.6–.4
A/D Input Pin Selection Bits
.3
.2–.1
.0
PS032408-0220
0
0
0
AD0
0
0
1
AD1
0
1
0
AD2
0
1
1
AD3
1
0
0
AD4
1
0
1
AD5
1
1
0
AD6
1
1
1
AD7
End-of-Conversion Bit (Read-only)
0
Conversion not complete
1
Conversion complete
Clock Source Selection Bits
0
0
fxx/16
0
1
fxx/8
1
0
fxx/4
1
1
fxx/1
Start or Enable Bit
0
Disable operation
1
Start operation
PRELIMINARY
4-6
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.2 BTCON: Basic Timer Control Register (D3H, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.4
Watchdog Timer Function Disable Code (for System Reset)
1
0
1
0
Others
.3–.2
.1
Disable watchdog timer function
Enable watchdog timer function
Basic Timer Input Clock Selection Bits (3)
0
0
fxx/4096
0
1
fxx/1024
1
0
fxx/128
1
1
fxx/16
Basic Timer Counter Clear Bit (1)
.0
0
No effect
1
Clear the basic timer counter value
Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters (2)
0
No effect
1
Clear both clock frequency dividers
NOTE:
1.
When you write a "1" to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write
operation, the BTCON.1 value is automatically cleared to "0".
2.
When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the
write operation, the BTCON.0 value is automatically cleared to "0".
3.
The fxx is selected clock for system (main OSC. or sub OSC).
PS032408-0220
PRELIMINARY
4-7
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.3 CLKCON: System Clock Control Register (D4H, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
–
–
0
0
–
–
–
RW
–
–
RW
RW
–
–
–
Read/Write
Addressing Mode
Register addressing mode only
.7
Oscillator IRQ Wake-up Function Bit
0
Enable IRQ for main wake-up in power down mode
1
Disable IRQ for main wake-up in power down mode
.6–.5
Not used for the S3F8S6B (must keep always "0")
.4–.3
CPU Clock (System Clock) Selection Bits (note)
.2–.0
0
0
fxx/16
0
1
fxx/8
1
0
fxx/2
1
1
fxx/1
Not used for the S3F8S6B (must keep always "0")
NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.
PS032408-0220
PRELIMINARY
4-8
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.4 FLAGS: System Flags Register (D5H, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
x
x
x
x
x
x
0
0
RW
RW
RW
RW
RW
RW
R
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
Carry Flag (C)
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Operation does not generate a carry or borrow condition
1
Operation generates a carry-out or borrow into high-order bit 7
Zero Flag (Z)
0
Operation result is a non-zero value
1
Operation result is zero
Sign Flag (S)
0
Operation generates a positive number (MSB = "0")
1
Operation generates a negative number (MSB = "1")
Overflow Flag (V)
0
Operation result is +127 or –128
1
Operation result is > +127 or < –128
Decimal Adjust Flag (D)
0
Add operation completed
1
Subtraction operation completed
Half-Carry Flag (H)
0
No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
1
Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3
Fast Interrupt Status Flag (FIS)
0
Interrupt return (IRET) in progress (when read)
1
Fast interrupt service routine in progress (when read)
Bank Address Selection Flag (BA)
0
Bank 0 is selected
1
Bank 1 is selected
PRELIMINARY
4-9
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.5 FMCON: Flash Memory Control Register (F9H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
–
–
0
RW
RW
RW
RW
R
–
–
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.4
Flash Memory Mode Selection Bits
0
1
0
1
Programming mode
1
0
1
0
Sector erase mode
0
1
1
0
Hard lock mode
Others
.3
Not available
Sector Erase Status Bit (Read-only)
0
Success sector erase
1
Fail sector erase
.2–.1
Not used for the S3F8S6B
.0
Flash Operation Start Bit
0
Operation stop bit
1
Operation start bit
NOTE: The FMCON.0 will be cleared automatically just after the corresponding operation completed.
PS032408-0220
PRELIMINARY
4-10
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.6 FMSECH: Flash Memory Sector Address Register-High Byte (F6H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.0
Flash Memory Sector Address Bits (High Byte)
The 15th-8th bits to select a sector of Flash ROM
NOTE: The high byte Flash memory sector address pointer value is higher eight bits of the 16-bit pointer address.
4.1.7 FMSECL: Flash Memory Sector Address Register-Low Byte (F7H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
Flash Memory Sector Address Bit (Low Byte)
The 7th bit to select a sector of Flash ROM
.6–.0
Don't care
NOTE: The low byte Flash memory sector address pointer value is lower eight bits of the 16-bit pointer address.
PS032408-0220
PRELIMINARY
4-11
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.8 FMUSR: Flash Memory User Programming Enable Register (F8H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.0
Flash Memory User Programming Enable Bits
1
0
1
0
0
1
0
Others
PS032408-0220
PRELIMINARY
1
Enable user programming mode
Disable user programming mode
4-12
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.9 IMR: Interrupt Mask Register (DDH, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
x
x
x
x
x
x
x
x
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P4.0–4.7
.6
.5
.4
.3
.2
.1
.0
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P2.0–2.7
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 5 (IRQ5) Enable Bit; UART0/1 Transmit, UART0/1 Receive
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 4 (IRQ4) Enable Bit; Watch Timer, SIO
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 3 (IRQ3) Enable Bit; Timer D0/D1 Match/Capture or Overflow
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 2 (IRQ2) Enable Bit; Timer C Match/Overflow
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 1 (IRQ1) Enable Bit; Timer B Match
0
Disable (mask)
1
Enable (unmask)
Interrupt Level 0 (IRQ0) Enable Bit; Timer A Match/Capture or Overflow
0
Disable (mask)
1
Enable (unmask)
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.
PS032408-0220
PRELIMINARY
4-13
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.10 INTPND: Interrupt Pending Register (F4H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
–
–
0
0
0
0
0
0
Read/Write
–
–
RW
RW
RW
RW
RW
RW
Addressing Mode
Register addressing mode only
.7–.6
Not used for the S3F8S6B
.5
Timer D1 Match/Capture Interrupt Pending Bit
.4
.3
.2
.1
.0
PS032408-0220
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
Timer D1 Overflow Interrupt Pending Bit
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
Timer D0 Match/Capture Interrupt Pending Bit
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
Timer D0 Overflow Interrupt Pending Bit
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
Timer A Match/Capture Interrupt Pending Bit
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
Timer A Overflow Interrupt Pending Bit
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
PRELIMINARY
4-14
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.11 IPH: Instruction Pointer-High Byte (DAH, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
x
x
x
x
x
x
x
x
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.0
Instruction Pointer Address (High Byte)
The high byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).
4.1.12 IPL: Instruction Pointer-Low Byte (DBH, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
x
x
x
x
x
x
x
x
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.0
Instruction Pointer Address (Low Byte)
The low byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).
PS032408-0220
PRELIMINARY
4-15
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.13 IPR: Interrupt Priority Register (FFH, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
x
x
x
x
x
x
x
x
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7, .4, and .1
Priority Control Bits for Interrupt Groups A, B, and C
.6
0
0
0
Group priority undefined
0
0
1
B>C>A
0
1
0
A>B>C
0
1
1
B>A>C
1
0
0
C>A>B
1
0
1
C>B>A
1
1
0
A>C>B
1
1
1
Group priority undefined
Interrupt Subgroup C Priority Control Bit
.5
0
IRQ6 > IRQ7
1
IRQ7 > IRQ6
Interrupt Group C Priority Control Bit
.3
0
IRQ5 > (IRQ6, IRQ7)
1
(IRQ6, IRQ7) > IRQ5
Interrupt Subgroup B Priority Control Bit
.2
0
IRQ3 > IRQ4
1
IRQ4 > IRQ3
Interrupt Group B Priority Control Bit
.0
0
IRQ2 > (IRQ3, IRQ4)
1
(IRQ3, IRQ4) > IRQ2
Interrupt Group A Priority Control Bit
0
IRQ0 > IRQ1
1
IRQ1 > IRQ0
NOTE: Interrupt group A -IRQ0, IRQ1
Interrupt group B -IRQ2, IRQ3, IRQ4
Interrupt group C -IRQ5, IRQ6, IRQ7
PS032408-0220
PRELIMINARY
4-16
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.14 IRQ: Interrupt Request Register (DCH, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Addressing Mode
Register addressing mode only
.7
Level 7 (IRQ7) Request Pending Bit; External Interrupts P4.0–4.7
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Not pending
1
Pending
Level 6 (IRQ6) Request Pending Bit; External Interrupts P2.0–2.7
0
Not pending
1
Pending
Level 5 (IRQ5) Request Pending Bit; UART0/1 Transmit, UART0/1 Receive
0
Not pending
1
Pending
Level 4 (IRQ4) Request Pending Bit; Watch Timer, SIO
0
Not pending
1
Pending
Level 3 (IRQ3) Request Pending Bit; Timer D0/D1 Match/Capture or Overflow
0
Not pending
1
Pending
Level 2 (IRQ2) Request Pending Bit; Timer C Match/Overflow
0
Not pending
1
Pending
Level 1 (IRQ1) Request Pending Bit; Timer B Match
0
Not pending
1
Pending
Level 0 (IRQ0) Request Pending Bit; Timer A Match/Capture or Overflow
0
Not pending
1
Pending
PRELIMINARY
4-17
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.15 LCON: LCD Control Register (F0H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
LCD Clock Selection Bits
.5–.3
.2–.1
.0
0
0
fw/28 (128 Hz)
0
1
fw/27 (256 Hz)
1
0
fw/26 (512 Hz)
1
1
fw/25 (1024 Hz)
LCD Duty and Bias Selection Bits
0
0
0
1/8 duty, 1/4 bias
0
0
1
1/4 duty, 1/3 bias
0
1
0
1/3 duty, 1/3 bias
0
1
1
1/3 duty, 1/2 bias
1
x
x
1/2 duty, 1/2 bias
LCD Bias Type Selection Bits (note)
0
0
VLC0 − VLC3, CA and CB pins are normal I/O pin
0
1
Capacitor bias; VLC0– VLC3, CA and CB pins are bias pin
1
0
Internal resistor bias (The voltage booster is always stopped and cut off);
VLC0 − VLC3 are bias pin, CA, and CB pins are normal pin
1
1
External resistor bias (The voltage booster is always stopped and cut off);
VLC0 − VLC3 are bias pin, CA, and CB pins are normal pin
LCD Display Control Bits
0
All LCD signals are low (The voltage booster is always stopped and cut off)
1
Turn display on (When LCON.2−.1 = "01", Run and connect voltage booster)
NOTE:
1.
When LCON.2-.1 are selected to '01', P5.0-.5 are automatically selected to VLCn, CA and CB pin. (n = 0 to 3).
When LCON.2-.1 are capacitor bias selected, LCON.0 is select to "1" after 1 millisecond delay.
2.
When LCON.2-.1 are selected to "10", P5.0-.3 are automatically selected to VLCn. (n = 0 to 3)
3.
When LCON.2-.1 are selected to "11", P5.0-.3 are automatically selected to VLCn. (n = 0 to 3)
4.
The clock and duty for LCD controller/driver is automatically initialized by hardware, whenever LCON register data value
is re-write. So, the LCON register don"t re-write frequently.
5.
The P5.3/VLC3-P5.0/VLC0 must be used as LCD bias pins if the LCD block is used. So, the LCON.2-.1 must not be set to
"00b" when LCON.0 = 1.
PS032408-0220
PRELIMINARY
4-18
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.16 LMOD: LCD Mode Control Register (F1H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
RESET Value
–
–
–
–
–
0
0
0
Read/Write
–
–
–
–
–
RW
RW
RW
Addressing
Mode
Register addressing mode only
.7–.3
Not used for the S3F8S6B
.0
In Run, Idle, and Sub Operating Modes
.2–.0
VLCD Voltage Selection Bits (Only when the capacitor bias is selected)
Values
1/4 Bias
1/3 Bias
1/2 Bias
0
0
0
3.6 V
3.15 V
2.20 V
0
0
1
3.8 V
3.375 V
2.40 V
0
1
0
4.0 V
3.60 V
2.60 V
0
1
1
4.2 V
3.825 V
2.80 V
1
0
0
4.4 V
4.050 V
3.00 V
1
0
1
4.6 V
4.275 V
Not available
1
1
0
4.8 V
4.50 V
Not available
1
1
1
5.0 V
Not available
Not available
In Sub Idle and Stop Modes
.2–.0
VLCD Voltage Selection Bits (Only when the capacitor bias is selected)
Values
1/4 Bias
1/3 Bias
1/2 Bias
0
0
0
3.6 V
3.15 V
2.20 V
0
0
1
3.8 V
3.375 V
2.40 V
0
1
0
4.0 V
3.60 V
Not available
0
1
1
4.2 V
Not available
Not available
1
0
0
4.4 V
Not available
Not available
1
0
1
4.6 V
Not available
Not available
1
1
0
4.8 V
Not available
Not available
1
1
1
5.0 V
Not available
Not available
NOTE:
1.
The voltage regulator and booster circuit provide constant LCD contrast level.
2.
Since the booster clock is generated by watch timer (fw). And the booster clock is almost 32 kHz.
PS032408-0220
PRELIMINARY
4-19
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.17 OSCCON: Oscillator Control Register (FAH, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
–
–
–
–
0
0
–
0
Read/Write
–
–
–
–
RW
RW
–
RW
Addressing Mode
Register addressing mode only
.7–.4
Not used for the S3F8S6B
.3
Main Oscillator Control Bit
.2
0
Main oscillator RUN
1
Main oscillator STOP
Sub Oscillator Control Bit
0
Sub oscillator RUN
1
Sub oscillator STOP
.1
Not used for the S3F8S6B
.0
System Clock Selection Bit
PS032408-0220
0
Select main oscillator for system clock
1
Select sub oscillator for system clock
PRELIMINARY
4-20
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.18 P0CONH: Port 0 Control Register-High Byte (E0H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P0.7/SEG5/COM7 Configuration Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P0.6/SEG4/COM6 Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P0.5/SEG3/COM5 Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P0.4/SEG2/COM4 Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
PRELIMINARY
4-21
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.19 P0CONL: Port 0 Control Register-Low Byte (E1H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P0.3/SEG1/COM3 Configuration Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P0.2/SEG0/COM2 Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P0.1/COM1 Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P0.0/COM0 Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
PRELIMINARY
4-22
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.20 P1CONH: Port 1 Control Register-High Byte (E2H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P1.7/TACLK/SEG11 Configuration Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Input mode (TACLK)
0
1
Not available
1
0
Alternative function (LCD signal)
1
1
Output mode
P1.6/TAOUT/TAPWM/TACAP/SEG10 Configuration Bits
0
0
Input mode (TACAP)
0
1
Alternative function (TAOUT/TAPWM)
1
0
Alternative function (LCD signal)
1
1
Output mode
P1.5/TxD1/SEG9 Configuration Bits
0
0
Input mode
0
1
Alternative function (TxD1)
1
0
Alternative function (LCD signal)
1
1
Output mode
P1.4/RxD1/SEG8 Configuration Bits
0
0
Input mode (RxD1)
0
1
Alternative function (RxD1 out)
1
0
Alternative function (LCD signal)
1
1
Output mode
PRELIMINARY
4-23
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.21 P1CONL: Port 1 Control Register-Low Byte (E3H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P1.3/TxD0/SEG7 Configuration Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Input mode
0
1
Alternative function (TxD0 out)
1
0
Alternative function (LCD signal)
1
1
Output mode
P1.2/RxD0/SEG6 Configuration Bits
0
0
Input mode (RxD0)
0
1
Alternative function (RxD0 out)
1
0
Alternative function (LCD signal)
1
1
Output mode
P1.1 Configuration Bits
0
0
Input mode
0
1
Not available
1
0
Not available
1
1
Output mode
P1.0 Configuration Bits
0
0
Input mode
0
1
Not available
1
0
Not available
1
1
Output mode
PRELIMINARY
4-24
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.22 P1PUR: Port 1 Pull-up Resistor Enable Register (E4H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
P1.7 Pull-up Resistor Enable Bit
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Pull-up disable
1
Pull-up enable
P1.6 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P1.5 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P1.4 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P1.3 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P1.2 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P1.1 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P1.0 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
PRELIMINARY
4-25
S3F8S6B Product Specification
Chapter 4. Control Registers
NOTE: A pull-up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push-pull output or
alternative function.
PS032408-0220
PRELIMINARY
4-26
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.23 PNE1: Port 1 N-channel Open-drain Mode Register (E5H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
P1.7 Output Mode Selection Bit
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Output mode, push-pull
1
Output mode, open-drain
P1.6 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P1.5 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P1.4 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P1.3 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P1.2 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P1.1 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P1.0 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
PRELIMINARY
4-27
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.24 P2CONH: Port 2 Control Register-High Byte (E6H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P2.7/INT7/SEG19 Configuration Bits
.5-.4
.3–.2
.1–.0
PS032408-0220
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P2.6/INT6/SEG18 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P2.5/INT5/SEG17 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P2.4/INT4/SEG16 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
PRELIMINARY
4-28
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.25 P2CONL: Port 2 Control Register-Low Byte (E7H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P2.3/INT3/SEG15 Configuration Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P2.2/INT2/SEG14 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P2.1/INT1/SEG13 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
P2.0/INT0/SEG12 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (LCD signal)
1
1
Output mode, push-pull
PRELIMINARY
4-29
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.26 P2INTH: Port 2 Interrupt Control Register-High Byte (E8H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P2.7/External interrupt (INT7) Enable Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P2.6/External interrupt (INT6) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P2.5/External interrupt (INT5) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P2.4/External interrupt (INT4) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
PRELIMINARY
4-30
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.27 P2INTL: Port 2 Interrupt Control Register-Low Byte (E9H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P2.3/External interrupt (INT3) Enable Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P2.2/External interrupt (INT2) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P2.1/External interrupt (INT1) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P2.0/External interrupt (INT0) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
PRELIMINARY
4-31
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.28 P2PND: Port 2 Interrupt Pending Register (EAH, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
P2.7/External Interrupt (INT7) Pending Bit
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P2.6/External Interrupt (INT6) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P2.5/External Interrupt (INT5) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P2.4/External Interrupt (INT4) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P2.3/External Interrupt (INT3) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P2.2/External Interrupt (INT2) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P2.1/External Interrupt (INT1) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P2.0/External Interrupt (INT0) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
PRELIMINARY
4-32
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.29 P3CONH: Port 3 Control Register-High Byte (EBH, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.5
P3.7/BUZ/PG7/SEG27 Configuration Bits
.4–.3
.2–.0
PS032408-0220
0
0
0
Input mode
0
0
1
Alternative function (PG7)
0
1
0
Alternative function (LCD signal)
0
1
1
Output mode
1
x
x
Alternative function (BUZ)
P3.6/TD1CLK/PG6/SEG26 Configuration Bits
0
0
Input mode (TD1CLK)
0
1
Alternative function (PG6)
1
0
Alternative function (LCD signal)
1
1
Output mode
P3.5/TD1OUT/TD1PWM/TD1CAP/PG5/SEG25 Configuration Bits
0
0
0
Input mode (TD1CAP)
0
0
1
Alternative function (PG5)
0
1
0
Alternative function (LCD signal)
0
1
1
Output mode
1
x
x
Alternative function (TD1OUT/TD1PWM)
PRELIMINARY
4-33
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.30 P3CONM: Port 3 Control Register-Middle Byte (ECH, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P3.4/TD0CLK/PG4/SEG24 Configuration Bits
.5–.3
.2–.0
PS032408-0220
0
0
Input mode (TD0CLK)
0
1
Alternative function (PG4)
1
0
Alternative function (LCD signal)
1
1
Output mode
P3.3/TD0OUT/TD0PWM/TD0CAP/PG3/SEG23 Configuration Bits
0
0
0
Input mode (TD0CAP)
0
0
1
Alternative function (PG3)
0
1
0
Alternative function (LCD signal)
0
1
1
Output mode
1
x
x
Alternative function (TD0OUT/TD0PWM)
P3.2/PG2/SEG22 Configuration Bits
0
0
0
Input mode
0
0
1
Alternative function (PG2)
0
1
0
Alternative function (LCD signal)
0
1
1
Output mode
1
x
x
Alternative function
PRELIMINARY
4-34
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.31 P3CONL: Port 3 Control Register-Low Byte (EDH, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
–
–
0
0
0
0
0
0
Read/Write
–
–
RW
RW
RW
RW
RW
RW
Addressing Mode
Register addressing mode only
.7–.6
Not used for the S3F8S6B
.5–.3
P3.1/TCOUT/PG1/SEG21 Configuration Bits
.2–.0
PS032408-0220
0
0
0
Input mode
0
0
1
Alternative function (PG1)
0
1
0
Alternative function (LCD signal)
0
1
1
Output mode
1
x
x
Alternative function (TCOUT)
P3.0/TBPWM/PG0/SEG20 Configuration Bits
0
0
0
Input mode
0
0
1
Alternative function (PG0)
0
1
0
Alternative function (LCD signal)
0
1
1
Output mode
1
x
x
Alternative function (TBPWM)
PRELIMINARY
4-35
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.32 P3PUR: Port 3 Pull-up Resistor Enable Register (EEH, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
P3.7 Pull-up Resistor Enable Bit
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Pull-up disable
1
Pull-up enable
P3.6 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P3.5 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P3.4 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P3.3 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P3.2 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P3.1 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
P3.0 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
PRELIMINARY
4-36
S3F8S6B Product Specification
Chapter 4. Control Registers
NOTE: A pull-up resistor of port 3 is automatically disabled only when the corresponding pin is selected as push-pull output or
alternative function.
PS032408-0220
PRELIMINARY
4-37
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.33 PNE3: Port 3 N-channel Open-drain Mode Register (EFH, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
P3.7 Output Mode Selection Bit
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Output mode, push-pull
1
Output mode, open-drain
P3.6 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P3.5 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P3.4 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P3.3 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P3.2 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P3.1 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P3.0 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
PRELIMINARY
4-38
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.34 P4CONH: Port 4 Control Register-High Byte (0CH, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P4.7/INT15/AD7 Configuration Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (AD7)
1
1
Output mode, push-pull
P4.6/INT14/AD6 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (AD6)
1
1
Output mode, push-pull
P4.5/INT13/AD5 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (AD5)
1
1
Output mode, push-pull
P4.4/INT12/AD4 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (AD4)
1
1
Output mode, push-pull
PRELIMINARY
4-39
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.35 P4CONL: Port 4 Control Register-Low Byte (0DH, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P4.3/INT11/AD3 Configuration Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (AD3)
1
1
Output mode, push-pull
P4.2/INT10/AD2 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (AD2)
1
1
Output mode, push-pull
P4.1/INT9/AD1 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (AD1)
1
1
Output mode, push-pull
P4.0/INT8/AD0 Configuration Bits
0
0
Schmitt trigger input mode
0
1
Schmitt trigger input mode, pull-up
1
0
Alternative function (AD0)
1
1
Output mode, push-pull
PRELIMINARY
4-40
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.36 P4INTH: Port 4 Interrupt Control Register-High Byte (0EH, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P4.7/External interrupt (INT15) Enable Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P4.6/External interrupt (INT14) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P4.5/External interrupt (INT13) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P4.4/External interrupt (INT12) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
PRELIMINARY
4-41
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.37 P4INTL: Port 4 Interrupt Control Register-Low Byte (0FH, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P4.3/External interrupt (INT11) Enable Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P4.2/External interrupt (INT10) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P4.1/External interrupt (INT9) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
P4.0/External interrupt (INT8) Enable Bits
0
0
Disable interrupt
0
1
Enable interrupt by falling edge
1
0
Enable interrupt by rising edge
1
1
Enable interrupt by both falling and rising edge
PRELIMINARY
4-42
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.38 P4PND: Port 4 Interrupt Pending Register (10H, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
P4.7/External Interrupt (INT15) Pending Bit
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P4.6/External Interrupt (INT14) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P4.5/External Interrupt (INT13) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P4.4/External Interrupt (INT12) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P4.3/External Interrupt (INT11) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P4.2/External Interrupt (INT10) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P4.1/External Interrupt (INT9) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
P4.0/External Interrupt (INT8) Pending Bit
0
Clear pending bit (when write)
1
Interrupt request is pending (when read)
PRELIMINARY
4-43
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.39 P5CONH: Port 5 Control Register-High Byte (F0H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P5.7/XTIN Configuration Bits
.5–.4
.3–.2
.1–.0
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (XTIN)
1
1
Output mode, push-pull
P5.6/XTOUT Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Alternative function (XTOUT)
1
1
Output mode, push-pull
P5.5/CB (NOTE) Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Not available
1
1
Output mode, push-pull
P5.4/CA (NOTE) Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Not available
1
1
Output mode, push-pull
NOTE: Refer to LCON register in Chapter 15
PS032408-0220
PRELIMINARY
4-44
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.40 P5CONL: Port 5 Control Register-Low Byte (F1H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P5.3/VLC3 (NOTE) Configuration Bits
.5–.4
.3–.2
.1–.0
0
0
Input mode
0
1
Input mode, pull-up
1
0
Not available
1
1
Output mode, push-pull
P5.2/VLC2 (NOTE) Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Not available
1
1
Output mode, push-pull
P5.1/VLC1 (NOTE) Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Not available
1
1
Output mode, push-pull
P5.0/VLC0 (NOTE) Configuration Bits
0
0
Input mode
0
1
Input mode, pull-up
1
0
Not available
1
1
Output mode, push-pull
NOTE: Refer to LCON register in Chapter15
PS032408-0220
PRELIMINARY
4-45
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.41 P6CONH: Port 6 Control Register-High Byte (F2H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
–
–
–
–
0
0
0
0
Read/Write
–
–
–
–
RW
RW
RW
RW
Addressing Mode
Register addressing mode only
.7–.4
Not used for the S3F8S6B
.3–.2
P6.5/SEG33 Configuration Bits
.1–.0
PS032408-0220
0
0
Input mode
0
1
Not available
1
0
Alternative function (LCD signal)
1
1
Output mode
P6.4/SEG32 Configuration Bits
0
0
Input mode
0
1
Not available
1
0
Alternative function (LCD signal)
1
1
Output mode
PRELIMINARY
4-46
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.42 P6CONL: Port 6 Control Register-Low Byte (F3H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
P6.3/SEG31 Configuration Bits
.5–.4
.3–.2
.1–.0
PS032408-0220
0
0
Input mode
0
1
Not available
1
0
Alternative function (LCD signal)
1
1
Output mode
P6.2/SO/SEG30 Configuration Bits
0
0
Input mode
0
1
Alternative function (SO)
1
0
Alternative function (LCD signal)
1
1
Output mode
P6.1/SI/SEG29 Configuration Bits
0
0
Input mode (SI)
0
1
Not available
1
0
Alternative function (LCD signal)
1
1
Output mode
P6.0/SCK/SEG28 Configuration Bits
0
0
Input mode (SCK)
0
1
Alternative function (SCK out)
1
0
Alternative function (LCD signal)
1
1
Output mode
PRELIMINARY
4-47
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.43 P6PUR: Port 6 Pull-up Resistor Enable Register (F4H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
–
–
0
0
0
0
0
0
Read/Write
–
–
RW
RW
RW
RW
RW
RW
Addressing Mode
Register addressing mode only
.7–.6
Not used for the S3F8S6B
.5
P6.5 Pull-up Resistor Enable Bit
.4
0
Pull-up disable
1
Pull-up enable
P6.4 Pull-up Resistor Enable Bit
.3
0
Pull-up disable
1
Pull-up enable
P3.3 Pull-up Resistor Enable Bit
.2
0
Pull-up disable
1
Pull-up enable
P6.2 Pull-up Resistor Enable Bit
.1
0
Pull-up disable
1
Pull-up enable
P6.1 Pull-up Resistor Enable Bit
.0
0
Pull-up disable
1
Pull-up enable
P6.0 Pull-up Resistor Enable Bit
0
Pull-up disable
1
Pull-up enable
NOTE: A pull-up resistor of port 6 is automatically disabled only when the corresponding pin is selected as push-pull output or
alternative function.
PS032408-0220
PRELIMINARY
4-48
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.44 PNE6: Port 6 N-channel Open-drain Mode Register (F5H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
–
–
0
0
0
0
0
0
Read/Write
–
–
RW
RW
RW
RW
RW
RW
Addressing Mode
Register addressing mode only
.7–.6
Not used for the S3F8S6B
.5
P6.5 Output Mode Selection Bit
.4
.3
.2
.1
.0
PS032408-0220
0
Output mode, push-pull
1
Output mode, open-drain
P6.4 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P6.3 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P6.2 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P6.1 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
P6.0 Output Mode Selection Bit
0
Output mode, push-pull
1
Output mode, open-drain
PRELIMINARY
4-49
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.45 PGCON: Pattern Generation Module Control Register (D0H, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
–
–
–
–
0
0
0
0
Read/Write
–
–
–
–
RW
RW
RW
RW
Addressing Mode
Register addressing mode only
.7–.4
Not used for the S3F8S6B
.3
S/W Trigger Start Bit
.5
.1–.0
PS032408-0220
0
No effect
1
S/W trigger start (auto clear)
PG Operation Disable/Enable Selection Bit
0
PG operation disable
1
PG operation Enable
Detection Voltage Selection Bits
0
0
Timer A match signal trigging
0
1
Timer B overflow signal trigging
1
0
Timer D0 match signal trigging
1
1
S/W trigging
PRELIMINARY
4-50
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.46 PP: Register Page Pointer (DFH, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.4
Destination Register Page Selection Bits
0
0
0
0
Destination: page 0
0
0
0
1
Destination: page 1
0
0
1
0
Destination: page 2
0
0
1
1
Destination: page 3
0
1
0
0
Destination: page 4
0
1
0
1
Destination: page 5
0
1
1
0
Destination: page 6
0
1
1
1
Destination: page 7
1
0
0
0
Destination: page 8
Others
.3 – .0
Not used for the S3F8S6B
Source Register Page Selection Bits
0
0
0
0
Source: page 0
0
0
0
1
Source: page 1
0
0
1
0
Source: page 2
0
0
1
1
Source: page 3
0
1
0
0
Source: page 4
0
1
0
1
Source: page 5
0
1
1
0
Source: page 6
0
1
1
1
Source: page 7
1
0
0
0
Source: page 8
Others
Not used for the S3F8S6B
NOTE:
1.
In the S3F8S6B microcontroller, the internal register file is configured as nine pages (Pages 0-7, 8). The pages 0-7 are
used for general purpose register file.
2.
The page 8 of S3F8S6B is used for LCD data register (30H to 51H) and system register (00H to 2FH).
PS032408-0220
PRELIMINARY
4-51
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.47 RP0: Register Pointer 0 (D6H, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
1
1
0
0
0
–
–
–
RW
RW
RW
RW
RW
–
–
–
Read/Write
Addressing Mode
Register addressing only
.7–.3
Register Pointer 0 Address Value
Register pointer 0 can independently point to one of the 256 byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8 byte register slices at one time as active working register space. After a reset,
RP0 points to address C0H in register set 1, selecting the 8 byte working register
slice C0H–C7H.
.2–.0
PS032408-0220
Not used for the S3F8S6B
PRELIMINARY
4-52
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.48 RP1: Register Pointer 1 (D7H, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
1
1
0
0
1
–
–
–
RW
RW
RW
RW
RW
–
–
–
Read/Write
Addressing Mode
Register addressing only
.7 – .3
Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 256 byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8 byte register slices at one time as active working register space. After a reset,
RP1 points to address C8H in register set 1, selecting the 8 byte working register
slice C8H–CFH.
.2 – .0
PS032408-0220
Not used for the S3F8S6B
PRELIMINARY
4-53
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.49 SIOCON: SIO Control Register (E7H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
SIO Shift Clock Selection Bit
.6
.5
.4
.3
.2
.1
.0
PS032408-0220
0
Internal clock (P.S clock)
1
External clock (SCK)
Data Direction Control Bit
0
MSB-first mode
1
LSB-first mode
SIO Mode Selection Bit
0
Receive-only mode
1
Transmit/Receive mode
Shift Clock Edge Selection Bit
0
Tx at falling edges, Rx at rising edges
1
Tx at rising edges, Rx at falling edges
SIO Counter Clear and Shift Start Bit
0
No action
1
Clear 3-bit counter and start shifting
SIO Shift Operation Enable Bit
0
Disable shifter and clock counter
1
Enable shifter and clock counter
SIO Interrupt Enable Bit
0
Disable SIO Interrupt
1
Enable SIO Interrupt
SIO Interrupt Pending Bit
0
No interrupt pending (when read), Clear pending condition (when write)
1
Interrupt is pending
PRELIMINARY
4-54
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.50 SPH: Stack Pointer-High Byte (D8H, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
x
x
x
x
x
x
x
x
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.0
Stack Pointer Address (High Byte)
The high byte stack pointer value is the upper eight bits of the 16-bit stack pointer
address (SP15–SP8). The lower byte of the stack pointer value is located in register
SPL (D9H). The SP value is undefined following a reset.
4.1.51 SPL: Stack Pointer-Low Byte (D9H, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
x
x
x
x
x
x
x
x
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.0
Stack Pointer Address (Low Byte)
The low byte stack pointer value is the lower eight bits of the 16-bit stack pointer
address (SP7−SP0). The upper byte of the stack pointer value is located in register
SPH (D8H). The SP value is undefined following a reset.
PS032408-0220
PRELIMINARY
4-55
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.52 STPCON: Stop Control Register (F5H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.0
STOP Control Bits
10100101
Enable stop instruction
Other values
Disable stop instruction
NOTE: Before execute the STOP instruction. You must set this STPCON register as "10100101b". Otherwise the STOP
instruction will not execute as well as reset will be generated.
PS032408-0220
PRELIMINARY
4-56
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.53 SYM: System Mode Register (DEH, Set 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
–
–
x
x
x
0
0
RW
–
–
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
Not used, But you must keep "0"
.6–.5
Not used for the S3F8S6B
.4–.2
Fast Interrupt Level Selection Bits (1)
.1
0
0
0
IRQ0
0
0
1
IRQ1
0
1
0
IRQ2
0
1
1
IRQ3
1
0
0
IRQ4
1
0
1
IRQ5
1
1
0
IRQ6
1
1
1
IRQ7
Fast Interrupt Enable Bit (2)
.0
0
Disable fast interrupt processing
1
Enable fast interrupt processing
Global Interrupt Enable Bit (3)
0
Disable all interrupt processing
1
Enable all interrupt processing
NOTE:
1.
You can select only one interrupt level at a time for fast interrupt processing.
2.
Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.
3.
Following a reset, you must enable global interrupt processing by executing an EI instruction
(not by writing a "1" to SYM.0).
PS032408-0220
PRELIMINARY
4-57
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.54 TACON: Timer A Control Register (E2H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.5
Timer A Input Clock Selection Bits
.4–.3
.2
.1
.0
0
0
0
fxx/1024
0
0
1
fxx/256
0
1
0
fxx/64
0
1
1
fxx/8
1
0
0
fxx/1
1
0
1
External clock (TACLK) falling edge
1
1
0
External clock (TACLK) rising edge
1
1
1
Counter stop
Timer A Operating Mode Selection Bits
0
0
Interval mode (TAOUT)
0
1
Capture mode (Capture on rising edge, counter running, OVF can occur)
1
0
Capture mode (Capture on falling edge, counter running, OVF can occur)
1
1
PWM mode (OVF and match interrupt can occur)
Timer A Counter Enable Bit
0
No effect
1
Clear the timer A counter (when write)
Timer A Match/Capture Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Timer A Overflow Interrupt Enable Bit
0
Disable overflow interrupt
1
Enable overflow interrupt
NOTE: The TACON.2 value is automatically cleared to "0" after being cleared counter.
PS032408-0220
PRELIMINARY
4-58
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.55 TBCON: Timer B Control Register (E3H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
Timer B Input Clock Selection Bits
.5–.4
.3
.2
.1
.0
PS032408-0220
0
0
fxx/1
0
1
fxx/2
1
0
fxx/4
1
1
fxx/8
Timer B Interrupt Time Selection Bits
0
0
Generating after low data is borrowed
0
1
Generating after high data is borrowed
1
0
Generating after low and high data are borrowed
1
1
Not available
Timer B Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Timer B Start/Stop Bit
0
Stop timer B
1
Start timer B
Timer B Mode Selection Bit
0
One-shot mode
1
Repeat mode
Timer B Output Flip-flop Control Bit
0
TBOF is low (TBPWM: low level for low data, high level for high data)
1
TBOF is high (TBPWM: high level for low data, low level for high data)
PRELIMINARY
4-59
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.56 TCCON: Timer C Control Register (ECH, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
Timer C Start/Stop Bit
.6–.4
.3
.2
.1
.0
0
Stop Timer C
1
Start Timer C
Timer C 3-Bits Prescaler Bits
0
0
0
Non divided
0
0
1
Divided by 2
0
1
0
Divided by 3
0
1
1
Divided by 4
1
0
0
Divided by 5
1
0
1
Divided by 6
1
1
0
Divided by 7
1
1
1
Divided by 8
Timer C Counter Clear Bit
0
No effect
1
Clear the timer C counter (when write)
Timer C Mode Selection Bit
0
fxx/1 & PWM mode
1
fxx/64 & interval mode
Timer C Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Timer C Interrupt Pending Bit
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
NOTE: The TCCON.3 value is automatically cleared to "0" after being cleared counter.
PS032408-0220
PRELIMINARY
4-60
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.57 TD0CON: Timer D0 Control Register (FAH, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.5
Timer D0 Input Clock Selection Bits
.4–.3
.2
.1
.0
0
0
0
fxx/1024
0
0
1
fxx/256
0
1
0
fxx/64
0
1
1
fxx/8
1
0
0
fxx/1
1
0
1
External clock (TD0CLK) falling edge
1
1
0
External clock (TD0CLK) rising edge
1
1
1
Counter stop
Timer D0 Operating Mode Selection Bits
0
0
Interval mode (TD0OUT)
0
1
Capture mode (Capture on rising edge, counter running, OVF can occur)
1
0
Capture mode (Capture on falling edge, counter running, OVF can occur)
1
1
PWM mode (OVF and match interrupt can occur)
Timer D0 Counter Clear Bit
0
No effect
1
Clear the timer D0 counter (when write)
Timer D0 Match/Capture Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Timer D0 Overflow Interrupt Enable Bit
0
Disable overflow interrupt
1
Enable overflow interrupt
NOTE: The TD0CON.2 value is automatically cleared to "0" after being cleared counter.
PS032408-0220
PRELIMINARY
4-61
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.58 TD1CON: Timer D1 Control Register (FBH, Set 1, Bank 1)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.5
Timer D1 Input Clock Selection Bits
.4–.3
.2
.1
.0
0
0
0
fxx/1024
0
0
1
fxx/256
0
1
0
fxx/64
0
1
1
fxx/8
1
0
0
fxx/1
1
0
1
External clock (TD1CLK) falling edge
1
1
0
External clock (TD1CLK) rising edge
1
1
1
Counter stop
Timer D1 Operating Mode Selection Bits
0
0
Interval mode (TD1OUT)
0
1
Capture mode (Capture on rising edge, counter running, OVF can occur)
1
0
Capture mode (Capture on falling edge, counter running, OVF can occur)
1
1
PWM mode (OVF and match interrupt can occur)
Timer D1 Counter Clear Bit
0
No effect
1
Clear the timer D1 counter (when write)
Timer D1 Match/Capture Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Timer D1 Overflow Interrupt Enable Bit
0
Disable overflow interrupt
1
Enable overflow interrupt
NOTE: The TD1CON.2 value is automatically cleared to "0" after being cleared counter.
PS032408-0220
PRELIMINARY
4-62
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.59 UART0CONH: UART 0 Control Register-High Byte (14H, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
UART 0 Mode Selection Bits
.5
0
0
Mode 0: shift register (fU/(16 (BRDATA0+1)))
0
1
Mode 1: 8-bit UART (fU/(16 (BRDATA0+1)))
1
0
Mode 2: 9-bit UART (fU/16)
1
1
Mode 3: 9-bit UART (fU/(16 (BRDATA0+1)))
Multiprocessor Communication Enable Bit (for modes 2 and 3 only)
.4
0
Disable
1
Enable
Serial Data Receive Enable Bit
.3
0
Disable
1
Enable
TB8 (Only when UART0CONL.7 = 0)
Location of the 9th data bit to be transmitted in UART 0 mode 2 or 3 ("0" or "1")
NOTE:
.2
If the UART0CONL.7 = 1, This bit is "don't care".
RB8 (Only when UART0CONL.7 = 0)
Location of the 9th data bit that was received in UART 0 mode 2 or 3 ("0" or "1")
NOTE:
.1
If the UART0CONL.7 = 1, This bit is "don't care".
UART 0 Receive Interrupt Enable Bit
.0
0
Disable Rx interrupt
1
Enable Rx interrupt
UART 0 Receive Interrupt Pending Bit
0
No interrupt pending(when read), Clear pending bit(when write)
1
Interrupt is pending(when read)
NOTE:
1.
In mode 2 and 3, if the MCE bit is set to "1" then the receive interrupt will not be activated if the received 9 th data bit "0".
In mode 1, if MCE = "1" the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the MCE
bit should be "0".
2.
The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
PS032408-0220
PRELIMINARY
4-63
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.60 UART0CONL: UART 0 Control Register-Low Byte (15H, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
UART 0 Transmit Parity-bit Auto-Generation Enable Bit (for modes 2 and 3
only)
.6
0
Disable parity-bit auto-generation
1
Enable parity-bit auto-generation
UART 0 Transmit Parity-bit Selection Bit (for modes 2 and 3 only)
0
Even parity-bit
1
Odd parity-bit
NOTE:
.5
UART 0 Receive Parity-bit Selection Bit (for modes 2 and 3 only)
0
Even parity-bit check
1
Odd parity-bit check
NOTE:
.4
.1
.0
PS032408-0220
If the UART0CONL.7 = 0, This bit is "don't care".
UART 0 Receive Parity-bit Error Status Bit (for modes 2 and 3 only)
0
No parity-bit error
1
Parity-bit error
NOTE:
.3–.2
If the UART0CONL.7 = 0, This bit is "don't care".
If the UART0CONL.7 = 0, This bit is "don't care".
UART 0 Clock Selection Bits
0
0
fxx/8
0
1
fxx/4
1
0
fxx/2
1
1
fxx/1
UART 0 Transmit Interrupt Enable Bit
0
Disable Tx interrupt
1
Enable Tx interrupt
UART 0 Transmit Interrupt Pending Bit
0
No interrupt pending(when read), Clear pending bit(when write)
1
Interrupt is pending(when read)
PRELIMINARY
64
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.61 UART1CONH: UART 1 Control Register-High Byte (18H, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7–.6
UART 1 Mode Selection Bits
.5
0
0
Mode 0: shift register (fU/(16 (BRDATA1+1)))
0
1
Mode 1: 8-bit UART (fU/(16 (BRDATA1+1)))
1
0
Mode 2: 9-bit UART (fU/16)
1
1
Mode 3: 9-bit UART (fU/(16 (BRDATA1+1)))
Multiprocessor Communication Enable Bit (for modes 2 and 3 only)
.4
0
Disable
1
Enable
Serial Data Receive Enable Bit
.3
0
Disable
1
Enable
TB8 (Only when UART1CONL.7 = 0)
Location of the 9th data bit to be transmitted in UART 1 mode 2 or 3 ("0" or "1")
NOTE: If the UART1CONL.7 = 1, This bit is "don't care".
.2
RB8 (Only when UART1CONL.7 = 0)
Location of the 9th data bit that was received in UART 1 mode 2 or 3 ("0" or "1")
NOTE: If the UART1CONL.7 = 1, This bit is "don't care".
.1
UART 1 Receive Interrupt Enable Bit
.0
0
Disable Rx interrupt
1
Enable Rx interrupt
UART 1 Receive Interrupt Pending Bit
0
No interrupt pending (when read), Clear pending bit (when write)
1
Interrupt is pending (when read)
NOTE:
1.
In mode 2 and 3, if the MCE bit is set to "1" then the receive interrupt will not be activated if the received 9 th data bit "0".
In mode 1, if MCE = "1" the receive interrupt will not be activated if a valid stop bit was not received. In mode 0, the MCE
bit should be "0".
2.
The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits for serial data receive and transmit.
PS032408-0220
PRELIMINARY
4-65
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.62 UART1CONL: UART 1 Control Register-Low Byte (19H, Page 8)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
UART 1 Transmit Parity-bit Auto-Generation Enable Bit (for modes 2 and 3
only)
.6
0
Disable parity-bit auto-generation
1
Enable parity-bit auto-generation
UART 1 Transmit Parity-bit Selection Bit (for modes 2 and 3 only)
0
Even parity-bit
1
Odd parity-bit
NOTE: If the UART1CONL.7 = 0, This bit is "don't care".
.5
UART 1 Receive Parity-bit Selection Bit (for modes 2 and 3 only)
0
Even parity-bit check
1
Odd parity-bit check
NOTE: If the UART1CONL.7 = 0, This bit is "don't care".
.4
UART 1 Receive Parity-bit Error Status Bit (for modes 2 and 3 only)
0
No parity-bit error
1
Parity-bit error
NOTE: If the UART1CONL.7 = 0, This bit is "don't care".
.3–.2
.1
.0
PS032408-0220
UART 1 Clock Selection Bits
0
0
fxx/8
0
1
fxx/4
1
0
fxx/2
1
1
fxx/1
UART 1 Transmit Interrupt Enable Bit
0
Disable Tx interrupt
1
Enable Tx interrupt
UART 1 Transmit Interrupt Pending Bit
0
No interrupt pending(when read), Clear pending bit(when write)
1
Interrupt is pending(when read)
PRELIMINARY
66
S3F8S6B Product Specification
Chapter 4. Control Registers
4.1.63 WTCON: Watch Timer Control Register (E6H, Set 1, Bank 0)
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
RESET Value
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Read/Write
Addressing Mode
Register addressing mode only
.7
Watch Timer Clock Selection Bit
.6
.5–.4
.3–.2
.1
.0
0
Main system clock divided by 27 (fxx/128)
1
Sub system clock (fxt)
Watch Timer Interrupt Enable Bit
0
Disable watch timer interrupt
1
Enable watch timer interrupt
Buzzer Signal Selection Bits
0
0
0.5 kHz
0
1
1 kHz
1
0
2 kHz
1
1
4 kHz
Watch Timer Speed Selection Bits
0
0
Set watch timer interrupt to 0.5s
0
1
Set watch timer interrupt to 0.25s
1
0
Set watch timer interrupt to 0.125s
1
1
Set watch timer interrupt to 1.995 ms
Watch Timer Enable Bit
0
Disable watch timer; Clear frequency dividing circuits
1
Enable watch timer
Watch Timer Interrupt Pending Bit
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
NOTE: Watch timer clock frequency (fw) is assumed to be 32.768 kHz.
PS032408-0220
PRELIMINARY
4-67
S3F8S6B Product Specification
5
Chapter 5. Interrupt Structure
Interrupt Structure
5.1 Overview
The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU
recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has
more than one vector address, the vector priorities are established in hardware. A vector address can be assigned
to one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight
possible interrupt levels: IRQ0−IRQ7, also called level 0−level 7. Each interrupt level directly corresponds to an
interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from
device to device. The S3F8S6B interrupt structure recognizes eight interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is
determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR
settings lets you define more complex priority relationships between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The
maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for
S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector
priorities are set in hardware. S3F8S6B uses thirty vectors.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.
Each vector can have several interrupt sources. In the S3F8S6B interrupt structure, there are thirty possible
interrupt sources.
When a service routine starts, the respective pending bit should be either cleared automatically by hardware or
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which
method would be used to clear its respective pending bit.
PS032408-0220
PRELIMINARY
5-1
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.2 Interrupt Types
The three components of the S3C8 interrupt structure described before ⎯ levels, vectors, and sources ⎯ are
combined to determine the interrupt structure of an individual device and to make full use of its available interrupt
logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.
The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):
•
Type 1:
One level (IRQn) + one vector (V1) + one source (S1)
•
Type 2:
One level (IRQn) + one vector (V1) + multiple sources (S1 – Sn)
•
Type 3:
One level (IRQn) + multiple vectors (V1 − Vn) + multiple sources (S1 – Sn, Sn+1 − Sn+m)
In the S3F8S6B microcontroller, two interrupt types are implemented.
Type 1:
Levels
Vectors
Sources
IRQn
V1
S1
S1
Type 2:
IRQn
V1
S2
S3
Sn
Type 3:
IRQn
V1
S1
V2
S2
V3
S3
Vn
Sn
Sn + 1
Sn + 2
Sn + m
NOTES:
1. The number of Sn and Vn value is expandable.
2. In the S3F8S6B implementation, interrupt types 1 and 3 are used.
Figure 5-1
PS032408-0220
S3C8-Series Interrupt Types
PRELIMINARY
5-2
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.3 S3F8S6B Interrupt Structure
The S3F8S6B microcontroller supports thirty interrupt sources. All thirty of the interrupt sources have a
corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific
interrupt structure, as shown in Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single
level are fixed in hardware).
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed.
PS032408-0220
PRELIMINARY
5-3
S3F8S6B Product Specification
Levels
nRESET
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Chapter 5. Interrupt Structure
Vectors
Sources
100H
CEH
D0H
D2H
D4H
D8H
DAH
DCH
DEH
E4H
E6H
E8H
EAH
ECH
EEH
F0H
F2H
F4H
F6H
F8H
FAH
FCH
FEH
B0H
B2H
B4H
B6H
B8H
BAH
BCH
BEH
Basic Timer Overflow
Timer A Match/Capture
Timer A Overflow
Timer B Match
Timer C Match/Overflow
Timer D0 Match/Capture
Timer D0 Overflow
Timer D1 Match/Capture
Timer D1 Overflow
SIO Interrupt
Watch Timer Overflow
UART 0 Data Transmit
UART 0 Data Receive
UART 1 Data Transmit
UART 1 Data Receive
P2.0 External Interrupt
P2.1 External Interrupt
P2.2 External Interrupt
P2.3 External Interrupt
P2.4 External Interrupt
P2.5 External Interrupt
P2.6 External Interrupt
P2.7 External Interrupt
P4.0 External Interrupt
P4.1 External Interrupt
P4.2 External Interrupt
P4.3 External Interrupt
P4.4 External Interrupt
P4.5 External Interrupt
P4.6 External Interrupt
P4.7 External Interrupt
Reset/Clear
H/W
S/W
H/W, S/W
H/W
H/W, S/W
S/W
H/W, S/W
S/W
H/W, S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
NOTES:
1. Within a given interrupt level, the low vector address has high priority.
For example, CEH has higher priority than D0H within the level IRQ0 the priorities
within each level are set at the factory.
2. External interrupts are triggered by a rising or falling edge, depending on the
corresponding control register setting.
Figure 5-2
PS032408-0220
S3F8S6B Interrupt Structure
PRELIMINARY
5-4
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.4 Interrupt Vector Addresses
All interrupt vector addresses for the S3F8S6B interrupt structure are stored in the vector address area of the
internal 64KB ROM, 0H–FFFFH.; (see Figure 5-3).
You can allocate unused locations in the vector address area as normal program memory. If you do so, please be
careful not to overwrite any of the stored vector addresses (Table 5.1 lists all vector addresses).
The program reset address in the ROM is 0100H.
The reset address of ROM can be changed by Smart Option in the S3F8S6B (full-Flash device). Refer to the
Chapter 21. Embedded Flash Memory Interface for more detailed contents.
(HEX)
FFFFH
(Decimal)
65535
64K- bytes
Internal
Program
Memory Area
8FFH
Available
ISP Sector
255
Interrupt Vector Area
Smart option Area
0
FFH
3FH
3CH
00H
Byte
Figure 5-3
PS032408-0220
ROM Vector Address Area
PRELIMINARY
5-5
S3F8S6B Product Specification
Table 5.1
Chapter 5. Interrupt Structure
Interrupt Vectors
Vector Address
Decimal
Value
Hex
Value
256
100H
206
Request
Interrupt Source
Reset/Clear
Interrupt
Level
Priority
in Level
H/W
Basic timer overflow
Reset
−
CEH
Timer A match/capture
IRQ0
0
208
D0H
Timer A overflow
−
1
210
D2H
Timer B match
IRQ1
−
212
D4H
Timer C match/overflow
IRQ2
−
216
D8H
Timer D0 match/capture
IRQ3
0
218
DAH
Timer D0 overflow
−
1
220
DCH
Timer D1 match/capture
−
2
222
DEH
Timer D1 overflow
−
3
228
E4H
SIO interrupt
IRQ4
0
230
E6H
Watch timer overflow
−
1
232
E8H
UART 0 data transmit
IRQ5
0
234
EAH
UART 0 data receive
−
1
236
ECH
UART 1 data transmit
−
2
238
EEH
UART 1data receive
−
3
240
F0H
P2.0 external interrupt
IRQ6
0
242
F2H
P2.1 external interrupt
−
1
244
F4H
P2.2 external interrupt
−
2
246
F6H
P2.3 external interrupt
−
3
248
F8H
P2.4 external interrupt
−
4
250
FAH
P2.5 external interrupt
−
5
252
FCH
P2.6 external interrupt
−
6
254
FEH
P2.7 external interrupt
−
7
176
B0H
P4.0 external interrupt
IRQ7
0
178
B2H
P4.1 external interrupt
−
1
180
B4H
P4.2 external interrupt
−
2
182
B6H
P4.3 external interrupt
−
3
184
B8H
P4.4 external interrupt
−
4
186
BAH
P4.5 external interrupt
−
5
188
BCH
P4.6 external interrupt
−
6
190
BEH
P4.7 external interrupt
−
7
PS032408-0220
PRELIMINARY
S/W
5-6
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
NOTE:
1.
Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2.
If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.
PS032408-0220
PRELIMINARY
5-7
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.5 Enable/Disable Interrupt Instructions (EI, DI)
Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then
serviced as they occur according to the established priorities.
NOTE: The system initialization routine executed after a reset must always contain an EI instruction to globally enable the
interrupt structure.
During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.
5.6 System-Level Interrupt Control Registers
In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:
•
The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.
•
The interrupt priority register, IPR, controls the relative priorities of interrupt levels.
•
The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to
each interrupt source).
•
The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable
fast interrupts and control the activity of external interface, if implemented).
Table 5.2
Control Register
Interrupt mask register
Interrupt Control Register Overview
ID
R/W
IMR
R/W
Bit settings in the IMR register enable or disable interrupt
processing for each of the eight interrupt levels: IRQ0–IRQ7.
Controls the relative processing priorities of the interrupt levels.
The seven levels of S3F8S6B are organized into three groups:
A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3
and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
Interrupt priority register
IPR
R/W
Interrupt request register
IRQ
R
System mode register
SYM
R/W
Function Description
This register contains a request pending bit for each interrupt
level.
This register enables/disables fast interrupt processing, dynamic
global interrupt processing, and external interface control (An
external memory interface is implemented in the S3F8S6B
microcontroller).
NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.
PS032408-0220
PRELIMINARY
5-8
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.7 Interrupt Processing Control Points
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The
system-level control points in the interrupt structure are:
•
Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0)
•
Interrupt level enable/disable settings (IMR register)
•
Interrupt level priority settings (IPR register)
•
Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE: When writing an application program that handles interrupt processing, be sure to include the necessary register file
address (register pointer) information.
EI
S
RESET
R
Q
Interrupt Request Register
(Read-only)
Polling
Cycle
IRQ0-IRQ7,
Interrupts
Interrupt Priority
Register
Vector
Interrupt
Cycle
Interrupt Mask
Register
Global Interrupt Control (EI,
DI or SYM.0 manipulation)
Figure 5-4
PS032408-0220
Interrupt Function Diagram
PRELIMINARY
5-9
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.8 Peripheral Interrupt Control Registers
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by the related peripheral (see Table 5.3).
Table 5.3
Interrupt Source
Interrupt Source Control and Data Registers
Interrupt Level
Register(s)
Location(s) in Set 1
Timer A match/capture
Timer A overflow
IRQ0
TACON
TACNT
TADATA
E2H, bank 0
E0H, bank 0
E1H, bank 0
Timer B match
IRQ1
TBCON
TBDATAH
TBDATAL
E3H, bank 0
E4H, bank 0
E5H, bank 0
IRQ2
TCCON
TCCNT
TCDATA
ECH, bank 0
EAH, bank 0
EBH, bank 0
IRQ3
TD0CON
TD0CNTH
TD0CNTL
TD0DATAH
TD0DATAL
TD1CON
TD1CNTH
TD1CNTL
TD1DATAH
TD1DATAL
FAH, bank 1
F6H, bank 1
F7H, bank 1
F8H, bank 1
F9H, bank 1
FBH, bank 1
FCH, bank 1
FDH, bank 1
FEH, bank 1
FFH, bank 1
IRQ4
SIOCON
SIODATA
SIOPS
WTCON
E7H, bank 0
E8H, bank 0
E9H, bank 0
E6H, bank 0
IRQ5
UART0CONH
UART0CONL
UDATA0
BRDATA0
UART1CONH
UART1CONL
UDATA1
BRDATA1
14H, page 8
15H, page 8
16H, page 8
17H, page 8
18H, page 8
19H, page 8
1AH, page 8
1BH, page 8
IRQ6
P2CONH
P2CONL
P2INTH
P2INTL
P2PND
E6H, bank 1
E7H, bank 1
E8H, bank 1
E9H, bank 1
EAH, bank 1
IRQ7
P4CONH
P4CONL
P4INTH
P4INTL
P4PND
0CH, page 8
0DH, page 8
0EH, page 8
0FH, page 8
10H, page 8
Timer C match/overflow
Timer D0 match/capture
Timer D0 overflow
Timer D1 match/capture
Timer D1 overflow
SIO interrupt
Watch timer overflow
UART 0 data transmit
UART 0 data receive
UART 1 data transmit
UART 1 data receive
P2.0 external interrupt
P2.1 external interrupt
P2.2 external interrupt
P2.3 external interrupt
P2.4 external interrupt
P2.5 external interrupt
P2.6 external interrupt
P2.7 external interrupt
P4.0 external interrupt
P4.1 external interrupt
P4.2 external interrupt
P4.3 external interrupt
P4.4 external interrupt
PS032408-0220
PRELIMINARY
5-10
S3F8S6B Product Specification
Interrupt Source
P4.5 external interrupt
P4.6 external interrupt
P4.7 external interrupt
Interrupt Level
Chapter 5. Interrupt Structure
Register(s)
Location(s) in Set 1
NOTE: If a interrupt is un-mask (Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt
should be written after a DI instruction is executed.
During the Port 2 and Port 4 state change, the unexpected external interrupts are occurred.
The unexpected external interrupts are occurred by port 2 and port 4state change. Therefore before port 2 and
port 4 states are changed to any value, you can execute the DI, EI instructions and pending bit clear.
The following steps must be taken to change:
1.
2.
3.
4.
Use DI instruction.
Change P4CONH/L, P4INTH/L
Clear Port 4 Interrupt Pending Register (P4PND) to "00000000B"
Use EI instruction.
Example 5-1
How to Prevent the Unexpected External Interrupts
1. This example shows how to change from the normal port mode to the interrupt port mode.
LD
LD
LD
•
•
•
DI
LD
LD
LD
LD
LD
EI
PP,#10001000B
P4CONH,#10101010B
P4CONL,#10101010B
; Select page 8
; P4.7~.4 Alternative function (AD4-AD7)
; P4.3~.0 Alternative function (AD0-AD3)
; for external interrupt setting mode
P4CONH,#01010101B
; P4.7~.4 Input mode with pull-up for interrupt
P4CONL,# 01010101B
; P4.3~.0 Input mode with pull-up for interrupt
P4INTH,#01010101B
; P4.7~.4 Enable interrupt falling edge
P4INTL,# 01010101B
; P4.3~.0 Enable interrupt falling edge
P4PND,#00000000B
; P4.7~.0 Interrupt pending bit clear
•
•
2. This example shows how to change from the interrupt port mode to the normal port mode.
LD
LD
LD
•
•
•
DI
LD
LD
LD
LD
LD
EI
PP,#10001000B
P4CONH,# 01010101B
P4CONL,# 01010101B
; Select page 8
; P4.7~.4 Input mode with pull-up for interrupt
; P4.3~.0 Input mode with pull-up for interrupt
; for normal port setting mode
P4CONH,# 10101010B
; P4.7~.4 Alternative function (AD4-AD7)
P4CONL,# 10101010B
; P4.3~.0 Alternative function (AD0-AD3)
P4INTH,# 00000000B
; P4.7~.4 Disable interrupt falling edge
P4INTL,# 00000000B
; P4.3~.0 Disable interrupt falling edge
P4PND,# 00000000B
; P4.7~.0 Interrupt pending bit clear
•
PS032408-0220
PRELIMINARY
5-11
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.9 System Mode Register (SYM)
The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to
control fast interrupt processing (see Figure 5-5).
A reset clears SYM.1 and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4−SYM.2, is
undetermined.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be
included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly
to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions
for this purpose.
System Mode Register (SYM)
DEH, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
Always logic "0"
.1
.0
LSB
Global interrupt enable bit: (3)
0 = Disable all interrupts processing
1 = Enable all interrupts processing
Not used for the S3F8S6B
Fast interrupt level
selection bits: (1)
0 0 0 = IRQ0
0 0 1 = IRQ1
0 1 0 = IRQ2
0 1 1 = IRQ3
1 0 0 = IRQ4
1 0 1 = IRQ5
1 1 0 = IRQ6
1 1 1 = IRQ7
Fast interrupt enable bit: (2)
0 = Disable fast interrupts processing
1 = Enable fast interrupts processing
NOTES:
1. You can select only one interrupt level at a time for fast interrupt processing.
2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt processing for the
interrupt level currently selected by SYM.2-SYM.4.
3. Following a reset, you must enable global interrupt processing by executing EI instruction
(not by writing a "1" to SYM.0)
Figure 5-5
PS032408-0220
System Mode Register (SYM)
PRELIMINARY
5-12
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.10 Interrupt Mask Register (IMR)
The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required
settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of
an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's
IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions
using the Register addressing mode.
Interrupt Mask Register (IMR)
DDH, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
IRQ2
IRQ7
NOTE:
IRQ6
IRQ5
IRQ1
.0
LSB
IRQ0
IRQ3
Interrupt level enable :
0 = Disable (mask) interrupt level
1 = Enable (un-mask) interrupt level
Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.
Figure 5-6
PS032408-0220
IRQ4
.1
Interrupt Mask Register (IMR)
PRELIMINARY
5-13
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.11 Interrupt Priority Register (IPR)
The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in
the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be
written to their required settings by the initialization routine.
When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two
sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This
priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register
priority definitions (see Figure 5-7):
•
Group A
IRQ0, IRQ1
•
Group B
IRQ2, IRQ3, IRQ4
•
Group C
IRQ5, IRQ6, IRQ7
IPR
Group A
A1
IPR
Group B
A2
B1
IPR
Group C
B2
B21
IRQ0
IRQ1
IRQ2 IRQ3
Figure 5-7
C1
B22
IRQ4
C2
C21
IRQ5 IRQ6
C22
IRQ7
Interrupt Request Priority Groups
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B"
would select the relationship C > B > A.
The functions of the other IPR bit settings are as follows:
•
IPR.5 controls the relative priorities of group C interrupts.
•
Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,
6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.
•
IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
PS032408-0220
PRELIMINARY
5-14
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
Interrupt Priority Register (IPR)
FFH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
Group priority:
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
= Undefined
=B>C>A
=A>B>C
=B>A>C
=C>A>B
=C>B>A
=A>C>B
= Undefined
Group B:
0 = IRQ2 > (IRQ3, IRQ4)
1 = (IRQ3, IRQ4) > IRQ2
Subgroup B:
0 = IRQ3 > IRQ4
1 = IRQ4 > IRQ3
Group C:
0 = IRQ5 > (IRQ6, IRQ7)
1 = (IRQ6, IRQ7) > IRQ5
Subgroup C:
0 = IRQ6 > IRQ7
1 = IRQ7 > IRQ6
Figure 5-8
PS032408-0220
LSB
Group A:
0 = IRQ0 > IRQ1
1 = IRQ1 > IRQ0
D7 D4 D1
0
0
0
0
1
1
1
1
.0
Interrupt Priority Register (IPR)
PRELIMINARY
5-15
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.12 Interrupt Request Register (IRQ)
You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all
levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same number:
bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that
level. A "1" indicates that an interrupt request has been generated for that level.
IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the
IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific
interrupt levels. After a reset, all IRQ status bits are cleared to "0".
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is
disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,
however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events
occurred while the interrupt structure was globally disabled.
Interrupt Request Regis ter (IRQ)
DCH, Set 1, Read-only
MSB
.7
.6
IRQ7
IRQ6
.5
IRQ5
Figure 5-9
PS032408-0220
.4
IRQ4
.3
IRQ3
.2
IRQ2
.1
IRQ1
.0
LSB
IRQ0
Interrupt level reques t pending bits :
0 = Interrupt level is not pending
1 = Interrupt level is pending
Interrupt Request Register (IRQ)
PRELIMINARY
5-16
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.13 Interrupt Pending Function Types
5.13.1 Overview
There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt
service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.
5.13.2 Pending Bits Cleared Automatically by Hardware
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting
to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine,
and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written
by application software.
In the S3F8S6B interrupt structure, the timer A overflow interrupt (IRQ0), the timer B match interrupt (IRQ1), the
timer C match/overflow interrupt (IRQ2), the timer D0/D1 overflow interrupt (IRQ3) belongs to this category of
interrupts in which pending condition is cleared automatically by hardware.
5.13.3 Pending Bits Cleared by the Service Routine
The second type of pending bit is the one that should be cleared by program software. The service routine must
clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be
written to the corresponding pending bit location in the source's mode or control register.
Example 5-2
How to Clear an Interrupt Pending Bit
As the following examples are shown, a load instruction should be used to clear an interrupt pending bit.
1.
SB1
LD
P2PND, #11111011B
; Clear P2.2's interrupt pending bit
INTPND, #11111101B
; Clear timer A match/capture interrupt pending bit
•
•
•
IRET
2.
SB0
LD
•
•
•
IRET
PS032408-0220
PRELIMINARY
5-17
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.14 Interrupt Source Polling Sequence
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request bit to "1".
2. The CPU polling procedure identifies a pending condition for that source.
3. The CPU checks the sources interrupt level.
4. The CPU generates an interrupt acknowledge signal.
5. Interrupt logic determines the interrupt's vector address.
6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).
7. The CPU continues polling for interrupt requests.
5.15 Interrupt Service Routines
Before an interrupt request is serviced, the following conditions must be met:
•
Interrupt processing must be globally enabled (EI, SYM.0 = "1")
•
The interrupt level must be enabled (IMR register)
•
The interrupt level must have the highest priority if more than one levels are currently requesting service
•
The interrupt must be enabled at the interrupt's source (peripheral control register)
When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.
The CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.
2. Save the program counter (PC) and status flags to the system stack.
3. Branch to the interrupt vector to fetch the address of the service routine.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the
PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.
PS032408-0220
PRELIMINARY
5-18
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.16 Generating interrupt Vector Addresses
The interrupt vector area in the ROM (00H−FFH) contains the addresses of interrupt service routines that
correspond to each level in the interrupt structure.
Vectored interrupt processing follows this sequence:
1. Push the program counter's low-byte value to the stack.
2. Push the program counter's high-byte value to the stack.
3. Push the FLAG register values to the stack.
4. Fetch the service routine's high-byte address from the vector location.
5. Fetch the service routine's low-byte address from the vector location.
6. Branch to the service routine specified by the concatenated 16-bit vector address.
NOTE: A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H−FFH.
5.17 Nesting of Vectored Interrupts
It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced.
To do this, you must follow these steps:
1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).
2. Load the IMR register with a new mask value that enables only the higher priority interrupt.
3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it
occurs).
4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the
previous mask value from the stack (POP IMR).
5. Execute an IRET.
Depending on the application, you may be able to simplify the procedure above to some extent.
5.18 Instruction Pointer (IP)
The instruction pointer (IP) is adopted by all the S3C8-series microcontrollers to control the optional high-speed
interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP
registers are IPH (high byte, IP15−IP8) and IPL (low byte, IP7−IP0).
PS032408-0220
PRELIMINARY
5-19
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.19 Fast Interrupt Processing
The feature called fast interrupt processing allows an interrupt within a given level to be completed in
approximately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast
interrupt processing, you write the appropriate 3-bit value to SYM.4−SYM.2. Then, to enable fast interrupt
processing for the selected level, you set SYM.1 to "1".
Two other system registers support fast interrupt processing:
•
The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the
program counter values), and
•
When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register
called FLAGS' ("FLAGS prime").
NOTE: For the S3F8S6B microcontroller, the service routine for any one of the eight interrupts levels: IRQ0–IRQ7 can be
selected for fast interrupt processing.
5.20 Procedure for Initiating Fast Interrupts
To initiate fast interrupt processing, follow these steps:
1. Load the start address of the service routine into the instruction pointer (IP).
2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)
3. Write a "1" to the fast interrupt enable bit in the SYM register.
5.21 Fast Interrupt Service Routine
When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:
1. The contents of the instruction pointer and the PC are swapped.
2. The FLAG register values are written to the FLAGS' ("FLAGS prime") register.
3. The fast interrupt status bit in the FLAGS register is set.
4. The interrupt is serviced.
5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction
pointer and PC values are swapped back.
6. The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register.
7. The fast interrupt status bit in FLAGS is cleared automatically.
PS032408-0220
PRELIMINARY
5-20
S3F8S6B Product Specification
Chapter 5. Interrupt Structure
5.22 Relationship to Interrupt Pending Bit Types
As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by
hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the
application program's interrupt service routine. You can select fast interrupt processing for interrupts with either
type of pending condition clear function - by hardware or by software.
5.23 Programming Guidelines
Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the
SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,
including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast
interrupt service routine ends.
PS032408-0220
PRELIMINARY
5-21
S3F8S6B Product Specification
6
Chapter 6. Instruction Set
Instruction Set
6.1 Overview
The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8
microcontrollers. There are 78 instructions.
The powerful data manipulation capabilities and features of the instruction set include:
•
A full complement of 8-bit arithmetic and logic operations, including multiply and divide
•
No special I/O instructions (I/O control/data registers are mapped directly into the register file)
•
Decimal adjustment included in binary-coded decimal (BCD) operations
•
16-bit (word) data can be incremented and decremented
•
Flexible instructions for bit addressing, rotate, and shift operations
6.1.1 Data Types
The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be
set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least
significant (right-most) bit.
6.1.2 Register Addressing
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory
addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."
6.1.3 Addressing Modes
There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative
(RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to
Section 3, "Addressing Modes."
PS032408-0220
PRELIMINARY
6-1
S3F8S6B Product Specification
Table 6.1
Mnemonic
Chapter 6. Instruction Set
Instruction Group Summary
Operands
Instruction
Load Instructions
CLR
dst
Clear
LD
dst,src
Load
LDB
dst,src
Load bit
LDE
dst,src
Load external data memory
LDC
dst,src
Load program memory
LDED
dst,src
Load external data memory and decrement
LDCD
dst,src
Load program memory and decrement
LDEI
dst,src
Load external data memory and increment
LDCI
dst,src
Load program memory and increment
LDEPD
dst,src
Load external data memory with pre-decrement
LDCPD
dst,src
Load program memory with pre-decrement
LDEPI
dst,src
Load external data memory with pre-increment
LDCPI
dst,src
Load program memory with pre-increment
LDW
dst,src
Load word
POP
dst
Pop from stack
POPUD
dst,src
Pop user stack (decrementing)
POPUI
dst,src
Pop user stack (incrementing)
PUSH
src
Push to stack
PUSHUD
dst,src
Push user stack (decrementing)
PUSHUI
dst,src
Push user stack (incrementing)
Arithmetic Instructions
ADC
dst,src
Add with carry
ADD
dst,src
Add
CP
dst,src
Compare
DA
dst
Decimal adjust
DEC
dst
Decrement
DECW
dst
Decrement word
DIV
dst,src
Divide
INC
dst
Increment
INCW
dst
Increment word
MULT
dst,src
Multiply
SBC
dst,src
Subtract with carry
SUB
dst,src
Subtract
Logic Instructions
AND
dst,src
Logical AND
COM
dst
Complement
PS032408-0220
PRELIMINARY
6-2
S3F8S6B Product Specification
Chapter 6. Instruction Set
Mnemonic
Operands
Instruction
OR
dst,src
Logical OR
XOR
dst,src
Logical exclusive OR
Program Control Instructions
BTJRF
dst,src
Bit test and jump relative on false
BTJRT
dst,src
Bit test and jump relative on true
CALL
dst
Call procedure
CPIJE
dst,src
Compare, increment and jump on equal
CPIJNE
dst,src
Compare, increment and jump on non-equal
DJNZ
r,dst
Decrement register and jump on non-zero
ENTER
Enter
EXIT
Exit
IRET
Interrupt return
JP
cc,dst
Jump on condition code
JP
dst
Jump unconditional
JR
cc,dst
Jump relative on condition code
NEXT
Next
RET
Return
WFI
Wait for interrupt
Bit Manipulation Instructions
BAND
dst,src
Bit AND
BCP
dst,src
Bit compare
BITC
dst
Bit complement
BITR
dst
Bit reset
BITS
dst
Bit set
BOR
dst,src
Bit OR
BXOR
dst,src
Bit XOR
TCM
dst,src
Test complement under mask
TM
dst,src
Test under mask
Rotate and Shift Instructions
RL
dst
Rotate left
RLC
dst
Rotate left through carry
RR
dst
Rotate right
RRC
dst
Rotate right through carry
SRA
dst
Shift right arithmetic
SWAP
dst
Swap nibbles
CPU Control Instructions
CCF
Complement carry flag
DI
Disable interrupts
PS032408-0220
PRELIMINARY
6-3
S3F8S6B Product Specification
Mnemonic
Operands
Instruction
EI
Enable interrupts
IDLE
Enter Idle mode
NOP
No operation
RCF
Reset carry flag
SB0
Set bank 0
SB1
Set bank 1
SCF
Set carry flag
SRP
src
Set register pointers
SRP0
src
Set register pointer 0
SRP1
src
Set register pointer 1
STOP
PS032408-0220
Chapter 6. Instruction Set
Enter Stop mode
PRELIMINARY
6-4
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.2 Flags Register (FLAGS)
The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits,
FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2
are used for BCD arithmetic.
The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank
address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register
can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.
Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For
example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will
occur to the Flags register producing an unpredictable result.
Figure 6-1
PS032408-0220
System Flags Register (FLAGS)
PRELIMINARY
6-5
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.2.1 Flag Descriptions
C
Carry Flag (FLAGS.7)
The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to
the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the
specified register. Program instructions can set, clear, or complement the carry flag.
Z
Zero Flag (FLAGS.6)
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For
operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is
logic zero.
S
Sign Flag (FLAGS.5)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the
result. A logic zero indicates a positive number and a logic one indicates a negative number.
V
Overflow Flag (FLAGS.4)
The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than
– 128. It is also cleared to "0" following logic operations.
D
Decimal Adjust Flag (FLAGS.3)
The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a
subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by
programmers, and cannot be used as a test condition.
H
Half-Carry Flag (FLAGS.2)
The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows
out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous
addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a
program.
FIS
Fast Interrupt Status Flag (FLAGS.1)
The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.
When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET
instruction is executed.
BA
Bank Address Flag (FLAGS.0)
The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected,
bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and
is set to "1" (select bank 1) when you execute the SB1 instruction.
PS032408-0220
PRELIMINARY
6-6
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.2.2 Instruction Set Notation
Table 6.2
Flag Notation Conventions
Flag
Description
C
Carry flag
Z
Zero flag
S
Sign flag
V
Overflow flag
D
Decimal-adjust flag
H
Half-carry flag
0
Cleared to logic zero
1
Set to logic one
*
Set or cleared according to operation
–
Value is unaffected
x
Value is undefined
Table 6.3
Instruction Set Symbols
Symbol
Description
dst
Destination operand
src
Source operand
@
Indirect register address prefix
PC
Program counter
IP
Instruction pointer
FLAGS
RP
Flags register (D5H)
Register pointer
#
Immediate operand or register address prefix
H
Hexadecimal number suffix
D
Decimal number suffix
B
Binary number suffix
opc
PS032408-0220
Opcode
PRELIMINARY
6-7
S3F8S6B Product Specification
Table 6.4
Notation
cc
Chapter 6. Instruction Set
Instruction Notation Conventions
Description
Actual Operand Range
Condition code
See list of condition codes in Table 6-6.
r
Working register only
Rn (n = 0 to 15)
rb
Bit (b) of working register
Rn.b (n = 0 to 15, b = 0 to 7)
r0
Bit 0 (LSB) of working register
Rn (n = 0 to 15)
rr
Working register pair
RRp (p = 0, 2, 4, ..., 14)
R
Register or working register
reg or Rn (reg = 0–255, n = 0 to 15)
Rb
Bit "b" of register or working register
reg.b (reg = 0 to 255, b = 0 to 7)
RR
Register pair or working register pair
reg or RRp (reg = 0 to 254, even number only, where
p = 0, 2, ..., 14)
IA
Indirect addressing mode
addr (addr = 0 to 254, even number only)
Ir
Indirect working register only
@Rn (n = 0 to 15)
IR
Indirect register or indirect working
register
@Rn or @reg (reg = 0 to 255, n = 0 to 15)
Irr
Indirect working register pair only
@RRp (p = 0, 2, ..., 14)
Indirect register pair or indirect working
register pair
@RRp or @reg (reg = 0–254, even only, where
p = 0, 2, ..., 14)
Indexed addressing mode
#reg [Rn] (reg = 0 to 255, n = 0 to 15)
XS
Indexed (short offset) addressing mode
#addr [RRp] (addr = range – 128 to + 127, where
p = 0, 2, ..., 14)
xl
Indexed (long offset) addressing mode
#addr [RRp] (addr = range 0v65535, where
p = 0, 2, ..., 14)
da
Direct addressing mode
addr (addr = range 0−65535)
ra
Relative addressing mode
addr (addr = number in the range + 127 to – 128 that is
an offset relative to the address of the next instruction)
im
Immediate addressing mode
#data (data = 0 to 255)
iml
Immediate (long) addressing mode
#data (data = range 0 to 65535)
IRR
X
PS032408-0220
PRELIMINARY
6-8
S3F8S6B Product Specification
Table 6.5
Chapter 6. Instruction Set
Opcode Quick Reference
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
1
2
3
4
5
6
7
U
0
DEC
R1
DEC
IR1
ADD
r1,r2
ADD
r1,Ir2
ADD
R2,R1
ADD
IR2,R1
ADD
R1,IM
BOR
r0–Rb
P
1
RLC
R1
RLC
IR1
ADC
r1,r2
ADC
r1,Ir2
ADC
R2,R1
ADC
IR2,R1
ADC
R1,IM
BCP
r1.b, R2
P
2
INC
R1
INC
IR1
SUB
r1,r2
SUB
r1,Ir2
SUB
R2,R1
SUB
IR2,R1
SUB
R1,IM
BXOR
r0–Rb
E
3
JP
IRR1
SRP/0/1
IM
SBC
r1,r2
SBC
r1,Ir2
SBC
R2,R1
SBC
IR2,R1
SBC
R1,IM
BTJR
r2.b, RA
R
4
DA
R1
DA
IR1
OR
r1,r2
OR
r1,Ir2
OR
R2,R1
OR
IR2,R1
OR
R1,IM
LDB
r0–Rb
5
POP
R1
POP
IR1
AND
r1,r2
AND
r1,Ir2
AND
R2,R1
AND
IR2,R1
AND
R1,IM
BITC
r1.b
N
6
COM
R1
COM
IR1
TCM
r1,r2
TCM
r1,Ir2
TCM
R2,R1
TCM
IR2,R1
TCM
R1,IM
BAND
r0–Rb
I
7
PUSH
R2
PUSH
IR2
TM
r1,r2
TM
r1,Ir2
TM
R2,R1
TM
IR2,R1
TM
R1,IM
BIT
r1.b
B
8
DECW
RR1
DECW
IR1
PUSHUD
IR1,R2
PUSHUI
IR1,R2
MULT
R2,RR1
MULT
IR2,RR1
MULT
IM,RR1
LD
r1, x, r2
B
9
RL
R1
RL
IR1
POPUD
IR2,R1
POPUI
IR2,R1
DIV
R2,RR1
DIV
IR2,RR1
DIV
IM,RR1
LD
r2, x, r1
L
A
INCW
RR1
INCW
IR1
CP
r1,r2
CP
r1,Ir2
CP
R2,R1
CP
IR2,R1
CP
R1,IM
LDC
r1, Irr2,
xL
E
B
CLR
R1
CLR
IR1
XOR
r1,r2
XOR
r1,Ir2
XOR
R2,R1
XOR
IR2,R1
XOR
R1,IM
LDC
r2, Irr2,
xL
C
RRC
R1
RRC
IR1
CPIJE
Ir,r2,RA
LDC
r1,Irr2
LDW
RR2,RR1
LDW
IR2,RR1
LDW
RR1,IML
LD
r1, Ir2
H
D
SRA
R1
SRA
IR1
CPIJNE
Irr,r2,RA
LDC
r2,Irr1
CALL
IA1
LD
IR1,IM
LD
Ir1, r2
E
E
RR
R1
RR
IR1
LDCD
r1,Irr2
LDCI
r1,Irr2
LD
R2,R1
LD
R2,IR1
LD
R1,IM
LDC
r1, Irr2, xs
X
F
SWAP
R1
SWAP
IR1
LDCPD
r2,Irr1
LDCPI
r2,Irr1
CALL
IRR1
LD
IR2,R1
CALL
DA1
LDC
r2, Irr1, xs
PS032408-0220
PRELIMINARY
6-9
S3F8S6B Product Specification
Chapter 6. Instruction Set
OPCODE MAP
LOWER NIBBLE (HEX)
–
8
9
A
B
C
D
E
F
U
0
LD
r1,R2
LD
r2,R1
DJNZ
r1,RA
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
NEXT
P
1
ENTER
P
2
EXIT
E
3
WFI
R
4
SB0
5
SB1
N
6
IDLE
I
7
B
8
DI
B
9
EI
L
A
RET
E
B
IRET
C
RCF
H
D
E
E
X
F
PS032408-0220
STOP
SCF
CCF
LD
r1,R2
LD
r2,R1
DJNZ
r1,RA
JR
cc,RA
PRELIMINARY
LD
r1,IM
JP
cc,DA
INC
r1
NOP
6-10
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.2.3 Condition Codes
The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after
a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.
Table 6.6
Mnemonic
Condition Codes
Binary
Description
Flags Set
F
0000
Always false
−
T
1000
Always true
−
0111
(NOTE)
Carry
C=1
1111
(NOTE)
No carry
C=0
0110
(NOTE)
Zero
Z=1
NZ
1110
(NOTE)
Not zero
Z=0
PL
1101
Plus
S=0
MI
0101
Minus
S=1
OV
0100
Overflow
V=1
NOV
1100
No overflow
V=0
EQ
0110 (NOTE)
Equal
Z=1
NE
1110 (NOTE)
Not equal
Z=0
GE
1001
Greater than or equal
(S
XOR
V) = 0
LT
0001
Less than
(S
XOR
V) = 1
GT
1010
Greater than
(Z
OR (S
XOR
V)) = 0
LE
0010
Less than or equal
(Z
OR (S
XOR
V)) = 1
UGE
1111 (NOTE)
Unsigned greater than or equal
C=0
ULT
0111 (NOTE)
Unsigned less than
C=1
UGT
1011
Unsigned greater than
(C = 0
ULE
0011
Unsigned less than or equal
(C
C
NC
Z
OR
AND
Z = 0) = 1
Z) = 1
NOTE:
1.
It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and
EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction,
however, EQ would probably be used.
2.
For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
PS032408-0220
PRELIMINARY
6-11
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3 Instruction Descriptions
This section contains detailed information and programming examples for each instruction in the SAM8 instruction
set. Information is arranged in a consistent format for improved readability and for fast referencing.
The following information is included in each instruction description:
•
Instruction name (mnemonic)
•
Full instruction name
•
Source/destination format of the instruction operand
•
Shorthand notation of the instruction's operation
•
Textual description of the instruction's effect
•
Specific flag settings affected by the instruction
•
Detailed description of the instruction's format, execution time, and addressing mode(s)
•
Programming example(s) explaining how to use the instruction
PS032408-0220
PRELIMINARY
6-12
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.1 ADC - Add with carry
ADC
dst,src
Operation:
dst dst + src + c
The source operand, along with the setting of the carry flag, is added to the destination operand
and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the
carry from the addition of low-order operands to be carried into the addition of high-order
operands.
Flags:
C:
Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D:
Always cleared to "0".
H:
Set if there is a carry from the most significant bit of the low-order four bits of the result;
cleared otherwise.
Format:
opc
opc
opc
Examples:
dst | src
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
12
r
r
6
13
r
lr
6
14
R
R
6
15
R
IR
6
16
R
IM
3
src
3
Addr Mode
dst
src
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register
03H = 0AH:
ADC
ADC
ADC
ADC
ADC
R1,R2
R1,@R2
01H,02H
01H,@02H
01H,#11H
→
→
→
→
→
R1 = 14H, R2
R1 = 1BH, R2
Register 01H
Register 01H
Register 01H
=
=
=
=
=
03H
03H
24H, register 02H = 03H
2BH, register 02H = 03H
32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and
the source working register R2 contains the value 03H. The statement "ADC R1, R2" adds 03H
and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
PS032408-0220
PRELIMINARY
6-13
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.2 ADD - Add
ADD
dst,src
Operation:
dst dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
C:
Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D:
Always cleared to "0".
H:
Set if a carry from the low-order nibble occurred.
Format:
opc
opc
opc
Examples:
dst | src
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
02
r
r
6
03
r
lr
6
04
R
R
6
05
R
IR
6
06
R
IM
3
src
3
Addr Mode
dst
src
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD
ADD
ADD
ADD
ADD
R1,R2
R1,@R2
01H,02H
01H,@02H
01H,#25H
→
→
→
→
→
R1 = 15H, R2
R1 = 1CH, R2
Register 01H
Register 01H
Register 01H
=
=
=
=
=
03H
03H
24H, register 02H = 03H
2BH, register 02H = 03H
46H
In the first example, destination working register R1 contains 12H and the source working register
R2 contains 03H. The statement "ADD R1, R2" adds 03H to 12H, leaving the value 15H in
register R1.
PS032408-0220
PRELIMINARY
6-14
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.3 AND - Logical AND
AND
dst,src
Operation:
dst dst AND src
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits
in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the
source are unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always cleared to "0".
D:
Unaffected.
H:
Unaffected.
Format:
opc
opc
opc
Examples:
dst | src
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
52
r
r
6
53
r
lr
6
54
R
R
6
55
R
IR
6
56
R
IM
3
src
3
Addr Mode
dst
src
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND
AND
AND
AND
AND
R1,R2
R1,@R2
01H,02H
01H,@02H
01H,#25H
→
→
→
→
→
R1 = 02H, R2 = 03H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source
working register R2 contains 03H. The statement "AND R1, R2" logically ANDs the source
operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
PS032408-0220
PRELIMINARY
6-15
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.4 BAND - Bit AND
BAND
dst,src.b
BAND
dst.b,src
Operation:
dst(0) dst(0) AND src(b)
or
dst(b) dst(b) AND src(0)
The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the
destination (or source). The resultant bit is stored in the specified bit of the destination. No other
bits of the destination are affected. The source is unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Cleared to "0".
V:
Undefined.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | b | 0
src
3
6
67
r0
Rb
opc
src | b | 1
dst
3
6
67
Rb
r0
NOTE: In the second byte of the 3 byte instruction formats, the destination (or source) address is four bits, the bit address "b"
is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H and register 01H = 05H:
BAND
BAND
R1,01H.1
01H.1,R1
→
→
R1 = 06H, register 01H = 05H
Register 01H = 05H, R1 = 07H
In the first example, source register 01H contains the value 05H (00000101B) and destination
working register R1 contains 07H (00000111B). The statement "BAND R1, 01H.1" ANDs the bit
value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value
06H (00000110B) in register R1.
PS032408-0220
PRELIMINARY
6-16
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.5 BCP - Bit Compare
BCP
dst,src.b
Operation:
dst(0) – src(b)
The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands
are unaffected by the comparison.
Flags:
C:
Unaffected.
Z:
Set if the two bits are the same; cleared otherwise.
S:
Cleared to "0".
V:
Undefined.
D:
Unaffected.
H:
Unaffected.
Format:
opc
dst | b | 0
src
Bytes
Cycles
Opcode
(Hex)
3
6
17
Addr Mode
dst
src
r0
Rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address "b" is three bits, and
the LSB address value is one bit in length.
Example:
Given: R1 = 07H and register 01H = 01H:
BCP
R1,01H.1
→
R1 = 07H, register 01H = 01H
If destination working register R1 contains the value 07H (00000111B) and the source register
01H contains the value 01H (00000001B), the statement "BCP R1, 01H.1" compares bit one of
the source register (01H) and bit zero of the destination register (R1). Because the bit values are
not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).
PS032408-0220
PRELIMINARY
6-17
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.6 BITC - Bit Complement
BITC
dst.b
Operation:
dst(b) NOT dst(b)
This instruction complements the specified bit within the destination without affecting any other
bits in the destination.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Cleared to "0".
V:
Undefined.
D:
Unaffected.
H:
Unaffected.
Format:
opc
dst | b | 0
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
57
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address "b"
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H
BITC
R1.1
→
R1 = 05H
If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is
cleared.
PS032408-0220
PRELIMINARY
6-18
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.7 BITR - Bit Reset
BITR
dst.b
Operation:
dst(b) 0
The BITR instruction clears the specified bit within the destination without affecting any other bits
in the destination.
Flags:
No flags are affected.
Format:
dst | b |
0
opc
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
77
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address "b"
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BITR
R1.1
→
R1 = 05H
If the value of working register R1 is 07H (00000111B), the statement "BITR
of the destination register R1, leaving the value 05H (00000101B).
PS032408-0220
PRELIMINARY
R1.1" clears bit one
6-19
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.8 BITS - Bit Set
BITS
dst.b
Operation:
dst(b) 1
The BITS instruction sets the specified bit within the destination without affecting any other bits in
the destination.
Flags:
No flags are affected.
Format:
opc
dst | b | 1
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
77
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address "b"
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BITS
R1.3
→
R1 = 0FH
If working register R1 contains the value 07H (00000111B), the statement "BITS
three of the destination register R1 to "1", leaving the value 0FH (00001111B).
PS032408-0220
PRELIMINARY
R1.3" sets bit
6-20
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.9 BOR - Bit OR
BOR
dst,src.b
BOR
dst.b,src
Operation:
dst(0) dst(0) OR src(b)
or
dst(b) dst(b) OR src(0)
The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the
destination (or the source). The resulting bit value is stored in the specified bit of the destination.
No other bits of the destination are affected. The source is unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Cleared to "0".
V:
Undefined.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | b | 0
src
3
6
07
r0
Rb
opc
src | b | 1
dst
3
6
07
Rb
r0
NOTE: In the second byte of the 3 byte instruction formats, the destination (or source) address is four bits, the bit address "b"
is three bits, and the LSB address value is one bit.
Examples:
Given: R1 = 07H and register 01H = 03H:
BOR
BOR
R1, 01H.1
01H.2, R1
→
→
R1 = 07H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 contains the value 07H (00000111B) and
source register 01H the value 03H (00000011B). The statement "BOR R1, 01H.1" logically ORs
bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H)
in working register R1.
In the second example, destination register 01H contains the value 03H (00000011B) and the
source working register R1 the value 07H (00000111B). The statement "BOR 01H.2, R1" logically
ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in
register 01H.
PS032408-0220
PRELIMINARY
6-21
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.10 BTJRF - Bit Test, Jump Relative on False
BTJRF
dst,src.b
Operation:
If src(b) is a "0", then PC PC
+
dst
The specified bit within the source operand is tested. If it is a "0", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRF instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
3
10
37
(Note 1)
opc
src | b |
0
dst
Addr Mode
dst
src
RA
rb
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the
LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BTJRF
SKIP,R1.3
→
PC jumps to SKIP location
If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP, R1.3"
tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the
memory location pointed to by the SKIP. (Remember that the memory location must be within the
allowed range of + 127 to − 128.)
PS032408-0220
PRELIMINARY
6-22
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.11 BTJRT - Bit Test, Jump Relative on True
BTJRT
dst,src.b
Operation:
If src(b) is a "1", then PC PC + dst
The specified bit within the source operand is tested. If it is a "1", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRT instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
3
10
37
(Note 1)
opc
src | b | 1
dst
Addr Mode
dst
src
RA
rb
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the
LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BTJRT
SKIP, R1.1
If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP, R1.1"
tests bit one in the source register (R1). Because it is a "1", the relative address is added to the
PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the
memory location must be within the allowed range of + 127 to − 128.)
PS032408-0220
PRELIMINARY
6-23
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.12 BXOR - Bit XOR
BXOR
dst,src.b
BXOR
dst.b,src
Operation:
dst(0) dst(0) XOR src(b)
or
dst(b) dst(b) XOR src(0)
The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)
of the destination (or source). The result bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Cleared to "0".
V:
Undefined.
D:
Unaffected.
H:
Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | b | 0
src
3
6
27
r0
Rb
opc
src | b | 1
dst
3
6
27
Rb
r0
NOTE: In the second byte of the 3 byte instruction formats, the destination (or source) address is four bits, the bit address "b"
is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):
BXOR
BXOR
R1,01H.1
01H.2,R1
→
→
R1 = 06H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 has the value 07H (00000111B) and source
register 01H has the value 03H (00000011B). The statement "BXOR R1, 01H.1" exclusive-ORs
bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit
zero of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected.
PS032408-0220
PRELIMINARY
6-24
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.13 CALL - Call Procedure
CALL
dst
Operation:
SP
@SP
SP
@SP
PC
SP – 1
PCL
SP –1
PCH
dst
The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The
specified destination address is then loaded into the program counter and points to the first
instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to
return to the original program flow. RET pops the top of the stack back into the program counter.
Flags:
No flags are affected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
3
14
F6
DA
opc
dst
2
12
F4
IRR
opc
dst
2
14
D4
IA
Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:
CALL
3521H
→
CALL
CALL
@RR0
#40H
→
→
SP = 0000H
(Memory locations 0000H = 1AH, 0001H = 4AH, where
4AH is the address that follows the instruction.)
SP = 0000H (0000H = 1AH, 0001H = 49H)
SP = 0000H (0000H = 1AH, 0001H = 49H)
In the first example, if the program counter value is 1A47H and the stack pointer contains the
value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the
stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the
value 3521H, the address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack
location 0001H (because the two-byte instruction format was used). The PC is then loaded with
the value 3521H, the address of the first instruction in the program sequence to be executed.
Assuming that the contents of the program counter and stack pointer are the same as in the first
example, if program address 0040H contains 35H and program address 0041H contains 21H, the
statement "CALL #40H" produces the same result as in the second example.
PS032408-0220
PRELIMINARY
6-25
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.14 CCF - Complement Carry Flag
CCF
Operation:
C NOT C
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero;
if C = "0", the value of the carry flag is changed to logic one.
Flags:
C:
Complemented.
No other flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
EF
Given: The carry flag = "0":
CCF
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing
its value from logic zero to logic one.
PS032408-0220
PRELIMINARY
6-26
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.15 CLR - Clear
CLR
dst
Operation:
dst "0"
The destination location is cleared to "0".
Flags:
No flags are affected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
B0
R
4
B1
IR
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR
CLR
00H
@01H
→
→
Register 00H = 00H
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.
PS032408-0220
PRELIMINARY
6-27
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.16 COM - Complement
COM
dst
Operation:
dst NOT dst
The contents of the destination location are complemented (one's complement); all "1s" are
changed to "0s", and vice-versa.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to "0".
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Given: R1 = 07H and register 07H
COM
COM
R1
@R1
→
→
=
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
60
R
4
61
IR
0F1H:
R1 = 0F8H
R1 = 07H, register 07H = 0EH
In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,
and vice-versa, leaving the value 0F8H (11111000B).
In the second example, Indirect Register (IR) addressing mode is used to complement the value
of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
PS032408-0220
PRELIMINARY
6-28
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.17 CP - Compare
CP
dst,src
Operation:
dst – src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags are set accordingly. The contents of both operands are unaffected by the
comparison.
Flags:
C:
Set if a "borrow" occurred (src > dst); cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
dst | src
opc
src
opc
Examples:
1.
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
A2
r
r
6
A3
r
lr
6
A4
R
R
6
A5
R
IR
6
A6
R
IM
3
src
3
Addr Mode
dst
src
Given: R1 = 02H and R2 = 03H:
CP
R1,R2
→
Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value
03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value
(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1".
2.
Given: R1 = 05H and R2 = 0AH:
CP
JP
INC
SKIP
R1,R2
UGE,SKIP
R1
LD
R3,R1
In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"
and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"
executes, the value 06H remains in working register R3.
PS032408-0220
PRELIMINARY
6-29
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.18 CPIJE - Compare, Increment, and Jump on Equal
CPIJE
dst,src,RA
Operation:
If dst – src =
Ir
0", PC
PC + RA
Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result is "0",
the relative address is added to the program counter and control passes to the statement whose
address is now in the program counter. Otherwise, the instruction immediately following the
CPIJE instruction is executed. In either case, the source pointer is incremented by one before the
next instruction is executed.
Flags:
No flags are affected.
Format:
opc
src
dst
RA
Bytes
Cycles
Opcode
(Hex)
3
12
C2
Addr Mode
dst
src
r
Ir
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 02H:
CPIJE
R1,@R2,SKIP
→
R2 = 04H, PC jumps to SKIP location
In this example, working register R1 contains the value 02H, working register R2 the value 03H,
and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value
02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that
the memory location must be within the allowed range of + 127 to − 128.)
PS032408-0220
PRELIMINARY
6-30
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.19 CPIJNE - Compare, Increment, and Jump on Non-Equal
CPIJNE
Operation:
dst,src,RA
If dst – src "0", PC
Ir
PC + RA
Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result is not
"0", the relative address is added to the program counter and control passes to the statement
whose address is now in the program counter; otherwise the instruction following the CPIJNE
instruction is executed. In either case the source pointer is incremented by one before the next
instruction.
Flags:
No flags are affected.
Format:
opc
src
dst
RA
Bytes
Cycles
Opcode
(Hex)
3
12
D2
Addr Mode
dst
src
r
Ir
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 04H:
CPIJNE R1,@R2,SKIP
→
R2 = 04H, PC jumps to SKIP location
Working register R1 contains the value 02H, working register R2 (the source pointer) the value
03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts
04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.
(Remember that the memory location must be within the allowed range of + 127 to − 128.)
PS032408-0220
PRELIMINARY
6-31
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.20 DA - Decimal Adjust
DA
dst
Operation:
dst DA dst
The destination operand is adjusted to form two 4-bit BCD digits following an addition or
subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table
indicates the operation performed. (The operation is undefined if the destination operand was not
the result of a valid addition or subtraction of BCD digits):
Carry
Before DA
Bits 4−7
Value (Hex)
H Flag
Before DA
Bits 0−3
Value (Hex)
Number Added
to Byte
Carry
After DA
0
0−9
0
0−9
00
0
0
0−8
0
A−F
06
0
0
0−9
1
0−3
06
0
ADD
0
A−F
0
0−9
60
1
ADC
0
9−F
0
A−F
66
1
0
A−F
1
0−3
66
1
1
0−2
0
0−9
60
1
1
0−2
0
A−F
66
1
1
0−3
1
0−3
66
1
0
0−9
0
0−9
00
=
− 00
0
SUB
0
0−8
1
6−F
FA
=
− 06
0
SBC
1
7−F
0
0−9
A0
=
− 60
1
1
6−F
1
6−F
9A
=
− 66
1
Instruction
Flags:
C:
Set if there was a carry from the most significant bit; cleared otherwise (see table).
Z:
Set if result is "0"; cleared otherwise.
S:
Set if result bit 7 is set; cleared otherwise.
V:
Undefined.
D:
Unaffected.
H:
Unaffected.
Format:
opc
PS032408-0220
dst
PRELIMINARY
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
40
R
4
41
IR
6-32
S3F8S6B Product Specification
Example:
Chapter 6. Instruction Set
Given: Working register R0 contains the value 15 (BCD), working register R1 contains
27 (BCD), and address 27H contains 46 (BCD):
ADD
DA
R1,R0
R1
;
;
C "0", H "0", Bits 4−7 = 3, bits 0−3 = C, R1 3CH
R1 3CH + 06
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is
incorrect, however, when the binary representations are added in the destination location using
standard binary arithmetic:
+
0001
0010
0011
0 1 0 1 15
0 1 1 1 27
1 1 0 0 = 3CH
The DA instruction adjusts this result so that the correct BCD representation is obtained:
+
0011
0000
0100
1100
0110
0 0 1 0 = 42
Assuming the same values given above, the statements
SUB
DA
27H,R0 ;
@R1
;
C "0", H "0", Bits 4–7 = 3, bits 0–3 = 1
@R1 31–0
leave the value 31 (BCD) in address 27H (@R1).
PS032408-0220
PRELIMINARY
6-33
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.21 DEC - Decrement
DEC
dst
Operation:
dst dst − 1
The contents of the destination operand are decremented by one.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
00
R
4
01
IR
Given: R1 = 03H and register 03H = 10H:
DEC
DEC
R1
@R1
→
→
R1 = 02H
Register 03H
0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1"
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by
one, leaving the value 0FH.
PS032408-0220
PRELIMINARY
6-34
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.22 DECW - Decrement Word
DECW
dst
Operation:
dst dst – 1
The contents of the destination location (which must be an even address) and the operand
following that location are treated as a single 16-bit value that is decremented by one.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
8
80
RR
8
81
IR
Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:
DECW
RR0
→
R0 = 12H, R1 = 33H
DECW
@R2
→→
Register 30H = 0FH, register 31H = 20H
In the first example, destination register R0 contains the value 12H and register R1 the value 34H.
The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and
decrements the value of R1 by one, leaving the value 33H.
NOTE: A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid
this problem, we recommend that you use DECW as shown in the following example:
LOOP:
PS032408-0220
DECW
LD
OR
JR
RR0
R2,R1
R2,R0
NZ,LOOP
PRELIMINARY
6-35
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.23 DI - Disable Interrupts
DI
Operation:
SYM (0) 0
Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all
interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,
but the CPU will not service them while interrupt processing is disabled.
Flags:
No flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
8F
Given: SYM = 01H:
DI
If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the
register and clears SYM.0 to "0", disabling interrupt processing.
Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.
PS032408-0220
PRELIMINARY
6-36
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.24 DIV - Divide (Unsigned)
DIV
dst,src
Operation:
dst src
dst (UPPER) REMAINDER
dst (LOWER) QUOTIENT
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is
stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the
destination. When the quotient is 28, the numbers stored in the upper and lower halves of the
destination for quotient and remainder are incorrect. Both operands are treated as unsigned
integers.
Flags:
C:
Set if the V flag is set and quotient is between 28 and 29 –1; cleared otherwise.
Z:
Set if divisor or quotient = "0"; cleared otherwise.
S:
Set if MSB of quotient = "1"; cleared otherwise.
V:
Set if quotient is 28 or if divisor = "0"; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
src
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
3
26/10
94
RR
R
26/10
95
RR
IR
26/10
96
RR
IM
NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.
Examples:
Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:
DIV
DIV
DIV
RR0,R2
RR0,@R2
RR0,#20H
→
→
→
R0 = 03H, R1 = 40H
R0 = 03H, R1 = 20H
R0 = 03H, R1 = 80H
In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H
(R1), and register R2 contains the value 40H. The statement "DIV RR0, R2" divides the 16-bit
RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the
value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination
register RR0 (R0) and the quotient in the lower half (R1).
PS032408-0220
PRELIMINARY
6-37
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.25 DJNZ - Decrement and Jump if Non-Zero
DJNZ
r,dst
Operation:
rr–1
If r 0, PC PC + dst
The working register being used as a counter is decremented. If the contents of the register are
not logic zero after decrementing, the relative address is added to the program counter and
control passes to the statement whose address is now in the PC. The range of the relative
address is + 127 to – 128, and the original value of the PC is taken to be the address of the
instruction byte following the DJNZ statement.
NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location
0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.
Flags:
No flags are affected.
Format:
r
Example:
|
opc
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
8 (jump taken)
rA
RA
8 (no jump)
r = 0 to F
Given: R1 = 02H and LOOP is the label of a relative address:
SRP
DJNZ
#0C0H
R1,LOOP
DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the
destination operand instead of a numeric relative address value. In the example, working register
R1 contains the value 02H, and LOOP is the label for a relative address.
The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.
Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative
address specified by the LOOP label.
PS032408-0220
PRELIMINARY
6-38
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.26 EI - Enable Interrupts
EI
Operation:
SYM (0) 1
An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to
be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was
set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when
you execute the EI instruction.
Flags:
No flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
9F
Given: SYM = 00H:
EI
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the
statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for
global interrupt processing.)
PS032408-0220
PRELIMINARY
6-39
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.27 ENTER - Enter
ENTER
Operation:
SP
@SP
IP
PC
IP
SP – 2
IP
PC
@IP
IP + 2
This instruction is useful when implementing threaded-code languages. The contents of the
instruction pointer are pushed to the stack. The program counter (PC) value is then written to the
instruction pointer. The program memory word that is pointed to by the instruction pointer is
loaded into the PC, and the instruction pointer is incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
1
14
1F
opc
Example:
The diagram below shows one example of how to use an ENTER statement.
Before
Address
IP
After
Data
Address
0050
IP
Address
PC
0040
SP
0022
22
Data
40
41
42
43
Data
Enter
1F
Address H 01
Address L 10
Address H
Mem ory
Stack
PS032408-0220
Data
0043
Address
PC
0110
SP
0020
20
21
22
IPH
IPL
Data
40
41
42
43
00
50
110
Data
Enter
1F
Address H 01
Address L 10
Address H
Routine
Mem ory
Stack
PRELIMINARY
6-40
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.28 EXIT - Exit
EXIT
Operation:
IP
SP
PC
IP
@SP
SP + 2
@IP
IP + 2
This instruction is useful when implementing threaded-code languages. The stack value is
popped and loaded into the instruction pointer. The program memory word that is pointed to by
the instruction pointer is then loaded into the program counter, and the instruction pointer is
incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode (Hex)
1
14 (internal stack)
2F
opc
16 (internal stack)
Example:
The diagram below shows one example of how to use an EXIT statement.
Before
Address
IP
After
Data
Address
0050
IP
Address
PC
SP
0022
20
21
22
IPH
IPL
Data
140
PCL old
PCH
Exit
Data
0060
60
00
60
SP
0022
22
Data
Main
2F
Mem ory
Stack
PS032408-0220
Address
PC
00
50
0052
Data
0040
50
51
Data
Mem ory
Stack
PRELIMINARY
6-41
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.29 IDLE - Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle
mode can be released by an interrupt request (IRQ) or an external reset operation.
Flags:
No flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
6F
Addr Mode
dst
src
–
–
The instruction
IDLE
stops the CPU clock but not the system clock.
PS032408-0220
PRELIMINARY
6-42
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.30 INC - Increment
INC
dst
Operation:
dst dst + 1
The contents of the destination operand are incremented by one.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
dst
|
opc
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
1
4
rE
r
r = 0 to F
opc
Examples:
dst
2
4
20
R
4
21
IR
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:
INC
INC
INC
R0
00H
@R0
→
→
→
R0 = 1CH
Register 00H = 0DH
R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement
"INC R0" leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it
contains the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value
of register 1BH from 0FH to 10H.
PS032408-0220
PRELIMINARY
6-43
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.31 INCW - Increment Word
INCW
dst
Operation:
dst dst + 1
The contents of the destination (which must be an even address) and the byte following that
location are treated as a single 16-bit value that is incremented by one.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
8
A0
RR
8
A1
IR
Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:
INCW
INCW
RR0
@R1
→
→
R0 = 1AH, R1 = 03H
Register 02H = 10H, register 03H = 00H
In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H
in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the
value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect
Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to
00H and register 02H from 0FH to 10H.
NOTE: A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW instruction. To
avoid this problem, we recommend that you use INCW as shown in the following example:
LOOP:
PS032408-0220
INCW
LD
OR
JR
RR0
R2,R1
R2,R0
NZ,LOOP
PRELIMINARY
6-44
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.32 IRET - Interrupt Return
IRET
IRET (Normal) IRET (Fast)
Operation:
FLAGS @SP
SP SP + 1
PC @SP
SP SP + 2
SYM(0) 1
PC IP
FLAGS FLAGS'
FIS 0
This instruction is used at the end of an interrupt service routine. It restores the flag register and
the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the
fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast
interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.
Flags:
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
Format:
IRET
(Normal)
Bytes
Cycles
Opcode (Hex)
opc
1
10 (internal stack)
BF
12 (internal stack)
Example:
IRET
(Fast)
Bytes
Cycles
Opcode (Hex)
opc
1
6
BF
In the figure below, the instruction pointer is initially loaded with 100H in the main program before
interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are
swapped. This causes the PC to jump to address 100H and the IP to keep the return address.
The last instruction in the service routine normally is a jump to IRET at address FFH. This causes
the instruction pointer to be loaded with 100H "again" and the program counter to jump back to
the main program. Now, the next interrupt can occur and the IP is still correct at 100H.
0H
FFH
100H
IRET
Interrupt
Service
Routine
JP to FFH
FFFFH
NOTE: In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of
the last two instructions. The IRET cannot be immediately proceeded by a clearing of the interrupt status (as with a
reset of the IPR register).
PS032408-0220
PRELIMINARY
6-45
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.33 JP - Jump
JP
cc,dst (Conditional)
JP
dst
Operation:
If
(Unconditional)
is true, PC dst
cc
The conditional JUMP instruction transfers program control to the destination address if the
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP
instruction is executed. The unconditional JP simply replaces the contents of the PC with the
contents of the specified register pair. Control then passes to the statement addressed by the PC.
Flags:
No flags are affected.
Format: (1)
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
3
8
ccD
DA
(2)
cc
|
opc
dst
cc = 0 to F
opc
dst
2
8
30
IRR
NOTE:
1.
The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump.
2.
In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:
JP
C,LABEL_W
JP
@00H
→
→
LABEL_W = 1000H, PC = 1000H
PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement
"JP C, LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to
that location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.
The second example shows an unconditional JP. The statement "JP @00" replaces the contents
of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
PS032408-0220
PRELIMINARY
6-46
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.34 JR - Jump Relative
JR
cc,dst
Operation:
If
is true, PC PC + dst
cc
If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program
counter; otherwise, the instruction following the JR instruction is executed.; (see list of condition
codes).
The range of the relative address is + 127, – 128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
6
ccB
RA
(1)
cc
|
opc
dst
cc = 0 to F
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H:
JR
C,LABEL_X
→
PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C, LABEL_X" will
pass control to the statement whose address is now in the PC. Otherwise, the program instruction
following the JR would be executed.
PS032408-0220
PRELIMINARY
6-47
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.35 LD - Load
LD
dst,src
Operation:
dst src
The contents of the source are loaded into the destination. The source's contents are unaffected.
Flags:
No flags are affected.
Format:
dst
src
|
|
opc
src
opc
dst
Bytes
Cycles
Opcode
(Hex)
2
4
rC
r
IM
4
r8
r
R
4
r9
R
r
2
Addr Mode
dst
src
r = 0 to F
opc
dst
opc
src
src
opc
2
dst
dst
opc
PS032408-0220
|
src
src
3
3
4
C7
r
lr
4
D7
Ir
r
6
E4
R
R
6
E5
R
IR
6
E6
R
IM
6
D6
IR
IM
dst
3
6
F5
IR
R
opc
dst
|
src
x
3
6
87
r
x [r]
opc
src
|
dst
x
3
6
97
x [r]
r
PRELIMINARY
6-48
S3F8S6B Product Specification
Examples:
Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H,
LOOP = 30H and register 3AH = 0FFH:
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
PS032408-0220
Chapter 6. Instruction Set
R0,#10H
R0,01H
01H,R0
R1,@R0
@R0,R1
00H,01H
02H,@00H
00H,#0AH
@00H,#10H
@00H,02H
R0,#LOOP[R1]
#LOOP[R0],R1
→
→
→
→
→
→
→
→
→
→
→
→
R0 = 10H
R0 = 20H, register 01H = 20H
Register 01H = 01H, R0 = 01H
R1 = 20H, R0 = 01H
R0 = 01H, R1 = 0AH, register 01H
Register 00H = 20H, register 01H
Register 02H = 20H, register 00H
Register 00H = 0AH
Register 00H = 01H, register 01H
Register 00H = 01H, register 01H
R0 = 0FFH, R1 = 0AH
Register 31H = 0AH, R0 = 01H, R1
PRELIMINARY
= 0AH
= 20H
= 01H
= 10H
= 02, register 02H = 02H
= 0AH
6-49
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.36 LDB - Load Bit
LDB
dst,src.b
LDB
dst.b,src
Operation:
dst(0) src(b)
or
dst(b) src(0)
The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the
source is loaded into the specified bit of the destination. No other bits of the destination are
affected. The source is unaffected.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | b |
0
src
3
6
47
r0
Rb
opc
src | b |
1
dst
3
6
47
Rb
r0
NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit address "b" is
three bits, and the LSB address value is one bit in length.
Examples:
Given: R0 = 06H and general register 00H = 05H:
LDB
LDB
R0,00H.2
00H.0,R0
→
→
R0 = 07H, register 00H = 05H
R0 = 06H, register 00H = 04H
In the first example, destination working register R0 contains the value 06H and the source
general register 00H the value 05H. The statement "LD R0, 00H.2" loads the bit two value of the
00H register into bit zero of the R0 register, leaving the value 07H in register R0.
In the second example, 00H is the destination register. The statement "LD 00H.0, R0" loads bit
zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general
register 00H.
PS032408-0220
PRELIMINARY
6-50
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.37 LDC/LDE - Load Memory
LDC/LDE
dst,src
Operation:
dst src
This instruction loads a byte from program or data memory into a working register or vice-versa.
The source values are unaffected. LDC refers to program memory and LDE to data memory. The
assembler makes "Irr" or "rr" values an even number for program memory and odd an odd
number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
1.
opc
dst | src
2
10
C3
r
Irr
2.
opc
src | dst
2
10
D3
Irr
r
3.
opc
dst | src
XS
3
12
E7
r
XS
[rr]
4.
opc
src | dst
XS
3
12
F7
XS
[rr]
r
5.
opc
dst | src
XLL
XLH
4
14
A7
r
XL [rr]
6.
opc
src | dst
XLL
XLH
4
14
B7
XL [rr]
r
7.
opc
dst | 0000
DAL
DAH
4
14
A7
r
DA
8.
opc
src | 0000
DAL
DAH
4
14
B7
DA
r
9.
opc
dst | 0001
DAL
DAH
4
14
A7
r
DA
10.
opc
src | 0001
DAL
DAH
4
14
B7
DA
r
NOTE:
1.
The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.
2.
For formats 3 and 4, the destination address "XS [rr]" and the source address "XS [rr]" are each one byte.
3.
For formats 5 and 6, the destination address "XL [rr]" and the source address "XL [rr]" are each two bytes.
4.
The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in
formats 9 and 10, are used to address data memory.
PS032408-0220
PRELIMINARY
6-51
S3F8S6B Product Specification
Examples:
Chapter 6. Instruction Set
Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations
0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations
0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:
LDC
R0,@RR2
LDE
R0,@RR2
LDC (NOTE) @RR2,R0
LDE
@RR2,R0
LDC
R0,#01H[RR2]
LDE
R0,#01H[RR2]
;R0
;R0
;R0
;R0
contents
= 1AH, R2 =
contents
= 2AH, R2 =
of program memory location 0104H
01H, R3 = 04H
of external data memory location 0104H
01H, R3 = 04H
;11H (contents of R0) is loaded into program memory
;location 0104H (RR2),
;working registers R0, R2, R3 → no change
;11H (contents of R0) is loaded into external data memory
;location 0104H (RR2),
;working registers R0, R2, R3 → no change
;R0 contents of program memory location 0105H
;(01H + RR2),
;R0 = 6DH, R2 = 01H, R3 = 04H
;R0 contents of external data memory location 0105H
;(01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H
LDC (NOTE) #01H[RR2],R0;11H (contents of R0) is loaded into program memory location
;0105H (01H + 0104H)
LDE
#01H[RR2],R0
;11H (contents of R0) is loaded into external data memory
;location 0105H (01H + 0104H)
LDC
R0,#1000H[RR2] ;R0 contents of program memory location 1104H
;(1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H
LDE
R0,#1000H[RR2] ;R0 contents of external data memory location 1104H
;(1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H
LDC
R0,1104H
;R0 contents of program memory location 1104H, R0 = 88H
LDE
R0,1104H
;R0 contents of external data memory location 1104H,
;R0 = 98H
LDC (NOTE) 1105H,R0
;11H (contents of R0) is loaded into program memory location
LDE
1105H,R0
;1105H, (1105H) 11H
;11H (contents of R0) is loaded into external data memory
;location 1105H, (1105H) 11H
NOTE: These instructions are not supported by masked ROM type devices.
PS032408-0220
PRELIMINARY
6-52
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.38 LDCD/LDED - Load Memory and Decrement
LDCD/LDED
dst,src
Operation:
dst src
rr rr – 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler
makes "Irr" an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
opc
Examples:
PS032408-0220
dst | src
Bytes
Cycles
Opcode
(Hex)
2
10
E2
Addr Mode
dst
src
r
Irr
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH,
and external data memory location 1033H = 0DDH:
LDCD
R8,@RR6
;
;
;
0CDH (contents of program memory location 1033H) is loaded
into R8 and RR6 is decremented by one
R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 − 1)
LDED
R8,@RR6
;
;
;
0DDH (contents of data memory location 1033H) is loaded
into R8 and RR6 is decremented by one (RR6 RR6 − 1)
R8 = 0DDH, R6 = 10H, R7 = 32H
PRELIMINARY
6-53
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.39 LDCI/LDEI - Load Memory and Increment
LDCI/LDEI
dst,src
Operation:
dst src
rr rr + 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data memory. The assembler makes
"Irr" even for program memory and odd for data memory.
Flags:
No flags are affected.
Format:
opc
Examples:
PS032408-0220
dst | src
Bytes
Cycles
Opcode
(Hex)
2
10
E3
Addr Mode
dst
src
r
Irr
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH
and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI
R8,@RR6
;
;
;
0CDH (contents of program memory location 1033H) is loaded
into R8 and RR6 is incremented by one (RR6 RR6 + 1)
R8 = 0CDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
;
;
;
0DDH (contents of data memory location 1033H) is loaded
into R8 and RR6 is incremented by one (RR6 RR6 + 1)
R8 = 0DDH, R6 = 10H, R7 = 34H
PRELIMINARY
6-54
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.40 LDCPD/LDEPD - Load Memory with Pre-Decrement
LDCPD/
LDEPD
dst,src
Operation:
rr rr – 1
dst src
These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is first
decremented. The contents of the source location are then loaded into the destination location.
The contents of the source are unaffected.
LDCPD refers to program memory and LDEPD refers to external data memory. The assembler
makes "Irr" an even number for program memory and an odd number for external data memory.
Flags:
No flags are affected.
Format:
opc
Examples:
PS032408-0220
src | dst
Bytes
Cycles
Opcode
(Hex)
2
14
F2
Addr Mode
dst
src
Irr
r
Given: R0 = 77H, R6 = 30H, and R7 = 00H:
LDCPD
@RR6,R0
;
;
;
;
(RR6 RR6 − 1)
77H (contents of R0) is loaded into program memory location
2FFFH (3000H − 1H)
R0 = 77H, R6 = 2FH, R7 = 0FFH
LDEPD
@RR6,R0
;
;
;
;
(RR6 RR6 − 1)
77H (contents of R0) is loaded into external data memory
location 2FFFH (3000H − 1H)
R0 = 77H, R6 = 2FH, R7 = 0FFH
PRELIMINARY
6-55
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.41 LDCPI/LDEPI - Load Memory with Pre-Increment
LDCPI/
LDEPI
dst,src
Operation:
rr rr + 1
dst src
These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is first
incremented. The contents of the source location are loaded into the destination location. The
contents of the source are unaffected.
LDCPI refers to program memory and LDEPI refers to external data memory. The assembler
makes "Irr" an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
opc
Examples:
PS032408-0220
src | dst
Bytes
Cycles
Opcode
(Hex)
2
14
F3
Addr Mode
dst
src
Irr
r
Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:
LDCPI
@RR6,R0
;
;
;
;
(RR6 RR6 + 1)
7FH (contents of R0) is loaded into program memory
location 2200H (21FFH + 1H)
R0 = 7FH, R6 = 22H, R7 = 00H
LDEPI
@RR6,R0
;
;
;
;
(RR6 RR6 + 1)
7FH (contents of R0) is loaded into external data memory
location 2200H (21FFH + 1H)
R0 = 7FH, R6 = 22H, R7 = 00H
PRELIMINARY
6-56
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.42 LDW - Load Word
LDW
dst,src
Operation:
dst src
The contents of the source (a word) are loaded into the destination. The contents of the source
are unaffected.
Flags:
No flags are affected.
Format:
opc
opc
Examples:
src
dst
dst
src
Bytes
Cycles
Opcode
(Hex)
3
8
C4
RR
RR
8
C5
RR
IR
8
C6
RR
IML
4
Addr Mode
dst
src
Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H,
register 02H = 03H, and register 03H = 0FH:
LDW
LDW
RR6,RR4
00H,02H
→
→
LDW
LDW
LDW
LDW
RR2,@R7
04H,@01H
RR6,#1234H
02H,#0FEDH
→
→
→
→
R6 = 06H, R7
Register 00H
register 02H
R2 = 03H, R3
Register 04H
R6 = 12H, R7
Register 02H
=
=
=
=
=
=
=
1CH,
03H,
03H,
0FH,
03H,
34H
0FH,
R4 = 06H, R5 = 1CH
register 01H = 0FH,
register 03H = 0FH
register 05H = 0FH
register 03H = 0EDH
In the second example, please note that the statement "LDW 00H, 02H" loads the contents of
the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in
general register 00H and the value 0FH in register 01H.
The other examples show how to use the LDW instruction with various addressing modes and
formats.
PS032408-0220
PRELIMINARY
6-57
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.43 MULT - Multiply (Unsigned)
MULT
dst,src
Operation:
dst dst src
The 8-bit destination operand (even register of the register pair) is multiplied by the source
operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination
address. Both operands are treated as unsigned integers.
Flags:
C:
Set if result is > 255; cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if MSB of the result is a "1"; cleared otherwise.
V:
Cleared.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
src
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
3
22
84
RR
R
22
85
RR
IR
22
86
RR
IM
Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:
MULT
MULT
MULT
00H, 02H
00H, @01H
00H, #30H
→
→
→
Register 00H = 01H, register 01H = 20H, register 02H = 09H
Register 00H = 00H, register 01H = 0C0H
Register 00H = 06H, register 01H = 00H
In the first example, the statement "MULT 00H, 02H" multiplies the 8-bit destination operand (in
the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The
16-bit product, 0120H, is stored in the register pair 00H, 01H.
PS032408-0220
PRELIMINARY
6-58
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.44 NEXT - Next
NEXT
PC @ IP
Operation:
IP IP + 2
The NEXT instruction is useful when implementing threaded-code languages. The program
memory word that is pointed to by the instruction pointer is loaded into the program counter. The
instruction pointer is then incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
1
10
0F
opc
Example:
The following diagram shows one example of how to use the NEXT instruction.
Before
Address
IP
After
Data
Address
0043
IP
Address
PC
0120
43
44
45
120
0045
Data
Address H 01
Address L 10
Address H
Next
Address
PC
0130
43
44
45
130
Mem ory
PS032408-0220
Data
Data
Address H
Address L
Address H
Routine
Mem ory
PRELIMINARY
6-59
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.45 NOP - No Operation
NOP
Operation:
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.
Flags:
No flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
FF
When the instruction
NOP
is encountered in a program, no operation occurs. Instead, there is a delay in instruction
execution time.
PS032408-0220
PRELIMINARY
6-60
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.46 OR - Logical OR
OR
dst,src
Operation:
dst
dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is
stored.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always cleared to "0".
D:
Unaffected.
H:
Unaffected.
Format:
opc
opc
opc
Examples:
dst | src
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
42
r
r
6
43
r
lr
6
44
R
R
6
45
R
IR
6
46
R
IM
3
src
3
Addr Mode
dst
src
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H,
and register 08H = 8AH:
OR
OR
OR
OR
OR
R0,R1
R0,@R2
00H,01H
01H,@00H
00H,#02H
→
→
→
→
→
R0 = 3FH, R1
R0 = 37H, R2
Register 00H
Register 00H
Register 00H
=
=
=
=
=
2AH
01H, register 01H = 37H
3FH, register 01H = 37H
08H, register 01H = 0BFH
0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH,
the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result
(3FH) in destination register R0.
The other examples show the use of the logical OR instruction with the various addressing modes
and formats.
PS032408-0220
PRELIMINARY
6-61
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.47 POP - Pop from Stack
POP
dst
Operation:
dst @SP
SP SP + 1
The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.
Flags:
No flags affected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
8
50
R
8
51
IR
Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH,
and stack register 0FBH = 55H:
POP
POP
00H
@00H
→
→
Register 00H = 55H, SP = 00FCH
Register 00H = 01H, register 01H = 55H, SP = 00FCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H"
loads the contents of location 00FBH (55H) into destination register 00H and then increments the
stack pointer by one. Register 00H then contains the value 55H and the SP points to location
00FCH.
PS032408-0220
PRELIMINARY
6-62
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.48 POPUD - Pop User Stack (Decrementing)
POPUD
dst,src
Operation:
dst src
IR IR – 1
This instruction is used for user-defined stacks in the register file. The contents of the register file
location addressed by the user stack pointer are loaded into the destination. The user stack
pointer is then decremented.
Flags:
No flags are affected.
Format:
opc
Example:
src
dst
Bytes
Cycles
Opcode
(Hex)
3
8
92
Addr Mode
dst
src
R
IR
Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH,
and register 02H = 70H:
POPUD
02H,@00H
→
Register 00H = 41H, register 02H = 6FH, register 42H = 6FH
If general register 00H contains the value 42H and register 42H the value 6FH, the statement
"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The
user stack pointer is then decremented by one, leaving the value 41H.
PS032408-0220
PRELIMINARY
6-63
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.49 POPUI - Pop User Stack (Incrementing)
POPUI
dst,src
Operation:
dst src
IR IR + 1
The POPUI instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user stack pointer are loaded into the destination. The user
stack pointer is then incremented.
Flags:
No flags are affected.
Format:
opc
Example:
src
dst
Bytes
Cycles
Opcode
(Hex)
3
8
93
Addr Mode
dst
src
R
IR
Given: Register 00H = 01H and register 01H = 70H:
POPUI
02H,@00H
→
Register 00H = 02H, register 01H = 70H, register 02H = 70H
If general register 00H contains the value 01H and register 01H the value 70H, the statement
"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user
stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.
PS032408-0220
PRELIMINARY
6-64
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.50 PUSH - Push To Stack
PUSH
src
Operation:
SP SP – 1
@SP src
A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)
into the location addressed by the decremented stack pointer. The operation then adds the new
value to the top of the stack.
Flags:
No flags are affected.
Format:
opc
src
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
8 (internal clock)
70
R
71
IR
8 (external clock)
8 (internal clock)
8 (external clock)
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:
PUSH
40H
→
Register 40H = 4FH, stack register 0FFH = 4FH,
SPH = 0FFH, SPL = 0FFH
PUSH
@40H
→
Register 40H = 4FH, register 4FH = 0AAH, stack register
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH
In the first example, if the stack pointer contains the value 0000H, and general register 40H the
value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It
then loads the contents of register 40H into location 0FFFFH and adds this new value to the top
of the stack.
PS032408-0220
PRELIMINARY
6-65
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.51 PUSHUD - Push User Stack (Decrementing)
PUSHUD
dst,src
Operation:
IR IR – 1
dst src
This instruction is used to address user-defined stacks in the register file. PUSHUD decrements
the user stack pointer and loads the contents of the source into the register addressed by the
decremented stack pointer.
Flags:
No flags are affected.
Format:
opc
Example:
dst
src
Bytes
Cycles
Opcode
(Hex)
3
8
82
Addr Mode
dst
src
IR
R
Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:
PUSHUD @00H,01H
→
Register 00H = 02H, register 01H = 05H, register 02H = 05H
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUD @00H, 01H" decrements the user stack pointer by one, leaving the value 02H. The
01H register value, 05H, is then loaded into the register addressed by the decremented user
stack pointer.
PS032408-0220
PRELIMINARY
6-66
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.52 PUSHUI - Push User Stack (Incrementing)
PUSHUI
dst,src
Operation:
IR IR + 1
dst src
This instruction is used for user-defined stacks in the register file. PUSHUI increments the user
stack pointer and then loads the contents of the source into the register location addressed by the
incremented user stack pointer.
Flags:
No flags are affected.
Format:
opc
Example:
dst
src
Bytes
Cycles
Opcode
(Hex)
3
8
83
Addr Mode
dst
src
IR
R
Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:
PUSHUI @00H,01H
→
Register 00H = 04H, register 01H = 05H, register 04H = 05H
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUI @00H, 01H" increments the user stack pointer by one, leaving the value 04H. The 01H
register value, 05H, is then loaded into the location addressed by the incremented user stack
pointer.
PS032408-0220
PRELIMINARY
6-67
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.53 RCF - Reset Carry Flag
RCF
RCF
Operation:
C0
The carry flag is cleared to logic zero, regardless of its previous value.
Flags:
C:
Cleared to "0".
No other flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
CF
Given: C = "1" or "0":
The instruction RCF clears the carry flag (C) to logic zero.
PS032408-0220
PRELIMINARY
6-68
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.54 RET - Return
RET
Operation:
PC @SP
SP SP + 2
The RET instruction is normally used to return to the previously executing procedure at the end of
a procedure entered by a CALL instruction. The contents of the location addressed by the stack
pointer are popped into the program counter. The next statement that is executed is the one that
is addressed by the new program counter value.
Flags:
No flags are affected.
Format:
opc
Bytes
Cycles
Opcode (Hex)
1
8 (internal stack)
AF
10 (internal stack)
Example:
Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:
RET
→
PC = 101AH, SP = 00FEH
The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte
of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the
PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to
memory location 00FEH.
PS032408-0220
PRELIMINARY
6-69
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.55 RL - Rotate Left
RL
dst
Operation:
C
dst (0)
dst (n + 1)
dst (7)
dst (7)
dst (n), n = 0 to 6
The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is
moved to the bit zero (LSB) position and also replaces the carry flag.
7
0
C
Flags:
C:
Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
90
R
4
91
IR
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:
RL
RL
00H
@01H
→
→
Register 00H = 55H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)
and setting the carry and overflow flags.
PS032408-0220
PRELIMINARY
6-70
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.56 RLC - Rotate Left Through Carry
RLC
dst
Operation:
dst (0)
C
dst (n + 1)
C
dst (7)
dst (n), n = 0 to 6
The contents of the destination operand with the carry flag are rotated left one bit position. The
initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7
0
C
Flags:
C:
Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
10
R
4
11
IR
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":
RLC
RLC
00H
@01H
Register 00H = 54H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement
"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag
and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H
(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
PS032408-0220
PRELIMINARY
6-71
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.57 RR - Rotate Right
RR
dst
Operation:
C
dst (7)
dst (n)
dst (0)
dst (0)
dst (n + 1), n = 0 to 6
The contents of the destination operand are rotated right one bit position. The initial value of bit
zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7
0
C
Flags:
C:
Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
E0
R
4
E1
IR
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:
RR
RR
00H
@01H
Register 00H = 98H, C = "1"
Register 01H = 02H, register 02H = 8BH, C = "1"
In the first example, if general register 00H contains the value 31H (00110001B), the statement
"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to
bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also
resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
PS032408-0220
PRELIMINARY
6-72
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.58 RRC - Rotate Right Through Carry
RRC
dst
Operation:
dst (7)
C
dst (n)
C
dst (0)
dst (n + 1), n = 0 to 6
The contents of the destination operand and the carry flag are rotated right one bit position. The
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7
(MSB).
7
0
C
Flags:
C:
Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z:
Set if the result is "0" cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
C0
R
4
C1
IR
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":
RRC
RRC
00H
@01H
→
→
Register 00H = 2AH, C = "1"
Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1")
replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new
value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both
cleared to "0".
PS032408-0220
PRELIMINARY
6-73
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.59 SB0 - Select Bank 0
SB0
Operation:
BANK 0
The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,
selecting bank 0 register addressing in the set 1 area of the register file.
Flags:
No flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
4F
The statement
SB0
clears FLAGS.0 to "0", selecting bank 0 register addressing.
PS032408-0220
PRELIMINARY
6-74
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.60 SB1 - Select Bank 1
SB1
Operation:
BANK 1
The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,
selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not
implemented in some S3C8-series microcontrollers.)
Flags:
No flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
5F
The statement
SB1
sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.
PS032408-0220
PRELIMINARY
6-75
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.61 SBC - Subtract with Carry
SBC
dst,src
Operation:
dst dst – src – c
The source operand, along with the current value of the carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source are
unaffected. Subtraction is performed by adding the two's-complement of the source operand to
the destination operand. In multiple precision arithmetic, this instruction permits the carry
("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of
high-order operands.
Flags:
C:
Set if a borrow occurred (src > dst); cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the
sign of the result is the same as the sign of the source; cleared otherwise.
D:
Always set to "1".
H:
Cleared if there is a carry from the most significant bit of the low-order four bits of the
result; set otherwise, indicating a "borrow".
Format:
opc
dst | src
opc
opc
Examples:
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
32
r
r
6
33
r
lr
6
34
R
R
6
35
R
IR
3
src
3
6
36
Addr Mode
dst
src
R
IM
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H,
and register 03H = 0AH:
SBC
SBC
SBC
SBC
SBC
R1,R2
R1,@R2
01H,02H
01H,@02H
01H,#8AH
R1 = 0CH, R2
R1 = 05H, R2
Register 01H
Register 01H
Register 01H
=
=
=
=
=
03H
03H, register 03H = 0AH
1CH, register 02H = 03H
15H,register 02H = 03H, register 03H = 0AH
5H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H,
the statement "SBC R1, R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.
PS032408-0220
PRELIMINARY
6-76
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.62 SCF - Set Carry Flag
SCF
Operation:
C1
The carry flag (C) is set to logic one, regardless of its previous value.
Flags:
C:
Set to "1".
No other flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
DF
The statement
SCF
sets the carry flag to logic one.
PS032408-0220
PRELIMINARY
6-77
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.63 SRA - Shift Right Arithmetic
SRA
dst
Operation:
dst (7)
C
dst (n)
dst (7)
dst (0)
dst (n + 1), n = 0 to 6
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.
7
6
0
C
Flags:
C:
Set if the bit shifted from the LSB position (bit zero) was "1".
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Always cleared to "0".
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
D0
R
4
D1
IR
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":
SRA
SRA
00H
@02H
Register 00H = 0CD, C = "0"
Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C
flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the
value 0CDH (11001101B) in destination register 00H.
PS032408-0220
PRELIMINARY
6-78
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.64 SRP/SRP0/SRP1 - Set Register Pointer
SRP
src
SRP0
src
SRP1
src
Operation:
If src (1) = 1 and src (0) = 0 then:
If src (1) = 0 and src (0) = 1 then:
If src (1) = 0 and src (0) = 0 then:
RP0 (3−7)
RP1 (3−7)
RP0 (4−7)
RP0 (3)
RP1 (4−7)
RP1 (3)
src (3−7)
src (3−7)
src (4−7),
0
src (4−7),
1
The source data bits one and zero (LSB) determine whether to write one or both of the register
pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register
pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.
Flags:
No flags are affected.
Format:
opc
Examples:
src
Bytes
Cycles
Opcode
(Hex)
Addr Mode
src
2
4
31
IM
The statement
SRP #40H
Sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location
0D7H to 48H.
The statement "SRP0
68H.
PS032408-0220
#50H" sets RP0 to 50H, and the statement "SRP1
PRELIMINARY
#68H" sets RP1 to
6-79
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.65 STOP - Stop Operation
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,
peripheral registers, and I/O port control and data registers are retained. Stop mode can be
released by an external reset operation or by external interrupts. For the reset operation, the
RESET pin must be held to Low level until the required oscillation stabilization interval has
elapsed.
Flags:
No flags are affected.
Format:
opc
Example:
Bytes
Cycles
Opcode
(Hex)
1
4
7F
Addr Mode
dst
src
–
–
The statement
STOP
halts all microcontroller operations.
PS032408-0220
PRELIMINARY
6-80
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.66 SUB - Subtract
SUB
dst,src
Operation:
dst dst – src
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.
Flags:
C:
Set if a "borrow" occurred; cleared otherwise.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result is negative; cleared otherwise.
V:
Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D:
Always set to "1".
H:
Cleared if there is a carry from the most significant bit of the low-order four bits of the
result; set otherwise indicating a "borrow".
Format:
opc
opc
opc
Examples:
dst |
src
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
22
r
r
6
23
r
lr
6
24
R
R
6
25
R
IR
6
26
R
IM
3
src
3
Addr Mode
dst
src
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB
SUB
SUB
SUB
SUB
SUB
R1,R2
R1,@R2
01H,02H
01H,@02H
01H,#90H
01H,#65H
R1 = 0FH, R2
R1 = 08H, R2
Register 01H
Register 01H
Register 01H
Register 01H
=
=
=
=
=
=
03H
03H
1EH, register 02H = 03H
17H, register 02H = 03H
91H; C, S, and V = "1"
0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.
PS032408-0220
PRELIMINARY
6-81
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.67 SWAP - Swap Nibbles
SWAP
dst
Operation:
dst (0 – 3) dst (4 – 7)
The contents of the lower four bits and upper four bits of the destination operand are swapped.
7
Flags:
4 3
0
C:
Undefined.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Undefined.
D:
Unaffected.
H:
Unaffected.
Format:
opc
Examples:
dst
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
2
4
F0
R
4
F1
IR
Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:
SWAP
SWAP
00H
@02H
Register 00H = 0E3H
Register 02H = 03H, register 03H = 4AH
In the first example, if general register 00H contains the value 3EH (00111110B), the statement
"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value
0E3H (11100011B).
PS032408-0220
PRELIMINARY
6-82
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.68 TCM - Test Complement Under Mask
TCM
dst,src
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the
source mask. The zero (Z) flag can then be checked to determine the result. The destination and
source operands are unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always cleared to "0".
D:
Unaffected.
H:
Unaffected.
Format:
opc
opc
opc
Examples:
dst | src
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
62
r
r
6
63
r
lr
6
64
R
R
6
65
R
IR
6
66
R
IM
3
src
3
Addr Mode
dst
src
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H,
and register 02H = 23H:
TCM
TCM
TCM
TCM
R0,R1
R0,@R1
00H,01H
00H,@01H
TCM
00H,#34
R0 = 0C7H, R1 = 02H, Z = "1"
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "1"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "1"
Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register
for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one
and can be tested to determine the result of the TCM operation.
PS032408-0220
PRELIMINARY
6-83
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.69 TM - Test Under Mask
TM
dst,src
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to
determine the result. The destination and source operands are unaffected.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to "0".
D:
Unaffected.
H:
Unaffected.
Format:
opc
opc
opc
Examples:
dst | src
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
72
r
r
6
73
r
lr
6
74
R
R
6
75
R
IR
6
76
R
IM
3
src
3
Addr Mode
dst
src
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H,
and register 02H = 23H:
TM
TM
TM
TM
R0,R1
R0,@R1
00H,01H
00H,@01H
TM
00H,#54H
R0 = 0C7H, R1 = 02H, Z = "0"
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "0"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TM R0, R1" tests bit one in the destination register
for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic
zero and can be tested to determine the result of the TM operation.
PS032408-0220
PRELIMINARY
6-84
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.70 WFI - Wait for Interrupt
WFI
Operation:
The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take
place during this wait state. The WFI status can be released by an internal interrupt, including a
fast interrupt .
Flags:
No flags are affected.
Format:
opc
Bytes
Cycles
Opcode
(Hex)
1
4n
3F
NOTE: (n = 1, 2, 3, …)
Example:
The following sample program structure shows the sequence of operations that follow a "WFI"
statement:
Main program
.
.
.
EI
WFI
(Next ins truction)
(Enable global interrupt)
(Wait for interrupt)
.
.
.
Interrupt occurs
Interrupt service routine
.
.
.
Clear interrupt flag
IRET
Service routine completed
PS032408-0220
PRELIMINARY
6-85
S3F8S6B Product Specification
Chapter 6. Instruction Set
6.3.71 XOR - Logical Exclusive OR
XOR
dst,src
Operation:
dst dst XOR src
The source operand is logically exclusive-ORed with the destination operand and the result is
stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever
the corresponding bits in the operands are different; otherwise, a "0" bit is stored.
Flags:
C:
Unaffected.
Z:
Set if the result is "0"; cleared otherwise.
S:
Set if the result bit 7 is set; cleared otherwise.
V:
Always reset to "0".
D:
Unaffected.
H:
Unaffected.
Format:
opc
opc
opc
Examples:
dst | src
src
dst
dst
Bytes
Cycles
Opcode
(Hex)
2
4
B2
r
r
6
B3
r
lr
6
B4
R
R
6
B5
R
IR
6
B6
R
IM
3
src
3
Addr Mode
dst
src
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H,
and register 02H = 23H:
XOR
XOR
XOR
XOR
XOR
R0,R1
R0,@R1
00H,01H
00H,@01H
00H,#54H
R0 = 0C5H, R1 = 02H
R0 = 0E4H, R1 = 02H, register 02H = 23H
Register 00H = 29H, register 01H = 02H
Register 00H = 08H, register 01H = 02H, register 02H = 23H
Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the
value 02H, the statement "XOR R0, R1" logically exclusive-ORs the R1 value with the R0 value
and stores the result (0C5H) in the destination register R0.
PS032408-0220
PRELIMINARY
6-86
S3F8S6B Product Specification
7
Chapter 7. Clock Circuit
Clock Circuit
7.1 Overview
The S3F8S6B microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and
peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU
clock frequency of S3F8S6B is determined by CLKCON register settings.
7.1.1 System Clock Circuit
The system clock circuit has the following components:
•
External crystal, ceramic resonator, RC oscillation source, or an external clock source
•
Oscillator stop and wake-up functions
•
Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)
•
System clock control register, CLKCON
•
Oscillator control register, OSCCON and STOP control register, STPCON
7.1.2 CPU Clock Notation
In this document, the following notation is used for descriptions of the CPU clock;
•
fx: main clock
•
fxt: sub clock
•
fxx: selected system clock
PS032408-0220
PRELIMINARY
7-1
S3F8S6B Product Specification
Chapter 7. Clock Circuit
7.2 Main Oscillator Circuits
XIN
XOUT
Figure 7-1
Crystal/Ceramic Oscillator (fX)
XIN
XOUT
Figure 7-2
External Oscillator (fX)
XIN
R
XOUT
Figure 7-3
PS032408-0220
RC Oscillator (fX)
PRELIMINARY
7-2
S3F8S6B Product Specification
Chapter 7. Clock Circuit
7.3 Sub Oscillator Circuits
32.768 kHz
XTIN
XTOUT
Figure 7-4
Crystal Oscillator (fxt)
XTIN
XTOUT
Figure 7-5
PS032408-0220
External Oscillator (fxt)
PRELIMINARY
7-3
S3F8S6B Product Specification
Chapter 7. Clock Circuit
7.4 Clock Status During Power-Down Modes
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
•
In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset
operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too
when the sub-system oscillator is running and watch timer is operating with sub-system clock.
•
In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/
counters. Idle mode is released by a reset or by an external or internal interrupt.
Stop Release
INT
Main-System
Oscillator
Circuit
fX
f Xt
Sub-system
Oscillator
Circuit
Watch Timer
LCD Controller
Selector 1
fXX
Stop
OSCCON.3
Stop
OSCCON.0
OSCCON.2
1/1-1/4096
STOP OSC
inst.
Frequency
Dividing
Circuit
STPCON
1/1
CLKCON.4-.3
1/2
1/8
1/16
Basic Timer
Timer/Counters A, B, C, D0/D1
Watch Timer
LCD Controller
SIO
UART 0/1
A/D Converter
LVR
PGM
Selector 2
CPU Clock
IDLE Instruction
Figure 7-6
PS032408-0220
System Clock Circuit Diagram
PRELIMINARY
7-4
S3F8S6B Product Specification
Chapter 7. Clock Circuit
7.5 System Clock Control Register (CLKCON)
The system clock control register, CLKCON, is located in the set 1, address D4H. It is read/write addressable and
has the following functions:
•
Oscillator frequency divide-by value
After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If
necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.
System Clock Control Register (CLKCON)
D4H, Set 1, R/W
MSB
.7
.6
.5
.4
Not used
(must keep always 0)
Oscillator IRQ wake-up function bit:
0 = Enable IRQ for main wake-up in power down mode
1 = Disable IRQ for main wake-up in power down mode
.3
.2
.1
.0
LSB
Not used
(must keep always 0)
Divide-by selection bits for CPU clock frequency:
00 = fXX/16
01 = fXX/8
10 = fXX/2
11 = fXX/1
NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock.
To select faster speed, load the appropriate values to CLKCON.3-.4.
Figure 7-7
PS032408-0220
System Clock Control Register (CLKCON)
PRELIMINARY
7-5
S3F8S6B Product Specification
Chapter 7. Clock Circuit
Oscillator Control Register (OSCCON)
FAH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
System clock selection bit:
0 = Main oscillator select
1 = Sub oscillator select
Not used for S3F8S6B
Not used for S3F8S6B
Sub system oscillator control bit:
0 = Sub oscillator RUN
1 = Sub oscillator STOP
Main system oscillator control bit:
0 = Main oscillator RUN
1 = Main oscillator STOP
Figure 7-8
PS032408-0220
Oscillator Control Register (OSCCON)
PRELIMINARY
7-6
S3F8S6B Product Specification
Chapter 7. Clock Circuit
7.6 Stop Control Register (STPCON)
The STOP control register, STPCON, is located in the bank 0 of set1, address F5H. It is read/write addressable
and has the following functions:
•
Enable/Disable STOP instruction
After a reset, the STOP instruction is disabled, because the value of STPCON is "other values".
If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B".
STOP Control Register (STPCON)
F5H, Set 1, bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
STOP Control bits:
Other values = Disable STOP instruction
10100101 = Enable STOP instruction
NOTE:
Before executing the STOP instruction, set the STPCON
register as "10100101b". Otherwise the STOP instruction
will not be executed and reset will be generated.
Figure 7-9
STOP Control Register (STPCON)
Example 7-1
How to Use Stop Instruction
This example shows how to go Stop mode when a main clock is selected as the system clock.
LD
STOP
NOP
NOP
NOP
LD
PS032408-0220
STOPCON,#1010010B
STOPCON,#00000000B
;
;
Enable STOP instruction
Enter Stop mode
;
;
Release Stop mode
Disable STOP instruction
PRELIMINARY
7-7
S3F8S6B Product Specification
Chapter 7. Clock Circuit
7.7 Switching the CPU Clock
Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as
the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch
dynamically between main and sub clocks and to modify operating frequencies.
OSCCON.0 selects the main clock (fx) or the sub clock (fxt) for the CPU clock. OSCCON .3 start or stop main
clock oscillation and OSCCON.2 start or stop sub clock oscillation. CLKCON.4–.3 controls the frequency divider
circuit, and divides the selected fxx clock by 1, 2, 8 and 16. If the sub clock (fxt) is selected for system clock, the
CLKCON.4–.3 must be set to "11".
For example, you are using the default CPU clock (normal operating mode and a main clock of fx/16) and you
want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set CLKCON.4.3 to "11", OSCCON.0 to "1", and OSCCON.3 to "1" by turns. This switches the clock from fx to fxt and stops main
clock oscillation.
The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to "0" to
enable main clock oscillation. Then, after a certain number of machine cycles have elapsed, select the main clock
by setting OSCCON.0 to "0".
Example 7-2
1.
This example shows how to change from the main clock to the sub clock:
MA2SUB OR
2.
Switching the CPU clock
CLKCON,#18H
LD
OSCCON,#01H
CALL
DLY16
OR
OSCCON,#08H
RET
;
;
;
;
Non-divided clock for system clock
Switches to the sub clock
Delay 16 ms
Stop the main clock oscillation
This example shows how to change from sub clock to main clock:
SUB2MA AND
DLY16
DEL
PS032408-0220
OSCCON,#07H
CALL
DLY16
AND
OSCCON,#06H
RET
SRP
#0C0H
LD
R0,#20H
NOP
DJNZ
R0,DEL
RET
;
;
;
PRELIMINARY
Start the main clock oscillation
Delay 16 ms
Switch to the main clock
7-8
S3F8S6B Product Specification
8
Chapter 8. RESET and Power-Down
RESET and Power-Down
8.1 System Reset
8.1.1 Overview
During a power-on reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The
nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This
procedure brings the S3F8S6B into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a
minimum time interval after the power supply comes within tolerance. The minimum required time of a reset
operation for oscillation stabilization is 1 millisecond.
Whenever a reset occurs during normal operation (that is, when both VDD and nRESET are High level), the
nRESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are then
reset to their default hardware values
In summary, the following sequence of events occurs during a reset operation:
•
All interrupt is disabled.
•
The watchdog function (basic timer) is enabled.
•
Ports 0-6 and set to input mode, and all pull-up resistors are disabled for the I/O port.
•
Peripheral control and data register settings are disabled and reset to their default hardware values.
•
The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
•
When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM
location 0100H (and 0101H) is fetched and executed at normal mode by smart option.
•
The reset address at ROM can be changed by Smart Option in the S3F8S6B (full-Flash device). Refer to "The
Chapter 21. Embedded Flash Memory Interface" for more detailed contents.
8.1.2 Normal Mode Reset Operation
In normal mode, the Test pin is tied to VSS. A reset enables access to the 64KB on-chip ROM. (The external
interface is not automatically configured).
NOTE: To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer
control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function
(which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010B" to the
upper nibble of BTCON.
PS032408-0220
PRELIMINARY
8-1
S3F8S6B Product Specification
Chapter 8. RESET and Power-Down
8.1.3 Hardware Reset Values
Table 8-1, 8-2, 8-3, 8-4 list the reset values for CPU and system registers, peripheral control registers, and
peripheral data registers following a reset operation. The following notation is used to represent reset values:
•
A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
•
An "x" means that the bit value is undefined after a reset.
•
A dash ("−") means that the bit is either not used or not mapped, but read 0 is the bit value.
Table 8.1
Register Name
S3F8S6B Set 1 Register and Values After RESET
Mnemonic
Address
Bit Values After RESET
Dec
Hex
7
6
5
4
3
2
1
0
Basic timer control register
BTCON
211
D3H
0
0
0
0
0
0
0
0
System clock control register
CLKCON
212
D4H
0
–
–
0
0
–
–
–
System flags register
FLAGS
213
D5H
x
x
x
x
x
x
0
0
Register pointer 0
RP0
214
D6H
1
1
0
0
0
–
–
–
Register pointer 1
RP1
215
D7H
1
1
0
0
1
–
–
–
Stack pointer (high byte)
SPH
216
D8H
x
x
x
x
x
x
x
x
Stack pointer (low byte)
SPL
217
D9H
x
x
x
x
x
x
x
x
Instruction pointer (high byte)
IPH
218
DAH
x
x
x
x
x
x
x
x
Instruction pointer (low byte)
IPL
219
DBH
x
x
x
x
x
x
x
x
Interrupt request register
IRQ
220
DCH
0
0
0
0
0
0
0
0
Interrupt mask register
IMR
221
DDH
x
x
x
x
x
x
x
x
System mode register
SYM
222
DEH
0
–
–
x
x
x
0
0
Register page pointer
PP
223
DFH
0
0
0
0
0
0
0
0
NOTE:
1.
An "x" means that the bit value is undefined following reset.
2.
A dash ('–') means that the bit is neither used nor mapped, but the bit is read as "0".
PS032408-0220
PRELIMINARY
8-2
S3F8S6B Product Specification
Table 8.2
Chapter 8. RESET and Power-Down
S3F8S6B Set 1, Bank 0 Register and Values after RESET
Register Name
Mnemonic
A/D Converter Data Register (High
Byte)
A/D Converter Data Register (Low
Byte)
Address
Bit Values after RESET
Dec
Hex
7
6
5
4
3
2
1
0
ADDATAH
208
D0H
x
x
x
x
x
x
x
x
ADDATAL
209
D1H
–
–
–
–
–
–
x
x
A/D Converter Control Register
ADCON
210
D2H
–
0
0
0
0
0
0
0
Timer A Counter Register
TACNT
224
E0H
0
0
0
0
0
0
0
0
Timer A Data Register
TADATA
225
E1H
1
1
1
1
1
1
1
1
Timer A Control Register
TACON
226
E2H
0
0
0
0
0
0
0
0
Timer B Control Register
TBCON
227
E3H
0
0
0
0
0
0
0
0
Timer B Data Register (High Byte)
TBDATAH
228
E4H
1
1
1
1
1
1
1
1
Timer B Data Register (Low Byte)
TBDATAL
229
E5H
1
1
1
1
1
1
1
1
Watch Timer Control Register
WTCON
230
E6H
0
0
0
0
0
0
0
0
SIO Control Register
SIOCON
231
E7H
0
0
0
0
0
0
0
0
SIO Data Register
SIODATA
232
E8H
0
0
0
0
0
0
0
0
SIO Pre-scaler Register
SIOPS
233
E9H
0
0
0
0
0
0
0
0
Timer C Counter Register
TCCNT
234
EAH
0
0
0
0
0
0
0
0
Timer C Data Register
TCDATA
235
EBH
1
1
1
1
1
1
1
1
Timer C Control Register
TCCON
236
ECH
0
0
0
0
0
0
0
0
Locations EDH–EFH are not mapped
LCD Control Register
LCON
240
F0H
0
0
0
0
0
0
0
0
LCD Mode Register
LMOD
241
F1H
–
–
–
–
–
0
0
0
Locations F2H–F3H are not mapped
Interrupt Pending Register
INTPND
244
F4H
–
–
0
0
0
0
0
0
STOP control register
STPCON
245
F5H
0
0
0
0
0
0
0
0
Flash Memory Sector Address
Register (High Byte)
FMSECH
246
F6H
0
0
0
0
0
0
0
0
Flash Memory Sector Address
Register (Low Byte)
FMSECL
247
F7H
0
0
0
0
0
0
0
0
Flash Memory User Programming
Enable Register
FMUSR
248
F8H
0
0
0
0
0
0
0
0
Flash Memory Control Register
FMCON
249
F9H
0
0
0
0
0
–
–
0
OSCCON
250
FAH
–
–
–
–
0
0
–
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
Oscillator Control Register
Locations FBH–FCH are not mapped
Basic Timer Counter
BTCNT
253
FDH
0
Location FEH are not mapped
Interrupt Priority Register
PS032408-0220
IPR
255
FFH
PRELIMINARY
x
8-3
S3F8S6B Product Specification
Table 8.3
Chapter 8. RESET and Power-Down
S3F8S6B Set 1, Bank 1 Register and Values after RESET
Register Name
Mnemonic
Address
Bit Values after RESET
Dec
Hex
7
6
5
4
3
2
1
0
Pattern Generation Control Register
PGCON
208
D0H
–
–
–
–
0
0
0
0
Pattern Generation Data Register
PGDATA
209
D1H
0
0
0
0
0
0
0
0
Port 0 Control Register (High Byte)
P0CONH
224
E0H
0
0
0
0
0
0
0
0
Port 0 Control Register (Low Byte)
P0CONL
225
E1H
0
0
0
0
0
0
0
0
Port 1 Control Register (High Byte)
P1CONH
226
E2H
0
0
0
0
0
0
0
0
Port 1 Control Register (Low Byte)
P1CONL
227
E3H
0
0
0
0
0
0
0
0
Port 1 Pull-up Resistor Enable
Register
P1PUR
228
E4H
0
0
0
0
0
0
0
0
Port 1 N-Channel Open-drain Mode
Register
PNE1
229
E5H
0
0
0
0
0
0
0
0
Port 2 Control Register (High Byte)
P2CONH
230
E6H
0
0
0
0
0
0
0
0
Port 2 Control Register (Low Byte)
P2CONL
231
E7H
0
0
0
0
0
0
0
0
Port 2 Interrupt Control Register
(High Byte)
P2INTH
232
E8H
0
0
0
0
0
0
0
0
Port 2 Interrupt Control Register
(Low Byte)
P2INTL
233
E9H
0
0
0
0
0
0
0
0
Port 2 Interrupt Pending Register
P2PND
234
EAH
0
0
0
0
0
0
0
0
Port 3 Control Register (High Byte)
P3CONH
235
EBH
0
0
0
0
0
0
0
0
Port 3 Control Register (Middle Byte)
P3CONM
236
ECH
0
0
0
0
0
0
0
0
Port 3 Control Register (Low Byte)
P3CONL
237
EDH
–
–
0
0
0
0
0
0
Port 3 Pull-up Resistor Enable
Register
P3PUR
238
EEH
0
0
0
0
0
0
0
0
Port 3 N-Channel Open-drain Mode
Register
PNE3
239
EFH
0
0
0
0
0
0
0
0
Port 5 Control Register (High Byte)
P5CONH
240
F0H
0
0
0
0
0
0
0
0
Port 5 Control Register (Low Byte)
P5CONL
241
F1H
0
0
0
0
0
0
0
0
Port 6 Control Register (High Byte)
P6CONH
242
F2H
–
–
–
–
0
0
0
0
Port 6 Control Register (Low Byte)
P6CONL
243
F3H
0
0
0
0
0
0
0
0
Port 6 Pull-up Resistor Enable
Register
P6PUR
244
F4H
–
–
0
0
0
0
0
0
Port 6 N-Channel Open-drain Mode
Register
PNE6
245
F5H
–
–
0
0
0
0
0
0
Timer D0 Counter Register (High
Byte)
TD0CNTH
246
F6H
0
0
0
0
0
0
0
0
Timer D0 Counter Register (Low
Byte)
TD0CNTL
247
F7H
0
0
0
0
0
0
0
0
Timer D0 Data Register (High Byte)
TD0DATAH
248
F8H
1
1
1
1
1
1
1
1
Timer D0 Data Register (Low Byte)
TD0DATAL
249
F9H
1
1
1
1
1
1
1
1
Location D2H is not mapped.
PS032408-0220
PRELIMINARY
8-4
S3F8S6B Product Specification
Register Name
Mnemonic
Chapter 8. RESET and Power-Down
Address
Bit Values after RESET
Dec
Hex
7
6
5
4
3
2
1
0
Timer D0 Control Register
TD0CON
250
FAH
0
0
0
0
0
0
0
0
Timer D1 Control Register
TD1CON
251
FBH
0
0
0
0
0
0
0
0
Timer D1 Counter Register (High
Byte)
TD1CNTH
252
FCH
0
0
0
0
0
0
0
0
Timer D1 Counter Register (Low
Byte)
TD1CNTL
253
FDH
0
0
0
0
0
0
0
0
Timer D1 Data Register (High Byte)
TD1DATAH
254
FEH
1
1
1
1
1
1
1
1
Timer D1 Data Register (Low Byte)
TD1DATAL
255
FFH
1
1
1
1
1
1
1
1
NOTE:
1.
An "x' means that the bit value is undefined following reset.
2.
A dash ('–') means that the bit is neither used nor mapped, but the bit is read as "0".
PS032408-0220
PRELIMINARY
8-5
S3F8S6B Product Specification
Table 8.4
Chapter 8. RESET and Power-Down
S3F8S6B Page 8 Register and Values After RESET
Register Name
Mnemonic
Address
Bit Values After RESET
Dec
Hex
7
6
5
4
3
2
1
0
Port 0 Data Register
P0
0
00H
0
0
0
0
0
0
0
0
Port 1 Data Register
P1
1
01H
0
0
0
0
0
0
0
0
Port 2 Data Register
P2
2
02H
0
0
0
0
0
0
0
0
Port 3 Data Register
P3
3
03H
0
0
0
0
0
0
0
0
Port 4 Data Register
P4
4
04H
0
0
0
0
0
0
0
0
Port 5 Data Register
P5
5
05H
0
0
0
0
0
0
0
0
Port 6 Data Register
P6
6
06H
x
x
0
0
0
0
0
0
Port 4 Control Register (High Byte)
P4CONH
12
0CH
0
0
0
0
0
0
0
0
Port 4 Control Register (Low Byte)
P4CONL
13
0DH
0
0
0
0
0
0
0
0
Port 4 Interrupt Control Register (High
Byte)
P4INTH
14
0EH
0
0
0
0
0
0
0
0
Port 4 Interrupt Control Register (Low
Byte)
P4INTL
15
0FH
0
0
0
0
0
0
0
0
Port 4 Interrupt Pending Register
P4PND
16
10H
0
0
0
0
0
0
0
0
UART 0 Control Register (High Byte)
UART0CONH
20
14H
0
0
0
0
0
0
0
0
UART 0 Control Register (Low Byte)
UART0CONL
21
15H
0
0
0
0
0
0
0
0
UART 0 Data Register
UDATA0
22
16H
x
x
x
x
x
x
x
x
UART 0 Baud Rate Data Register
BRDATA0
23
17H
1
1
1
1
1
1
1
1
UART 1 Control Register (High Byte)
UART1CONH
24
18H
0
0
0
0
0
0
0
0
UART 1 Control Register (Low Byte)
UART1CONL
25
19H
0
0
0
0
0
0
0
0
UART 1 Data Register
UDATA1
26
1AH
x
x
x
x
x
x
x
x
UART 1 Baud Rate Data Register
BRDATA1
27
1BH
1
1
1
1
1
1
1
1
Locations 07H–0BH are not mapped.
Locations 11H−13H are not mapped.
Locations 1CH−2FH are not mapped.
NOTE:
1.
An "x" means that the bit value is undefined following reset.
2.
A dash ('–') means that the bit is neither used nor mapped, but the bit is read as "0".
PS032408-0220
PRELIMINARY
8-6
S3F8S6B Product Specification
Chapter 8. RESET and Power-Down
8.2 Power-Down Modes
8.2.1 Stop Mode
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all
peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 A.
All system functions stop when the clock "freezes", but data stored in the internal register file is retained. Stop
mode can be released in one of two ways: by a reset or by interrupts, for more details see Figure 7-6.
NOTE: Do not use Stop mode if you are using an external clock source because XIN or XTIN input must be restricted internally
to VSS to reduce current leakage.
8.2.1.1 Using nRESET to Release Stop Mode
Stop mode is released when the nRESET signal is released and returns to high level: all system and peripheral
control registers are reset to their default hardware values and the contents of all data registers are retained. A
reset operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to
"00B". After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization
routine by fetching the program instruction stored in ROM location 0100H (and 0101H)
8.2.1.2 Using an External Interrupt to Release Stop Mode
External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can
use to release Stop mode in a given situation depends on the microcontroller's current internal operating mode.
The external interrupts in the S3F8S6B interrupt structure that can be used to release Stop mode are:
•
External interrupts P2.0−P2.7, P4.0−P4.7 (INT0−INT15)
Please note the following conditions for Stop mode release:
•
If you release Stop mode using an external interrupt, the current values in system and peripheral control
registers are unchanged except STPCON register.
•
If you use an internal or external interrupt for Stop mode release, you can also program the duration of the
oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before
entering Stop mode.
•
When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains
unchanged and the currently selected clock value is used.
•
The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service
routine, the instruction immediately following the one that initiated Stop mode is executed.
8.2.1.3 Using an Internal Interrupt to Release Stop Mode
Activate any enabled interrupt, causing Stop mode to be released. Other things are same as using external
interrupt.
PS032408-0220
PRELIMINARY
8-7
S3F8S6B Product Specification
Chapter 8. RESET and Power-Down
8.2.1.4 How to Enter into Stop Mode
Handling STPCON register then writing STOP instruction (keep the order).
LD
STOP
NOP
NOP
NOP
STPCON,#10100101B
8.2.2 Idle Mode
Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some
peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU, but all
peripherals timers remain active. Port pins retain the mode (input or output) they had at the time Idle mode was
entered.
There are two ways to release Idle mode:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4
and CLKCON.3 are cleared to "00B". If interrupts are masked, a reset is the only way to release Idle mode.
2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle
mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock
value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction
immediately following the one that initiated Idle mode is executed.
PS032408-0220
PRELIMINARY
8-8
S3F8S6B Product Specification
9
Chapter 9. I/O Port
I/O Port
9.1 Overview
The S3F8S6B microcontroller has seven bit-programmable I/O ports, P0−P6. The port 6 is a 6-bit port and the
others are 8-bit ports. This gives a total of 54 I/O pins. Each port can be flexibly configured to meet application
design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O
instructions are required. Table 9.1 provides a general overview of the S3F8S6B I/O port functions.
Table 9.1
Port
S3F8S6B Port Configuration Overview
Configuration Options
0
1-bit programmable I/O port.
Input or push-pull output mode selected by software; software assignable pull-ups.
P0.0–P0.7 can alternately be used as outputs for LCD COM/SEG.
1
1-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.
Alternately P1.0–P1.7 can be used as TxD0, RxD0, TxD1, RxD1, TAOUT/TAPWM/TACAP, TACLK
or LCD SEG.
2
1-bit programmable I/O port.
Schmitt trigger input or push-pull output mode selected by software; software assignable pull-ups.
P2.0–P2.7 can be used as inputs for external interrupts INT0–INT7 (with noise filter, interrupt enable
and pending control).
Alternatively P2.0-P2.7 can be used as LCD SEG.
3
1-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.
Alternately P3.0–P3.7 can be used as TBPWM/PG0, TCOUT/PG1, PG2,
TD0OUT/TD0PWM/TD0CAP/PG3, TD0CLK/PG4, TD1OUT/TD1PWM/TD1CAP/PG5, TD1CLK/PG6,
BUZ/PG7 or LCD SEG.
4
The P4.2-P4.7 are the I/O port with bit-programmable pins, but the P4.0/P4.1 are the I/O port with
two-bits-programmable pins.
Schmitt trigger input or push-pull in output mode selected by software; software assignable pull-ups.
P4.0–P4.7 can be used as inputs for external interrupts INT8–INT15 (with noise filter, interrupt
enable and pending control).
Alternatively P4.0-P4.7 can be used as AD0–AD7.
5
1-bit programmable I/O port.
Input or push-pull output mode selected by software; software assignable pull-ups.
P5.0–P5.7 can alternately be used as VLC0–VLC3, CA, CB, XTOUT, XTIN.
6
1-bit programmable I/O port.
Input or push-pull, open-drain output mode selected by software; software assignable pull-ups.
P6.0–P6.5 can alternately be used as SCK, SI, SO, or LCD SEG.
PS032408-0220
PRELIMINARY
9-1
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2 Port Data Registers
Table 9.2 gives you an overview of the register locations of all twelve S3F8S6B I/O port data registers. Data
registers for ports 0, 1, 2, 3, 4, 5 and 6 have the general format shown in Figure 9-1.
Table 9.2
Register Name
Port Data Register Summary
Mnemonic
Decimal
Hex
Location
RW
Port 0 data register
P0
0
00H
Page 8
RW
Port 1 data register
P1
1
01H
Page 8
RW
Port 2 data register
P2
2
02H
Page 8
RW
Port 3 data register
P3
3
03H
Page 8
RW
Port 4 data register
P4
4
04H
Page 8
RW
Port 5 data register
P5
5
05H
Page 8
RW
Port 6 data register
P6
6
06H
Page 8
RW
S3F8S6B I/O Port Data Register Format (n = 0-6)
MSB
.7
.6
.5
.4
.3
.2
.1
.0
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
Pn.1
Pn.0
Figure 9-1
PS032408-0220
LSB
S3F8S6B I/O Port Data Register Format
PRELIMINARY
9-2
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.1 Port 0
Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading
the port 0 data register, P0 at location 00H in page 8. P0.0–P0.7 can serve as inputs (with or without pull-ups),
and push-pull outputs. And, they can serve as segment pins for LCD also.
9.2.1.1 Port 0 Control Register (P0CONH, P0CONL)
Port 0 has two 8-bit control registers: P0CONH for P0.4-P0.7 and P0CONL for P0.0-P0.3. A reset clears the
P0CONH and P0CONL registers to "00H", configuring all pins to input mode. You use control registers settings to
select input (with or without pull-ups) or push-pull output mode and enable the alternative functions.
Port 0 Control Register, High Byte (P0CONH)
E0H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
P0.7/COM7/ P0.6/COM6/ P0.5/COM5/
SEG5
SEG4
SEG3
.1
.0
LSB
P0.4/COM4/
SEG2
P0CONH bit-pair pin configuration settings:
00
Input mode
01
Input mode, pull-up
10
Alternative function (LCD signal)
11
Output mode, push-pull
Figure 9-2
PS032408-0220
Port 0 High-Byte Control Register (P0CONH)
PRELIMINARY
9-3
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 0 Control Register, Low Byte (P0CONL)
E1H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
P0.3/COM3/ P0.2/COM2/
SEG1
SEG0
.3
.2
P0.1/COM1
.1
.0
LSB
P0.0/COM0
P0CONL bit-pair pin configuration settings:
00
Input mode
01
Input mode, pull-up
10
Alternative function (LCD signal)
11
Output mode, push-pull
Figure 9-3
PS032408-0220
Port 0 Low-Byte Control Register (P0CONL)
PRELIMINARY
9-4
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.2 Port 1
Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading
the port 1 data register, P1 at location 01H in page 8. P1.0–P1.7 can serve as inputs (with or without pull-ups),
and outputs (push pull or open-drain). And the P1.7–P1.2 can serve as segment pins for LCD or you can configure
the following alternative functions:
•
Low-byte pins (P1.0-P1.3): RxD0, TxD0
•
High-byte pins (P1.4-P1.7): RxD1, TxD1, TAOUT/TAPWM/TACAP, TACLK
9.2.2.1 Port 1 Control Register (P1CONH, P1CONL)
Port 1 has two 8-bit control registers: P1CONH for P1.4–P1.7 and P1CONL for P1.0–P1.3. A reset clears the
P1CONH and P1CONL registers to "00H", configuring all pins to input mode. You use control registers settings to
select input or output mode and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 1 control registers must also be enabled in the associated peripheral module.
9.2.2.2 Port 1 Pull-Up Resistor Enable Register (P1PUR)
Using the port 1 pull-up resistor enable register, P1PUR (E4H, set1, bank1), you can configure pull-up resistors to
individual port 1 pins.
PS032408-0220
PRELIMINARY
9-5
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.2.3 Port 1 N-Channel Open-Drain Mode Register (PNE1)
Using the port 1 n-channel open-drain mode register, PNE1 (E5H, set1, bank1), you can configure push-pull or
open-drain output mode to individual port 1 pins.
Port 1 Control Register, High Byte (P1CONH)
E2H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1.7/TACLK P1.6/TAOUT/TAPP1.5/TxD1/ P1.4/RxD1/S
/SEG11
WM/TACAP/
SEG9
EG8
SEG10
P1CONH bit-pair pin configuration settings:
00
Input mode (TACLK, TACAP, RxD1)
01
10
Alternative function (TAOUT/TAPWM, TxD1, RxD1)
11
Output mode
Alternative function (LCD signal)
Figure 9-4
Port 1 High-Byte Control Register (P1CONH)
Port 1 Control Register, Low Byte (P1CONL)
E3H, Set 1, Bank 1, R/W
MSB
.7
.6
P1.3/TxD0
/SEG7
.5
.4
P1.2/RxD0
/SEG6
.3
.2
P1.1
.1
.0
LSB
P1.0
P1CONL bit-pair pin configuration settings:
00
01
10
11
Input mode (RxD0)
Alternative function (TxD0, RxD0)
Alternative function (LCD signal)
Output mode
Figure 9-5
PS032408-0220
Port 1 Low-Byte Control Register (P1CONL)
PRELIMINARY
9-6
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 1 Pull-up Resistor Enable Register (P1PUR)
E4H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
P1.7
P1.6
P1.5
P1.4
.3
.2
P1.3 P1.2
.1
P1.1
.0
LSB
P1.0
P1PUR bit configuration settings:
0
Disable Pull-up Resistor
1
Enable Pull-up Resistor
NOTE: A pull-up resistor of port 1 is automatically disabled
only when the corresponding pin is selected as
push-pull output or alternative function.
Figure 9-6
Port 1 Pull-up Resistor Enable Register (P1PUR)
Port 1 N-Channel Open-drain Mode Register (PNE1)
E5H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
P1.7
P1.6
P1.5
P1.4
.3
.2
P1.3 P1.2
.1
P1.1
.0
LSB
P1.0
PNE1 bit configuration settings:
Figure 9-7
PS032408-0220
0
Push-pull output mode
1
Open-drain output mode
Port 1 N-Channel Open-drain Mode Register (PNE1)
PRELIMINARY
9-7
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.3 Port 2
Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading
the port 2 data register, P2 at location 02H in page 8. P2.0–P2.7 can serve as inputs (with or without pull-ups),
and push pull outputs. And the P2.7–P2.0 can serve as segment pins for LCD or you can configure the following
alternative functions:
•
Low-byte pins (P2.0–P2.3): INT0-INT3
•
High-byte pins (P2.4–P2.7): INT4-INT7
9.2.3.1 Port 2 Control Register (P2CONH, P2CONL)
Port 2 has two 8-bit control registers: P2CONH for P2.4-P2.7 and P2CONL for P2.0-P2.3. A reset clears the
P2CONH and P2CONL registers to "00H", configuring all pins to input mode. In input mode, three different
selections are available:
•
Schmitt trigger input with interrupt generation on falling signal edges.
•
Schmitt trigger input with interrupt generation on rising signal edges.
•
Schmitt trigger input with interrupt generation on falling/rising signal edges.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 2 control registers must also be enabled in the associated peripheral module.
9.2.3.2 Port 2 Interrupt Enable and Pending Registers (P2INTH, P2INTL, P2PND)
To process external interrupts at the port 2 pins, the additional control registers are provided: the port 2 interrupt
enable register P2INTH (high byte, E8H, set 1, bank 1), P2INTL (Low byte, E9H, set1, bank1) and the port 2
interrupt pending register P2PND (EAH, set 1, bank 1).
The port 2 interrupt pending register P2PND lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests
by polling the P2PND register at regular intervals.
When the interrupt enable bit of any port 2 pin is "1", a rising or falling signal edge at that pin will generate an
interrupt request. The corresponding P2PND bit is then automatically set to "1" and the IRQ level goes low to
signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application
software must the clear the pending condition by writing a "0" to the corresponding P2PND bit.
PS032408-0220
PRELIMINARY
9-8
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 2 Control Register, High Byte (P2CONH)
E6H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
P2.7/INT7/
SEG19
.4
P2.6/INT6/
SEG18
.3
.2
P2.5/INT5/
SEG17
.1
.0
LSB
P2.4/INT4/
SEG16
P2CONH bit-pair pin configuration settings:
00
Schmitt trigger input mode
01
Schmitt trigger input mode, pull-up
10
Alternative function (LCD signal)
11
Push-pull output mode
Figure 9-8
Port 2 High-Byte Control Register (P2CONH)
Port 2 Control Register, Low Byte (P2CONL)
E7H, Set 1, Bank 1, R/W
MSB
.7
.6
P2.3/INT3/
SEG15
.5
.4
P2.2/INT2/
SEG14
.3
.2
P2.1/INT1/
SEG13
.1
.0
LSB
P2.0/INT0/
SEG12
P2CONL bit-pair pin configuration settings:
00
Schmitt trigger input mode
01
Schmitt trigger input mode, pull-up
10
Alternative function (LCD signal)
11
Output mode, push-pull
Figure 9-9
PS032408-0220
Port 2 Low-Byte Control Register (P2CONL)
PRELIMINARY
9-9
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 2 Interrupt Control Register, High Byte (P2INTH)
E8H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
INT7
.4
.3
INT6
.2
.1
INT5
.0
LSB
INT4
P2INTH bit-pair pin configuration settings:
00
Disable interrupt
01
Enable interrupt by falling edge
10
Enable interrupt by rising edge
11
Enable interrupt by both falling and rising edge
Figure 9-10
Port 2 High-Byte Interrupt Control Register (P2INTH)
Port 2 Interrupt Control Register, Low Byte (P2INTL)
E9H, Set 1, Bank 1, R/W
MSB
.7
.6
INT3
.5
.4
INT2
.3
.2
INT1
.1
.0
LSB
INT0
P2INTL bit-pair pin configuration settings:
00
Disable interrupt
01
Enable interrupt by falling edge
10
Enable interrupt by rising edge
11
Enable interrupt by both falling and rising edge
Figure 9-11
PS032408-0220
Port 2 Low-Byte Interrupt Control Register (P2INTL)
PRELIMINARY
9-10
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 2 Interrupt Pending Register (P2PND)
EAH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0
P2PND bit configuration settings:
0
Interrupt request is not pending,
pending bit clear when write 0
1
Interrupt request is pending
Figure 9-12
PS032408-0220
Port 2 Interrupt Pending Register (P2PND)
PRELIMINARY
9-11
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.4 Port 3
Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading
the port 3 data register, P3 at location 03H in page 8. P3.0–P3.7 can serve as inputs (with or without pull-ups),
and outputs (push pull or open-drain). And the P3.7–P3.0 can serve as segment pins for LCD or you can configure
the following alternative functions:
•
Low-byte pins (P3.0–P3.1): TBPWM/PG0, TCOUT/PG1
•
Middle-byte pins (P3.2–P3.4): PG2, TD0OUT/TD0PWM/TD0CAP/PG3, TD0CLK/PG4
•
High-byte pins (P3.5–P3.7): TD1OUT/TD1PWM/TD1CAP/PG5, TD1CLK/PG6, BUZ/PG7
9.2.4.1 Port 3 Control Registers (P3CONH, P3CONM P3CONL)
Port 3 has three 8-bit control registers: P3CONH for P3.5–P3.7, P3CONM for P3.2–P3.4 and P3CONL for P3.0–
P3.1. A reset clears the P3CONH, P3CONM and P3CONL registers to "00H", configuring all pins to input mode.
You use control registers settings to select input or output mode, and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 3 control registers must also be enabled in the associated peripheral module.
9.2.4.2 Port 3 Pull-Up Resistor Enable Register (P3PUR)
Using the port 3 pull-up resistor enable register, P3PUR (EEH, set1, bank1), you can configure pull-up resistors to
individual port 3 pins.
PS032408-0220
PRELIMINARY
9-12
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.4.3 Port 3 N-Channel Open-Drain Mode Register (PNE3)
Using the port 3 n-channel open-drain mode register, PNE3 (EFH, set1, bank1), you can configure push-pull or
open-drain output mode to individual port 3 pins.
Port 3 Control Register, High Byte (P3CONH)
EBH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
P3.7/BUZ/
PG7/SEG27
.1
.0
LSB
P3.5/TD1OUT/
TD1PWM/TD1CAP/
PG5/SEG25
P3.6/TD1CLK/PG6/SEG26
bit-pair pin configuration settings:
00
01
10
11
.2
Input mode (TD1CLK)
P3CONH bit-pair pin configuration settings:
Alternative function (PG6)
000 Input mode (TD1CAP)
Alternative function (LCD signal)
001 Alternative function (PG5, PG7)
Output mode
010 Alternative function (LCD signal)
011 Output mode
1xx Alternative function (TD1OUT/TD1PWM, BUZ)
Figure 9-13
Port 3 High-Byte Control Register (P3CONH)
Port 3 Control Register, Middle Byte (P3CONM)
ECH, Set 1, Bank 1, R/W
MSB
.7
P3.4/TD0CLK/PG4/SEG24
bit-pair pin configuration settings:
00
01
10
11
.5
.4
.3
.2
.1
.0
LSB
P3.3/TD0OUT/
P3.2/PG2/SEG22
TD0PWM/TD0CAP/
PG3/SEG23
Input mode (TD0CLK)
P3CONM bit-pair pin configuration settings:
Alternative function (PG4)
Alternative function (LCD signal) 000 Input mode (TD0CAP)
Output mode
001 Alternative function (PG2, PG3)
010 Alternative function (LCD signal)
011 Output mode
1xx Alternative function (TD0OUT/TD0PWM)
Figure 9-14
PS032408-0220
.6
Port 3 Middle-Byte Control Register (P3CONM)
PRELIMINARY
9-13
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 3 Control Register, Low Byte (P3CONL)
EDH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
Not used for the
S3F8S6B
.4
.3
.2
.1
.0
LSB
P3.0/TBPWM/PG0
/SEG20
P3.1/TCOUT/
PG1/SEG21
P3CONL bit-pair pin configuration settings:
000
001
010
011
1xx
Input mode
Alternative function (PG0, PG1)
Alternative function (LCD signal)
Output mode
Alternative function (TBPWM, TCOUT)
Figure 9-15
Port 3 Low-Byte Control Register (P3CONL)
Port 3 Pull-up Resistor Enable Register (P3PUR)
EEH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
P3.7
P3.6
P3.5
P3.4
.3
.2
.1
.0
P3.3
P3.2
P3.1
P3.0
LSB
P3PUR bit configuration settings:
0
Disable Pull-up Resistor
1
Enable Pull-up Resistor
NOTE: A pull-up resistor of port 3 is automatically disabled
only when the corresponding pin is selected as
push-pull output or alternative function.
Figure 9-16
PS032408-0220
Port 3 Pull-Up Resistor Enable Register (P3PUR)
PRELIMINARY
9-14
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 3 N-Channel Open-drain Mode Register (PNE3)
EFH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
P3.7
P3.6
P3.5
P3.4
.3
.2
P3.3 P3.2
.1
P3.1
.0
LSB
P3.0
PNE3 bit configuration settings:
Figure 9-17
PS032408-0220
0
Push-pull output mode
1
Open-drain output mode
Port 3 N-Channel Open-Drain Mode Register (PNE3)
PRELIMINARY
9-15
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.5 Port 4
Port 4 is an 8-bit I/O port that can be used for general purpose I/O as A/D converter inputs, AD0-AD7. Port 4 pins
are accessed directly by writing or reading the port 4 data register, P4 at location 04H in page 8. P4.0–P4.7 can
serve as inputs (with or without pull-ups), and push-pull outputs or you can configure the following alternative
functions:
•
Low-byte pins (P4.0–P4.3): INT8-INT11/AD0-AD3
•
High-byte pins (P4.4–P4.7): INT12-INT15/AD4-AD7
9.2.5.1 Port 4 Control Register (P4CONH, P4CONL)
Port 4 has two 8-bit control registers: P4CONH for P4.4-P4.7 and P4CONL for P4.0-P4.3. A reset clears the
P4CONH and P4CONL registers to "00H", configuring all pins to input mode. In input mode, three different
selections are available:
•
Schmitt trigger input with interrupt generation on falling signal edges.
•
Schmitt trigger input with interrupt generation on rising signal edges.
•
Schmitt trigger input with interrupt generation on falling/rising signal edges.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 4 control registers must also be enabled in the associated peripheral module.
9.2.5.2 Port 4 Interrupt Enable and Pending Registers (P4INTH, P4INTL, P4PND)
To process external interrupts at the port 4 pins, the additional control registers are provided: the port 4 interrupt
enable register P4INTH (high byte, 0EH, page 8), P4INTL (Low byte, 0FH, page 8) and the port 4 interrupt
pending register P4PND (10H, page 8).
The port 4 interrupt pending register P4PND lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests
by polling the P4PND register at regular intervals.
When the interrupt enable bit of any port 4 pin is "1", a rising or falling signal edge at that pin will generate an
interrupt request. The corresponding P4PND bit is then automatically set to "1" and the IRQ level goes low to
signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application
software must the clear the pending condition by writing a "0" to the corresponding P4PND bit.
PS032408-0220
PRELIMINARY
9-16
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 4 Control Register, High Byte (P4CONH)
0CH, Page 8, R/W
MSB
.7
.6
P4.7/INT15
/AD7
.5
.4
P4.6/INT14
/AD6
.3
.2
P4.5/INT13
/AD5
.1
.0
LSB
P4.4/INT12
/AD4
P4CONH bit-pair pin configuration settings:
00
Schmitt trigger input mode
01
Schmitt trigger input mode, pull-up
10
Alternative function (AD4-AD7)
11
Output mode, push-pull
Figure 9-18
Port 4 High-Byte Control Register (P4CONH)
Port 4 Control Register, Low Byte (P4CONL)
0DH, Page 8, R/W
MSB
.7
.6
P4.3/INT11
/AD3
.5
.4
P4.2/INT10
/AD2
.3
.2
P4.1/INT9
/AD1
.1
.0
LSB
P4.0/INT8
/AD0
P4CONL bit-pair pin configuration settings:
00
Schmitt trigger input mode
01
Schmitt trigger input mode, pull-up
10
Alternative function (AD0-AD3)
11
Output mode, push-pull
Figure 9-19
PS032408-0220
Port 4 Low-Byte Control Register (P4CONL)
PRELIMINARY
9-17
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 4 Interrupt Control Register, High Byte (P4INTH)
0EH, Page 8, R/W
MSB
.7
.6
INT15
.5
.4
INT14
.3
.2
INT13
.1
.0
LSB
INT12
P4INTH bit-pair pin configuration settings:
00
Disable interrupt
01
Enable interrupt by falling edge
10
Enable interrupt by rising edge
11
Enable interrupt by both falling and rising edge
Figure 9-20
Port 4 High-Byte Interrupt Control Register (P4INTH)
Port 4 Interrupt Control Register, Low Byte (P4INTL)
0FH, Page 8, R/W
MSB
.7
.6
INT11
.5
.4
INT10
.3
.2
INT9
.1
.0
LSB
INT8
P4INTL bit-pair pin configuration settings:
00
Disable interrupt
01
Enable interrupt by falling edge
10
Enable interrupt by rising edge
11
Enable interrupt by both falling and rising edge
Figure 9-21
PS032408-0220
Port 4 Low-Byte Interrupt Control Register (P4INTL)
PRELIMINARY
9-18
S3F8S6B Product Specification
Chapter 9. I/O Port
Port4 Interrupt Pending Register (P4PND)
10H, Page 8, R/W
MSB
.7
PND15
.6
PND14
Figure 9-22
PS032408-0220
.5
.4
PND13
PND12
.3
PND11
.2
PND10
.1
PND9
.0
LSB
PND8
P4PND bit configuration settings:
0
Interrupt request is not pending,
pending bit clear when write 0
1
Interrupt request is pending
Port 4 Interrupt Pending Register (P4PND)
PRELIMINARY
9-19
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.6 Port 5
Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading
the port 5 data register, P5 at location 05H in page 8. P5.0–P5.7 can serve as inputs (with or without pull-ups) and
push-pull outputs or you can configure the following alternative functions:
•
Low-byte pins (P5.0–P5.3): VLC0–VLC3
•
High-byte pins (P5.4–P5.7): CA, CB, XTOUT, XTIN
9.2.6.1 Port 5 Control Registers (P5CONH, P5CONL)
Port 5 has two 8-bit control registers: P5CONH for P5.4–P5.7 and P5CONL for P5.0–P5.3. A reset clears the
P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers settings to
select input (with or without pull-ups) or push-pull output mode and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 5 control registers must also be enabled in the associated peripheral module.
Port 5 Control Register, High Byte (P5CONH)
F0H, Set 1, Bank 1, R/W
MSB
.7
.6
P5.7/XTIN
.5
.4
P5.6/XTOUT
.3
.2
P5.5/CB
.1
.0
LSB
P5.4/CA
P5CONH bit-pair pin configuration settings:
00
01
10
Input mode
Input mode, pull-up
Alternative function (XTOUT, XTIN)
11
Output mode, push-pull
NOTE: Refer to LCON register in Chapter 15.
Figure 9-23
PS032408-0220
Port 5 High-Byte Control Register (P5CONH)
PRELIMINARY
9-20
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 5 Control Register, Low Byte (P5CONL)
F1H, Set 1, Bank 1, R/W
MSB
.7
.6
P5.3/VLC3
.5
.4
P5.2/VLC2
.3
.2
P5.1/VLC1
.1
.0
LSB
P5.0/VLC0
P5CONL bit-pair pin configuration settings:
00
01
Input mode
Input mode, pull-up
10
11
Not available
Output mode, push-pull
NOTE: Refer to LCON register in Chapter 15.
Figure 9-24
PS032408-0220
Port 5 Low-Byte Control Register (P5CONL)
PRELIMINARY
9-21
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.7 Port 6
Port 6 is an 8-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading
the port 6 data register, P6 at location 06H in page 8. P6.0–P6.5 can serve as inputs (with or without pull-ups),
and outputs (push pull or open-drain). And the P6.5–P6.0 can serve as segment pins for LCD or you can configure
the following alternative functions:
•
Low-byte pins (P6.0-P6.3): SCK, SI, SO
9.2.7.1 Port 6 Control Register (P6CONH, P6CONL)
Port 6 has two 8-bit control registers: P6CONH for P6.4–P6.5 and P6CONL for P6.0–P6.3. A reset clears the
P6CONH and P6CONL registers to "00H", configuring all pins to input mode. You use control registers settings to
select input or output mode and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using the
port 6 control registers must also be enabled in the associated peripheral module.
9.2.7.2 Port 6 Pull-Up Resistor Enable Register (P6PUR)
Using the port 6 pull-up resistor enable register, P6PUR (F4H, set1, bank1), you can configure pull-up resistors to
individual port 6 pins.
PS032408-0220
PRELIMINARY
9-22
S3F8S6B Product Specification
Chapter 9. I/O Port
9.2.7.3 Port 6 N-Channel Open-Drain Mode Register (PNE6)
Using the port 6 n-channel open-drain mode register, PNE6 (F5H, set1, bank1), you can configure push-pull or
open-drain output mode to individual port 6 pins.
Port 6 Control Register, High Byte (P6CONH)
F2H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
Not used for the S3F8S6B
.3
.2
.1
.0
LSB
P6.5/SEG33 P6.4/SEG32
P6CONH bit-pair pin configuration settings:
00
01
10
Input mode
Not available
Alternative function (LCD signal)
11
Output mode
Figure 9-25
Port 6 High-Byte Control Register (P6CONH)
Port 6 Control Register, Low Byte (P6CONL)
F3H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P6.3/SEG31 P6.2/SEG30 P6.1/SEG29 P6.0/SEG28
/SO
/SI
/SCK
P6CONL bit-pair pin configuration settings:
00
01
10
Input mode (SCK, SI)
Alternative function (SCK, SO)
Alternative function (LCD signal)
11
Output mode
Figure 9-26
PS032408-0220
Port 6 Low-Byte Control Register (P6CONL)
PRELIMINARY
9-23
S3F8S6B Product Specification
Chapter 9. I/O Port
Port 6 Pull-up Resistor Enable Register (P6PUR)
F4H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
P6.5
P6.4
.3
.2
.1
.0
P6.3
P6.2
P6.1
P6.0
LSB
Not used for the S3F8S6B
P6PUR bit configuration settings:
0
Disable Pull-up Resistor
1
Enable Pull-up Resistor
NOTE: A pull-up resistor of port 6 is automatically disabled
only when the corresponding pin is selected as
push-pull output or alternative function.
Figure 9-27
Port 6 Pull-up Resistor Enable Register (P6PUR)
Port 6 N-Channel Open-drain Mode Register (PNE6)
F5H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
P6.5
P6.4
.3
.2
P6.3 P6.2
.1
P6.1
.0
LSB
P6.0
Not used for the S3F8S6B
PNE6 bit configuration settings:
Figure 9-28
PS032408-0220
0
Push-pull output mode
1
Open-drainl output mode
Port 6 N-Channel Open-drain Mode Register (PNE6)
PRELIMINARY
9-24
S3F8S6B Product Specification
10
Chapter 10. Basic Timer
Basic Timer
10.1 Overview
S3F8S6B has an 8-bit basic timer.
10.1.1 Basic Timer (BT)
You can use the basic timer (BT) in two different ways:
•
As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.
•
To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
The functional components of the basic timer block are:
•
Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer
•
8-bit basic timer counter, BTCNT (set 1, Bank 0, FDH, read-only)
•
Basic timer control register, BTCON (set 1, D3H, read/write)
PS032408-0220
PRELIMINARY
10-1
S3F8S6B Product Specification
Chapter 10. Basic Timer
10.2 Basic Timer Control Register (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,
address D3H, and is read/write addressable using Register addressing mode.
A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of
fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register
control bits BTCON.7–BTCON.4.
The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during the normal operation
by writing a "1" to BTCON.1. To clear the frequency dividers, write a "1" to BTCON.0.
Basic TImer Control Register (BTCON)
D3H, Set 1, R/W
MSB
.7
.6
.5
.4
.3
Watchdog timer enable bits:
1010B
= Disable watchdog function
Other value = Enable watchdog function
.2
.1
.0
LSB
Divider clear bit:
0 = No effect
1= Clear dvider
Basic timer counter clear bit:
0 = No effect
1= Clear BTCNT
Basic timer input clock selection bits:
00 = fXX/4096
01 = fXX/1024
10 = fXX/128
11 = fXX/16
Figure 10-1
PS032408-0220
Basic Timer Control Register (BTCON)
PRELIMINARY
10-2
S3F8S6B Product Specification
Chapter 10. Basic Timer
10.3 Basic Timer Function Description
10.3.1 Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to
any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to
"00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by
the current CLKCON register setting), divided by 4096, as the BT clock.
The MCU is resented whenever a basic timer counter overflow occurs, During normal operation, the application
program must prevent the overflow, and the accompanying reset operation, from occurring, To do this, the BTCNT
value must be cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken
by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
10.3.2 Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when Stop
mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).
When BTCNT.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate
the clock signal off to the CPU so that it can resume the normal operation.
In summary, the following events occur when Stop mode is released:
1. During the Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and
oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an interrupt is
used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.
3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows.
4. When a BTCNT.4 overflow occurs, the normal CPU operation resumes.
PS032408-0220
PRELIMINARY
10-3
S3F8S6B Product Specification
Chapter 10. Basic Timer
RESET or STOP
Bit 1
Bits 3, 2
Basic Timer Control Register
(Write '1010xxxxB' to Disable)
Data Bus
fXX/4096
Clear
fXX/1024
fXX
DIV
fXX/128
MUX
8-Bit Up Counter
(BTCNT, Read-Only)
OVF
RESET
fXX/16
Start the CPU (NOTE)
R
Bit 0
NOTE:
During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
Figure 10-2
PS032408-0220
Basic Timer Block Diagram
PRELIMINARY
10-4
S3F8S6B Product Specification
11
Chapter 11. 8-Bit Timer A/B
8-Bit Timer A/B
11.1 8-Bit Timer A
11.1.1 Overview
The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A has three operating modes, one of which you
select using the appropriate TACON setting:
•
Interval timer mode (Toggle output at TAOUT pin)
•
Capture input mode with a rising or falling edge trigger at the TACAP pin
•
PWM mode (TAPWM)
Timer A has the following functional components:
•
Clock frequency divider (fxx divided by 1024, 256, 64, 8 or 1) with multiplexer
•
External clock input pin (TACLK)
•
8-bit counter (TACNT), 8-bit comparator, and 8-bit reference data register (TADATA)
•
I/O pins for capture input (TACAP) or PWM or match output (TAPWM, TAOUT)
•
Timer A overflow interrupt (IRQ0 vector D0H) and match/capture interrupt (IRQ0 vector CEH) generation
•
Timer A control register, TACON (set 1, Bank 0, E2H, read/write)
PS032408-0220
PRELIMINARY
11-1
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
11.1.2 Timer A Control Register (TACON)
You use the timer A control register, TACON, to
•
Select the timer A operating mode (interval timer, capture mode, or PWM mode)
•
Select the timer A input clock frequency
•
Clear the timer A counter, TACNT
•
Enable the timer A overflow interrupt or timer A match/capture interrupt
TACON is located in set 1, Bank 0 at address E2H, and is read/write addressable using Register addressing
mode.
A reset clears TACON to '00H'. This sets timer A to normal interval timer mode, selects an input clock frequency of
fxx/1024, and disables all timer A interrupts. You can clear the timer A counter at any time during normal operation
by writing a "1" to TACON.2.
The timer A overflow interrupt (TAOVF) is interrupt level IRQ0 and has the vector address D0H. When a timer A
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware
or must be cleared by software.
To enable the timer A match/capture interrupt (IRQ0, vector CEH), you must write TACON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls INTPND.1. When a "1" is detected, a
timer A match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition
must be cleared by software by writing a "0" to the timer A match/capture interrupt pending bit, INTPND.1.
Timer A Control Register (TACON)
E2H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
Timer A input clock selection bits:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx/1
101 = External clock (TACLK) falling edge
110 = External clock (TACLK) rising edge
111 = Counter stop
.3
.2
.1
.0
LSB
Timer A overflow interrupt enable bit:
0 = Disable oveflow interrupt
1 = Enable overflow interrupt
Timer A match/capture interrupt enable bit:
0 = DIsable interrupt
1 = Enable interrupt
Timer A counter clear bit:
0 = No effect
1 = Clear the timer A counter (when write)
Timer A operating mode selection bits:
00 = Interval mode (TAOUT)
01 = Capture mode (capture on rising edge,
Counter running, OVF can occur)
10 = Capture mode (Capture on falling edge,
Counter running, OVF can occur)
11 = PWM mode (OVF and match interrupt can occur)
Figure 11-1
PS032408-0220
Timer A Control Register (TACON)
PRELIMINARY
11-2
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
11.1.3 Timer A Function Description
11.1.3.1 Timer A Interrupts (IRQ0, Vectors CEH and D0H)
The timer A can generate two interrupts: the timer A overflow interrupt (TAOVF), and the timer A match/capture
interrupt (TAINT). TAOVF is interrupt level IRQ0, vector D0H. TAINT also belongs to interrupt level IRQ0, but is
assigned the separate vector address, CEH.
A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or
should be cleared by software in the interrupt service routine by writing a "0" to the INTPND.0 interrupt pending bit.
However, the timer A match/capture interrupt pending condition must be cleared by the application's interrupt
service routine by writing a "0" to the INTPND.1 interrupt pending bit.
11.1.3.2 Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
timer A reference data register, TADATA. The match signal generates a timer A match interrupt (TAINT, vector
CEH) and clears the counter.
If, for example, you write the value "10H" to TADATA, the counter will increment until it reaches "10H". At this
point, the timer A interrupt request is generated, the counter value is reset, and counting resumes. With each
match, the level of the signal at the timer A output pin is inverted (see Figure 11-2).
Interrupt Enable/Disable
Capture Signal
8-Bit Up Counter
CLK
8-Bit Comparator
TACON.1
R (Clear)
M
U
X
Match
TAINT (IRQ0)
INTPND.1
(Match INT)
Pending
TAOUT
Timer A Buffer Register
TACON.4-.3
Match Signal
TACON.2
TAOVF
Timer A Data Register
Figure 11-2
PS032408-0220
Simplified Timer A Function Diagram: Interval Timer Mode
PRELIMINARY
11-3
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
11.1.3.3 Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
TAPWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the timer A data register. In PWM mode, however, the match signal does not clear the counter.
Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".
Although you can use the match signal to generate a timer A overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the TAPWM pin is held to Low level as long as the reference data
value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the data
value is greater than ( > ) the counter value. One pulse width is equal to tCLK 256 (see Figure 11-3).
TACON.0
Capture Signal
Interrupt Enable/Disable
TACON.1
TAOVF(IRQ0)
8-Bit Up Counter
CLK
8-Bit Comparator
INTPND.0
(Overflow INT)
M
U
X
Match
Timer A Buffer Register
TAINT (IRQ0)
INTPND.1
Pending
TACON.4-.3
Match Signal
TACON.2
TAOVF
(Match INT)
TAPWM
Output
High level when
data > counter,
Lower level when
data < counter
Timer A Data Register
Figure 11-3
PS032408-0220
Simplified Timer A Function Diagram: PWM Mode
PRELIMINARY
11-4
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
11.1.3.4 Capture Mode
In capture mode, a signal edge that is detected at the TACAP pin opens a gate and loads the current counter
value into the timer A data register. You can select rising or falling edges to trigger this operation.
Timer A also gives you capture input source: the signal edge at the TACAP pin. You select the capture input by
setting the values of the timer A capture input selection bits in the port 1 control register, P1CONH.5–.4, (set 1,
bank 1, E2H). When P1CONH.5–.4 is "00" the TACAP input is selected.
Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever
a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded
into the timer A data register.
By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you
can calculate the pulse width (duration) of the signal that is being input at the TACAP pin (see Figure 11-4).
TACON.0
TAOVF(IRQ0)
CLK
8-Bit Up Counter
INTPND.0
(Overflow INT)
Interrupt Enable/Disable
TACON.1
TACAP
Match Signal
M
U
X
TAINT (IRQ0)
INTPND.1
(Capture INT)
Pending
TACON.4-.3
TACON.4-.3
Timer A Data Register
Figure 11-4
PS032408-0220
Simplified Timer A Function Diagram: Capture Mode
PRELIMINARY
11-5
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
11.1.4 Block Diagram
TACON.0
TACON.7-.5
TAOVF
OVF
Data Bus
fXX/1024
fXX/256
fXX/64
fXX/8
fXX/1
8
U
TACLK
Clear
R
TACON.1
X
Vss
M
8-bit Comparator
Match
U
M
U
X
TACAP
(IRQ0)
TACON.2
M
8-bit Up-Counter
(Read Only)
INTPND.0
TAINT
INTPND.1
(IRQ0)
X
TAOUT
TAPWM
Timer A Buffer Register
TACON.4-.3
TACON.4-.3
Match Signal
TACON.2
TAOVF
PG output signal
Timer A Data Register
8
Data Bus
Figure 11-5
PS032408-0220
Timer A Functional Block Diagram
PRELIMINARY
11-6
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
11.2 8-Bit Timer B
11.2.1 Overview
The S3F8S6B micro-controller has an 8-bit counter called timer B. Timer B, which can be used to generate the
carrier frequency of a remote controller signal.
Timer B has two functions:
•
As a normal interval timer, generating a timer B interrupt at programmed time intervals.
•
To supply a clock source to the 8-bit timer/counter module, timer B, for generating the timer B overflow
interrupt.
Timer B Control Register (TBCON)
E3H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
Timer B input clock selection bits:
00 = fxx
01 = fxx/2
10 = fxx/4
11 = fxx/8
.1
.0
LSB
Timer B output flip-flop control bit:
0 = TBOF is low(TBPWM: low level for
low data, high level for high data)
1 = TBOF is high(TBPWM: high level for
low data, low level for high data)
Timer B interrupt time selection bits:
00 = Generating after low data is borrowed
01 = Generating after high data is borrowed
10 = Generating after low and high data are borrowed
11 = Not available
Timer B mode selection bit:
0 = One-shot mode
1 = Repeating mode
Timer B start/stop bit:
0 = Stop timer B
1 = Start timer B
Timer B interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
NOTE: Pending condition of timer B is cleared automatically by hardware.
Figure 11-6
PS032408-0220
Timer B Control Register
PRELIMINARY
11-7
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
11.2.2 Block diagram
TBCON.6-.7
TBCON.2
PG output signal
fXX/1
fXX/2
M
CLK
fXX/4
U
fXX/8
X
Repeat Control
8-bit
Down Counter
MUX
Interrupt Control
TBCON.0
(TBOF)
To Other Block
(TBPWM)
TBCON.3
INT.GEN
IRQ1
(TBINT)
Timer B Data
Low Byte Register
TBCON.4-.5
Timer B Data
High Byte Register
8
Data Bus
NOTE:
The value of the TBDATAL register is loaded into the 8-bit counter when the operation of the timer B
starts. If a borrow occurs in the counter, the value of the TBDATAH register is loaded into the 8-bit
counter. However, if the next borrow occurs, the value of the TBDATAL register is loaded into the
8-bit counter.
Figure 11-7
PS032408-0220
Timer B Functional Block Diagram
PRELIMINARY
11-8
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
11.2.3 Timer b PULSE WIDTH CALCULATIONS
tLOW
tHIGH
tLOW
To generate the above repeated waveform consisted of low period time, tLOW, and high period time, tHIGH.
When TBOF = 0,
tLOW = (TBDATAL + 2) 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.
tHIGH = (TBDATAH + 2) 1/fx, 0H < TBDATAH < 100H, where fx = The selected clock.
When TBOF = 1,
tLOW = (TBDATAH + 2) 1/fx, 0H < TBDATAH < 100H, where fx = The selected clock.
tHIGH = (TBDATAL + 2) 1/fx, 0H < TBDATAL < 100H, where fx = The selected clock.
To make tLOW = 24 s and tHIGH = 15 us.
fOSC = 4 MHz, fx = 4 MHz/4 = 1 MHz
When TBOF = 0,
tLOW = 24 s = (TBDATAL + 2) /fx = (TBDATAL + 2) 1 s, TBDATAL = 22.
tHIGH = 15 s = (TBDATAH + 2) /fx = (TBDATAH + 2) 1 s, TBDATAH = 13.
When TBOF = 1,
tHIGH = 15 s = (TBDATAL + 2) /fx = (TBDATAL + 2) 1 s, TBDATAL = 13.
tLOW = 24 s = (TBDATAH + 2) /fx = (TBDATAH + 2) 1 s, TBDATAH = 22.
PS032408-0220
PRELIMINARY
11-9
S3F8S6B Product Specification
Chapter 11. 8-Bit Timer A/B
0H
Tim er B Clock
TBOF = '0'
TBDATAL = 01-FFH
TBDATAH = 00H
Low
TBOF = '0'
TBDATAL = 00H
TBDATAH = 01-FFH
High
TBOF = '0'
TBDATAL = 00H
TBDATAH = 00H
Low
TBOF = '1'
TBDATAL = 00H
TBDATAH = 00H
High
0H
100H
200H
Tim er B Clock
TBOF = '1'
TBDATAL = DEH
TBDATAH = 1EH
E0H
TBOF = '0'
TBDATAL = DEH
TBDATAH = 1EH
E0H
TBOF = '1'
TBDATAL = 7EH
TBDATAH = 7EH
TBOF = '0'
TBDATAL = 7EH
TBDATAH = 7EH
Figure 11-8
PS032408-0220
20H
20H
80H
80H
80H
80H
Timer B Output Flip-Flop Waveforms in Repeat Mode
PRELIMINARY
11-10
S3F8S6B Product Specification
Example 11-1
Chapter 11. 8-Bit Timer A/B
To Generate 38 kHz, 1/3 Duty Signal Through P3.0
This example sets Timer B to the repeat mode, sets the oscillation frequency as the Timer B clock source, and
TBDATAH and TBDATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are:
8.795 s
17.59 s
37.9 kHz 1/3 Duty
•
Timer B is used in repeat mode
•
Oscillation frequency is 4 MHz (0.25
•
TBDATAH = 8.795 s/0.25 s = 35.18, TBDATAL = 17.59 s/0.25 s = 70.36
•
Set P3.0 to TBPWM mode.
ORG
s)
0100H
; Reset address
LD
TBDATAL,#(70-2)
; Set 17.5
s
LD
TBDATAH,#(35-2)
; Set 8.75
s
LD
TBCON,#00000111B
; Clock Source fxx
START DI
•
•
•
; Disable Timer B interrupt.
; Select repeat mode for Timer B.
; Start Timer B operation.
; Set Timer B Output flip-flop (TBOF) high.
OR
P3CONL,#07H
; Set P3.0 to TBPWM mode.
; This command generates 38 kHz, 1/3 duty pulse signal
through P3.0.
•
•
•
PS032408-0220
PRELIMINARY
11-11
S3F8S6B Product Specification
Example 11-2
Chapter 11. 8-Bit Timer A/B
To Generate a One Pulse Signal Through P3.0
This example sets Timer B to the one shot mode, sets the oscillation frequency as the Timer B clock source, and
TBDATAH and TBDATAL to make a 40 s width pulse. The program parameters are:
40 s
•
Timer B is used in one shot mode
•
Oscillation frequency is 4 MHz (1 clock = 0.25 s)
•
TBDATAH = 40 s/0.25 s = 160, TBDATAL = 1
•
Set P3.0 to TBPWM mode
ORG
0100H
;
Reset address
LD
TBDATAH,# (160-2)
; Set 40
LD
TBDATAL,# 1
; Set any value except 00H
LD
TBCON,#00000001B
; Clock Source fOSC
START DI
•
•
•
s
; Disable Timer B interrupt.
; Select one shot mode for Timer B.
; Stop Timer B operation.
; Set Timer B output flip-flop (TBOF) high
OR
P3CONL, #07H
; Set P3.0 to TBPWM mode.
LD
; Start Timer B operation
•
•
Pulse_out:
TBCON,#00000101B
; To make the pulse at this point.
•
•
; After the instruction is executed, 0.75 s is required
; before the falling edge of the pulse starts.
•
PS032408-0220
PRELIMINARY
11-12
S3F8S6B Product Specification
12
Chapter 12. 8-Bit Timer C
8-Bit Timer C
12.1 8-Bit Timer C
12.1.1 Overview
The 8-bit timer C is an 8-bit general-purpose timer/counter.
Timer C has two operating mode, you can select one of them using the appropriate TCCON setting:
•
Interval timer mode (Toggle output at TCOUT pin), only match interrupt occurs
•
PWM mode (TCPWM pin), match and overflow interrupt can occur
Timer C has the following functional components:
•
Clock frequency divider with multiplexer
•
8-bit counter, 8-bit comparator, and 8-bit reference data register (TCDATA)
•
PWM or match output (TCOUT/TCPWM)
•
Timer C match/overflow interrupt (IRQ2, vector D4H) generation
•
Timer C control register, TCCON (set 1, bank0, ECH, read/write)
PS032408-0220
PRELIMINARY
12-1
S3F8S6B Product Specification
Chapter 12. 8-Bit Timer C
12.1.2 Timer c Control Register (TcCON)
You use the timer C control register, TCCON, to
•
Select the timer C operating mode (fxx/1 & PWM mode or fxx/64 & interval mode)
•
Select the timer C 3-bits prescaler
•
Clear the timer C counter, TCCNT
•
Enable the timer C match/overflow interrupt
•
Start the timer C
TCCON is located in set 1, Bank 0 at address ECH, and is read/write addressable using Register addressing
mode.
A reset clears TCCON to '00H'. This sets timer C to fxx/1&PWM timer mode, selects a 3-bits prescaler of non
divided, stop timer C and disables all timer C interrupts. You can clear the timer C counter at any time during
normal operation by writing a "1" to TCCON.3.
To enable the timer C match/overflow interrupt (IRQ2, vector D4H), you must write TCCON.7 and TCCON.1 to "1".
To generate the exact time interval, you should write TCCON.3 and 0, which cleared counter and interrupt pending
bit. To detect an interrupt pending condition when TCINT is disabled, the application program poll pending bit,
TCCON.0. When a "1" is detected, a timer C match/overflow interrupt is pending. When the TCINT sub-routine
has been serviced, the pending condition is cleared automatically by hardware or must be cleared by software by
writing a "0" to the timer C interrupt pending bit, TCCON.0.
Timer C Control Register (TCCON)
ECH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer C interrupt Pending bit:
0 = Interrupt request is not pending
(Clear pending bit when write "0")
1 = Interrupt request is pending
Timer C start/stop bit:
0 = Stop timer C
1 = Start timer C
Timer C 3-bits prescaler bits:
Timer C interrupt enable bit:
000 = Non divided
0 = DIsable interrupt
001 = Divided by 2
1 = Enable interrupt
010 = Divided by 3
Timer C counter clear bit:
011 = Divided by 4
0 = fxx/1 & PWM mode
100 = Divided by 5
1 = fxx/64 & interval mode
101 = Divided by 6
110 = Divided by 7
Timer C counter clear bit:
111 = Divided by 8
0 = No effect
1 = Clear the timer C counter (when write)
Figure 12-1
PS032408-0220
Timer C Control Register (TCCON)
PRELIMINARY
12-2
S3F8S6B Product Specification
Chapter 12. 8-Bit Timer C
12.1.3 Block Diagram
TCCON.1
TCCON.7
TCCON.6-.4
Data bus
overflow
8
3-bit
Prescaler
8-bit up-counter
(read only)
TCINT
Pending
TCCON.0
Clear
TCCON.3
TCCON.1
8-bit comparator
TCINT
Pending
TCCON.2
TCCON.0
fxx/1
fxx/64
Timer C buffer reg
M
U
X
TCCON.2
TCOUT/TCPWM
Timer C data register
8
Data bus
NOTE:
When PWM mode, match signal cannot clear counter.
Figure 12-2
PS032408-0220
Timer C Function Block Diagram
PRELIMINARY
12-3
S3F8S6B Product Specification
13
Chapter 13. 16-Bit Timer D0/D1
16-Bit Timer D0/D1
13.1 16-Bit Timer D0
13.1.1 Overview
The 16-bit timer D0 is an 16-bit general-purpose timer.
Timer D0 has three operating modes, one of which you select using the appropriate TD0CON, TD0CON setting is
•
Interval timer mode (Toggle output at TD0OUT pin)
•
Capture input mode with a rising or falling edge trigger at the TD0CAP pin
•
PWM mode (TD0PWM); PWM output shares their output port with TD0OUT pin
Timer D0 has the following functional components:
•
Clock frequency divider (fxx divided by 1024, 256, 64, 8, 1) with multiplexer
•
External clock input pin (TD0CLK)
•
A 16-bit counter (TD0CNTH/L), a 16-bit comparator, and two 16-bit reference data register (TD0DATAH/L)
•
I/O pins for capture input (TD0CAP), or match output (TD0OUT)
•
Timer D0 overflow interrupt (IRQ3, vector D8H) and match/capture interrupt (IRQ3, vector DAH) generation
•
Timer D0 control register, TD0CON (set 1, Bank 1, FAH, read/write)
PS032408-0220
PRELIMINARY
13-1
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.1.2 Timer D0 Control Register (TD0CON)
You use the timer D0 control register, TD0CON, to
•
Select the timer D0 operating mode (interval timer, capture mode, or PWM mode)
•
Select the timer D0 input clock frequency
•
Clear the timer D0 counter, TD0CNTH/TD0CNTL
•
Enable the timer D0 overflow interrupt or timer D0 match/capture interrupt
TD0CON is located in set 1 and bank 1 at address FAH, and is read/write addressable using Register addressing
mode.
A reset clears TD0CON to "00H". This sets timer D0 to normal interval timer mode, selects an input clock
frequency of fxx/1024, and disables all timer D0 interrupts. To disable the counter operation, please set
TD0CON.7-.5 to 111B. You can clear the timer D0 counter at any time during normal operation by writing a "1" to
TD0CON.2.
The timer D0 overflow interrupt (TD0OVF) is interrupt level IRQ3 and has the vector address DAH. When a timer
D0 overflow interrupt occurs and is serviced interrupt (IRQ3, vector DAH), you must write TD0CON.0 to "1". When
a timer D0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by
hardware or must be cleared by software.
To enable the timer D0 match/capture interrupt (IRQ3, vector D8H), you must write TD0CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls INTPND.3. When a "1" is detected, a
timer D0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer D0 match/capture interrupt pending bit,
INTPND.3.
Timer D0 Control Register (TD0CON)
FAH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
Timer D0 input clock selection bits:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx/1
101 = External clock (TD0CLK) falling edge
110 = External clock (TD0CLK) rising edge
111 = Counter stop
.3
.2
.1
.0
LSB
Timer D0 overflow interrupt enable:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer D0 match/capture interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer D0 counter clear bit:
0 = No effect
1 = Clear the timer D0 counter (when write)
Timer D0 operating mode selection bits:
00 = Interval mode (TD0OUT)
01 = Capture mode (capture on rising edge, counter running, OVF can occur)
10 = Capture mode (capture on falling edge, counter running, OVF can occur)
11 = PWM mode (OVF and match interrupt can occur)
NOTE: Refer to the interrupt pending register (INTPND) for the timer D0's pending bits.
Figure 13-1
PS032408-0220
Timer D0 Control Register (TD0CON)
PRELIMINARY
13-2
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.1.3 Timer D0 Function Description
13.1.3.1 Timer D0 Interrupts (IRQ3, Vectors D8H and DAH)
The timer D0 can generate two interrupts: the timer D0 overflow interrupt (TD0OVF), and the timer D0
match/capture interrupt (TD0INT). TD0OVF is belongs to interrupt level IRQ3, vector DAH. TD0INT also belongs
to interrupt level IRQ3, but is assigned the separate vector address, D8H.
A timer D0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or
should be cleared by software in the interrupt service routine by writing a "0" to the INTPND.2 interrupt pending bit.
However, the timer D0 match/capture interrupt pending condition must be cleared by the application's interrupt
service routine by writing a "0" to the INTPND.3 interrupt pending bit.
13.1.3.2 Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
timer D0 reference data register, TD0DATAH/TD0DATAL. The match signal generates a timer D0 match interrupt
(TD0INT, vector D8H) and clears the counter.
If, for example, you write the value "1087H" to TD0DATAH/TD0DATAL, the counter will increment until it reaches
"1087H". At this point, the timer D0 interrupt request is generated, the counter value is reset, and counting
resumes. With each match, the level of the signal at the timer D0 output pin is inverted (see Figure 13-2).
Interrupt Enable/Disable
Capture Signal
CLK
TD0CON.1
R (Clear)
16-Bit Up Counter
M
U
X
Match
16-Bit Comparator
TD0INT
(IRQ3)
INTPND.3
(Match INT)
Pending
TD0OUT
Timer D0 Buffer Register
TD0CON.4-.3
Match Signal
TD0CON.2
TD0OVF
Timer D0 Data Register
Figure 13-2
PS032408-0220
Simplified Timer D0 Function Diagram: Interval Timer Mode
PRELIMINARY
13-3
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.1.3.3 Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
TD0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the timer D0 data register. In PWM mode, however, the match signal does not clear the counter.
Instead, it runs continuously, overflowing at "FFFFH", and then continues incrementing from "0000H".
Although you can use the match signal to generate a timer D0 overflow interrupt, interrupts are not typically used
in PWM-type applications. Instead, the pulse at the TD0PWM pin is held to Low level as long as the reference
data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the
data value is greater than ( > ) the counter value. One pulse width is equal to tCLK 65536 (see Figure 13-3).
Interrupt Enable/Disable
Capture Signal
CLK
16-Bit Up Counter
16-Bit Comparator
TD0CON.1
R (Clear)
M
U
X
Match
Timer D0 Buffer Register
TD0INT
(IRQ3)
INTPND.3
Pending
TD0CON.4-.3
Match Signal
TD0CON.2
TD0OVF
(Match INT)
TD0PWM
Output
High level when
data > counter,
Lower level when
data < counter,
Timer D0 Data Register
Figure 13-3
PS032408-0220
Simplified Timer D0 Function Diagram: PWM Mode
PRELIMINARY
13-4
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.1.3.4 Capture Mode
In capture mode, a signal edge that is detected at the TD0CAP pin opens a gate and loads the current counter
value into the timer D0 data register. You can select rising or falling edges to trigger this operation.
Timer D0 also gives you capture input source: the signal edge at the TD0CAP pin. You select the capture input by
setting the values of the timer D0 capture input selection bits in the port 3 control register, P3CONM (set 1, bank 1,
ECH). When P3CONM.5–.3 is "000", the TD0CAP input is selected.
Both kinds of timer D0 interrupts can be used in capture mode: the timer D0 overflow interrupt is generated
whenever a counter overflow occurs; the timer D0 match/capture interrupt is generated whenever the counter
value is loaded into the timer D0 data register.
By reading the captured data value in TD0DATAH/TD0DATAL, and assuming a specific value for the timer D0
clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the TD0CAP pin
(see Figure 13-4).
TD0CON.0
TD0OVF
(IRQ3)
CLK
16-Bit Up Counter
INTPND.2
(Overflow INT)
Interrupt Enable/Disable
TD0CON.1
TD0CAP input
M
U
X
Match Signal
TD0CON.4-.3
M
U
X
TD0INT
(IRQ3)
INTPND.3
(Capture INT)
Pending
TD0CON.4-.3
Timer D0 Data Register
Figure 13-4
PS032408-0220
Simplified Timer D0 Function Diagram: Capture Mode
PRELIMINARY
13-5
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.1.4 Block Diagram
TD0CON.0
OVF
TD0CON.7-.5
TD0OVF
(IRQ3)
INTPND.2
Data Bus
fXX/1024
fXX/256
fXX/64
fXX/8
fXX/1
TD0CON.2
8
M
U
16-bit Up-Counter
(Read Only)
Clear
R
TD0CON.1
TD0CLK
X
M
16-bit Comparator
Vss
Match U
TD0INT
INTPND.3
(IRQ3)
X
M
U
X
TD0CAP
TD0OUT
TD0PWM
Timer D0 Buffer Register
TD0CON.4-.3
PG output signal
TD0CON.4-.3
Match Signal
TD0CON.2
TD0OVF
Timer D0 Data Register
8
Data Bus
Figure 13-5
PS032408-0220
Timer D0 Functional Block Diagram
PRELIMINARY
13-6
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.2 16-bit timer D1
13.2.1 Overview
The 16-bit timer D1 is a 16-bit general-purpose timer.
Timer D1 has three operating modes, one of which you select using the appropriate TD1CON, TD1CON setting is
•
Interval timer mode (Toggle output at TD1OUT pin)
•
Capture input mode with a rising or falling edge trigger at the TD1CAP pin
•
PWM mode (TD1PWM); PWM output shares their output port with TD1OUT pin
Timer D1 has the following functional components:
•
Clock frequency divider (fxx divided by 1024, 256, 64, 8, 1) with multiplexer
•
External clock input pin (TD1CLK)
•
A 16-bit counter (TD1CNTH/L), a 16-bit comparator, and two 16-bit reference data register (TD1DATAH/L)
•
I/O pins for capture input (TD1CAP), or match output (TD1OUT)
•
Timer D1 overflow interrupt (IRQ3, vector DEH) and match/capture interrupt (IRQ3, vector DCH) generation
•
Timer D1 control register, TD1CON (set 1, Bank 1, FBH, read/write)
PS032408-0220
PRELIMINARY
13-7
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.2.2 Timer D1 Control Register (TD1CON)
You use the timer D1 control register, TD1CON, to
•
Select the timer D1 operating mode (interval timer, capture mode, or PWM mode)
•
Select the timer D1 input clock frequency
•
Clear the timer D1 counter, TD1CNTH/TD1CNTL
•
Enable the timer D1 overflow interrupt or timer D1 match/capture interrupt
TD1CON is located in set 1 and bank 1 at address FBH, and is read/write addressable using Register addressing
mode.
A reset clears TD1CON to '00H'. This sets timer D1 to normal interval timer mode, selects an input clock
frequency of fxx/1024, and disables all timer D1 interrupts. To disable the counter operation, please set
TD1CON.7-.5 to 111B. You can clear the timer D1 counter at any time during normal operation by writing a "1" to
TD1CON.2.
The timer D1 overflow interrupt (TD1OVF) is interrupt level IRQ3 and has the vector address DEH. When a timer
D1 overflow interrupt occurs and is serviced interrupt (IRQ3, vector DEH), you must write TD1CON.0 to "1". When
a timer D1 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by
hardware or must be cleared by software.
To enable the timer D1 match/capture interrupt (IRQ3, vector DCH), you must write TD1CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls INTPND.5. When a "1" is detected, a
timer D1 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer D1 match/capture interrupt pending bit,
INTPND.5.
Timer D1 Control Register (TD1CON)
FBH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
Timer D1 input clock selection bits:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx/1
101 = External clock (TD1CLK) falling edge
110 = External clock (TD1CLK) rising edge
111 = Counter stop
.3
.2
.1
.0
LSB
Timer D1 overflow interrupt enable:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer D1 match/capture interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer D1 counter clear bit:
0 = No effect
1 = Clear the timer D1 counter (when write)
Timer D1 operating mode selection bits:
00 = Interval mode (TD1OUT)
01 = Capture mode (capture on rising edge, counter running, OVF can occur)
10 = Capture mode (capture on falling edge, counter running, OVF can occur)
11 = PWM mode (OVF and match interrupt can occur)
NOTE: Refer to the interrupt pending register (INTPND) for the timer D1's pending bits.
Figure 13-6
PS032408-0220
Timer D1 Control Register (TD1CON)
PRELIMINARY
13-8
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.2.3 Timer D1 Function Description
13.2.3.1 Timer D1 Interrupts (IRQ3, Vectors DCH and DEH)
The timer D1 can generate two interrupts: the timer D1 overflow interrupt (TD1OVF), and the timer D1
match/capture interrupt (TD1INT). TD1OVF is belongs to interrupt level IRQ3, vector DEH. TD1INT also belongs
to interrupt level IRQ3, but is assigned the separate vector address, DCH.
A timer D1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or
should be cleared by software in the interrupt service routine by writing a "0" to the INTPND.4 interrupt pending bit.
However, the timer D1 match/capture interrupt pending condition must be cleared by the application's interrupt
service routine by writing a "0" to the INTPND.5 interrupt pending bit.
13.2.3.2 Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
timer D1 reference data register, TD1DATAH/TD1DATAL. The match signal generates a timer D1 match interrupt
(TD1INT, vector DCH) and clears the counter.
If, for example, you write the value "1087H" to TD1DATAH/TD1DATAL, the counter will increment until it reaches
"1087H". At this point, the timer D1 interrupt request is generated, the counter value is reset, and counting
resumes. With each match, the level of the signal at the timer D1 output pin is inverted (see Figure 13-7).
Interrupt Enable/Disable
Capture Signal
CLK
TD1CON.1
R (Clear)
16-Bit Up Counter
M
U
X
Match
16-Bit Comparator
TD1INT
(IRQ3)
INTPND.5
(Match INT)
Pending
TD1OUT
Timer D1 Buffer Register
TD1CON.4-.3
Match Signal
TD1CON.2
TD1OVF
Timer D1 Data Register
Figure 13-7
PS032408-0220
Simplified Timer D1 Function Diagram: Interval Timer Mode
PRELIMINARY
13-9
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.2.3.3 Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
TD1PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the timer D1 data register. In PWM mode, however, the match signal does not clear the counter.
Instead, it runs continuously, overflowing at "FFFFH", and then continues incrementing from "0000H".
Although you can use the match signal to generate a timer D1 overflow interrupt, interrupts are not typically used
in PWM-type applications. Instead, the pulse at the TD1PWM pin is held to Low level as long as the reference
data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the
data value is greater than ( > ) the counter value. One pulse width is equal to tCLK 65536 (see Figure 13-8).
Interrupt Enable/Disable
Capture Signal
CLK
16-Bit Up Counter
16-Bit Comparator
TD1CON.1
R (Clear)
M
U
X
Match
Timer D1 Buffer Register
TD1CON.4-.3
Match Signal
TD1CON.2
TD1OVF
TD1INT
(IRQ3)
INTPND.5
(Match INT)
Pending
TD1PWM
Output
High level when
data > counter,
Lower level when
data < counter,
Timer D1 Data Register
Figure 13-8
PS032408-0220
Simplified Timer D1 Function Diagram: PWM Mode
PRELIMINARY
13-10
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.2.3.4 Capture Mode
In capture mode, a signal edge that is detected at the TD1CAP pin opens a gate and loads the current counter
value into the timer D1 data register. You can select rising or falling edges to trigger this operation.
Timer D1 also gives you capture input source: the signal edge at the TD1CAP pin. You select the capture input by
setting the values of the timer D1 capture input selection bits in the port 3 control register, P3CONH (set 1, bank 1,
EBH). When P3CONH.2–.0 is "000", the TD1CAP input is selected.
Both kinds of timer D1 interrupts can be used in capture mode: the timer D1 overflow interrupt is generated
whenever a counter overflow occurs; the timer D1 match/capture interrupt is generated whenever the counter
value is loaded into the timer D1 data register.
By reading the captured data value in TD1DATAH/TD1DATAL, and assuming a specific value for the timer D1
clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the TD1CAP pin
(see Figure 13-9).
TD1CON.0
TD1OVF
(IRQ3)
CLK
16-Bit Up Counter
INTPND.4
(Overflow INT)
Interrupt Enable/Disable
TD1CON.1
TD1CAP input
M
U
X
Match Signal
TD1CON.4-.3
M
U
X
TD1INT
(IRQ3)
INTPND.5
(Capture INT)
Pending
TD1CON.4-.3
Timer D1 Data Register
Figure 13-9
PS032408-0220
Simplified Timer D1 Function Diagram: Capture Mode
PRELIMINARY
13-11
S3F8S6B Product Specification
Chapter 13. 16-Bit Timer D0/D1
13.2.4 Block Diagram
TD1CON.0
OVF
TD1CON.7-.5
TD1OVF
(IRQ3)
INTPND.4
Data Bus
fXX/1024
fXX/256
fXX/64
fXX/8
fXX/1
8
M
U
Clear
16-bit Up-Counter
(Read Only)
TD1CON.2
R
TD1CLK
TD1CON.1
X
16-bit Comparator
Vss
M
U
X
TD1CAP
M
Match
TD1INT
U
INTPND.5
X
(IRQ3)
TD1OUT
TD1PWM
Timer D1 Buffer Register
TD1CON.4-.3
TD1CON.4-.3
Match Signal
TD1CON.2
TD1OVF
Timer D1 Data Register
8
Data Bus
Figure 13-10
PS032408-0220
Timer D1 Functional Block Diagram
PRELIMINARY
13-12
S3F8S6B Product Specification
14
Chapter 14. Watch Timer
Watch Timer
14.1 Overview
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To
start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1".
And if you want to service watch timer overflow interrupt (IRQ4, vector E6H), then set the WTCON.6 to "1".
The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application's
interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit.
After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically
set to "1", and interrupt requests commence in 1.995 ms, 0.125, 0.25 and 0.5-second intervals by setting Watch
timer speed selection bits (WTCON.3–.2).
The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By
setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an
interrupt every 1.995 ms. High-speed mode is useful for timing events for program debugging sequences.
The watch timer supplies the clock frequency for the LCD controller (f LCD). Therefore, if the watch timer is disabled,
the LCD controller does not operate.
Watch timer has the following functional components:
•
Real Time and Watch-Time Measurement
•
Using a Main Clock Source or Sub clock
•
Clock Source Generation for LCD Controller (fLCD)
•
I/O pin for Buzzer Output Frequency Generator (BUZ)
•
Timing Tests in High-Speed Mode
•
Watch timer overflow interrupt (IRQ4, vector E6H) generation
•
Watch timer control register, WTCON (set 1, bank 0, E6H, read/write)
PS032408-0220
PRELIMINARY
14-1
S3F8S6B Product Specification
Chapter 14. Watch Timer
14.2 Watch Timer CONTROL Register (WTCON)
The watch timer control register, WTCON is used to select the watch timer interrupt time and Buzzer signal, to
enable or disable the watch timer function. It is located in set 1, bank 0 at address E6H, and is read/write
addressable using register addressing mode.
A reset clears WTCON to "00H". This disable the watch timer.
So, if you want to use the watch timer, you must write appropriate value to WTCON.
Watch Timer Control Register (WTCON)
E6H, Set 1, Bank 0, R/W
MSB
.7
.5
.6
.4
.3
Watch timer INT Enable/Disable bit:
0 = Disable watch timer INT
1 = Enable watch timer INT
.0
LSB
Watch timer Enable/Disable bit:
0 = Disable watch timer
(Clear frequency dividing circuits)
1 = Enable watch timer
Buzzer signal selection bits:
00 = 0.5 kHz
01 = 1 kHz
10 = 2 kHz
11 = 4 kHz
PS032408-0220
.1
Watch timer interrupt pending bit:
0 = Interrupt request is not pending
(Clear pending bit when write"0")
1 = Interrupt request is pending
Watch timer clock selection bit:
0 = Select main clock divided by 27 (fx/128)
1 = Select sub clock (fxt)
Figure 14-1
.2
Watch timer speed selection bits:
00 = Set watch timer interrupt to 0.5 s
01 = Set watch timer interrupt to 0.25 s
10 = Set watch timer interrupt to 0.125 s
11 = Set watch timer interrupt to 1.995 ms
Watch Timer Control Register (WTCON)
PRELIMINARY
14-2
S3F8S6B Product Specification
Chapter 14. Watch Timer
14.3 Watch Timer Circuit Diagram
WTCON.7
BUZ
WT INT
Enable/Disable
WTCON.6
WTCON.6
WTCON.5
MUX
WTCON.4
8
WTCON.3
WTCON.2
WTCON.1
WTINT
fw/64 (0.5 kHz)
fw/32 (1 kHz)
fw/16 (2 kHz)
fw/8 (4 kHz)
Enable/Disable
Selector
Circuit
WTCON.0
(Pending Bit)
(IRQ4)
WTCON.0
0.5S
Clock
Selector
fw
32.768 kHz
Frequency
Dividing
Circuit
0.25S
0.125S
1.995mS
fLCD = 1024 Hz
fx = Main clock (where fx = 4.19 MHz)
fxt = Sub clock (32.768 kHz)
fxt
fx/128
Figure 14-2
PS032408-0220
fw = Watch timer frequency
Watch Timer Circuit Diagram
PRELIMINARY
14-3
S3F8S6B Product Specification
15
Chapter 15. LCD Controller/Driver
LCD Controller/Driver
15.1 Overview
The S3F8S6B microcontroller can directly drive an up-to-224-dot (28 segments 8 commons) LCD panel.
Its LCD block has the following components:
•
LCD controller/driver
•
Display RAM (30H–51H) for storing display data in page 8
•
6 common/segment output pins (COM2/SEG0–COM7/SEG5)
•
64 segment output pins (SEG6–SEG33)
•
2 common output pins (COM0–COM1)
•
Four LCD operating power supply pins (VLC0–VLC3)
•
LCD bias by internal/external register and capacitor bias
The LCD control register, LCON, is used to turn the LCD display on and off, select LCD clock frequency, LCD duty
and bias, and LCD bias type. The LCD mode control register, LMOD, is used to selects VLCD voltage. Data
written to the LCD display RAM can be automatically transferred to the segment signal pins without any program
control. When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even in the
main clock Stop or Idle modes.
LCD data stored in the display RAM locations are transferred to the segment signal pins automatically without
program control.
2
8-Bit Data Bus
4
LCD
Controller/Driver
CA-CB
VLC0-VLC3
COM0-COM1
2
8
6
COM2-COM7
/SEG0-SEG5
SEG6-SEG33
28
Figure 15-1
PS032408-0220
LCD Function Diagram
PRELIMINARY
15-1
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.2 LCD Circuit Diagram
SEG33/P6.5
Port
Latch
SEG/Port
Driver
SEG28/P6.0
SEG12/P2.0
Data Bus
SEG6/P1.2
LCD
Display RAM
(830H-851H)
COM7/SEG5/P0.7
COM/Port
Driver
COM3/SEG1/P0.3
COM2/SEG0/P0.2
fLCD
COM1/P0.1
COM0/P0.0
LCON
Timing
Controller
LMOD
LCD Voltage
Control
Figure 15-2
PS032408-0220
VLC0
VLC1
VLC2
VLC3
CA
CB
LCD Circuit Diagram
PRELIMINARY
15-2
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.3 LCD RAM Address Area
RAM addresses of 30H - 75H page 8 are used as LCD data memory. These locations can be addressed by 1-bit
or 8-bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; When the bit
value is "0", the display is turned off.
Display RAM data are sent out through the segment pins, SEG0–SEG33, using the direct memory access (DMA)
method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display
can be allocated to general-purpose use.
COM
Bit
SEG0
SEG1
SEG2
SEG3
SEG4
------
SEG32
SEG33
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
.0
.1
.2
.3
.4
.5
.6
.7
830H
831H
832H
833H
834H
------
850H
851H
Figure 15-3
PS032408-0220
LCD Display Data RAM Organization
PRELIMINARY
15-3
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.4 LCD control register (lCON)
A LCON is located in set1, bank0 at address F0H, and is read/write addressable using register addressing mode.
It has the following control functions.
•
LCD duty and bias selection
•
LCD clock selection
•
LCD display control
•
Internal/External LCD dividing resistors or capacitor bias selection
The LCON register is used to turn the LCD display on/off, to select duty and bias, to select LCD clock and LCD
bias type. A reset clears the LCON registers to "00H", configuring turns off the LCD display, select 1/8 duty and
1/4 bias, select 128Hz for LCD clock, and no-select any LCD bias type.
The LCD clock signal determines the frequency of COM signal scanning of each segment output. Since the LCD
clock is generated by watch timer clock (fw), the watch timer should be enabled when the LCD display is turned
on. The LCD frame rate is the LCD clock frequency times the duty cycle (LCD clock * LCD duty), as shown in
Table 15.1.
Table 15.1. LCD Frame Rate
LCD Frame Frequency
Units
LCD Clock
Frequency
Static
1/2 Duty
1/3 Duty
1/4 Duty
1/8 Duty
128
128
64
43
32
16
256
256
128
85
64
32
512
512
256
171
128
64
1024
1024
512
341
256
128
Hz
NOTE: The clock and duty for LCD controller/driver is automatically initialized by hardware, whenever the LCON register data
value is rewritten. Therefore, the LCON register does not rewrite frequently.
PS032408-0220
PRELIMINARY
15-4
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
LCD Control Register (LCON)
F0H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
LCD display control bit:
0 = All LCD signals are low (The voltage
booster is always stopped and cut off)
1 = Turn display on (When LCON.2-.1 = "01",
run and connect voltage booster)
LCD clock selection bits:
00 = fw/2 8 (128 Hz)
01 = fw/2 7 (256 Hz)
10 = fw/2 6 (512 Hz)
11 = fw/2 5 (1024 Hz)
LCD duty and bias selection bits:
000 = 1/8 duty, 1/4 bias
001 = 1/4 duty, 1/3 bias
010 = 1/3 duty, 1/3 bias
011 = 1/3 duty, 1/2 bias
1xx = 1/2 duty, 1/2 bias
LCD bias type selection bits:
00 = VLC0-VLC3, CA and CB pins are normal I/O pin
01 = Cap bias; VLC0-VLC3, CA and CB pins are bias pin
10 = Internal resistor bias (The voltage booster is always stopped and
cut off); VLC0-VLC3 are bias pin, CA and CB are norma I/O pin
11 = External resistor bias (The voltage booster is always stopped and
cut off); VLC0-VLC3 are bias pin, CA and CB are norma I/O pin
NOTES:
1. When LCON.2-.1 are selected to '01', P5.0-.5 are automatically selected to LVCn, CA and CB pin. (n=0-3)
When LCON.2-.1 are capacitor bias selected, LCON.0 is select to '1' after 1milisecond delay.
Refer to programming tip in page 15-16.
2. When LCON.2-.1 are selected to '10', P5.0-.3 are automatically selected to VLCn. (n=0-3)
3. When LCON.2-.1 are selected to '11', P5.0-.3 are automatically selected to VLCn. (n=0-3)
4. The P5.3/VLC3-P5.0/VLC0 must be used as LCD bias pins if the LCD block is used. So, the LCON.2-.1
must not be set to '00b' when LCON.0=1.
5. "x" means don't care.
Figure 15-4
PS032408-0220
LCD Control Register (LCON)
PRELIMINARY
15-5
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.5 LCD MODE Control Register (LMOD)
A LMOD is located in set 1, bank 0 at address F1H, and is read/write addressable using Register addressing
mode. It has the following control functions.
•
VLCD voltage selection
The LMOD register is used to select VLCD voltage. A reset clears the LMOD registers to "00H", configuring select
3.6 V (when 1/4 bias) for VLCD voltage.
LCD Mode Control Register (LMOD)
F1H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used but keep always '0'
VLCD Voltage Selection Bits:
(Only when the capacitor bias is selected)
1/2 bias
1/4 bias 1/3 bias
000
001
010
011
100
101
110
111
3.6V
3.8V
4.0V
4.2V
4.4V
4.6V
4.8V
5.0V
3.150V
3.375V
3.600V
3.825V
4.050V*
4.275V*
4.500V*
Not Available
2.20V
2.40V
2.60V*
2.80V*
3.00V*
Not Available
Not Available
Not Available
NOTES:
1. The voltage regulator and booster circuit provide constant LCD contrast level.
2. Since the booster clock is generated by watch timer clock (fw). And the booster clock is almost 32kHz.
3. For ½ bias, this value is valid under Run, Main/Sub Idle modes.
4. * Indicates mode is not available in Sub Idle and Stop modes.
Figure 15-5
PS032408-0220
LCD Mode Control Register (LMOD)
PRELIMINARY
15-6
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.6 Internal Resistor Bias Pin Connection
1/4 Bias
1/3 Bias
VDD
VDD
LCON.0
LCON.0
VLC0
VLC1
VLC2
VLC3
VLC0
R
VLC1
R
R
VLC2
VLCD
VLC3
R
R
VLCD
VSS
CA
NC
CA
NC
CB
LCON.2-.1 = "10": Select internal resistor bias
NC
R
R
VSS
NC
R
CB
LCON.2-.1 = "10": Select internal resistor bias
1/2 Bias
VDD
LCON.0
VLC0
VLC1
VLC2
VLC3
R
R
2R
2R
VLCD
VSS
NC
CA
NC
CB
LCON.2-.1 = "10": Select internal resistor bias
NOTES:
1. The CA and CB pins are not connected when the internal resistor bias is selected.
2. VLC0 and VLC1 should be connected at 1/3 bias.
3. VLC0, VLC1, and VLC2 should be connected at 1/2 bias.
Figure 15-6
PS032408-0220
Internal Resistor Bias Pin Connection
PRELIMINARY
15-7
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.7 External Resistor Bias Pin Connection
1/4 Bias
1/3 Bias
VDD
VDD
LCON.0
LCON.0
VLC0
R`
R`
R`
VLC0
VLC1
VLC1
R`
VLC2
VLCD
R`
VLC3
R`
VLC2
VLC3
VLCD
R`
VSS
VSS
NC
CA
NC
CA
NC
LCON.2-.1 = "11": Select external resistor bias
(Disable internal resistors)
CB
NC
CB
LCON.2-.1 = "11": Select external resistor bias
(Disable internal resistors)
1/2 Bias
VDD
LCON.0
VLC0
VLC1
VLC2
R`
VLC3
VLCD
R`
VSS
NC
CA
NC
CB
LCON.2-.1 = "11": Select external resistor bias
(Disable internal resistors)
NOTES:
1. The CA and CB pins are not connected when the external resistor bias is selected.
2. VLC0 and VLC1 should be connected at 1/3 bias.
3. VLC0, VLC1, and VLC2 should be connected at 1/2 bias.
Figure 15-7
PS032408-0220
External Resistor Bias Pin Connection
PRELIMINARY
15-8
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.8 Capacitor Bias Pin Connection
1/3 Bias
1/4 Bias
VLC0
VLC0
0.1uF
VLC1
0.1uF
VLC2
0.1uF
VLC2
0.1uF
VLCD
VLC3
0.1uF
VLC1
0.1uF
VLC3
0.1uF
VLCD
VSS
VSS
CA
CA
0.1uF
LCON.2-.1 = "01": Select capacitor bias
0.1uF
LCON.2-.1 = "01": Select capacitor bias
CB
CB
1/2 Bias
VLC0
VLC1
VLC2
0.1uF
VLC3
0.1uF
VLCD
VSS
CA
0.1uF
LCON.2-.1 = "01": Select capacitor bias
CB
NOTES:
1. VLC0 and VLC1 should be connected at 1/3 bias.
2. VLC0, VLC1, and VLC2 should be connected at 1/2 bias.
Figure 15-8
PS032408-0220
Capacitor Bias Pin Connection
PRELIMINARY
15-9
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.9 Common (COM) Signals
The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
•
In 1/8 duty mode, COM0-COM7 (SEG6–SEG33) pins are selected.
•
In 1/4 duty mode, COM0-COM3 (SEG2–SEG33) pins are selected.
•
In 1/3 duty mode, COM0-COM2 (SEG1–SEG33) pins are selected.
•
In 1/2 duty mode, COM0-COM1 (SEG0–SEG33) pins are selected.
PS032408-0220
PRELIMINARY
15-10
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
15.10 Segment (SEG) Signals
The 34 LCD segment signal pins are connected to corresponding display RAM locations at page 8. Bits of the
display RAM are synchronized with the common signal output pins.
When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin.
When the display bit is "0", a 'no-select' signal to the corresponding segment pin.
Select
Non-Select
FR
1 Frame
VLC0,1,2
COM
VLC3
V SS
VLC0,1,2
SEG
VLC3
V SS
VLC0,1,2
VLC3
COM-SEG
V SS
-VLC3
-VLC0,1,2
Figure 15-9
Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode
Select
Non-Select
FR
1 Frame
COM
VLC0,1
VLC2
VLC3
VSS
SEG
VLC0,1
VLC2
VLC3
VSS
COM-SEG
VLC0,1
VLC2
VLC3
VSS
-VLC3
-VLC2
-VLC0,1
Figure 15-10
PS032408-0220
Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode
PRELIMINARY
15-11
S3F8S6B Product Specification
COM0
0
Chapter 15. LCD Controller/Driver
1
0
1
VLC0
SEG0
VSS
1 Frame
VLC0 (VLC1,VLC2)
COM1
COM0
VLC3
VSS
SEG1
SEG2
SEG3
VLC0 (VLC1,VLC2)
COM1
VLC3
VSS
VLC0 (VLC1,VLC2)
SEG0
VLC3
VSS
VLC0 (VLC1,VLC2)
SEG1
VLC3
VSS
+V LC0 (VLC1,VLC2)
+V LC3
SEG0-COM0
0V
-V LC3
-V LC0 (VLC1,VLC2)
NOTE:
Figure 15-11
PS032408-0220
VLC0 = VLC1,VLC2
LCD Signal Waveforms (1/2 Duty, 1/2 Bias)
PRELIMINARY
15-12
S3F8S6B Product Specification
SEG3
SEG2
Chapter 15. LCD Controller/Driver
SEG1
0
1
2
0
1
2
VLC0
VSS
COM0
1 Frame
VLC0 (VLC1)
VLC2
COM1
COM0
VLC3
COM2
VSS
VLC0 (VLC1)
VLC2
COM1
VLC3
VSS
VLC0 (VLC1)
VLC2
COM2
VLC3
VSS
VLC0 (VLC1)
VLC2
SEG1
VLC3
VSS
VLC0 (VLC1)
VLC2
SEG2
VLC3
VSS
+V LC0(VLC1)
+V LC2
+V LC3
0V
SEG1-COM0
- V LC3
- V LC2
- V LC0(VLC1)
NOTE:
Figure 15-12
PS032408-0220
VLC0 = VLC1
LCD Signal Waveforms (1/3 Duty, 1/3 Bias)
PRELIMINARY
15-13
S3F8S6B Product Specification
Chapter 15. LCD Controller/Driver
SEG2
SEG3
0
1
2
3
0
1
2
3
VLC0
VSS
COM0
1 Frame
COM1
VLC0(VLC1)
COM2
VLC2
COM0
VLC3
COM3
VSS
VLC0(VLC1)
VLC2
COM1
VLC3
VSS
VLC0(VLC1)
VLC2
COM2
VLC3
VSS
VLC0(VLC1)
VLC2
VLC3
COM3
VSS
VLC0(VLC1)
VLC2
SEG2
VLC3
VSS
VLC0(VLC1)
VLC2
SEG3
VLC3
VSS
+V LC0(VLC1)
+V LC2
+V LC3
0V
COM0-SEG2
- V LC3
- V LC2
- V LC0(VLC1)
NOTE:
Figure 15-13
PS032408-0220
VLC0 = VLC1
LCD Signal Waveforms (1/4 Duty, 1/3 Bias)
PRELIMINARY
15-14
S3F8S6B Product Specification
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
Chapter 15. LCD Controller/Driver
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
VLC0
VSS
FR
1 Frame
VLC0
S
E
G
6
S
E
G
7
S
E
G
8
S S
E E
G G
9 10
VLC1
COM0
VLC2
VLC3
VSS
VLC0
VLC1
COM1
VLC2
VLC3
VSS
VLC0
VLC1
COM2
VLC2
VLC3
VSS
VLC0
VLC1
SEG6
VLC2
VLC3
VSS
+VLC0
+VLC1
+VLC2
+VLC3
SEG6-COM0
0V
-VLC3
-VLC2
-VLC1
-VLC0
PS032408-0220
PRELIMINARY
15-15
S3F8S6B Product Specification
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Chapter 15. LCD Controller/Driver
VLC0
VSS
FR
1 Frame
VLC0
VLC1
SEG7
VLC2
VLC3
VSS
+VLC0
+VLC1
+VLC2
+VLC3
SEG7-COM0
0V
-VLC3
-VLC2
-VLC1
-VLC0
Figure 15-14
PS032408-0220
LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
PRELIMINARY
15-16
S3F8S6B Product Specification
Example 15-1
Chapter 15. LCD Controller/Driver
LCD Display on, After Capacitor Bias Selected
This example shows how to display on after capacitor bias selected:
.
.
.
LCD_cap_bias
AND
OR
CALL
OR
RET
LCON,#0FBH
LCON,#02H
Delay1mS
LCON,#01H
; Capacitor bias select
; Delay 1ms
; Turn on LCD display
.
.
.
Delay1mS
DEL
NOP
PS032408-0220
LD
R0,#20H
DJNZ
RET
R0,DEL
PRELIMINARY
15-17
S3F8S6B Product Specification
16
Chapter 16. 10-Bit Analog-To-Digital Converter
10-Bit Analog-To-Digital Converter
16.1 Overview
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at
one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the
AVREF and AVSS values. The A/D converter has the following components:
•
Analog comparator with successive approximation logic
•
D/A converter logic (resistor string type)
•
ADC control register (ADCON)
•
Eight multiplexed analog data input pins (AD0–AD7)
•
10-bit A/D conversion data output register (ADDATAH/L)
•
8-bit digital input port (Alternately, I/O port.)
•
AVREF and AVSS pins, AVSS is internally connected to VSS
PS032408-0220
PRELIMINARY
16-1
S3F8S6B Product Specification
Chapter 16. 10-Bit Analog-To-Digital Converter
16.2 Function Description
To initiate an analog-to-digital conversion procedure, at the first you must set ADCEN signal for ADC input enable
at port 4, the pin set with alternative function can be used for ADC analog input. And you write the channel
selection data in the A/D converter control register ADCON.4–.6 to select one of the eight analog input pins (AD0–
7) and set the conversion start or disable bit, ADCON.0. The read-write ADCON register is located in set 1, bank 0
at address D2H. The pins which are not used for ADC can be used for normal I/O.
During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the
approximate half-way point of an 10-bit register). This register is then updated automatically during each
conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time.
You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6–.4) in
the ADCON register. To start the A/D conversion, you should set the start bit, ADCON.0. When a conversion is
completed, ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the
ADDATAH/L register where it can be read. The A/D converter then enters an Idle state. Remember to read the
contents of ADDATAH/L before another conversion starts. Otherwise, the previous result will be overwritten by the
next conversion result.
NOTE: Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at
the AD0–AD7 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input
level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process,
there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished.
PS032408-0220
PRELIMINARY
16-2
S3F8S6B Product Specification
Chapter 16. 10-Bit Analog-To-Digital Converter
16.3 Conversion Timing
The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D
conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for
conversion clock with an 8 MHz fxx clock frequency, one clock cycle is 1 us. Each bit conversion requires 4 clocks,
the conversion rate is calculated as follows:
4 clocks/bit 10 bits + set-up time = 50 clocks, 50 clock 1 s = 50 s at 1 MHz
16.4 A/D Converter Control Register (ADCON)
The A/D converter control register, ADCON, is located at address D2H in set 1, bank 0. It has three functions:
•
Analog input pin selection (ADCON.6–.4)
•
End-of-conversion status detection (ADCON.3)
•
ADC clock selection (ADCON.2–.1)
•
A/D operation start or disable (ADCON.0)
After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input
pins (AD0–AD7) can be selected dynamically by manipulating the ADCON.4–6 bits. And the pins not used for
analog input can be used for normal I/O function.
A/D Converter Control Register (ADCON)
D2H, Set1, Bank 0, R/W (EOC bit is read-only)
MSB
.7
.6
.5
.4
.3
.2
Not used for S3F8S6B
.1
.0
LSB
Start or disable bit:
0 = Disable operation
1 = Start operation
A/D input pin selection bits:
0 0 0 = AD0
0 0 1 = AD1
0 1 0 = AD2
0 1 1 = AD3
1 0 0 = AD4
1 0 1 = AD5
1 1 0 = AD6
1 1 1 = AD7
Clock Selection bit:
0 0 = fxx/16
0 1 = fxx/8
1 0 = fxx/4
1 1 = fxx/1
End-of-conversion bit:
0 = Conversion not complete
1 = Conversion complete
NOTES:
After ADC is started, at least 4-NOP instructions should come before checking EOC bit
Figure 16-1
PS032408-0220
A/D Converter Control Register (ADCON)
PRELIMINARY
16-3
S3F8S6B Product Specification
Chapter 16. 10-Bit Analog-To-Digital Converter
A/D Converter Data Register, High Byte (ADDATAH)
D0H, Set 1, Bank 0, Read Only
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
A/D Converter Data Register, Low Byte (ADDATAL)
D1H, Set1, Bank 0, Read Only
MSB
Figure 16-2
.1
.0
LSB
A/D Converter Data Register (ADDATAH/L)
16.5 Internal Reference Voltage Levels
In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input
level must remain within the range AVSS to AVREF (usually, AVREF VDD).
Different reference voltage levels are generated internally along the resistor tree during the analog conversion
process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AV REF.
PS032408-0220
PRELIMINARY
16-4
S3F8S6B Product Specification
Chapter 16. 10-Bit Analog-To-Digital Converter
16.6 Block Diagram
ADCON.2-.1
ADCON.6-.4
(Select one input pin of the assigned pins)
To ADCON.3
(EOC Flag)
Clock
Selector
ADCON.0
(AD/C Enable)
M
Input Pins
AD0-AD7
(P4.0-P4.7)
Analog
Comparator
.
.
.
U
+
X
ADCON.0
(AD/C Enable)
P4CONH/L
(Assign Pins to ADC Input)
10-bit D/A
Converter
Figure 16-3
PS032408-0220
Successive
Approximation
Logic & Register
Upper 8-bit is loaded to
A/D Conversion
Data Register
AVREF
AVSS
Conversion
Result
(ADDATAH/L)
A/D Converter Functional Block Diagram
PRELIMINARY
16-5
S3F8S6B Product Specification
Chapter 16. 10-Bit Analog-To-Digital Converter
V DD
Reference
Voltage
Input
(AV REF VDD)
10 F
+
-
A
REF
V
C 103
V DD
Analog
Input Pin
AD0-AD7
C 101
S3FS6B
AVSS
Figure 16-4
PS032408-0220
Recommended A/D Converter Circuit for Highest Absolute Accuracy
PRELIMINARY
16-6
S3F8S6B Product Specification
17
Chapter 17. Serial I/O Interface
Serial I/O Interface
17.1 Overview
Serial I/O module, SIO can interface with various types of external device that require serial data transfer.
The components of each SIO function block are:
•
8-bit control register (SIOCON)
•
Clock selector logic
•
8-bit data buffer (SIODATA)
•
8-bit pre-scaler (SIOPS)
•
3-bit serial clock counter
•
Serial data I/O pins (SI, SO)
•
Serial clock input/output pins (SCK)
The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.
17.2 Programming Procedure
To program the SIO modules, follow these basic steps:
1. Configure the I/O pins at port (SO, SCK, SI) by loading the appropriate value to the P6CONL register if
necessary.
2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this
operation, SIOCON.2 must be set to "1" to enable the data shifter.
3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON.1) to "1".
4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation
starts.
5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) is set to "1" and an
SIO interrupt request is generated.
PS032408-0220
PRELIMINARY
17-1
S3F8S6B Product Specification
Chapter 17. Serial I/O Interface
17.3 SIO Control Register (SIOCON)
The control register for serial I/O interface module, SIOCON, is located at E7H in set 1, bank 0. It has the control
settings for SIO module.
•
Clock source selection (internal or external) for shift clock
•
Interrupt enable
•
Edge selection for shift operation
•
Clear 3-bit counter and start shift operation
•
Shift operation (transmit) enable
•
Mode selection (transmit/receive or receive-only)
•
Data direction selection (MSB first or LSB first)
A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source
at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the
interrupt are disabled. The selected data direction is MSB-first.
Serial I/O Module Control Register (SIOCON)
E7H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
Data direction control bit:
0 = MSB-first mode
1 = LSB-first mode
.0
LSB
SIO interrupt enable bit:
0 = Disable SIO interrupt
1 = Enable SIO interrupt
SIO mode selection bit:
0 = Receive only mode
1 = Transmit/receive mode
Shift clock edge selection bit:
0 = TX at falling edges, Rx at rising edges
1 = TX at rising edges, Rx at falling edges
PS032408-0220
.1
SIO interrupt pending bit:
0 = No interrupt pending
0 = Clear pending condition
(when write)
1 = Interrupt is pending
SIO shift clock selection bit:
0 = Internal clock (P.S Clock)
1 = External clock (SCK)
Figure 17-1
.2
SIO shift operation enable bit:
0 = Disable shifter and clock counter
1 = Enable shifter and clock counter
SIO counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting
Serial I/O Module Control Registers (SIOCON)
PRELIMINARY
17-2
S3F8S6B Product Specification
Chapter 17. Serial I/O Interface
17.4 SIO Pre-Scaler Register (SIOPS)
The control register for serial I/O interface module, SIOPS, is located at E9H in set 1, bank 0.
The value stored in the SIO pre-scaler register, SIOPS, lets you determine the SIO clock rate (baud rate) as
follows:
Baud rate = Input clock (fxx/4)/(Pre-scaler value + 1), or SCK input clock, where the input clock is fxx/4
SIO Pre-scaler Register (SIOPS)
E9H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Baud rate = (fxx/4)/(SIOPS +1)
Figure 17-2
PS032408-0220
SIO Pre-scaler Register (SIOPS)
PRELIMINARY
17-3
S3F8S6B Product Specification
Chapter 17. Serial I/O Interface
17.5 Block Diagram
CLK
SIO INT
3-Bit Counter
Clear
SIOCON.0
IRQ4
Pending
SIOCON.1
(Interrupt Enable)
SIOCON.3
SIOCON.7
SIOCON.4
(Edge Select)
SIOCON.2
(Shift Enable)
M
SCK
SIOPS (E9H, bank 0)
fxx/2
8-bit P.S.
1/2
U
X
SIOCON.5
(Mode Select)
CLK 8-Bit SIO Shift Buffer
(SIODATA, E8H, bank 0)
8
SO
SIOCON.6
(LSB/MSB First
Mode Select)
SI
Data Bus
Figure 17-3
PS032408-0220
SIO Functional Block Diagram
PRELIMINARY
17-4
S3F8S6B Product Specification
Chapter 17. Serial I/O Interface
17.6 Serial I/O Timing Diagram
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
IRQ4
Set SIOCON.3
Figure 17-4
Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
IRQ4
Set SIOCON.3
Figure 17-5
PS032408-0220
Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
PRELIMINARY
17-5
S3F8S6B Product Specification
18
Chapter 18. UART 0
UART 0
18.1 Overview
The UART 0 block has a full-duplex serial port with programmable operating modes:
There is one synchronous mode and three UART (Universal Asynchronous Receiver/Transmitter) modes:
•
Serial I/O with baud rate of fU/(16 (BRDATA0 + 1))
•
8-bit UART mode; variable baud rate
•
9-bit UART mode; fU/16
•
9-bit UART mode, variable baud rate
UART 0 receive and transmit buffers are both accessed via the data register, UDATA0, is page 8 at address 16H.
Writing to the UART data register loads the transmit buffer; reading the UART data register accesses a physically
separate receive buffer.
When accessing a receive data buffer (shift register), reception of the next byte can begin before the previously
received byte has been read from the receive register. However, if the first byte has not been read by the time the
next byte has been completely received, one of the bytes will be lost.
In all operating modes, transmission is started when any instruction (usually a write operation) uses the UDATA0
register as its destination address. In mode 0, serial data reception starts when the receive interrupt pending bit
(UART0CONH.0) is "0" and the receive enable bit (UART0CONH.4) is "1". In mode 1, 2, and 3, reception starts
whenever an incoming start bit ("0") is received and the receive enable bit (UART0CONH.4) is set to "1".
PS032408-0220
PRELIMINARY
18-1
S3F8S6B Product Specification
Chapter 18. UART 0
18.2 Programming Procedure
To program the UART 0 modules, follow these basic steps:
1. Configure P1.2 and P1.3 to alternative function (RxD0 (P1.2), TxD0 (P1.3)) for UART module by setting the
P1CONL register to appropriately value.
2. Load an 8-bit value to the UART0CONH/L control register to properly configure the UART I/O module.
3. For interrupt generation, set the UART 0 I/O interrupt enable bit (UART0CONH.1 or UART0CONL.1) to "1".
4. When you transmit data to the UART 0 buffer, write data to UDATA0, the shift operation starts.
5. When the shift operation (receive/transmit) is completed, UART 0 pending bit (UART0CONH.0 or
UART0CONL.0) is set to "1" and an UART 0 interrupt request is generated.
18.3 UART 0 High-Byte Control Register (UART0CONh)
The control register for the UART 0 is called UART0CONH in page 8 at address 14H.
It has the following control functions:
•
Operating mode and baud rate selection
•
Multiprocessor communication and interrupt control
•
Serial receive enable/disable control
•
9th data bit location for transmit and receive operations (modes 2 and 3 only)
•
UART 0 receive interrupt control
A reset clears the UART0CONH value to "00H". So, if you want to use UART 0 module, you must write
appropriate value to UART0CONH.
18.4 UART 0 Low-Byte Control Register (UART0CONl)
The control register for the UART 0 is called UART0CONL in page 8 at address 15H.
It has the following control functions:
•
UART 0 transmit and receive parity-bit control
•
UART 0 clock selection
•
UART 0 transmit interrupt control
A reset clears the UART0CONL value to "00H". So, if you want to use UART 0 module, you must write appropriate
value to UART0CONL.
PS032408-0220
PRELIMINARY
18-2
S3F8S6B Product Specification
Chapter 18. UART 0
UART 0 Control Register, High Byte (UART0CONH)
14H, Page 8, R/W
MSB
MS1
MS0
MCE
RE
TB8
RB8
RIE
RIP
LSB
Uart 0 receive interrupt pending bit:
0 = No interrupt pending(when read),
clear pending bit(when write)
1 = Interrupt is pending(when read)
Operating mode and
baud rate selection bits:
(see table below)
Multiprocessor communication(1)
enable bit (for modes 2 and 3 only):
0 = Disable
1 = Enable
Uart 0 receive interrupt enable bit:
0 = Disable Rx interrupt
1 = Enable Rx interrupt
Serial data receive enable bit:
0 = Disable
1 = Enable
RB8(3) (Only when UART0CONL.7 = 0):
Location of the 9th data bit that was
received in UART 0 mode 2 or 3 ("0" or "1")
TB8(3) (Only when UART0CONL.7 = 0):
Location of the 9th data bit to be
transmitted in UART 0 mode 2 or 3 ("0" or "1")
MS1 MS0 Mode Description(2) Baud Rate
0
0
1
1
0
1
0
1
0
1
2
3
Shift register
8-bit UART
9-bit UART
9-bit UART
(fu/(16 x (BRDATA0 + 1)))
(fu/(16 x (BRDATA0 + 1)))
(fu /16)
(fu/(16 x (BRDATA0 + 1)))
NOTES:
1. In mode 2 or 3, if the UART0CONH.5 bit is set to "1" then the receive interrupt will not be
activated if the received 9th data bit is "0". In mode 1, if UART0CONH.5 = "1" then the
receive interrut will not be activated if a valid stop bit was not received.
In mode 0, the UART0CONH.5 bit should be "0"
2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits
for serial data receive and transmit.
3. If the UART0CONL.7 = 1, This bit is "don't care".
Figure 18-1
PS032408-0220
UART 0 High Byte Control Register (UART0CONH)
PRELIMINARY
18-3
S3F8S6B Product Specification
Chapter 18. UART 0
UART 0 Control Register, Low Byte (UART0CONL)
15H, Page 8, R/W
MSB
.7
.4
.5
.6
.2
.3
TIE
TIP
LSB
Uart 0 transmit interrupt pending bit:
0 = No interrupt pending(when read),
clear pending bit(when write)
1 = Interrupt is pending(when read)
UART 0 transmit parity-bit autogeneration enable bit(2):
0 = Disable parity-bit auto-generation
1 = Enable parity-bit auto-generation
Uart 0 transmit interrupt enable bit:
0 = Disable Tx interrupt
1 = Enable Tx interrupt
UART 0 transmit parity-bit
selection bit(1),(2):
0 = Even parity-bit
1 = Odd parity-bit
UART 0 receive parity-bit
selection bit(1),(2):
0 = Even parity-bit check
1 = Odd parity-bit check
Uart 0 clock selection bits:
00 = fxx/8
01 = fxx/4
10 = fxx/2
11 = fxx/1
UART 0 receive parity-bit
error status bit(1),(2):
0 = No parity-bit error
1 = Parity-bit error
NOTES:
1. If the UART0CONL.7 = 0, This bit is "don't care".
2. The bits UART0CONL.7-.4 are for mode 2 and 3 only.
Figure 18-2
PS032408-0220
UART 0 Low Byte Control Register (UART0CONL)
PRELIMINARY
18-4
S3F8S6B Product Specification
Chapter 18. UART 0
18.5 UART 0 Interrupt Pending bits
In mode 0, the receive interrupt pending bit UART0CONH.0 is set to "1" when the 8th receive data bit has been
shifted. In mode 1, the UART0CONH.0 bit is set to "1" at the halfway point of the stop bit's shift time. In mode 2, or
3, the UART0CONH.0 bit is set to "1" at the halfway point of the RB8 bit's shift time. When the CPU has
acknowledged the receive interrupt pending condition, the UART0CONH.0 bit must then be cleared by software in
the interrupt service routine.
In mode 0, the transmit interrupt pending bit UART0CONL.0 is set to "1" when the 8th transmit data bit has been
shifted. In mode 1, 2, or 3, the UART0CONL.0 bit is set at the start of the stop bit. When the CPU has
acknowledged the transmit interrupt pending condition, the UART0CONL.0 bit must then be cleared by software in
the interrupt service routine.
18.6 UART 0 Data Register (UDATA0)
UART 0 Data Register (UDATA0)
16H, Page 8, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Transmit or receive data
Figure 18-3
UART 0 Data Register (UDATA0)
18.7 UART 0 Baud Rate Data Register (BRDATA0)
The value stored in the UART 0 baud rate register, BRDATA0, lets you determine the UART clock rate (baud
rate).
UART 0 Baud Rate Data Register (BRDATA0)
17H, Page 8, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Baud rate data
Figure 18-4
PS032408-0220
UART 0 Baud Rate Data Register (BRDATA0)
PRELIMINARY
18-5
S3F8S6B Product Specification
Chapter 18. UART 0
18.8 Baud Rate Calculations
18.8.1 Mode 0 Baud Rate Calculation
In mode 0, the baud rate is determined by the UART baud rate data register, BRDATA0 in page 8 at
address 17H: Mode 0 baud rate = fU/(16 (BRDATA0 + 1)).
18.8.2 Mode 2 Baud Rate Calculation
The baud rate in mode 2 is fixed at the fU clock frequency divided by 16: Mode 2 baud rate = fU/16
18.8.3 Modes 1 and 3 Baud Rate Calculation
In modes 1 and 3, the baud rate is determined by the UART baud rate data register, BRDATA0 in page 8 at
address 17H: Mode 1 and 3 baud rate = fU/(16 (BRDATA0 + 1))
Table 18.1
Mode
Mode 2
Mode 0
Mode 1
Mode 3
PS032408-0220
Commonly Used Baud Rates Generated by BRDATA0
Baud Rate
UART Clock (fU)
BRDATA0
Decimal
Hexadecimal
x
x
0.5 MHz
8 MHz
230,400 Hz
11.0592 MHz
02
02H
115,200 Hz
11.0592 MHz
05
05H
57,600 Hz
11.0592 MHz
11
0BH
38,400 Hz
11.0592 MHz
17
11H
19,200 Hz
11.0592 MHz
35
23H
9,600 Hz
11.0592 MHz
71
47H
4,800 Hz
11.0592 MHz
143
8FH
62,500 Hz
10 MHz
09
09H
9,615 Hz
10 MHz
64
40H
38,461 Hz
8 MHz
12
0CH
12,500 Hz
8 MHz
39
27H
19,230 Hz
4 MHz
12
0CH
9,615 Hz
4 MHz
25
19H
PRELIMINARY
18-6
S3F8S6B Product Specification
Chapter 18. UART 0
18.9 Block Diagram
Data Bus
TB8
MS0
MS1
BRDATA0
1/8
1/4
1/2
MUX
fU
S
D
CLK
Q
UDATA0
CLK
Baud Rate
Generator
MS0
MS1
RxD0
Zero Detector
1/1
UART0CONL.3-.2
Write to
UDATA0
TxD0
Shift
Start
Tx Control
Tx Clock
EN
TIP
Send
TxD0
Shift
Clock
TIE
IRQ5
Interrupt
RIE
RIP
Rx Clock
RE
RIP
Receive
Rx Control
Start
1-to-0
Transition
Detector
Shift
Shift
Value
Bit Detector
Shift
Register
MS0
MS1
UDATA0
RxD0
Data Bus
Figure 18-5
PS032408-0220
UART 0 Functional Block Diagram
PRELIMINARY
18-7
S3F8S6B Product Specification
Chapter 18. UART 0
18.10 uart 0 Mode 0 Function Description
In mode 0, UART 0 is input and output through the RxD0 (P1.2) pin and TxD0 (P1.3) pin outputs the shift clock.
Data is transmitted or received in 8-bit units only. The LSB of the 8-bit value is transmitted (or received) first.
18.10.1 Mode 0 Transmit Procedure
1. Select the UART 0 clock, UART0CONL.3 and .2.
2. Clear the UART 0 transmit parity-bit auto generation enable bit (UART0CONL.7).
3. Select mode 0 by setting UART0CONH.7 and .6 to "00B".
4. Write transmission data to the shift register UDATA0 (16H, page 8) to start the transmission operation.
18.10.2 Mode 0 Receive Procedure
1. Select the UART 0 clock, UART0CONL.3 and .2.
2. Clear the UART 0 transmit parity-bit auto generation enable bit (UART0CONL.7).
3. Select mode 0 by setting UART0CONH.7 and .6 to "00B".
4. Clear the receive interrupt pending bit (UART0CONH.0) by writing a "0" to UART0CONH.0.
5. Set the UART receive enable bit (UART0CONH.4) to "1".
6. The shift clock will now be output to the TxD0 (P1.3) pin and will read the data at the RxD0 (P1.2) pin. A
UART 0 receive interrupt occurs when UART0CONH.1 is set to "1".
Write to Shift Register (UDATA0)
RxD0 (Data Out)
D0
D1
D2
D3
D4
D5
D6
Transmit
Shift
D7
TxD0 (Shift Clock)
TIP
Clear RIP and set RE
RIP
Receive
RE
Shift
D0
RxD0 (Data In)
D1
D2
D3
D4
D5
D6
D7
TxD0 (Shift Clock)
1
Figure 18-6
PS032408-0220
2
3
4
5
6
7
8
Timing Diagram for Serial Port Mode 0 Operation
PRELIMINARY
18-8
S3F8S6B Product Specification
Chapter 18. UART 0
18.11 Serial Port Mode 1 Function Description
In mode 1, 10-bits are transmitted (through the TxD0 (P1.3) pin) or received (through the RxD0 (P1.2) pin).
Each data frame has three components:
•
Start bit ("0")
•
8 data bits (LSB first)
•
Stop bit ("1")
The baud rate for mode 1 is variable.
18.11.1 Mode 1 Transmit Procedure
1. Select the UART 0 clock, UART0CONL.3 and .2.
2. Clear the UART 0 transmit parity-bit auto generation enable bit (UART0CONL.7).
3. Select the baud rate to be generated by BRDATA0.
4. Select mode 1 (8-bit UART) by setting UART0CONH bits 7 and 6 to "01B".
5. Write transmission data to the shift register UDATA0 (16H, page 8). The start and stop bits are generated
automatically by hardware.
18.11.2 Mode 1 Receive Procedure
1. Select the UART 0 clock, UART0CONL.3 and .2.
2. Clear the UART 0 transmit parity-bit auto generation enable bit (UART0CONL.7).
3. Select the baud rate to be generated by BRDATA0.
4. Select mode 1 and set the RE (Receive Enable) bit in the UART0CONH register to "1".
5. The start bit low ("0") condition at the RxD0 (P1.2) pin will cause the UART 0 module to start the serial data
receive operation.
PS032408-0220
PRELIMINARY
18-9
S3F8S6B Product Specification
Chapter 18. UART 0
Tx
Clock
Shift
TxD0
D0
D1
D2
D3
D4
D5
D6
D7
Start Bit
D0
D1
D2
D3
D4
D5
D6
Start Bit
Stop Bit
Transmit
Write to Shift Register (UDATA0)
TIP
Rx
Clock
RxD0
D7
Stop Bit
Receive
Bit Detect Sample Time
Shift
RIP
Figure 18-7
PS032408-0220
Timing Diagram for Serial Port Mode 1 Operation
PRELIMINARY
18-10
S3F8S6B Product Specification
Chapter 18. UART 0
18.12 Serial Port Mode 2 Function Description
In mode 2, 11-bits are transmitted (through the TxD0 (P1.3) pin) or received (through the RxD0 (P1.2) pin). Each
data frame has four components:
•
Start bit ("0")
•
8 data bits (LSB first)
•
Programmable 9th data bit
•
Stop bit ("1")
The 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the TB8 bit (UART0CONH.3).
When receiving, the 9th data bit that is received is written to the RB8 bit (UART0CONH.2), while the stop bit is
ignored. The baud rate for mode 2 is fU/16 clock frequency.
18.12.1 Mode 2 Transmit Procedure
1. Select the UART 0 clock, UART0CONL.3 and .2.
2. Select the UART 0 transmit parity-bit auto generation enable or disable bit (UART0CONL.7).
3. Select mode 2 (9-bit UART) by setting UART0CONH bits 7 and 6 to "10B". Also, select the 9th data bit to be
transmitted by writing TB8 to "0" or "1".
4. Write transmission data to the shift register, UDATA0 (16H, page 8), to start the transmit operation.
18.12.2 Mode 2 Receive Procedure
1. Select the UART 0 clock, UART0CONL.3 and .2.
2. Select the UART 0 transmit parity-bit auto generation enable or disable bit (UART0CONL.7).
3. Select mode 2 and set the receive enable bit (RE) in the UART0CONH register to "1".
4. The receive operation starts when the signal at the RxD0 (P1.2) pin goes to low level.
PS032408-0220
PRELIMINARY
18-11
S3F8S6B Product Specification
Chapter 18. UART 0
Tx
Clock
Write to Shift Register (UDATA0)
TxD0
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Start Bit
Transmit
Shift
Stop Bit
TIP
Rx
Clock
RxD0
RB8
Stop
Bit
Receive
Bit Detect Sample Time
Shift
RIP
Figure 18-8
PS032408-0220
Timing Diagram for Serial Port Mode 2 Operation
PRELIMINARY
18-12
S3F8S6B Product Specification
Chapter 18. UART 0
18.13 Serial Port Mode 3 Function Description
In mode 3, 11-bits are transmitted (through the TxD0 (P1.3) pin) or received (through the RxD0 (P1.2) pin). Mode
3 is identical to mode 2 except for baud rate, which is variable.
Each data frame has four components:
•
Start bit ("0")
•
8 data bits (LSB first)
•
Programmable 9th data bit
•
Stop bit ("1")
18.13.1 Mode 3 Transmit Procedure
1. Select the UART 0 clock, UART0CONL.3 and .2.
2. Select the UART 0 transmit parity-bit auto generation enable or disable bit (UART0CONL.7).
3. Select mode 3 operation (9-bit UART) by setting UART0CONH bits 7 and 6 to "11B". Also, select the 9th data
bit to be transmitted by writing UART0CONH.3 (TB8) to "0" or "1".
4. Write transmission data to the shift register, UDATA0 (16H, page 8), to start the transmit operation.
18.13.2 Mode 3 Receive Procedure
1. Select the UART 0 clock, UART0CONL.3 and .2.
2. Select the UART 0 transmit parity-bit auto generation enable or disable bit (UART0CONL.7).
3. Select mode 3 and set the RE (Receive Enable) bit in the UART0CONH register to "1".
4. The receive operation will be started when the signal at the RxD0 (P1.2) pin goes to low level.
PS032408-0220
PRELIMINARY
18-13
S3F8S6B Product Specification
Chapter 18. UART 0
Tx
Clock
Write to Shift Register (UDATA0)
TxD0
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Start Bit
Transmit
Shift
Stop Bit
TIP
Rx
Clock
RxD0
RB8
Stop
Bit
Receive
Bit Detect Sample Time
Shift
RIP
Figure 18-9
PS032408-0220
Timing Diagram for Serial Port Mode 3 Operation
PRELIMINARY
18-14
S3F8S6B Product Specification
Chapter 18. UART 0
18.14 Serial Communication for Multiprocessor Configurations
The S3F8-series multiprocessor communication features lets a "master" S3F8S6B send a multiple-frame serial
message to a "slave" device in a multi- S3F8S6B configuration. It does this without interrupting other slave devices
that may be on the same serial line.
This feature can be used only in UART modes 2 or 3. In these modes 2 and 3, 9 data bits are received. The 9th bit
value is written to RB8 (UART0CONH.2). The data receive operation is concluded with a stop bit. You can
program this function so that when the stop bit is received, the serial interrupt will be generated only if RB8 = "1".
To enable this feature, you set the MCE bit in the UART0CONH register. When the MCE bit is "1", serial data
frames that are received with the 9th bit = "0" do not generate an interrupt. In this case, the 9th bit simply
separates the address from the serial data.
18.14.1 Sample Protocol for Master/Slave Interaction
When the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out
an address byte to identify the target slave. Note that in this case, an address byte differs from a data byte: In an
address byte, the 9th bit is "1" and in a data byte, it is "0".
The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being
addressed. The addressed slave then clears its MCE bit and prepares to receive incoming data bytes.
The MCE bits of slaves that were not addressed remain set, and they continue operating normally while ignoring
the incoming data bytes.
While the MCE bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit.
For mode 1 reception, if MCE is "1", the receive interrupt will be issue unless a valid stop bit is received.
PS032408-0220
PRELIMINARY
18-15
S3F8S6B Product Specification
Chapter 18. UART 0
18.14.2 Setup Procedure for Multiprocessor Communications
Follow these steps to configure multiprocessor communications:
1. Set all S3F8S6B devices (masters and slaves) to UART mode 2 or 3.
2. Write the MCE bit of all the slave devices to "1".
3. The master device's transmission protocol is:
−
First byte: the address
identifying the target
slave device (9th bit = "1")
−
Next bytes: data
(9th bit = "0")
−
4. When the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is "1".
The targeted slave compares the address byte to its own address and then clears its MCE bit in order to
receive incoming data. The other slaves continue operating normally.
Full-Duplex Multi-S3F8S6B Interconnect
TxD
RxD
TxD
RxD
TxD
RxD
Master
Slave 1
Slave 2
S3F8S6B
S3F8S6B
S3F8S6B
Figure 18-10
PS032408-0220
TxD
...
RxD
Slave n
S3F8S6B
Connection Example for Multiprocessor Serial Data Communications
PRELIMINARY
18-16
S3F8S6B Product Specification
19
Chapter 19. UART 1
UART 1
19.1 Overview
The UART 1 block has a full-duplex serial port with programmable operating modes: There is one synchronous
mode and three UART (Universal Asynchronous Receiver/Transmitter) modes:
•
Serial I/O with baud rate of fU/(16 (BRDATA1+1))
•
8-bit UART mode; variable baud rate
•
9-bit UART mode; fU/16
•
9-bit UART mode, variable baud rate
UART 1 receive and transmit buffers are both accessed via the data register, UDATA1, is page 8 at address 1AH.
Writing to the UART data register loads the transmit buffer; reading the UART data register accesses a physically
separate receive buffer.
When accessing a receive data buffer (shift register), reception of the next byte can begin before the previously
received byte has been read from the receive register. However, if the first byte has not been read by the time the
next byte has been completely received, one of the bytes will be lost.
In all operating modes, transmission is started when any instruction (usually a write operation) uses the UDATA1
register as its destination address. In mode 0, serial data reception starts when the receive interrupt pending bit
(UART1CONH.0) is "0" and the receive enable bit (UART1CONH.4) is "1". In mode 1, 2, and 3, reception starts
whenever an incoming start bit ("0") is received and the receive enable bit (UART1CONH.4) is set to "1".
PS032408-0220
PRELIMINARY
19-1
S3F8S6B Product Specification
Chapter 19. UART 1
19.2 Programming Procedure
To program the UART 1 modules, follow these basic steps:
1. Configure P1.4 and P1.5 to alternative function (RxD1 (P1.4), TxD1 (P1.5)) for UART module by setting the
P1CONH register to appropriately value.
2. Load an 8-bit value to the UART1CONH/L control register to properly configure the UART I/O module.
3. For interrupt generation, set the UART 1 I/O interrupt enable bit (UART1CONH.1 or UART1CONL.1) to "1".
4. When you transmit data to the UART 1 buffer, write data to UDATA1, the shift operation starts.
5. When the shift operation (receive/transmit) is completed, UART 1 pending bit (UART1CONH.0 or
UART1CONL.0) is set to "1" and an UART 1 interrupt request is generated.
19.3 UART 1 High-Byte Control Register (UART1CONh)
The control register for the UART 1 is called UART1CONH in page 8 at address 18H.
It has the following control functions:
•
Operating mode and baud rate selection
•
Multiprocessor communication and interrupt control
•
Serial receive enable/disable control
•
9th data bit location for transmit and receive operations (modes 2 and 3 only)
•
UART 1 receive interrupt control
A reset clears the UART1CONH value to "00H". So, if you want to use UART 1 module, you must write
appropriate value to UART1CONH.
19.4 UART 1 Low-Byte Control Register (UART1CONl)
The control register for the UART 1 is called UART1CONL in page 8 at address 19H.
It has the following control functions:
•
UART 1 transmit and receive parity-bit control
•
UART 1 clock selection
•
UART 1 transmit interrupt control
A reset clears the UART1CONL value to "00H". So, if you want to use UART 1 module, you must write appropriate
value to UART1CONL.
PS032408-0220
PRELIMINARY
19-2
S3F8S6B Product Specification
Chapter 19. UART 1
UART 1 Control Register, High Byte (UART1CONH)
18H, Page 8, R/W
MSB
MS1
MS0
MCE
RE
TB8
RB8
RIE
RIP
LSB
Uart 1 receive interrupt pending bit:
0 = No interrupt pending(when read),
clear pending bit(when write)
1 = Interrupt is pending(when read)
Operating mode and
baud rate selection bits:
(see table below)
Multiprocessor communication(1)
enable bit (for modes 2 and 3 only):
0 = Disable
1 = Enable
Uart 1 receive interrupt enable bit:
0 = Disable Rx interrupt
1 = Enable Rx interrupt
Serial data receive enable bit:
0 = Disable
1 = Enable
RB8(3) (Only when UART1CONL.7 = 0):
Location of the 9th data bit that was
received in UART 1 mode 2 or 3 ("0" or "1")
TB8(3) (Only when UART1CONL.7 = 0):
Location of the 9th data bit to be
transmitted in UART 1 mode 2 or 3 ("0" or "1")
MS1 MS0 Mode Description(2) Baud Rate
0
0
1
1
0
1
0
1
0
1
2
3
Shift register
8-bit UART
9-bit UART
9-bit UART
(fu/(16 x (BRDATA1 + 1)))
(fu/(16 x (BRDATA1 + 1)))
(fu /16)
(fu/(16 x (BRDATA1 + 1)))
NOTES:
1. In mode 2 or 3, if the UART1CONH.5 bit is set to "1" then the receive interrupt will not be
activated if the received 9th data bit is "0". In mode 1, if UART1CONH.5 = "1" then the
receive interrut will not be activated if a valid stop bit was not received.
In mode 0, the UART1CONH.5 bit should be "0"
2. The descriptions for 8-bit and 9-bit UART mode do not include start and stop bits
for serial data receive and transmit.
3. If the UART1CONL.7 = 1, This bit is "don't care".
Figure 19-1
PS032408-0220
UART 1 High Byte Control Register (UART1CONH)
PRELIMINARY
19-3
S3F8S6B Product Specification
Chapter 19. UART 1
UART 1 Control Register, Low Byte (UART1CONL)
19H, Page 8, R/W
MSB
.7
.4
.5
.6
.2
.3
TIE
TIP
LSB
Uart 1 transmit interrupt pending bit:
0 = No interrupt pending(when read),
clear pending bit(when write)
1 = Interrupt is pending(when read)
UART 1 transmit parity-bit autogeneration enable bit(2):
0 = Disable parity-bit auto-generation
1 = Enable parity-bit auto-generation
Uart 1 transmit interrupt enable bit:
0 = Disable Tx interrupt
1 = Enable Tx interrupt
UART 1 transmit parity-bit
selection bit(1),(2):
0 = Even parity-bit
1 = Odd parity-bit
UART 1 receive parity-bit
selection bit(1),(2):
0 = Even parity-bit check
1 = Odd parity-bit check
Uart 1 clock selection bits:
00 = fxx/8
01 = fxx/4
10 = fxx/2
11 = fxx/1
UART 1 receive parity-bit
error status bit(1),(2):
0 = No parity-bit error
1 = Parity-bit error
NOTES:
1. If the UART1CONL.7 = 0, This bit is "don't care".
2. The bits UART1CONL.7-.4 are for mode 2 and 3 only.
Figure 19-2
PS032408-0220
UART 1 Low Byte Control Register (UART1CONL)
PRELIMINARY
19-4
S3F8S6B Product Specification
Chapter 19. UART 1
19.5 UART 1 Interrupt Pending Bits
In mode 0, the receive interrupt pending bit UART1CONH.0 is set to "1" when the 8th receive data bit has been
shifted. In mode 1, the UART1CONH.0 bit is set to "1" at the halfway point of the stop bit's shift time. In mode 2, or
3, the UART1CONH.0 bit is set to "1" at the halfway point of the RB8 bit's shift time. When the CPU has
acknowledged the receive interrupt pending condition, the UART1CONH.0 bit must then be cleared by software in
the interrupt service routine.
In mode 0, the transmit interrupt pending bit UART1CONL.0 is set to "1" when the 8th transmit data bit has been
shifted. In mode 1, 2, or 3, the UART1CONL.0 bit is set at the start of the stop bit. When the CPU has
acknowledged the transmit interrupt pending condition, the UART1CONL.0 bit must then be cleared by software in
the interrupt service routine.
19.6 UART 1 Data Register (UDATA1)
UART 1 Data Register (UDATA1)
1AH, Page 8, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Transmit or receive data
Figure 19-3
UART 1 Data Register (UDATA1)
19.7 UART 1 Baud Rate Data Register (BRDATA1)
The value stored in the UART 1 baud rate register, BRDATA1, lets you determine the UART clock rate (baud
rate).
UART 1 Baud Rate Data Register (BRDATA1)
1BH, Page 8, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Baud rate data
Figure 19-4
PS032408-0220
UART 1 Baud Rate Data Register (BRDATA1)
PRELIMINARY
19-5
S3F8S6B Product Specification
Chapter 19. UART 1
19.8 Baud Rate Calculations
19.8.1 Mode 0 Baud Rate Calculation
In mode 0, the baud rate is determined by the UART baud rate data register, BRDATA1 in page 8 at
address 1BH: Mode 0 baud rate = fU/(16 (BRDATA1 + 1)).
19.8.2 Mode 2 Baud Rate Calculation
The baud rate in mode 2 is fixed at the fU clock frequency divided by 16: Mode 2 baud rate = fU/16
19.8.3 Modes 1 and 3 Baud Rate Calculation
In modes 1 and 3, the baud rate is determined by the UART baud rate data register, BRDATA1 in page 8 at
address 1BH: Mode 1 and 3 baud rate = fU/(16 (BRDATA1 + 1))
Table 19.1
Mode
Mode 2
Mode 0
Mode 1
Mode 3
PS032408-0220
Commonly Used Baud Rates Generated by BRDATA1
Baud Rate
UART Clock (fU)
BRDATA1
Decimal
Hexadecimal
x
x
0.5 MHz
8 MHz
230,400 Hz
11.0592 MHz
02
02H
115,200 Hz
11.0592 MHz
05
05H
57,600 Hz
11.0592 MHz
11
0BH
38,400 Hz
11.0592 MHz
17
11H
19,200 Hz
11.0592 MHz
35
23H
9,600 Hz
11.0592 MHz
71
47H
4,800 Hz
11.0592 MHz
143
8FH
62,500 Hz
10 MHz
09
09H
9,615 Hz
10 MHz
64
40H
38,461 Hz
8 MHz
12
0CH
12,500 Hz
8 MHz
39
27H
19,230 Hz
4 MHz
12
0CH
9,615 Hz
4 MHz
25
19H
PRELIMINARY
19-6
S3F8S6B Product Specification
Chapter 19. UART 1
19.9 Block Diagram
Data Bus
TB8
MS0
MS1
BRDATA1
1/8
1/4
1/2
MUX
fU
S
D
CLK
Q
UDATA1
CLK
Baud Rate
Generator
MS0
MS1
RxD1
Zero Detector
1/1
UART1CONL.3-.2
Write to
UDATA1
TxD1
Shift
Start
Tx Control
Tx Clock
EN
TIP
Send
TxD1
Shift
Clock
TIE
IRQ5
Interrupt
RIE
RIP
Rx Clock
RE
RIP
Receive
Rx Control
Start
1-to-0
Transition
Detector
Shift
Shift
Value
Bit Detector
Shift
Register
MS0
MS1
UDATA1
RxD1
Data Bus
Figure 19-5
PS032408-0220
UART 1 Functional Block Diagram
PRELIMINARY
19-7
S3F8S6B Product Specification
Chapter 19. UART 1
19.10 UART 1 Mode 0 Function Description
In mode 0, UART 1 is input and output through the RxD1 (P1.4) pin and TxD1 (P1.5) pin outputs the shift clock.
Data is transmitted or received in 8-bit units only. The LSB of the 8-bit value is transmitted (or received) first.
19.10.1 Mode 0 Transmit Procedure
1. Select the UART 1 clock, UART1CONL.3 and .2.
2. Clear the UART 1 transmit parity-bit auto generation enable bit (UART1CONL.7).
3. Select mode 0 by setting UART1CONH.7 and .6 to "00B".
4. Write transmission data to the shift register UDATA1 (1AH, page 8) to start the transmission operation.
19.10.2 Mode 0 Receive Procedure
1. Select the UART 1 clock, UART1CONL.3 and .2.
2. Clear the UART 1 transmit parity-bit auto generation enable bit (UART1CONL.7).
3. Select mode 0 by setting UART1CONH.7 and .6 to "00B".
4. Clear the receive interrupt pending bit (UART1CONH.0) by writing a "0" to UART1CONH.0.
5. Set the UART receive enable bit (UART1CONH.4) to "1".
6. The shift clock will now be output to the TxD1 (P1.5) pin and will read the data at the RxD1 (P1.4) pin. A
UART 1 receive interrupt occurs when UART1CONH.1 is set to "1".
Write to Shift Register (UDATA1)
RxD1 (Data Out)
D0
D1
D2
D3
D4
D5
D6
Transmit
Shift
D7
TxD1 (Shift Clock)
TIP
Clear RIP and set RE
RIP
Receive
RE
Shift
D0
RxD1 (Data In)
D1
D2
D3
D4
D5
D6
D7
TxD1 (Shift Clock)
1
Figure 19-6
PS032408-0220
2
3
4
5
6
7
8
Timing Diagram for Serial Port Mode 0 Operation
PRELIMINARY
19-8
S3F8S6B Product Specification
Chapter 19. UART 1
19.11 Serial Port Mode 1 Function Description
In mode 1, 10-bits are transmitted (through the TxD1 (P1.5) pin) or received (through the RxD1 (P1.4) pin). Each
data frame has three components:
•
Start bit ("0")
•
8 data bits (LSB first)
•
Stop bit ("1")
The baud rate for mode 1 is variable.
19.11.1 Mode 1 Transmit Procedure
1. Select the UART 1 clock, UART1CONL.3 and .2.
2. Clear the UART 1 transmit parity-bit auto generation enable bit (UART1CONL.7).
3. Select the baud rate to be generated by BRDATA1.
4. Select mode 1 (8-bit UART) by setting UART1CONH bits 7 and 6 to "01B".
5. Write transmission data to the shift register UDATA1 (1AH, page 8). The start and stop bits are generated
automatically by hardware.
19.11.2 Mode 1 Receive Procedure
1. Select the UART 1 clock, UART1CONL.3 and .2.
2. Clear the UART 1 transmit parity-bit auto generation enable bit (UART1CONL.7).
3. Select the baud rate to be generated by BRDATA1.
4. Select mode 1 and set the RE (Receive Enable) bit in the UART1CONH register to "1".
5. The start bit low ("0") condition at the RxD1 (P1.4) pin will cause the UART 1 module to start the serial data
receive operation.
PS032408-0220
PRELIMINARY
19-9
S3F8S6B Product Specification
Chapter 19. UART 1
Tx
Clock
Shift
TxD1
D0
D1
D2
D3
D4
D5
D6
D7
Start Bit
D0
D1
D2
D3
D4
D5
D6
Start Bit
Stop Bit
Transmit
Write to Shift Register (UDATA1)
TIP
Rx
Clock
RxD1
D7
Stop Bit
Receive
Bit Detect Sample Time
Shift
RIP
Figure 19-7
PS032408-0220
Timing Diagram for Serial Port Mode 1 Operation
PRELIMINARY
19-10
S3F8S6B Product Specification
Chapter 19. UART 1
19.12 Serial Port Mode 2 Function Description
In mode 2, 11-bits are transmitted (through the TxD1 (P1.5) pin) or received (through the RxD1 (P1.4) pin). Each
data frame has four components:
•
Start bit ("0")
•
8 data bits (LSB first)
•
Programmable 9th data bit
•
Stop bit ("1")
The 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the TB8 bit (UART1CONH.3).
When receiving, the 9th data bit that is received is written to the RB8 bit (UART1CONH.2), while the stop bit is
ignored. The baud rate for mode 2 is fU/16 clock frequency.
19.12.1 Mode 2 Transmit Procedure
1. Select the UART 1 clock, UART1CONL.3 and .2.
2. Select the UART 1 transmit parity-bit auto generation enable or disable bit (UART1CONL.7).
3. Select mode 2 (9-bit UART) by setting UART1CONH bits 7 and 6 to "10B". Also, select the 9th data bit to be
transmitted by writing TB8 to "0" or "1".
4. Write transmission data to the shift register, UDATA1 (1AH, page 8), to start the transmit operation.
19.12.2 Mode 2 Receive Procedure
1. Select the UART 1 clock, UART1CONL.3 and .2.
2. Select the UART 1 transmit parity-bit auto generation enable or disable bit (UART1CONL.7).
3. Select mode 2 and set the receive enable bit (RE) in the UART1CONH register to "1".
4. The receive operation starts when the signal at the RxD1 (P1.4) pin goes to low level.
PS032408-0220
PRELIMINARY
19-11
S3F8S6B Product Specification
Chapter 19. UART 1
Tx
Clock
Write to Shift Register (UDATA1)
TxD1
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Start Bit
Transmit
Shift
Stop Bit
TIP
Rx
Clock
RxD1
RB8
Stop
Bit
Receive
Bit Detect Sample Time
Shift
RIP
Figure 19-8
PS032408-0220
Timing Diagram for Serial Port Mode 2 Operation
PRELIMINARY
19-12
S3F8S6B Product Specification
Chapter 19. UART 1
19.13 Serial Port Mode 3 Function Description
In mode 3, 11-bits are transmitted (through the TxD1 (P1.5) pin) or received (through the RxD1 (P1.4) pin). Mode
3 is identical to mode 2 except for baud rate, which is variable.
Each data frame has four components:
•
Start bit ("0")
•
8 data bits (LSB first)
•
Programmable 9th data bit
•
Stop bit ("1")
19.13.1 Mode 3 Transmit Procedure
1. Select the UART 1 clock, UART1CONL.3 and .2.
2. Select the UART 1 transmit parity-bit auto generation enable or disable bit (UART1CONL.7).
3. Select mode 3 operation (9-bit UART) by setting UART1CONH bits 7 and 6 to "11B". Also, select the 9th data
bit to be transmitted by writing UART1CONH.3 (TB8) to "0" or "1".
4. Write transmission data to the shift register, UDATA1 (1AH, page 8), to start the transmit operation.
19.13.2 Mode 3 Receive Procedure
1. Select the UART 1 clock, UART1CONL.3 and .2.
2. Select the UART 1 transmit parity-bit auto generation enable or disable bit (UART1CONL.7).
3. Select mode 3 and set the RE (Receive Enable) bit in the UART1CONH register to "1".
4. The receive operation will be started when the signal at the RxD1 (P1.4) pin goes to low level.
PS032408-0220
PRELIMINARY
19-13
S3F8S6B Product Specification
Chapter 19. UART 1
Tx
Clock
Write to Shift Register (UDATA1)
TxD1
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Start Bit
Transmit
Shift
Stop Bit
TIP
Rx
Clock
RxD1
RB8
Stop
Bit
Receive
Bit Detect Sample Time
Shift
RIP
Figure 19-9
PS032408-0220
Timing Diagram for Serial Port Mode 3 Operation
PRELIMINARY
19-14
S3F8S6B Product Specification
Chapter 19. UART 1
19.14 Serial Communication for Multiprocessor Configurations
The S3F-series multiprocessor communication features lets a "master" S3F8S6B send a multiple-frame serial
message to a "slave" device in a multi- S3F8S6B configuration. It does this without interrupting other slave devices
that may be on the same serial line.
This feature can be used only in UART modes 2 or 3. In these modes 2 and 3, 9 data bits are received. The 9th bit
value is written to RB8 (UART1CONH.2). The data receive operation is concluded with a stop bit. You can
program this function so that when the stop bit is received, the serial interrupt will be generated only if RB8 = "1".
To enable this feature, you set the MCE bit in the UART1CONH register. When the MCE bit is "1", serial data
frames that are received with the 9th bit = "0" do not generate an interrupt. In this case, the 9th bit simply
separates the address from the serial data.
19.14.1 Sample Protocol for Master/Slave Interaction
When the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out
an address byte to identify the target slave. Note that in this case, an address byte differs from a data byte: In an
address byte, the 9th bit is "1" and in a data byte, it is "0".
The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being
addressed. The addressed slave then clears its MCE bit and prepares to receive incoming data bytes.
The MCE bits of slaves that were not addressed remain set, and they continue operating normally while ignoring
the incoming data bytes.
While the MCE bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit.
For mode 1 reception, if MCE is "1", the receive interrupt will be issue unless a valid stop bit is received.
PS032408-0220
PRELIMINARY
19-15
S3F8S6B Product Specification
Chapter 19. UART 1
19.14.2 Setup Procedure for Multiprocessor Communications
Follow these steps to configure multiprocessor communications:
1. Set all S3F8S6B devices (masters and slaves) to UART mode 2 or 3.
2. Write the MCE bit of all the slave devices to "1".
3. The master device's transmission protocol is:
−
First byte: the address
identifying the target
slave device (9th bit = "1")
−
Next bytes: data
(9th bit = "0")
4. When the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is "1".
The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive
incoming data. The other slaves continue operating normally.
Full-Duplex Multi-S3F8S6B Interconnect
TxD
RxD
Master
S3F8S6B
Figure 19-10
PS032408-0220
TxD
RxD
Slave 1
TxD
RxD
Slave 2
S3F8S6B
S3F8S6B
...
TxD
RxD
Slave n
S3F8S6B
Connection Example for Multiprocessor Serial Data Communications
PRELIMINARY
19-16
S3F8S6B Product Specification
20
Chapter 20. Pattern Generation Module
Pattern Generation Module
20.1 Overview
20.1.1 PAttern Gneration Flow
You can output up to 8-bit through P3.0-P3.7 by tracing the following sequence. First of all, you have to change
the PGDATA into what you want to output. And then you have to set the PGCON to enable the pattern generation
module and select the triggering signal. From now, bits of PGDATA are on the P3.0-P3.7 whenever the selected
triggering signal happens.
Data write to PG DATA
Triggering signal selection : PGCON.3-.0
Triggering signal generation
Data output through P3.7-P3.0
Figure 20-1
PS032408-0220
Pattern Generation Flow
PRELIMINARY
20-1
S3F8S6B Product Specification
Chapter 20. Pattern Generation Module
Pattern Generation Module Control Register (PGCON)
D0H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Detection voltage selection bit:
00 = Timer A match signal triggering
01 = Timer B overflow signal triggering
10 = Timer D0 match signal triggering
11 = S/W trggering
Not used for the S3F8S6B
PG operation disable/enable selection bit:
0 = PG operation disable
1 = PG operation enable
S/W trigger start bit:
0 = No effect
1 = S/W trigger start (auto clera)
Figure 20-2
Pattern Generation Control Register (PGCON)
PGDATA
(Bank1, D1H)
PG Buffer
.7
.7
P3.7
.6
.6
P3.6
.5
.5
P3.5
.4
.4
P3.4
.3
.3
P3.3
.2
.2
P3.2
.1
.1
P3.1
.0
.0
P3.0
Software (PGCON.3)
Timer A match signal
Timer B overflow signal
Timer D0 match signal
PGCON.2
Figure 20-3
PS032408-0220
Pattern Generation Circuit Diagram
PRELIMINARY
20-2
S3F8S6B Product Specification
Example 20-1
ORG
0000h
ORG
0100h
INITIAL:
SB0
LD
LD
LD
LD
LD
LD
SB1
LD
LD
LD
SB0
Chapter 20. Pattern Generation Module
Using the Pattern Generation
SYM, #00h
IMR, #01h
SPH, #0h
SPL, #0FFh
BTCON, #10100011b
CLKCON, #00011000b
;
;
;
;
;
;
Disable Global/Fast interrupt → SYM
Enable IRQ0 interrupt
High byte of stack pointer → SPH
Low byte of stack pointer → SPL
Disable Watchdog
Non-divided (fxx)
P3CONH,#00101001b
P3CONM,#01001001b
P3CONL,#00001001b
;
;
;
Enable PG output
Enable PG output
Enable PG output
PGDATA, #10101010b
PGCON, #00000100b
; PG data setting
; Triggering by Timer A match then pattern data are output
EI
MAIN:
NOP
NOP
SB1
LD
OR
SB0
NOP
NOP
JR
T,MAIN
.END
PS032408-0220
PRELIMINARY
20-3
S3F8S6B Product Specification
21
Chapter 21. Embedded Flash Memory Interface
Embedded Flash Memory Interface
21.1 Overview
The S3F8S6B has an on-chip Flash memory internally instead of masked ROM. The Flash memory is accessed
by "LDC" instruction and the type of sector erase and a byte programmable Flash, a user can program the data in
a Flash memory area any time you want. The S3F8S6B's embedded 64KB memory has two operating features as
below:
•
User Program Mode
•
Tool Program Mode: Refer to the chapter 24. S3F8S6B Flash MCU.
PS032408-0220
PRELIMINARY
21-1
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.2 User Program Mode
This mode supports sector erase, byte programming, byte read and one protection mode (Hard lock protection).
The read protection mode is available only in Tool Program mode. So in order to make a chip into read protection,
you need to select a read protection option when you program a initial your code to a chip by using Tool Program
mode by using a programming tool.
The S3F8S6B has the pumping circuit internally; therefore, 12.5V into VPP (Test) pin is not needed. To program a
Flash memory in this mode several control registers will be used. There are four kind functions – programming,
reading, sector erase and hard lock protection
NOTE:
1.
The user program mode cannot be used when the CPU operates with the subsystem clock.
2.
Be sure to execute the DI instruction before starting user program mode. The user program mode checks the interrupt
request register (IRQ). If an interrupt request is generated, user program mode is stopped.
3.
User program mode is also stopped by an interrupt request that is masked even in the DI status. To prevent this, Be
disable the interrupt by using the each peripheral interrupt enable bit.
PS032408-0220
PRELIMINARY
21-2
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.2.1 Flash Memory Control Registers (User Program Mode)
21.2.1.1 Flash Memory Control Register
FMCON register is available only in user program mode to select the Flash Memory operation mode; sector erase,
byte programming, and to make the Flash memory into a hard lock protection.
Flash Memory Control Register (FMCON)
F9H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Flash operation start bit:
0 = Operation stop
1 = Operation start
(This bit will be cleared automatically
just after the corresponding operation
completed).
Flash memory mode selection bits:
0101 = Programming mode
1010 = Sector erase mode
0110 = Hard lock mode
others = Not available
Sector erase status bit:
0 = Success sector erase
1 = Fail sector erase
Not used for S3F8S6B
Figure 21-1
Flash Memory Control Register (FMCON)
The bit0 of FMCON register (FMCON.0) is a start bit for Erase and Hard Lock operation mode. Therefore,
operation of Erase and Hard Lock mode is activated when you set FMCON.0 to "1". Additionally, wait a time of
Erase (Sector erase) or Hard lock to complete its operation before a byte programming or a byte read of same
sector area by using "LDC" instruction. When you read or program a byte data from or into Flash memory, this bit
is not needed to manipulate.
The sector erase status bit is read only. Even if IMR bits are "0", the interrupt is serviced during the operation of
"Sector erase", when the each peripheral interrupt enable bit is set "1" and interrupt pending bit is set "1". If an
interrupt is requested during the operation of "Sector erase", the operation of "Sector erase" is discontinued, and
the interrupt is served by CPU. Therefore, the sector erase status bit should be checked after executing "Sector
erase". The "sector erase" operation is success if the bit is logic "0", and is failure if the bit is logic "1".
NOTE: When the ID code, "A5H", is written to the FMUSR register. A mode of sector erase, user program, and hard lock may
be executed unfortunately. So, it should be careful of the above situation.
PS032408-0220
PRELIMINARY
21-3
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.2.1.2 Flash Memory User Programming Enable Register
The FMUSR register is used for a safety operation of the Flash memory. This register will protect undesired erase
or program operation from malfunctioning of CPU caused by an electrical noise.
After reset, the user-programming mode is disabled, because the value of FMUSR is "00000000B" by reset
operation. If necessary to operate the Flash memory, you can use the user programming mode by setting the
value of FMUSR to "10100101B". The other value of "10100101b", User Program mode is disabled.
Flash Memory User Programming Enable Register (FMUSR)
F8H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Flash memory user programming enable bits:
10100101: Enable user programming mode
Other values: Disable user programming mode
Figure 21-2
PS032408-0220
Flash Memory User Programming Enable Register (FMUSR)
PRELIMINARY
21-4
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.2.1.3 Flash Memory Sector Address Registers
There are two sector address registers for addressing a sector to be erased. The FMSECL (Flash Memory Sector
Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Sector
Address Register High Byte) indicates the high byte of sector address.
The FMSECH is needed for S3F8S6B because it has 512 sectors. One sector consists of 128 bytes. Each sector's
address starts XX00H or XX80H that is a base address of sector is XX00H or XX80H. So FMSECL register 6-0
don't mean whether the value is '1' or '0'. We recommend that the simplest way is to load sector base address into
FMSECH and FMSECL register.
When programming the Flash memory, you should write data after loading sector base address located in the
target address to write data into FMSECH and FMSECL register. If the next operation is also to write data, you
should check whether next address is located in the same sector or not. In case of other sectors, you must load
sector address to FMSECH and FMSECL register according to the sector.
Flash Memory Sector Address Register (FMSECH)
F6H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Flash Memory Setor Address (High Byte)
NOTE:
Figure 21-3
The high-byte flash memory sector address pointer
value is the higher eight bits of the 16-bit pointer address.
Flash Memory Sector Address Register High Byte (FMSECH)
Flash Memory Sector Address Register (FMSECL)
F7H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Don't care
Flash Memory Sector Address (Low Byte)
NOTE:
Figure 21-4
PS032408-0220
The low-byte flash memory sector address pointer
value is the lower eight bits of the 16-bit pointer address.
Flash Memory Sector Address Register Low Byte (FMSECL)
PRELIMINARY
21-5
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.3 ISPTM (On-Board Programming) Sector
ISPTM sectors located in program memory area can store On Board Program software (Boot program code for
upgrading application code by interfacing with I/O port pin). The ISPTM sectors can not be erased or programmed
by LDC instruction for the safety of On Board Program software.
The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart
Option. If you don't like to use ISP sector, this area can be used as a normal program memory (can be erased or
programmed by LDC instruction) by setting ISP disable bit ("1") at the Smart Option. Even if ISP sector is selected,
ISP sector can be erased or programmed in the Tool Program mode, by Serial programming tools.
The size of ISP sector can be varied by settings of Smart Option. You can choose appropriate ISP sector size
according to the size of On Board Program software.
(HEX)
FFFFH
(Decimal)
65535
64K- bytes
Internal
Program
Memory Area
8FFH
Available
ISP Sector
255
Interrupt Vector Area
Smart option Area
0
FFH
3FH
3CH
00H
Byte
Figure 21-5
PS032408-0220
Program Memory Address Space
PRELIMINARY
21-6
S3F8S6B Product Specification
Table 21.1
Smart Option (003EH) ISP size selection bit
Chapter 21. Embedded Flash Memory Interface
ISP Sector Size
Area of ISP sector
ISP sector size
x
–
0
0
0
100H – 1FFH (256 Byte)
256 Bytes
0
0
1
100H – 2FFH (512 Byte)
512 Bytes
0
1
0
100H – 4FFH (1024 Byte)
1024 Bytes
0
1
1
100H – 8FFH (2048 Byte)
2048 Bytes
Bit 2
Bit 1
Bit 0
1
x
0
NOTE: The area of the ISP sector selected by Smart Option bit (003EH.2 – 003EH.0) can not be erased and programmed by
LDC instruction in User Program mode.
21.3.1 ISP Reset Vector and ISP Sector Size
If you use ISP sectors by setting the ISP Enable/Disable bit to "0" and the Reset Vector Selection bit to "0" at the
Smart Option, you can choose the reset vector address of CPU as shown in Table 21.2 by setting the ISP Reset
Vector Address Selection bits.
Table 21.2
Smart Option (003EH)
ISP Reset Vector Address Selection Bit
Reset Vector Address
Reset Vector
Address After POR
Usable Area for
ISP Sector
ISP Sector Size
Bit 7
Bit 6
Bit 5
1
x
x
0100H
–
–
0
0
0
0200H
100H – 1FFH
256 Bytes
0
0
1
0300H
100H – 2FFH
512 Bytes
0
1
0
0500H
100H – 4FFH
1024 Bytes
0
1
1
0900H
100H – 8FFH
2048 Bytes
NOTE: The selection of the ISP reset vector address by Smart Option (003EH.7 – 003EH.5) is not dependent of the selection
of ISP sector size by Smart Option (003EH.2 – 003EH.0).
PS032408-0220
PRELIMINARY
21-7
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.4 Sector Erase
User can erase a Flash memory partially by using sector erase function only in User Program Mode. The only unit
of Flash memory to be erased and programmed in User Program Mode is called sector.
The program memory of S3F8S6B is divided into 512 sectors for unit of erase and programming. Every sector has
all 128 byte sizes of program memory areas. So each sector should be erased first to program a new data (byte)
into a sector.
Minimum 10 ms delay time for erase is required after setting sector address and triggering erase start bit
(FMCON.0). Sector Erase is not supported in Tool Program Modes (MDS mode tool or Programming tool).
Sector 511
(128 byte)
Sector 510
(128 byte)
FFFFH
FF7FH
FEFFH
3FFFH
Sector 127
(128 byte)
3F7FH
05FFH
Sector 11
(128 byte)
Sector 10
(128 byte)
Sector 0-9
(128 byte x 10)
Figure 21-6
057FH
0500H
04FFH
0000H
Sector Configurations in User Program Mode
The Sector Erase Procedure in User Program Mode
1. If the procedure of Sector Erase needs to be stopped by any interrupt, set the appropriately bit of Interrupt
ask Enable Register (IMR) and the appropriately peripheral interrupt enable bit. Otherwise clear all bits of
nterrupt Mask Enable Register (IMR) and all peripheral interrupt enable bits.
2. Set Flash Memory User Programming Enable Register (FMUSR) to "10100101B".
3. Set Flash Memory Sector Address Register (FMSECH/ FMSECL).
4. Check user's ID code (written by user)
5. Set Flash Memory Control Register (FMCON) to "10100001B".
6. Set Flash Memory User Programming Enable Register (FMUSR) to "00000000B".
7. Check the "Sector erase status bit" whether "Sector erase" is success or not.
PS032408-0220
PRELIMINARY
21-8
S3F8S6B Product Specification
Example 21-1
Chapter 21. Embedded Flash Memory Interface
Sector Erase
•
•
SB0
reErase:
LD
FMUSR,Temp0
; User Program mode enable
; Temp0 = #0A5H
; Temp0 variable is must be setting another routine
LD
FMSECH,#10H
LD
FMSECL,#00H
; Set sector address (1000H–107FH)
CP
UserID_Code,#User_value
; Check user's ID code (written by user)
JR
NE,Not_ID_Code
; If not equal, jump to Not_ID_Code
LD
FMCON,Temp1
; Start sector erase
; User_value is any value by user
; Temp1 = #0A1H
; Temp1 variable is must be setting another routine
; Dummy Instruction, This instruction must be
needed
NOP
NOP
; Dummy Instruction, This instruction must be
needed
LD
TM
FMUSR,#0
FMCON,#00001000B
; User Program mode disable
; Check "Sector erase status bit"
JR
NZ,reErase
; Jump to reErase if fail
LD
FMUSR,#0
; User Program mode disable
LD
FMCON,#0
; Sector erase mode disable
•
•
•
Not_ID_Code:
SB0
•
•
•
NOTE: In case of Flash User Mode, the Tmep0 to Temp1's data values are must be setting another routine.
Temp0 to Temp (n) variables are should be defined by user.
PS032408-0220
PRELIMINARY
21-9
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.5 Programming
A Flash memory is programmed in one byte unit after sector erase. And for programming safety's sake, must set
FMSECH and FMSECL to Flash memory sector value.
The write operation of programming starts by "LDC" instruction.
You can write until 128 byte, because this Flash sector's limit is 128 byte.
So, if you written 128 byte, must reset FMSECH and FMSECL.
The Program Procedure in User Program Mode
1. Must erase sector before programming.
2. Set Flash Memory User Programming Enable Register (FMUSR) to "10100101B".
3. Set Flash Memory Sector Register (FMSECH, FMSECL) to sector value of write address.
4. Load a Flash memory upper address into upper register of pair working register.
5. Load a Flash memory lower address into lower register of pair working register.
6. Load a transmission data into a working register.
7. Check user's ID code (written by user)
8. Set Flash Memory Control Register (FMCON) to "01010001B".
9. Load transmission data to Flash memory location area on 'LDC' instruction by indirectly addressing mode
10. Set Flash Memory User Programming Enable Register (FMUSR) to "00000000B".
PS032408-0220
PRELIMINARY
21-10
S3F8S6B Product Specification
Example 21-2
Chapter 21. Embedded Flash Memory Interface
Programming
•
•
SB0
LD
FMUSR,Temp0
; User Program mode enable
; Temp0 = #0A5H
; Temp0 variable is must be setting another routine
LD
FMSECH,#17H
LD
FMSECL,#80H
; Set sector address (1780H-17FFH)
LD
R2,#17H
; Set a ROM address in the same sector 1780H–17FFH
LD
R3,#84H
LD
R4,#78H
; Temporary data
CP
UserID_Code,#User_value
; Check user's ID code (written by user)
; User_value is any value by user
JR
NE,Not_ID_Code
; If not equal, jump to Not_ID_Code
LD
FMCON,Temp1
; Start program
; Temp1 = #51H
; Temp1 variable is must be setting another routine
LDC
NOP
@RR2,R4
; Write the data to a address of same sector(1784H)
; Dummy Instruction, This instruction must be
needed
LD
FMUSR,#0
; User Program mode disable
LD
FMUSR,#0
; User Program mode disable
LD
FMCON,#0
; Programming mode disable
•
•
•
•
Not_ID_Code:
SB0
•
•
•
•
NOTE: In case of Flash User Mode, the Tmep0 to Temp1's data values are must be setting another routine.
Temp0 to Temp(n) variables are should be defined by user.
PS032408-0220
PRELIMINARY
21-11
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.6 Reading
The read operation of programming starts by "LDC" instruction.
The Reading Procedure in User Program Mode
1. Load a Flash memory upper address into upper register of pair working register.
2. Load a Flash memory lower address into lower register of pair working register.
3. Load receive data from Flash memory location area on "LDC' instruction by indirectly addressing mode
Example 21-3
Reading
•
•
LD
R2,#3H
; Load Flash memory upper address
; to upper of pair working register
LD
R3,#0
; Load Flash memory lower address
; to lower pair working register
LOOP: LDC
R0,@RR2
; Read data from Flash memory location
; (Between 300H and 3FFH)
INC
R3
CP
R3,#0H
JP
NZ,LOOP
•
•
•
•
PS032408-0220
PRELIMINARY
21-12
S3F8S6B Product Specification
Chapter 21. Embedded Flash Memory Interface
21.7 Hard Lock Protection
User can set Hard Lock Protection by write "0110" in FMCON.7-4. If this function is enabled, the user cannot write
or erase the data in a Flash memory area. This protection can be released by the chip erase execution (in the tool
program mode).
In terms of user program mode, the procedure of setting Hard Lock Protection is following that. Whereas in tool
mode the manufacturer of serial tool writer could support Hardware Protection. Please refer to the manual of serial
program writer tool provided by the manufacturer.
The Hard Lock Protection Procedure in User program mode
1. Set Flash Memory User Programming Enable Register (FMUSR) to "10100101B".
2. Check user's ID code (written by user)
3. Set Flash Memory Control Register (FMCON) to "01100001B".
4. Set Flash Memory User Programming Enable Register (FMUSR) to "00000000B".
PS032408-0220
PRELIMINARY
21-13
S3F8S6B Product Specification
Example 21-4
Chapter 21. Embedded Flash Memory Interface
Hard Lock Protection
•
•
SB0
LD
FMUSR,Temp0
; User Program mode enable
; Temp0 = #0A5H
; Temp0 variable is must be setting another routine
CP
UserID_Code,#User_value
; Check user's ID code (written by user)
JR
NE,Not_ID_Code
; If not equal, jump to Not_ID_Code
LD
FMCON,Temp1
; Hard Lock mode set & start
; User_value is any value by user
; Temp1 = #61H
; Temp1 variable is must be setting another routine
NOP
LD
; Dummy Instruction, This instruction must be
needed
FMUSR,#0
; User Program mode disable
LD
FMUSR,#0
; User Program mode disable
LD
FMCON,#0
; Hard Lock Protection mode disable
•
•
•
•
Not_ID_Code:
SB0
•
•
•
•
NOTE: In case of Flash User Mode, the Tmep0 to Temp1's data values are must be setting another routine.
Temp0 to Temp(n) variables are should be defined by user.
PS032408-0220
PRELIMINARY
21-14
S3F8S6B Product Specification
22
Chapter 22. Electrical Data
Electrical Data
22.1 Overview
In this chapter, S3F8S6B electrical characteristics are presented in tables and graphs.
The information is arranged in the following order:
•
Absolute maximum ratings
•
Input/output capacitance
•
D.C. electrical characteristics
•
A.C. electrical characteristics
•
Oscillation characteristics
•
Oscillation stabilization time
•
Data retention supply voltage in Stop mode
•
LVR timing characteristics
•
Serial I/O timing characteristics
•
A/D converter electrical characteristics
•
LCD capacitor bias electrical characteristics
•
UART timing characteristics
•
Internal Flash ROM electrical characteristics
•
Operating voltage range
PS032408-0220
PRELIMINARY
22-1
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.2 Absolute Maximum Ratings
Table 22.1
Absolute Maximum Ratings
(TA = 25 C)
Parameter
Supply voltage
Symbol
Conditions
VDD
–
Input voltage
VI
Output voltage
VO
Output current high
IOH
Rating
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
Ports 0-6
–
One I/O pin active
– 15
All I/O pins active
– 60
One I/O pin active
+ 30 (Peak value)
Total pin current for ports
+ 100 (Peak value)
IOL
Operating temperature
TA
–
– 40 to + 85
TSTG
–
– 65 to + 150
PS032408-0220
PRELIMINARY
V
– 0.3 to VDD + 0.3
Output current low
Storage temperature
Unit
mA
C
22-2
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.3 D.C. Electrical Characteristics
Table 22.2
D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Operating voltage
Symbol
VDD
Conditions
Min.
Typ.
Max.
fx = 0.4 – 4.2 MHz,
fxt = 32.768 kHz
1.8
–
5.5
fx = 0.4 – 12.0 MHz
2.2
–
5.5
VIH1
All input pins except VIH2
0.7 VDD
VIH2
P2, P4
0.8 VDD
VIH3
nRESET
0.8 VDD
VIH4
XIN, XOUT
VDD – 0.1
VIL1
All input pins except VIL2
VIL2
P2, P4
VIL3
nRESET
VIL4
XIN, XOUT
VOH
VDD = 4.5 V to 5.5 V
IOH = –1 mA
All output ports
VDD – 1.5
VOL1
VDD = 4.5 V to 5.5 V
IOL = 10 mA
All output ports
–
ILIH1
VIN = VDD
All input pins except ILIH2
ILIH2
VIN = VDD
XIN, XOUT, XTIN, XTOUT
ILIL1
VIN = 0 V
All input pins except for nRESET,
ILIL2
ILIL2
VIN = 0 V
XIN, XOUT, XTIN, XTOUT
Output high leakage
current
ILOH
VOUT = VDD
All output pins
–
–
3
Output low leakage
current
ILOL
VOUT = 0 V
All output pins
–
–
–3
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input high leakage
current
Input low leakage
current
PS032408-0220
Unit
VDD
–
VDD
VDD
V
VDD
0.3 VDD
–
–
0.2 VDD
0.2 VDD
0.1
PRELIMINARY
–
–
V
–
2.0
3
–
–
20
–3
–
A
–
– 20
22-3
S3F8S6B Product Specification
Chapter 22. Electrical Data
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
LCD voltage dividing
resistor
Oscillator feed back
resistors
Symbol
Conditions
40
65
90
ROSC1
VDD = 5 V, TA= 25 C
XIN = VDD, XOUT = 0 V
420
850
1700
ROSC2
VDD = 5 V, TA= 25 C
XTIN = VDD, XTOUT = 0 V
2200
4500
9000
VIN = 0 V; VDD = 5 V
Ports 0–6, TA = 25 C
25
50
100
VIN = 0 V; VDD = 3 V
Ports 0 to 6, TA = 25 C
50
100
150
VIN = 0 V; VDD = 5 V
TA = 25 C, nRESET
150
250
400
VIN = 0 V; VDD = 3 V
TA = 25 C, nRESET
300
500
700
0.75 VDD –
0.2
0.75
VDD
0.75 VDD
+ 0.2
0.50 VDD –
0.2
0.5
VDD
0.5 VDD
+ 0.2
0.25 VDD –
0.2
0.25
VDD
0.25 VDD
+ 0.2
–
–
120
RL2
VLC1
VLC2
VDD = 2.7 V to 5.5 V
LCD clock = 0 Hz, VLC0 = VDD
VLC3
|VLCD – COMi| Voltage
drop (i = 0 to 7)
VDC
|VLCD – SEGx| Voltage
drop (x = 0 to 33)
VDS
PS032408-0220
Max.
TA = 25 C
Pull-up resistor
(1)
Typ.
RLCD
RL1
Middle output voltage
Min.
– 15 A per common pin
Unit
k
V
mV
– 15 A per segment pin
PRELIMINARY
–
–
120
22-4
S3F8S6B Product Specification
Chapter 22. Electrical Data
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
IDD1 (2)
IDD2 (2)
Conditions
Run mode:
VDD = 5.0 V
Crystal oscillator
C1 = C2 = 22 pF
Min.
12.0 MHz
4.2 MHz
–
Supply current (1)
IDD5 (4)
2.2
4.0
1.2
2.0
4.2 MHz
0.8
1.5
Idle mode:
VDD = 5.0 V
Crystal oscillator
C1 = C2 = 22 pF
12.0 MHz
1.3
2.3
0.8
1.5
VDD = 3.0 V
4.2 MHz
0.4
0.8
80.0
120.0
85.0
140.0
6.0
15.0
4.2 MHz
–
Run mode:
VDD = 3.0 V, TA = 25 C
32 kHz crystal oscillator
C = 0.1 F, No panel load
Cap bias LCD on
Unit
mA
–
Sub Idle mode:
VDD = 3.0 V, TA = 25 C
32 kHz crystal oscillator
IDD4 (3)
Max.
VDD = 3.0V
Sub Operating mode:
VDD = 3.0 V, TA = 25 C
32 kHz crystal oscillator
IDD3 (3)
Typ.
Idle mode:
VDD = 3.0 V, TA = 25C
32 kHz crystal oscillator
C = 0.1 F, No panel load
Cap bias LCD on
–
Stop mode: VDD = 5.0 V, TA =
25C
A
10.0
20.0
–
0.3
3.0
Stop mode: VDD = 5.0 V, TA =
+85C
–
3.0
8.0
Stop mode: VDD = 5.0 V, TA = -40
to +85C
–
–
8.0
NOTE: It is middle output voltage when the VDD and VLC0 pin are connected.
1.
Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, the
LVR block, and external output current loads.
2.
IDD1 and IDD2 include a power consumption of sub clock oscillation.
3.
IDD3 and IDD4 are the current when the main clock oscillation stops and the sub clock is used.
4.
IDD5 is the current when the main and sub clock oscillation stops.
5.
Every value in this table is measured when bits 4-3 of the system clock control register (CLKCON.4–.3) is set to 11B.
PS032408-0220
PRELIMINARY
22-5
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.4 A.C. Electrical Characteristics
Table 22.3
A.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Interrupt input high, low
width (P2, P4)
tINTH, tINTL
nRESET input low width
tRSL
Conditions
Min.
Typ.
Max.
Unit
All interrupt, VDD = 5 V
500
–
–
ns
Input, VDD = 5 V
10
–
–
s
NOTE: If width of interrupt or reset pulse is greater than min. value, pulse is always recognized as valid pulse.
tINTL
tINTH
External
Interrupt
0.8 VDD
0.2 VDD
Figure 22-1
Input Timing for External Interrupts
tRSL
nRESET
0.2 VDD
Figure 22-2
PS032408-0220
Input Timing for nRESET
PRELIMINARY
22-6
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.5 Input/Output Capacitance
Table 22.4
Input/Output Capacitance
(TA = – 40 C to + 85 C, VDD = 0 V )
Parameter
Symbol
Input
capacitance
CIN
Output
capacitance
COUT
I/O capacitance
Conditions
Min.
Typ.
Max.
Unit
f = 1 MHz; unmeasured pins
are returned to VSS
–
–
10
pF
CIO
22.6 Data Retention Supply Voltage in Stop Mode
Table 22.5
Data Retention Supply Voltage in Stop Mode
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Data retention
supply voltage
VDDDR
–
1.8
–
5.5
V
Data retention
supply current
IDDDR
–
–
1
A
PS032408-0220
Stop mode, TA = 25 C
VDDDR = 1.8V
Disable LVR block
PRELIMINARY
22-7
S3F8S6B Product Specification
Chapter 22. Electrical Data
~
~
nRESET
Occurs Oscillation
Stabilization
Time
Normal
Operating Mode
Stop Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instrction
nRESET
0.8 VDD
0.2 VDD
NOTE:
tWAIT
tWAIT is the same as 4096 x 16 x 1/fxx.
Figure 22-3
Stop Mode Release Timing Initiated by nRESET
VDD
~
~
~
~
Oscillation
Stabillization TIme
IDLE Mode
Stop Mode
Data Retention Mode
VDDDR
Normal
Operation Mode
Execution of
STOP Instruction
Interrupt
0.2VDD
tWAIT
NOTE:
tWAIT is the same as 16 x 1/fBT. (fBT is basic timer clock selected)
Figure 22-4
PS032408-0220
Stop Mode Release Timing Initiated by Interrupts
PRELIMINARY
22-8
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.7 A/D Converter Electrical Characteristics
Table 22.6
A/D Converter Electrical Characteristics
(TA = – 25 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Resolution
–
–
–
10
–
bit
Total accuracy
–
–
–
3
–
2
–
1
Integral linearity error
ILE
AVREF = 5.12 V
VSS = 0 V
CPU clock = 12.0 MHz
Differential linearity
error
DLE
Offset error of top
EOT
1
3
Offset error of bottom
EOB
1
3
–
LSB
TCON
–
25
–
–
S
Analog input voltage
VIAN
–
AVSS
–
AVREF
V
Analog input
impedance
RAN
–
2
–
–
M
Analog reference
voltage
AVREF
–
1.8
–
VDD
Analog ground
AVSS
–
VSS
–
VSS + 0.3
Analog input current
IADIN
–
–
10
A
0.5
1.5
mA
100
500
nA
Conversion time
(1)
VDD = 5.0 V
VDD = 5.0 V
Analog block current
(2)
IADC
VDD = 5.0 V
When power down mode
–
V
NOTE:
1.
"Conversion time" is the time required from the moment a conversion operation starts until it ends.
2.
IADC is an operating current during A/D converter.
PS032408-0220
PRELIMINARY
22-9
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.8 Low Voltage Reset Electrical Characteristics
Table 22.7
Low Voltage Reset Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Voltage of LVR
Symbol
VLVR
Test Condition
TA = 25 C
Min.
Typ.
Max.
1.8
1.9
2.0
2.0
2.2
2.4
Unit
V
tR
–
10
–
–
S
VDD voltage off time
tOFF
–
0.5
–
–
S
Hysteresis
V
–
–
50
150
mV
Current consumption
ILVR
–
30
60
A
VDD voltage rising time
VDD = 3.0 V
NOTE: The current of LVR circuit is consumed when LVR is enabled by "Smart Option".
tOFF
tR
0.9VDD
VDD
0.1VDD
Figure 22-5
PS032408-0220
LVR (Low Voltage Reset) Timing
PRELIMINARY
22-10
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.9 Synchronous SIO Electrical Characteristics
Table 22.8
Synchronous SIO Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
SCK Cycle time
tKCY
SCK high, low width
tKH, tKL
SI setup time to SCK high
tSIK
SI hold time to SCK high
tKSI
Output delay for SCK to SO
tKSO
Conditions
Min.
External SCK source
1,000
Internal SCK source
1,000
External SCK source
500
Internal SCK source
Typ.
tKCY/2-50
External SCK source
250
Internal SCK source
250
External SCK source
400
Internal SCK source
400
External SCK source
Unit
–
–
ns
300
–
Internal SCK source
Max.
250
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
SI
Input Data
0.2 VDD
tKSO
SO
Output Data
Figure 22-6
PS032408-0220
Serial Data Transfer Timing
PRELIMINARY
22-11
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.10 UART Timing Characteristics
Table 22.9
UART Timing Characteristics in Mode 0 (12.0 MHz)
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V, Load Capacitance = 80 pF)
Parameter
Symbol
Min.
Typ.
Max.
Serial port clock cycle time
tSCK
1,160
tCPU 16
1,500
Output data setup to clock rising edge
tS1
500
tCPU 13
–
Clock rising edge to input data valid
tS2
–
–
500
Output data hold after clock rising edge
tH1
tCPU – 50
tCPU
–
Input data hold after clock rising edge
tH2
0
–
–
Serial port clock High, Low level width
tHIGH, tLOW
450
tCPU
8
Unit
ns
890
NOTE:
1.
All timings are in nanoseconds (ns) and assume a 12.0-MHz CPU clock frequency.
2.
The unit tCPU means one UART clock period.
tHIGH
tSCK
tLOW
0.7VDD
0.3VDD
Figure 22-7
PS032408-0220
Waveform for UART Timing Characteristics
PRELIMINARY
22-12
S3F8S6B Product Specification
Chapter 22. Electrical Data
tSCK
Shift
Clock
tH1
Data
Out
tS1
D0
D1
tS2
Data
In
Valid
D4
D5
D6
D7
Valid
Valid
Valid
Valid
Valid
Valid
The symbols shown in this diagram are defined as follows:
fSCK
tS1
tS2
tH1
tH2
Figure 22-8
PS032408-0220
D3
tH2
Valid
NOTE:
D2
Serial port clock cycle time
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge
Timing Waveform for the UART Module
PRELIMINARY
22-13
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.11 LCD Capacitor Bias Electrical Characteristics
Table 22.10
LCD Capacitor Bias Electrical Characteristics (Normal and Idle Mode)
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
VLC3
VLC3
Conditions
Connect a 1㏁ load
resistance between
VLC3 and VSS
VDD = 2.0V to 5.5V
(No panel load)
1/4 Bias
1/3 Bias
Liquid crystal
drive voltage
VLC3
1/2 Bias
Min.
Typ.
LMOD.2-.0 = 0
0.90
LMOD.2-.0 = 1
0.95
LMOD.2-.0 = 2
1.00
LMOD.2-.0 = 3
LMOD.2-.0 = 4
Typ.×0.85
1.05
1.10
LMOD.2-.0 = 5
1.15
LMOD.2-.0 = 6
1.20
LMOD.2-.0 = 7
1.25
LMOD.2-.0 = 0
1.05
LMOD.2-.0 = 1
1.125
LMOD.2-.0 = 2
1.20
LMOD.2-.0 = 3
Typ.×0.85
1.275
LMOD.2-.0 = 4
1.350*
LMOD.2-.0 = 5
1.425*
LMOD.2-.0 = 6
1.50*
LMOD.2-.0 = 0
1.10
LMOD.2-.0 = 1
1.20
LMOD.2-.0 = 2
Typ.×0.85
1.30*
LMOD.2-.0 = 3
1.40*
LMOD.2-.0 = 4
1.50*
Max.
Unit
Typ.×1.15
Typ.×1.15
V
Typ.×1.15
VLC2
Connect a 1 M load resistance
between VLC2 and VSS (No panel load)
2×VLC3×0.9
–
2×VLC3×1.1
VLC1
Connect a 1 M load resistance
between VLC1 and VSS (No panel load)
3×VLC3×0.9
–
3×VLC3×1.1
VLC0
Connect a 1 M load resistance
between VLC0 and VSS (No panel load)
4×VLC3×0.9
–
4×VLC3×1.1
NOTE: It is characteristics when a 1 M load resistance is connected to only a selected symbol (VLC0 - VLC3) node at VDD =
2.0 V to 5.5 V. The value of VLCN (N = 0 to 2) is determined by VLC3 that is measured.
* Unsupported modes for Sub Idle and Stop mode operation.
PS032408-0220
PRELIMINARY
22-14
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.12 Main Oscillator Characteristics
Table 22.11
Main Oscillator Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock Configuration
Parameter
C1
Test Condition
Min.
Typ.
Max.
2.2 V – 5.5 V
0.4
–
12.0
1.8 V – 5.5 V
0.4
–
4.2
2.2 V – 5.5 V
0.4
–
12.0
1.8 V – 5.5 V
0.4
–
4.2
2.2 V – 5.5 V
0.4
–
12.0
1.8 V – 5.5 V
0.4
–
4.2
5.0V
0.4
–
2
Units
XIN
Crystal
XOUT
Main oscillation
frequency
C1
XIN
Ceramic
Oscillator
XOUT
Main oscillation
frequency
MHz
XIN
External
Clock
XIN input frequency
XOUT
XIN
RC
Oscillator
Frequency
R
XOUT
PS032408-0220
MHz
3.0V
PRELIMINARY
0.4
–
1
22-15
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.13 Sub Oscillation Characteristics
Table 22.12
Sub Oscillation Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock Configuration
Parameter
Test Condition
Min.
Typ.
Max.
Units
Sub oscillation
frequency
1.8 V – 5.5 V
–
32.7
68
–
kHz
XTIN input
frequency
1.8 V – 5.5 V
32
–
100
C1
XTIN
Crystal
C2
XTOUT
XTIN
External
clock
PS032408-0220
XTOUT
PRELIMINARY
22-16
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.14 Main Oscillation Stabilization Time
Table 22.13
Main Oscillation Stabilization Time
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Test Condition
Ceramic
fx > 1 MHz
Oscillation stabilization occurs when VDD is equal
to the minimum oscillator voltage range.
External clock
XIN input high and low width (tXH, tXL)
Crystal
Min.
Typ.
Max.
–
–
40
–
–
10
62.5
–
1250
Unit
ms
ns
1/fx
tXL
tXH
XIN
VDD - 0.1V
0.1V
Figure 22-9
PS032408-0220
0.1V
Clock Timing Measurement at XIN
PRELIMINARY
22-17
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.15 Sub Oscillation Stabilization Time
Table 22.14
Sub Oscillation Stabilization Time
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Test Condition
Min.
Typ.
Max.
Unit
–
–
–
10
s
5
–
15
s
Crystal
External clock
XTIN input high and low width (tXTH, tXTL)
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1V
0.1V
Figure 22-10
PS032408-0220
0.1V
Clock Timing Measurement at XTIN
PRELIMINARY
22-18
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.16 Operating Voltage Range
Instruction Clock
Main oscillation frequency
3.0MHz
12.0 MHz
1.05 MHz
4.2 MHz
0.5 MHz
2.0 MHz
100 kHz
400 kHz
3
1.8V
4
5
2.2V
5.5V
Supply Voltage (V)
CPU Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 22-11
PS032408-0220
Operating Voltage Range
PRELIMINARY
22-19
S3F8S6B Product Specification
Chapter 22. Electrical Data
22.17 Internal Flash ROM Electrical Characteristics
Table 22.15
Internal Flash ROM Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Programming time (1)
Chip erasing Time
(2)
Sector erasing Time (3)
Read frequency
Number of writing/erasing
Conditions
Ftp
Ftp1
–
Min.
Typ.
Max.
Unit
20
25
30
s
32
50
70
4
8
12
ms
ms
Ftp2
fR
–
–
–
12
MHz
FNWE
–
10,000 (4)
–
–
Times
NOTE:
1.
The Programming time is the time during which one byte (8-bit) is programmed.
2.
The Chip erasing time is the time during which all 64KB block is erased.
3.
The Sector erasing time is the time during which all 128 byte block is erased.
4.
The Chip erasing is available in Tool Program Mode only.
PS032408-0220
PRELIMINARY
22-20
S3F8S6B Product Specification
23
Chapter 23. Mechanical Data
Mechanical Data
23.1 Overview
The S3F8S6B microcontroller is currently available in 64-pin-QFP/LQFP/SDIP package.
23.90 0.30
0-8
20.00 0.20
+ 0.10
14.00 0.20
0.10 MAX
64-QFP-1420F
0.80 0.20
17.90 0.30
0.15 - 0.05
#64
#1
1.00
+ 0.10
0.40 - 0.05
0.15 MAX
0.05 MIN
(1.00)
2.65 0.10
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 23-1
PS032408-0220
Package Dimensions (64-QFP-1420F)
PRELIMINARY
23-1
S3F8S6B Product Specification
Figure 23-2
PS032408-0220
Chapter 23. Mechanical Data
Package Dimensions (64-LQFP-1010)
PRELIMINARY
23-2
S3F8S6B Product Specification
#33
0-15
0.2
5
64-SDIP-750
+0
- 0 .1
.05
19.05
17.00 ± 0.2
#64
Chapter 23. Mechanical Data
0.45± 0.1
(1.34)
NOTE:
Dimensions are in millimeters.
Figure 23-3
PS032408-0220
1.778
1.00 ± 0.1
5.08 MAX
57.80 ± 0.2
3.30 ± 0.3
58.20 MAX
4.10 ± 0.2
#32
0.51 MIN
#1
Package Dimensions (64-SDIP-750)
PRELIMINARY
23-3
S3F8S6B Product Specification
24
Chapter 24. S3F8S6B Flash MCU
S3F8S6B Flash MCU
24.1 Overview
The S3F8S6B single-chip CMOS microcontroller is the Flash MCU. It has an on-chip Flash MCU ROM. The Flash
ROM is accessed by serial data format.
NOTE: This chapter is about the Tool Program Mode of Flash MCU. If you want to know the User Program Mode, refer to the
chapter 21. Embedded Flash Memory Interface.
PS032408-0220
PRELIMINARY
24-1
S3F8S6B Product Specification
Chapter 24. S3F8S6B Flash MCU
24.2 Pin Assignments
P2.2/INT2/SEG14
P2.1/INT1/SEG13
P2.0/INT0/SEG12
P1.7/TACLK/SEG11
P1.6/TAOUT/TAPWM/TACAP/SEG10
P1.5/TXD1/SEG9
P1.4/RXD1/SEG8
P1.3/TXD0/SEG7
P1.2/RXD0/SEG6
P1.1
P1.0
AVSS
AVREF
52
53
54
55
56
57
58
59
60
61
62
63
64
P4.7/INT15/AD7
P4.6/INT14/AD6
P4.5/INT13/AD5
P4.4/INT12/AD4
P4.3/INT11/AD3
P4.2/INT10/AD2
P4.1/INT9/AD1
P4.0/INT8/AD0
VDD
VSS1
XOUT
XIN
TEST
P5.7/XTIN
P5.6/XTOUT
nRESET
P5.5/CB
P5.4/CA
P5.3/VLC3
1
2
3
4
5
6
7 (SDAT)
8 (SCLK)
9
10
(64-QFP-1420F)
11
12
13
14
15
16
17
18
19
S3F8S6B
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG15/INT3/P2.3
SEG16/INT4/P2.4
SEG17/INT5/P2.5
SEG18/INT6/P2.6
SEG19/INT7/P2.7
SEG20/TBPWM/PG0/P3.0
SEG21/TCOUT/TCPWM/PG1/P3.1
SEG22/PG2/P3.2
SEG23/TD0OUT/TD0PWM/TD0CAP/PG3/P3.3
IVCREF
VSS2
SEG24/TD0CLK/PG4/P3.4
SEG25/TD1OUT/TD1PWM/TD1CAP/PG5/P3.5
SEG26/TD1CLK/PG6/P3.6
SEG27/BUZ/PG7/P3.7
SEG28/SCK/P6.0
SEG29/SI/P6.1
SEG30/SO/P6.2
SEG31/P6.3
32
31
30
29
28
27
26
25
24
23
22
21
20
SEG32/P6.4
SEG33/P6.5
COM0/P0.0
COM1/P0.1
COM2/SEG0/P0.2
COM3/SEG1/P0.3
COM4/SEG2/P0.4
COM5/SEG3/P0.5
COM6/SEG4/P0.6
COM7/SEG5/P0.7
VLC0/P5.0
VLC1/P5.1
VLC2/P5.2
Figure 24-1
PS032408-0220
S3F8S6B Pin Assignments (64-QFP-1420F)
PRELIMINARY
24-1
S3F8S6B Product Specification
Chapter 24. S3F8S6B Flash MCU
P2.5/INT5/SEG17
P2.4/INT4/SEG16
P2.3/INT3/SEG15
P2.2/INT2/SEG14
P2.1/INT1/SEG13
P2.0/INT0/SEG12
P1.7/TACLK/SEG11
P1.6/TAOUT/TAPWM/TACAP/SEG10
P1.5/TXD1/SEG9
P1.4/RXD1/SEG8
P1.3/TXD0/SEG7
P1.2/RXD0/SEG6
P1.1
P1.0
AVSS
AVREF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P4.7/INT15/AD7
P4.6/INT14/AD6
P4.5/INT13/AD5
P4.4/INT12/AD4
P4.3/INT11/AD3
P4.2/INT10/AD2
P4.1/INT9/AD1
P4.0/INT8/AD0
VDD
VSS1
XOUT
XIN
TEST
P5.7/XTIN
P5.6/XTOUT
nRESET
1
2
3
4
5
6
7 (SDAT)
8 (SCLK)
9
10
11
12
13
14
15
16
S3F8S6B
64-LQFP-1010
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P2.6/INT6/SEG18
P2.7/INT7/SEG19
P3.0/PG0/TBPWM/SEG20
P3.1/PG1/TCOUT/TCPWM/SEG21
P3.2/PG2/SEG22
P3.3/PG3/TD0OUT/TD0PWM/TD0CAP/SEG23
IVCREF
VSS2
P3.4/PG4/TD0CLK/SEG24
P3.5/PG5/TD1OUT/TD1PWM/TD1CAP/SEG25
P3.6/PG6/TD1CLK/SEG26
P3.7/PG7/BUZ/SEG27
P6.0/SCK/SEG28
P6.1/SI/SEG29
P6.2/SO/SEG30
P6.3/SEG31
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P6.4/SEG32
P6.5/SEG33
P0.0/COM0
P0.1/COM1
P0.2/COM2/SEG0
P0.3/COM3/SEG1
P0.4/COM4/SEG2
P0.5/COM5/SEG3
P0.6/COM6/SEG4
P0.7/COM7/SEG5
P5.0/VLC0
P5.1/VLC1
P5.2/VLC2
P5.3/VLC3
P5.4/CA
P5.5/CB
Figure 24-2
PS032408-0220
S3F8S6B Pin Assignments (64-LQFP-1010)
PRELIMINARY
24-2
S3F8S6B Product Specification
P1.4/RXD1/SEG8
P1.3/TXD0/SEG7
P1.2/RXD0/SEG6
P1.1
P1.0
AVSS
AVREF
P4.7/INT15/AD7
P4.6/INT14/AD6
P4.5/INT13/AD5
P4.4/INT12/AD4
P4.3/INT11/AD3
P4.2/INT10/AD2
P4.1/INT9/AD1
P4.0/INT8/AD0
VDD
VSS1
XOUT
XIN
TEST
P5.7/XTIN
P5.6/XTOUT
nRESET
P5.5/CB
P5.4/CA
P5.3/VLC3
P5.2/VLC2
P5.1/VLC1
P5.0/VLC0
P0.7/SEG5/COM7
P0.6/SEG4/COM6
P0.5/SEG3/COM5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Figure 24-3
PS032408-0220
S3F8S6B
(64-SDIP-750)
Chapter 24. S3F8S6B Flash MCU
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
38
38
37
36
35
34
33
SEG9/TXD1/P1.5
SEG10/TAOUT/TAPWM/TACAP/P1.6
SEG11/TACLK/P1.7
SEG12/INT0/P2.0
SEG13/INT1/P2.1
SEG14/INT2/P2.2
SEG15/INT3/P2.3
SEG16/INT4/P2.4
SEG17/INT5/P2.5
SEG18/INT6/P2.6
SEG19/INT7/P2.7
SEG20/TBPWM/PG0/P3.0
SEG21/TCOUT/TCPWM/PG1/P3.1
SEG22/PG2/P3.2
SEG23/TD0OUT/TD0PWM/TD0CAP/PG3/P3.3
IVCREF
VSS2
SEG24/TD0CLK/PG4/P3.4
SEG25/TD1OUT/TD1PWM/TD1CAP/PG5/P3.5
SEG26/TD1CLK/PG6/P3.6
SEG27/BUZ/PG7/P3.7
SEG28/SCK/P6.0
SEG29/SI/P6.1
SEG30/SO/P6.2
SEG31/P6.3
SEG32P6.4
SEG33/P6.5
COM0/P0.0
COM1/P0.1
COM2/SEG0/P0.2
COM3/SEG1/P0.3
COM4/SEG2/P0.4
S3F8S6B Pin Assignments (64-SDIP-750)
PRELIMINARY
24-3
S3F8S6B Product Specification
Table 24.1
Chapter 24. S3F8S6B Flash MCU
Descriptions of Pins Used to Read/Write the Flash ROM
During Programming
Main Chip
Pin Name
Pin Name
Pin No.
I/O
Function
P4.1
SDAT
7(14)
I/O
Serial data pin. Output port when reading and input port
when writing. Can be assigned as a Input/push-pull output
port.
P4.0
SCLK
8(15)
I/O
Serial clock pin. Input only pin.
TEST
VPP
13(20)
I
Tool mode selection when TEST/ VPP pin sets Logic value
"1". If user uses the Flash writer tool mode (ex.spw2+
etc..), user should be connected
TEST/VPP pin to VDD. (S3F8S6B supplies high voltage
12.5V by internal high voltage generation circuit.)
nRESET
nRESET
16(23)
I
Chip Initialization
IVCREF
IVCREF
42(49)
–
A capacitor (0.1 F) must be connected between IVCREF
and VSS.
VDD, VSS1
VDD, VSS
9(16),
10(17)
–
Power supply pin for logic circuit. VDD should be tied to 5V
during programming.
NOTE: Parentheses indicate pin number for 64-SDIP-750 package.
Test Pin Voltage
The TEST pin on socket board for MTP writer must be connected to VDD (5.0V) with RC delay as the figure 24-3
(only when SPW 2+ and GW-pro2 are used to). The TEST pin on socket board must not be connected Vpp
(12.5V) which is generated from MTP Writer. So the specific socket board for S3F8S6B must be used, when
writing or erasing using MTP writer.
VDD
R (330Ω)
VPP
C (0.1uF)
Figure 24-4
PS032408-0220
RC Delay Circuit
PRELIMINARY
24-4
S3F8S6B Product Specification
Chapter 24. S3F8S6B Flash MCU
24.3 On Board Writing
The S3F8S6B needs only 6 signal lines including VDD and GND pins for writing internal Flash memory with serial
protocol. Therefore the on-board writing is possible if the writing signal lines are considered when the PCB of
application board is designed.
24.3.1 Circuit Design Guide
At the Flash writing, the writing tool needs 6 signal lines that are GND, VDD, nRESET, TEST, SDAT and SCLK.
When you design the PCB circuits, you should consider the usage of these signal lines for the on-board writing.
In case of TEST pin, normally test pin is connected to GND but in writing mode the programming these two cases,
a resistor should be inserted between the TEST pin and GND. The nRESET, SDAT and SCLK should be treated
under the same consideration.
Please be careful to design the related circuit of these signal pins because rising/falling timing of VPP, SCLK and
SDAT is very important for proper programming.
R
SCLK
To Application circuit
SCLK(I/O)
R
SDAT
SDAT(I/O)
To Application circuit
R
nRESET
nRESET
To Application circuit
R
VPP
VPP(TEST)
C VPP
C nRESET
VDD
VPP
SDAT
VSS
VDD
nRESET
SCLK
C nRESET and C VPP are used to
improve the noise effect.
GND
IVCREF
0.1uF
C
SPW-uni , GW-uni , AS-pro, US-pro
Figure 24-5
PCB Design Guide for on Board Programming
NOTE: If writer tool is the SPW 2+ and GW-pro2, reference to the page 24-4.
PS032408-0220
PRELIMINARY
24-5
S3F8S6B Product Specification
Chapter 24. S3F8S6B Flash MCU
24.3.2 Reference Table for Connection
Table 24.2
Reference Table for Connection
Pin Name
I/O mode
in Applications
Resistor
(Need)
Required value
VPP (TEST)
Input
Yes
RVpp is 10 k to 50 k.
CVpp is 0.01 F to 0.02 F.
nRESET
Input
Yes
RnRESET is 2 k to 5 k.
CnRESET is 0.01 F to 0.02 F.
Input
Yes
RSDAT is 2 k to 5 k.
Output
No (NOTE)
–
Input
Yes
RSCLK is 2 k to 5 k.
SDAT (I/O)
SCLK (I/O)
Output
No
(NOTE)
–
NOTE:
1.
In on-board writing mode, very high-speed signal will be provided to pin SCLK and SDAT. And it will cause some damages
to the application circuits connected to SCLK or SDAT port if the application circuit is designed as high speed response
such as relay control circuit. If possible, the I/O configuration of SDAT, SCLK pins had better be set to input mode.
2.
The value of R, C in this table is recommended value. It varies with circuit of system.
PS032408-0220
PRELIMINARY
24-6
S3F8S6B Product Specification
25
Chapter 25. Development Tools
Development Tools
25.1 Overview
Zilog provides a powerful and easy-to-use development support system on a turnkey basis. This development
support system is composed of a host system, debugging tools, and supporting software. Any standard computer
running Windows 7 (32-/64-bit), Windows Vista (32-/64-bit), and Windows XP operating systems can be used as a
host
A sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator,
OPENice-i500 and SK-1200, for the S3C7-, S3C9- and S3C8- microcontroller families. Zilog also offers supporting
software that includes, debugger, an assembler, and a program for setting options.
25.1.1 Target Boards
Target boards are available for all the S3C8/S3F8-series microcontrollers. All the required target system cables
and adapters are included on the device-specific target board. TB8S6B is a specific target board for the
development of application systems using S3F8S6B.
25.1.2 Programming Socket Adapter
When you program S3F8S6B's Flash memory by using an emulator or OTP/MTP writer, you need a specific
programming socket adapter for S3F8S6B.
PS032408-0220
PRELIMINARY
25-1
S3F8S6B Product Specification
Chapter 25. Development Tools
IBM-PC AT or Compatible
Emulator [SK-1200 (RS-232, USB), OPENice i-500 (RS-232)
or OPENIce I-2000(RS-232,USB)]
RS-232C/USB
Target
Application
System
OTP/MTP Writer Block
RAM Break/Display Block
BUS
Probe
Adapter
Trace/Timer Block
SAM8 Base Block
POD
TB8S6B
Target
Board
EVAChip
Power Supply Block
Figure 25-1
PS032408-0220
Emulator Product Configuration
PRELIMINARY
25-2
S3F8S6B Product Specification
Chapter 25. Development Tools
25.2 TB8S6B Target Board
The TB8S6B target board can be used for development of the S3F8S6B microcontroller.
The TB8S6B target board is operated as target CPU with Emulator (SK-1200, OPENice-i500/2000)).
IDLE
P5.6
P5.7
2
P5.6/XTOUT
VDD
AVREF
VCC
CN3
50
1
60
200
208 QFP
S3E8S60
EVA Chip
CN1
TB Mode Selection
Main Mode
31
SW1
Figure 25-2
6
7
8
1
2
3
4
5
6
7
8
B13
B14
B15
5
B11
B12
4
32
63
VDD
34
64
SW2 Smart Option Source
External
B9
B10
3
B8
2
33
150
Smart Option
B5
B6
B7
1
B0
"1"
110
ON
B1
B2
"0"
2
160
100
Eva Mode
CN4
J102
1
4
1
J101
JP2
X4
(sub-clock)
SW6
1
P5.7/XTIN
100-Pin Connector
100-Pin Connector
J1
+
+
ON
STOP
GND
7411
40-Pin Connector
U2
On Board writing
40-Pin Connector
RESET
CN52
On
CN10
Off
SCLK
SDAT
VPP
VDD
VSS
nRESET
TB8S6B
To User_VCC
CN9
In-Circuit
Emulator
(SK-1200,
OPENicei500/2000)
Internal
CN5
TB8S6B Target Board Configuration
NOTE: The symbol " " marks start point of jumper signals.
PS032408-0220
PRELIMINARY
25-3
S3F8S6B Product Specification
Table 25.1
Symbols
Chapter 25. Development Tools
Components of TB8S6B
Usage
Description
CN1
100-pin connector
Connection between emulator and TB8S6B target board.
J101, J102
40-pin connector
Connection between target board and user application
system
RESET
Push button
Generation low active reset signal to S3E8S60 EVA-chip
VCC, GND
POWER connector
External power connector for TB8S6B
STOP, IDLE LED
STOP/IDLE Display
Indicate the status of STOP or IDLE of S3E8S60 EVA-chip
on TB8S6B target board
Table 25.2
JP#
CN3
Description
Setting of the Jumper in TB8S6B
1-2 Connection
2-3 Connection
AVREF power source
VDD
JP2
Clock source selection
When using the internal clock source which is generated from
Emulator, join connector 2-3 and 4-5 pin. If user wants to use
the external clock source like a crystal, user should change
the jumper setting from 1-2 to 5-6 and connect J1 to an
external clock source.
J1
External clock source
Connecting points for external clock source
CN4
Target board mode
selection
MAIN-Mode
EVA-Mode
Join 2-3
CN5
Smart option source
selection
The Smart Option is
selected by external smart
option switch (SW1&SW2)
The Smart Option is selected
by internal smart option area
(003EH–0003FH of ROM). But
this selection is not available.
Join 1-2
Smart option selection
The Smart Option can be selected by this switch when the
Smart Option source is selected by external. The B7–B0 are
comparable to the 003EH.7–.0. The B15–B8 are comparable
to the 003FH.7–.0. Refer to the page 2-3.
SW1,
SW2
CN9
CN10
To
User_Vcc
LCD bias
Target System is
supplied VDD
User power
Default
Setting
Emulator
2-3
4-5
Need capacitors When capacitor bias mode
Need resistors When external resistor bias mode
Target Board is supplied
VDD from user System.
Target Board is not supplied
VDD from user System.
•
IDLE LED
This is LED is ON when the evaluation chip (S3E8S60) is in Idle mode.
•
STOP LED
This LED is ON when the evaluation chip (S3E8S60) is in Stop mode.
PS032408-0220
Join 1-2
PRELIMINARY
Join 1-2
25-4
S3F8S6B Product Specification
Chapter 25. Development Tools
J101
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
40-Pin DIP Connector
P4.7/INT15/AD7
P4.5/INT13/AD5
P4.3/INT11/AD3
P4.1/INT9/AD1
VDD
N.C
N.C
P5.6/XTOUT
P5.5/CB
P5.3/VLC3
P5.1/VLC1
P0.7/SEG5/COM7
P0.5/SEG3/COM5
P0.3/SEG1/COM3
P0.1/COM1
P6.5/SEG33
N.C
N.C
N.C
N.C
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
P4.6/INT14/AD6
P4.4/INT12/AD4
P4.2/INT10/AD2
P4.0/INT8/AD0
VSS1
N.C
P5.7/XTIN
nRESET
P5.4/CA
P5.2/VLC2
P5.0/VLC0
P0.6/SEG4/COM6
P0.4/SEG2/COM4
P0.2/SEG0/COM2
P0.0/COM0
P6.4/SEG32
N.C
N.C
N.C
N.C
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
P6.2/SO/SEG30
P6.0/SCK/SEG28
P3.6/TD1CLK/PG6/SEG26
P3.4/TD0CLK/PG4/SEG24
IVCREF
P3.2/PG2/SEG22
P3.0/TBPWM/PG0/SEG20
P2.6/INT6/SEG18
P2.4/INT4/SEG16
P2.2/INT2/SEG14
P2.0/INT0/SEG12
P1.6/TAOUT/TAPWMTACAP/SEG10
P1.4/RXD1/SEG8
P1.2/RxD0/SEG6
P1.0
AVREF
N.C
N.C
N.C
N.C
J102
Figure 25-3
PS032408-0220
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
40-Pin DIP Connector
P6.3/SEG31
P6.1/SI/SEG29
P3.7/BUZ/PG7/SEG27
P3.5/TD1OUT/TD1PWM/TD1CAP/PG5/SEG25
VSS2
P3.3/TD0OUT/TD0PWM/TD0CAP/PG3/SEG23
P3.1/TCOUT/TCPWM/PG1/SEG21
P2.7/INT7/SEG19
P2.5/INT5/SEG17
P2.3/INT3/SEG15
P2.1/INT1/SEG13
P1.7/TACLK/SEG11
P1.5/TXD1/SEG9
P1.3/TxD0/SEG7
P1.1
AVSS
N.C
N.C
N.C
N.C
40-Pin Connectors (J101, J102) for TB8S6B
PRELIMINARY
25-5
S3F8S6B Product Specification
J102
J102
J101
40-Pin DIP Connector
1
Target System
2
33
34
33
1
2
31
32
Target Cable for 40-Pin
Connector
31
32
63 64
Figure 25-4
PS032408-0220
34
J101
63 64
40-Pin DIP Connectors
Target Board
Chapter 25. Development Tools
S3E8S60 Cables for 64-QFP Package
PRELIMINARY
25-6
S3F8S6B Product Specification
Chapter 25. Development Tools
25.2.1 Third Parties for Development Tools
Zilog provides a complete line of development tools that support the S3 Family of Microcontrollers. With long
experience in developing MCU systems, these third party firms are bonafide leaders in MCU development tool
technology.
25.2.2 In-Circuit Emulators
•
OPENice-i500/2000
•
SK-1200 SmartKit
25.2.3 OTP/MTP Programmers
•
GW-Uni2
•
AS-Pro2
•
Elnec programmers
To obtain the S3 Family development tools that will satisfy your S3F80QB development objectives, contact your
local Zilog Sales Office, or visit Zilog’s Third Party Tools page to review our list of third party tool suppliers.
PS030808-0220
PRELIMINARY
25-7
工商网监
湘ICP备2023018690号
