Z02201
V.22BIS DATA PUMP WITH
INTEGRATED AFE
Product Specification
PS000904-0107
Copyright © 2007 by ZiLOG, Inc. All rights reserved.
www.zilog.com
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©2007 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology
described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR
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IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
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PS000904-0107
Disclaimer
Z02201
V.22BIS Data Pump with Integrated AFE
iii
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Environmental and power requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Analog Inputs: Type AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Analog Outputs: Type A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Hardware Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Synchronous Serial Interface Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Host Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Eye Pattern Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Technical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configurations and Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Tone Generation and Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transmitted Data Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Transmit Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Receiver Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Carrier Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Microprocessor Interface Register and Bit Definitions: . . . . . . . . . . . . . . . . 25
RAMI, RXI, and TXI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interface RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Pump Interface RAM Access Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Modem Data Pump RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Interface RAM Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Transmitting Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Tone Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PS000904-0107
Z02201
V.22BIS Data Pump with Integrated AFE
iv
Call-Progress Monitoring Using Biquad Tone Detectors . . . . . . . . . . . . . . . . . .
Simultaneous Transmission and Detection of Tones . . . . . . . . . . . . . . . . . . . .
Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tone Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Handshake Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Originating Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Answering Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Making a V.22bis Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Originating Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Answering Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDLC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling HDLC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Pump Firmware Version Number and Part Number . . . . . . . . . . . . . . . . .
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example DAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Eye Pattern Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z02201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS000904-0107
54
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57
59
59
60
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62
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66
66
70
72
73
75
Z02201
V.22BIS Data Pump with Integrated AFE
1
Features
Device
Data
Pump
AFE
Speed (MHz)
Z02201
16-Bit
Integrated
12.288
•
•
Combined data pump and Analog Front-End (AFE)
•
FSK (V.23 1200/75 bps, V.21/Bell 103 300 bps), DPSK (V.22/Bell 212A 1200
bps), or QAM encoding (V.22bis 2400 bps)
•
•
Automatic handshake plus full manual control over handshake timings
•
•
•
•
Programmable Bi-Quad tone detectors for call-progress tone detection
•
•
•
•
Simultaneous tone generation and detection
•
•
•
•
Low power consumption: 50 mA typical
Full duplex data modem throughput to 2400 bps
– ITU V.22bis, V.23, V.22, V.21
– Bell 212A and Bell 103
Scrambler/descrambler functions plus selectable control over internal data pump
functions
Adaptive equalization to compensate for a wide variety of line conditions
Programmable transmit attenuation and selectable receive threshold
Fully programmable call-progress detectors, signal quality detectors, tone
detectors, tone generators, and transmit signal levels which aid in rapid country
qualifications
Host port allows direct parallel interface to standard 8-bit microprocessors
HDLC framing at all speeds
On-chip peripherals
– Full-duplex voice band AFE with 12-bit resolution
– Synchronous Serial Interface port
– Eye pattern interface
44-Pin PQFP and PLCC packages
Single +5 VDC power supply
0 °C to +70 °C commercial temperature range
Note: International Telecommunications Union (ITU), formerly CCITT.
PS000904-0107
Z02201
V.22BIS Data Pump with Integrated AFE
2
General Description
The Z02201 is a synchronous single-chip modem solution that provides a means
to construct a V.22bis modem capable of 2400 bps full duplex over dial-up lines.
The Z02201 is specifically designed for use in embedded modem applications
where space, performance, and low power consumption are key requirements.
Operating over the Public Switched Telephone Network (PSTN), the Z02201
meets the modem standards for V.22bis, V.22, V.23, V.21, Bell 212A, and Bell 103.
A typical modem application can be made by simply adding a control
microprocessor (host), phone-line interface, and DTE interface.
The Z02201 performs HDLC framing at all speeds. This capability eliminates the
requirement for an external Serial Input/Output (SIO) device for Data Terminal
Equipment (DTE) in products incorporating error control.
All modulation, demodulation, filtering, A/D and D/A conversion functions for
transmit and receive are provided on-chip. Automatic and selectable compromise
equalizers are included to optimize performance over a wide range of line types.
The Z02201 device compensates for a wide variety of adverse line conditions by
using a combination of fixed link, fixed cable, and adaptive equalizers.
The Z02201 provides comprehensive selectable and programmable tone generation and detection.
All digital I/O signals are TTL compatible. The parallel interface is compatible with
standard 8-bit microprocessors, allowing direct access to eight I/O registers and
indirect access to the modem RAM.
The RAM access capability allows the host to retrieve diagnostic data, modem/
line status and control data, and set programmable coefficients. The serial
interface is used for data transfers. All control and status information is transferred
by means of the parallel interface.
The Z02201 transmit drivers and receive amplifiers can be connected directly to a
Data Access Arrangement (DAA) by means of a transformer. Completing this
connection reduces the external circuits to a minimum.
In addition, the Z02201 offers further system level savings by providing built-in
filters for both the Transmitter Analog Output and the Receiver Analog Input, thus
eliminating the need for external filtering components.
The Z02201 device operates on a single +5 VDC power supply. During periods of
no traffic, the host can place the modem into SLEEP mode, reducing power
consumption to less than 1 percent of full load power.
PS000904-0107
Z02201
V.22BIS Data Pump with Integrated AFE
3
Note: All signals with an overline, are active Low. For example, B/W,
in which WORD is active Low; or B/W, in which BYTE is active
Low.
Power connections follow conventional descriptions below:
PS000904-0107
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
Z02201
V.22BIS Data Pump with Integrated AFE
4
RESET
HD7–HD0
HA2–HA0
HCS
HWR
HRD
HIRQ
Parallel
Interface
A/D Converter
RXI+
RXI–
D/A Converter
TXO–
TXO+
Oscillator
EXTAL
XTAL
Digital
Signal
TXD
RXD
RTS
RLSD
TCLK
RCLK
Serial
Interface
Processor
OH
Eye Pattern
Interface
8K ROM
Figure 1. Z02201 Block Diagram
PS000904-0107
EYEOUT
EYECLK
EYESTB
Z02201
V.22BIS Data Pump with Integrated AFE
5
User Information
The ZiLOG Z02201 data pump can be selected for either parallel or serial
synchronous data transfer under software control. Figure 2 indicates a block
diagram of the general modem chip interface. The hardware and software
configurations can be customized for a particular modem application. The parallel
interface allows direct access to 7 I/O registers, indirect access to the modem
RAM, and is compatible with the Z8, Z80, Z18X family, and other 8-bit
microprocessors. The serial interface is used for data transfer. Controls and status
information are transferred via the parallel interface. The RAM access capability
allows indirect access to diagnostic data, additional status control, and programmable coefficients. The hardware and software interfaces are presented in the
subsequent sections.
Parallel
DTE
Host
Processor
Line
Interface
Data
Access
Arrangement
Z02201
Serial
Speaker
(Optional)
Eye Pattern
Interface
(Optional)
Oscilloscope
(Optional)
Figure 2. Z02201 System Block Diagram
PS000904-0107
Telephone
Line
Z02201
V.22BIS Data Pump with Integrated AFE
EYESTB
EYEOUT
EYECLK
TEST1
GND
RESET
VDD
EXTAL
XTAL
TEST2/RCLK
RTS
6
7
6
1
40
39
Z02201 PLCC
18
28
OH
TXD
TCLK
RXD
RLSD
HD7
HD6
HD5
HD4
HD3
HD2
HCS
HA0
HA1
HA2
HIRQ
HWR
VDD
HRD
GND
HD0
HD1
AVDD
TX0+
TX0–
AGND
Vref
AGND
CF1
CF2
RXI–
RXI+
AVDD
Eyestb
Eyeout
Eyeclk
Test1
GND
RESET
Vdd
Extal
Xtal
Test2/RClk
RTS
Figure 3. Z02201 44-Lead PLCC Pin Identification
33 32 31 30 29 28 27 26 25 24 23
34
22
35
21
20
36
19
37
18
38
17
39
Z02201 LQFP
16
40
15
41
14
42
13
43
12
44
1 2 3 4 5 6 7 8 9 10 11
OH
TxD
TClk
RxD
RLSD
HD7
HD6
HD5
HD4
HD3
HD2
HCS
HA0
HA1
HA2
HIRQ
HWR
Vdd
HRD
Gnd
HD0
HD1
AVdd
TXO+
TXOAgnd
Vref
Agnd
CF1
CF2
RXIRXI+
AVdd
Figure 4. Z02201 44-Lead LQFP Pin Identification
PS000904-0107
Z02201
V.22BIS Data Pump with Integrated AFE
7
Pin Description
Table 1. Z02201 Pin Assignments
PS000904-0107
PLCC Pin
LQFP Pin
Signal
Direction
1
28
RESET
2
29
Gnd
3
30
Test1
Input
4
31
Eyeclk
Output
5
32
Eyeout
Output
6
33
Eyestb
Output
7
34
AVdd
8
35
TXO+
Output
9
36
TXO-
Output
10
37
Agnd
11
38
Vref
12
39
Agnd
13
40
CF1
Input
14
41
CF2
Input
15
42
RXI-
Input
16
43
RXI+
Input
17
44
AVdd
18
1
HCS
Input
19
2
HA0
Input
20
3
HA1
Input
21
4
HA2
Input
22
5
HIRQ
Output
23
6
HWR
Input
24
7
Vdd
25
8
HRD
26
9
Gnd
27
10
HD0
Input/Output
28
11
HD1
Input/Output
Output
Input
Z02201
V.22BIS Data Pump with Integrated AFE
8
Table 1. Z02201 Pin Assignments (Continued)
PLCC Pin
LQFP Pin
Signal
Direction
29
12
HD2
Input/Output
30
13
HD3
Input/Output
31
14
HD4
Input/Output
32
15
HD5
Input/Output
33
16
HD6
Input/Output
34
17
HD7
Input/Output
35
18
RLSD
Output
36
19
RxD
Output
37
20
TClk
Output
38
21
TxD
Input
39
22
OH
Output
40
23
RTS
Input
41
24
Test2/RClk
Input/Output
42
25
Xtal
Output
43
26
Extal
Input
44
27
Vdd
Pin Functions
HD7–HD0 Host Data Bus (Bidirectional, Active High)—HD0–HD7 constitutes an 8-
bit bidirectional data bus used for the transfer of control and status information.
HCS Host Chip Select (Input, Active Low)—When CS is Low, data transfer between
the data pump and the host is enabled. Data transfers to the data pump registers
are 8 bits wide.
HWR Host Write Enable Strobe (Input, Active Low)—The write enable strobe is an
active Low signal that is used to initiate a write operation to the data pump. During
a write operation, data is sent to the data pump by the host via the host data bus.
HRD Host Read Enable Strobe (Input, Active Low)—The read enable strobe is an
active Low signal that is used to initiate a read operation from the data pump. During a read operation, data is transferred out of the data pump by the host via the
host data bus.
HIRQ Host Interrupt Request (Output, Active Low)—The HIRQ is an open-drain
output that can be tied through an external pull-up resistor to the digital power
PS000904-0107
Z02201
V.22BIS Data Pump with Integrated AFE
9
supply VDD. The HIRQ active Low data pump output can be activated when the
host selects this option or requests by setting the RXIE or TXIE bits in the data
pump Host Register. This pin can be connected to the host interrupt request pin to
initiate host service.
RESET Reset (Input, Active Low)—The RESET signal places the device into its
reset state.
HA2–HA0 Host Address (Input, Active High)—These three register select lines
(pins) are used for addressing the controller-accessible internal registers of the
data pump. When HCS is active, the state of the HA2–HA0 is used as the internal
data pump interface register address. HA2 is the most significant bit; HA0 is the
least significant bit.
RLSD Receive Line Signal Detect (Output, Active Low)—This pin indicates when
an input signal has been detected.
RXD Receive Data (Output)—The data pump serial receive data is presented by
the data pump to the local DTE on the RXD output.
TCLK Transmit Serial Data Clock (Output)—The serial data output clock is a syn-
chronous data clock used to transfer serial data via synchronous serial interface
between the data pump and the host. The clock frequencies are 2400, 1200, and
300 Hz, corresponding to the supported data bit rates.
TXD Transmit Data (Input)—The data pump accepts the serial transmit data from
the local DTE on the TXD input when the data pump is configured to the serial
transmit data mode. The serial transmit data mode is selected when the TDPM bit
(bit 4) of the RAM CONTROL/DATA PUMP STATUS register (Register 6) is reset to
0.
OH Off Hook Relay Control (Output, Active Low)—This pin is activated to drive a
relay which engages the modem with the phone line (the modem equivalent of
picking up the receiver).
RTS Request To Send (Input, Active Low)—The logical OR of this pin and the
RTSP bit (bit 3 of register 4), determines the data pump mode of operation. When
the result of the logical OR of these two bits is logic 1, the data pump is in transmit
mode at the selected speed, thereby placing the data pump in receive mode. In
STANDBY mode, the state of this pin is insignificant.
EYECLK Eye Pattern Clock (Output, Active High)—Data is valid at the rising edge
of the clock. The EYECLK can be used to clock an external Digital-to-Analog (D/A)
converter shift register for eye pattern display.
EYEOUT Eye Pattern Data (Output, Active High)—This pin controls the serial 16-bit
eye pattern output data. The first 8 bits is the EYEX data, and the next 8-bits are
the EYEY data. This data can be used for display on an oscilloscope X and Y-axis
following D/A conversion.
PS000904-0107
Z02201
V.22BIS Data Pump with Integrated AFE
10
EYESTB Serial Eye Pattern Strobe (Output, Active High)—This signal is used for
loading an external D/A converter.
TXO+ Transmit Differential Analog Output Positive (Analog Output)—The TXO+,
TXO– is capable of driving a 600-ohm resistive load over a leased line or public
switched telephone network via a Data Access Arrangement (DAA). The TXO–
and TXO+ can be configured either as a differential or single-ended output driver.
TXO– Transmit Differential Analog Output Negative (Analog Output)—The TXO–,
TXO+ is capable of driving a 600-ohm resistive load over a leased line or public
switched telephone network via a Data Access Arrangement (DAA).
RXI– Receive Differential Analog Input Negative (Analog Input)—
RXI+ Receive Differential Analog Input Positive (Analog Input)—
TEST1 Test Pin 1 (Input, Active High)—This pin is a test pin and must be tied to
digital ground.
TEST2/RCLK Test Pin 2, Receive Data Clock (Output, Active High)—This pin is a
test pin and must be tied to digital ground through a pull-down resistor. The resistor should be Low enough to ensure this pin floats below 0.8V when the part is in
the RESET state. After RESET, this pin becomes the Receive Data Clock Output.
The resistor should be high enough such that the output can be driven to logic 1.
This pin is a synchronous data clock used to transfer serial data between the data
pump and the host. The clock frequencies are 2400, 1200, and 300 Hz corresponding to the supported data bit rates.
Vref Reference Voltage (Output, Active High—An internally generated reference
voltage.
XTAL Crystal (Output, Active High)—Crystal oscillator connection. This pin must
be left open if an external clock is used instead of a crystal. The data pump chip
can be connected to an external crystal circuit consisting of 24.576-MHz (parallel
resonant) crystal, a resistor, and two capacitors.
EXTAL External Clock/ Crystal (Input, Active High)—Crystal oscillator connection.
An external clock can be input to the Z02280 on this pin when a crystal is not
used. The oscillator input is not a TTL level (see DC characteristics in Table 4).
CF1 and CF2 Integration Capacitor Pins 1 and 2 (Analog Input)—Connect an 82pF
capacitor between CF2 and CF1 to complete the internal feedback integration filter for improved Analog-to-Digital (A/D) conversion performance.
GND Digital ground–0 Volts—
VDD Digital Power–5 Volts—
AVDD Analog Power–5 Volts—
AGND Analog Ground–0 Volts—
PS000904-0107
Z02201
V.22BIS Data Pump with Integrated AFE
11
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
Symbol
Description
Min
Max
Units
VCC
Supply Voltage
–0.3
+7.0
V
TOPR
(com)
Operating Temperature 0
+70
°C
TSTG
Storage Temperature
+150
°C
–65
Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This rating is a stress rating only. Operation of
the device at any condition above those indicated in the operational sections of
these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Standard Test Conditions
The DC Parameters were tested as per Table 6. The Z02201 tester has active
loads which are used to test the loading for IOH and IOR.
Available operating temperature range is: where: S = Standard Temperature
Range
S = 0°C to +70°C
Voltage Supply Range:
+4.5 V ≤ VCC ≤ + 5.5 V
All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for
each 50 pF increase in load up to a maximum of 150 pF for the data bus, and 100
pF for address and control lines.
PS000904-0107
Z02201
V.22BIS Data Pump with Integrated AFE
12
Environmental and power requirements
The modem power and environmental requirements are indicated in Table 3 and Table 4.Table 5 provides
the crystal specifications.
Table 3. Power Requirements
Current Typical
@ 25°C
Current
Maximum @ 0°C
+5 VDC,
Operating
50 mA
