Z32AN00NW200SG

Encore! 32™ Series Microcontroller (Z32AN) High Performance ARM9 SoC Data Sheet DS0200-003 Copyright ©2009 by Zilog, Inc. All Rights Reserved www.zilog.com WARNING: DO NOT USE IN LIFE SUPPORT LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2009 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. TM Encore! 32 is a trademark of Zilog, Inc. ARM® and Thumb® are registered trademarks of ARM Limited in the European Union and other countries. All other product or service names are the property of their respective owners. Revision History Each instance in the revision history reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Date August 2008 September 23, 2008 February 25, 2009 Revision Level 001 002 003 Description Original issue Updated part numbers Updated AC Characteristics Page Number All Chapter 23 Chapter 21, pg. 179 Z32AN Series Data Sheet The Z32AN Series is a highly integrated System-on-Chip (SoC) based on the ARM922T core. Available in a 256-BGA package, the Z32AN Series provides a rich set of features on a single chip and enables designers to lower manufacturing costs and reduce time-to-market for embedded applications.       200 MHz ARM922T Core o 32/16-bit RISC Core (ARMv4T) o 16-bit Thumb Instruction Capable o 8k/8k I/D Caches o MMU supporting Linux and Windows CE o JTAG Embedded ICE Support 64 KB Embedded zero-wait-state-SRAM Vectored Interrupt Controller FIPS-180-2 compliant SHA-1 Hash Generator Dual External Bus Interface o 24-bit address, 16-bit data o SDRAM in 16-512 MB configurations o 10 chip selects o External DMA support Power Management Unit o 14-40 MHz oscillator and PLL o 32.768 kHz Oscillator for RTC o Clock disable per peripheral o 3 Modes: Active, Idle, and Battery-Backup o Wake from idle capability  2 SmartCard Interface Controllers (Optional) o Interfaces directly to ON Semiconductor (NCN6001) SmartCard Controller  Magnetic Card Reader (Optional) o Support for ISO 7811-3 and Compliance o Direct Interface to Magnetic Head o Simultaneous Three Track Reading 7811-6  8 independent DMA Channels o SmartCard, MCR, UARTs, SPIs, LCD, external peripherals and Mem-to-Mem o Up to 16 MB transfer capability    Voltage: Dual 1.8V and 3.3V supplies Embedded boot ROM w/external boot option NIST 800-22 compliant Random Number Generator  Display Controller Interface o Directly Compatible with popular LCD Displays, Text or Graphic Modes o Interface to 4/8-bit Data, 3 Control, 1 Contrast  9 Timer/Counters o Five 32-bit cascadable o Four 16-bit with PWM Operation o Counter, PWM, Capture and Compare Modes o 4 Dedicated I/Os  Up to 76 General Purpose I/Os o 16 dedicated (with open drain capability) o All Configurable as Edge/Level Interrupts o Full Input/Output/Tri-state Control o GPIO Wake capability  USB 2.0 full speed OTG o 16 endpoints o Dedicated DMA  3 UARTs o 1 x 8-wire Interface o 2 x 4-wire Interface (1 shared with IrDA endec)       4-channel, 10-bit SAR ADC, 45 kSps Real Time Clock Watchdog Timer 2 Dedicated SPI Interfaces 3.3V I/Os w/5V tolerant I/O for UART and SPI 256 BGA Package. Boundary scan capable DS0200-003 Page ii Z32AN Series Data Sheet Table of Contents Chapter 1: Pin Description ............................................................................................. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 System Pins ............................................................................................................................................. 1 External Bus Interface........................................................................................................................... 1 Secondary External Bus Interface ...................................................................................................... 1 External DMA Interface........................................................................................................................ 2 Timer/Counter........................................................................................................................................ 2 RTC........................................................................................................................................................... 2 UARTs ....................................................................................................................................................... 2 1.7.1 UART0...................................................................................................................................2 1.7.2 UART1...................................................................................................................................2 1.7.3 UART2...................................................................................................................................3 SPI............................................................................................................................................................. 3 1.8.1 Port 0....................................................................................................................................3 1.8.2 Port 1....................................................................................................................................3 USB Interface ......................................................................................................................................... 3 SmartCard Interface ............................................................................................................................ 4 1.10.1 Port 0....................................................................................................................................4 1.10.2 Port 1....................................................................................................................................4 1.10.3 SmartCard SPI Interface ....................................................................................................4 LCD Display Interface .......................................................................................................................... 4 Dedicated General Purpose I/O......................................................................................................... 4 ADC......................................................................................................................................................... 4 Magnetic Card Reader ....................................................................................................................... 5 JTAG ........................................................................................................................................................ 5 Power ...................................................................................................................................................... 5 Pin Assignments, 256 BGA Package.................................................................................................. 6 Chapter 2: Reset..............................................................................................................7 2.1 2.2 2.3 System Reset .......................................................................................................................................... 7 Hard Reset.............................................................................................................................................. 7 Peripheral Reset .................................................................................................................................... 7 Chapter 3: System Clocks and Power Management ................................................. 8 3.1 3.2 3.3 3.4 3.5 Power Modes......................................................................................................................................... 9 3.1.1 HALT - ARM922 Wait for Interrupt ......................................................................................9 3.1.1 IDLE ......................................................................................................................................9 3.1.2 STOP .....................................................................................................................................9 3.1.3 Battery Back Up ..................................................................................................................9 Wake Mechanisms ............................................................................................................................... 9 Main Oscillator External Circuits ....................................................................................................... 10 System Clocking Notes ...................................................................................................................... 10 PMU Registers: (Base → FFFFE000h).................................................................................................. 11 3.5.1 Offset 000h: PMUPLL – PMU PLL Register.........................................................................11 3.5.2 Offset 004h: PMUCLK – PMU Clock Control Register .....................................................12 3.5.3 Offset 008h: PMUCKEN – PMU Clock Enable Register...................................................13 3.5.4 Offset 00Ch: PMURESET – PMU Reset Register................................................................14 3.5.5 Offset 014h: PMUID – PMU ID Register ............................................................................14 3.5.6 Offset 01Ch: PMUCFG – PMU Configuration Register ...................................................15 Chapter 4: ARM922T Core and Embedded ICE ......................................................... 16 Chapter 5: Memory Organization ............................................................................... 17 5.1 DS0200-003 Memory Map ....................................................................................................................................... 17 Page iii Z32AN Series Data Sheet 5.2 5.3 5.4 5.5 5.6 Accesses............................................................................................................................................... 18 Restricted / Reserved Addresses...................................................................................................... 18 ROM/SRAM Remapping .................................................................................................................... 18 Internal SRAM....................................................................................................................................... 18 5.5.1 Clock Disable....................................................................................................................18 5.5.2 Zeroization .........................................................................................................................18 5.5.3 Address FFFF8068h: INT_SRAM_CLR – Internal SRAM Clear Register ............................18 Internal ROM and Boot Program...................................................................................................... 19 5.6.1 Boot locations ...................................................................................................................19 5.6.2 External Memory Image Format .....................................................................................19 5.6.3 Boot Sequence.................................................................................................................20 5.6.4 Boot ROM MMU Table......................................................................................................20 Chapter 6: Interrupt Controller (INTC)......................................................................... 21 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Interrupt Channels and Sources....................................................................................................... 21 Interrupt Priority.................................................................................................................................... 21 Configuring the Interrupt Controller ................................................................................................ 22 ISR Invocation ...................................................................................................................................... 22 ISR Return from Interrupt .................................................................................................................... 22 Interrupt Nesting.................................................................................................................................. 22 Interrupt Latching ............................................................................................................................... 23 Registers: Base → FFFFF000h.............................................................................................................. 23 6.8.1 Offset 000h: INTC_EN – Interrupt Controller Enable Register ........................................23 6.8.2 Offset 004h: INTC_ESET – Interrupt Controller Enable Set Register ...............................24 6.8.3 Offset 008h: INTC_ECLR – Interrupt Controller Enable Clear Register..........................24 6.8.4 Offset 00Ch: INTC_DFLT – Default Vector Register ........................................................24 6.8.5 Offset 010h: INTC_ISTA – Interrupt Status Register..........................................................24 6.8.6 Offset 014h: INTC_RSTA – Raw Interrupt Status Register................................................24 6.8.7 Offset 018h: INTC_IDBG – IRQ Processor Debug Register .............................................25 6.8.8 Offset 01Ch: INTC_FDBG – FIQ Processor Debug Register............................................25 6.8.9 Offset 020h: INTC_SWINT – Software Interrupt Register.................................................25 6.8.10 Offset 024h: INTC_SWINT_SET – Software Interrupt Set Register ...................................25 6.8.11 Offset 028h: INTC_SWINT_CLR – Software Interrupt Clear Register .............................26 6.8.12 INTC_VECN – Channel N Vector Register ......................................................................26 6.8.13 INTC_CFGN – Channel N Configuration Register..........................................................27 6.8.14 Offset F00h: INTC_IVEC – IRQ Vector Register ...............................................................27 6.8.15 Offset F04h: INTC_FVEC – FIQ Vector Register ...............................................................27 6.8.16 Offset F08h: INTC_IEND – IRQ End-of-Interrupt Register ................................................28 6.8.17 Offset F0Ch: INTC_FEND – FIQ End-of-Interrupt Register ...............................................28 Chapter 7: External Bus Interface (EBI) ....................................................................... 29 7.1 7.2 7.3 7.4 DS0200-003 Asynchronous Memory Controller ................................................................................................... 29 7.1.1 Programmable Features..................................................................................................29 7.1.2 Asynchronous Single Read and Write Transactions ......................................................31 7.1.3 Asynchronous Page Read Transactions.........................................................................32 7.1.4 Clock Divided Transactions .............................................................................................33 SDRAM Controller................................................................................................................................ 34 7.2.1 Operation..........................................................................................................................34 7.2.2 Address Mapping .............................................................................................................34 7.2.3 Supported Configurations ...............................................................................................35 7.2.4 SDRAM Performance .......................................................................................................35 7.2.5 Open Bank Policy .............................................................................................................35 7.2.6 Power Saving Modes .......................................................................................................36 7.2.7 Pin Multiplexing .................................................................................................................36 7.2.8 Programmer’s Guide........................................................................................................36 Example Configurations .................................................................................................................... 37 Registers (Base → FFFF8000h)............................................................................................................ 41 Page iv Z32AN Series Data Sheet Chapter 8: DMA Controller........................................................................................... 49 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 Channel Arbitration and Bursts......................................................................................................... 49 DMA Source and Destination Addressing ...................................................................................... 50 Data Movement from the DMA FIFO to the Destination ............................................................. 51 Memory Buffer Alignment ................................................................................................................. 51 Count-to-Zero Condition ................................................................................................................... 52 Chaining Buffers .................................................................................................................................. 52 DMA Interrupts..................................................................................................................................... 52 Channel Time-outs.............................................................................................................................. 52 Register Accesses Restrictions .......................................................................................................... 53 Memory-to-Memory DMA ................................................................................................................. 53 External DMA ....................................................................................................................................... 53 Registers (Base → FFFF4000h)............................................................................................................ 54 8.12.1 Global Registers................................................................................................................54 8.12.2 Per-Channel Registers ......................................................................................................55 Chapter 9: Magnetic Card Reader (MCR) ................................................................. 60 9.1 9.2 9.3 Magnetic Card Reading Overview................................................................................................. 60 Direct Mode Operation of MCR....................................................................................................... 61 9.2.1 Peak Detection Algorithm ...............................................................................................61 9.2.2 Stored Peak Information ..................................................................................................61 9.2.3 Peak Detection Timer and Time-out...............................................................................62 9.2.4 Card Time-out and Track Timers .....................................................................................62 9.2.5 Dynamic Minimum Thresholds.........................................................................................62 9.2.6 MCR Interrupts ..................................................................................................................62 9.2.7 Acquiring Raw ADC Samples..........................................................................................63 9.2.8 Programming Guide ........................................................................................................63 9.2.9 Card Time-out and Track Timers .....................................................................................64 Registers (Base → FFFF3000h)............................................................................................................ 64 9.3.1 Offset 000h: MCR_CTRL – MCR Control Register ...........................................................65 9.3.2 Offset 004h: MCR_INT – MCR Interrupt Register .............................................................66 9.3.3 Offset 008h: MCR_TMR – MCR Timing Register ..............................................................66 9.3.4 Offset 00Ch: MCR_FIFO – MCR FIFO Register.................................................................67 9.3.5 Offset 010h: MCR_ADC – MCR ADC Register ................................................................67 9.3.6 MCRn_DCO – MCR DC Offset Registers (MCR0: 014h, MCR1: 018h, MCR2: 01Ch)...68 9.3.7 MCRn_THRS – MCR Threshold Registers (MCR0: 020h, MCR1: 024h, MCR2: 028h) .....68 9.3.8 Offset 02Ch: MCR_AUX_ADC – MCR Auxiliary ADC Register .......................................68 Chapter 10: Smart Card Controller ............................................................................. 69 10.1 SPI Interface ......................................................................................................................................... 69 10.1.1 Smart Card Controller Interrupt Management .............................................................69 10.1.2 Reset and Power-up Management ...............................................................................70 10.1.3 Chip to Smart Card Interface Mapping ........................................................................70 10.1.4 DMA Interface ..................................................................................................................70 10.1.5 Synchronous Smart Card Handling ................................................................................70 10.1.6 Interrupt Generation ........................................................................................................70 10.2 Blocks .................................................................................................................................................... 71 10.2.1 UART ...................................................................................................................................71 10.2.2 Programmable Baud Rate Generator (BRG) ................................................................71 10.2.3 Controller...........................................................................................................................72 10.2.4 Timing Checker.................................................................................................................73 10.2.5 Interrupt Generation ........................................................................................................73 10.3 Registers................................................................................................................................................ 74 10.3.1 Global Registers (Base → FFFF0000h) .............................................................................74 10.3.2 Smart Card UART Mode Registers (Base: SC0 → FFFF0100h, SC1 → FFFF0200h).........79 10.3.3 Smart Card Controller Registers (Base: SC0 → FFFF0100h, SC1 → FFFF0200h)............86 DS0200-003 Page v Z32AN Series Data Sheet Chapter 11: Real-Time Clock (RTC) ............................................................................ 93 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Real-Time Clock Time/Counter Registers........................................................................................ 93 RTC Alarm............................................................................................................................................. 93 RTC Wake ............................................................................................................................................. 93 RTC Oscillator Source ......................................................................................................................... 93 RTC Battery Backup............................................................................................................................ 93 RTC Reset.............................................................................................................................................. 93 Oscillator External Circuit................................................................................................................... 94 RTC Registers (Base → FFFFB000h).................................................................................................... 94 11.8.1 Current Time Registers......................................................................................................94 11.8.2 Alarm Registers .................................................................................................................96 11.8.3 Control Registers...............................................................................................................98 11.9 RTC Locking ......................................................................................................................................... 99 11.9.1 Address FFFFC00Ch: RTC_APB_STA – RTC APB Status Register .....................................99 11.9.2 Address FFFFC694h: RTC_LCK1 – RTC Lock 1 Register.................................................100 11.9.3 Address FFFFC698h: RTC_LCK2 – RTC Lock 2 Register.................................................100 Chapter 12: Random Number Generator (RNG) ..................................................... 101 12.1 Programming Guide......................................................................................................................... 101 12.2 RNG Registers (Base → FFFFA000h)................................................................................................ 101 12.2.1 Offset 000h: RNG_DATA – Random Number Generator Data Register ....................101 12.2.2 Offset 004h: RNG_CTRL – Random Number Generator Control Register .................102 Chapter 13: SHA-1 ...................................................................................................... 103 13.1 Programming Guide......................................................................................................................... 103 13.2 SHA-1 Registers (Base → FFFF9000h) .............................................................................................. 103 13.2.1 Offset 000h: SHA1_H – Hashed Value ...........................................................................103 13.2.2 Offset 014h: SHA1_DATA_IN – Data In ..........................................................................103 13.2.3 Offset 018h: SHA1_CONTROL – SHA-1 Control .............................................................104 13.2.4 Offset 01Ch: SHA1_STATUS – SHA-1 Status ....................................................................104 13.2.5 Offset 020h: SHA1_WH – SHA-1 Initialization Value ......................................................104 Chapter 14: Analog-to-Digital Converter (ADC) ..................................................... 105 14.1 Voltage Reference........................................................................................................................... 105 14.2 Clock / Sample Rate ........................................................................................................................ 105 14.3 Modes of Operation......................................................................................................................... 105 14.3.1 Continuous Rotating ......................................................................................................105 14.3.2 Single Shot .......................................................................................................................105 14.4 DMA Operation................................................................................................................................. 105 14.5 Registers (Base → FFFF2000h).......................................................................................................... 106 14.5.1 Offset 000h: ADC_CFG – ADC Configuration Register ...............................................106 14.5.2 Offset 004h: ADC_CMD – ADC Command Register...................................................107 14.5.3 Offset 008h: ADC_FIFO – ADC FIFO ..............................................................................107 14.5.4 Offset 00Ch: ADC_INT – ADC Interrupt Register ..........................................................108 14.5.5 Offset 010h: ADC_STA – ADC Status Register...............................................................109 Chapter 15: LCD Interface ......................................................................................... 110 15.1 Interface Timing ................................................................................................................................ 110 15.1.1 Read Cycle .....................................................................................................................110 15.1.2 Write Cycle......................................................................................................................110 15.2 Read and Write Commands........................................................................................................... 111 15.3 4-bit and 8-bit Operation ................................................................................................................ 111 15.4 DMA Operation................................................................................................................................. 111 15.5 LCD Interface Registers (Base → FFFED000h)............................................................................... 111 15.5.1 Offset 000h: LCD_CFG – LCD Configuration Register .................................................111 15.5.2 Offset 004h: LCD_RD – LCD Read Register ..................................................................112 DS0200-003 Page vi Z32AN Series Data Sheet 15.5.3 Offset 008h: LCD_WR – LCD Write Register ..................................................................112 Chapter 16: Timers ...................................................................................................... 113 16.1 Watchdog Timer (WDT).................................................................................................................... 113 16.1.1 Enabling...........................................................................................................................113 16.1.2 Time Delay Period Selection..........................................................................................113 16.1.3 Registers (Base → FFFEC000h) .......................................................................................114 16.2 16-bit PWM Timers (Timers 3 to 0).................................................................................................... 115 16.2.1 Operation........................................................................................................................115 16.2.2 Timer Input/Output Polarity Bit Modes (TxCTL.TPOL) ...................................................119 16.2.3 Reading the Timer Count Values ..................................................................................120 16.2.4 Timer Output Signal Operation .....................................................................................120 16.2.5 Registers (TMR0→FFFE3000h, TMR1→FFFE4000h, TMR2→FFFE5000h, TMR3→FFFE6000h) 120 16.3 32-bit Timers (Timers 8 to 4).............................................................................................................. 123 16.3.1 Operation........................................................................................................................123 16.3.2 Timer Operating Modes .................................................................................................123 16.3.3 UART Mode .....................................................................................................................125 16.3.4 Reading the Timer Count Values ..................................................................................125 16.3.5 Registers (Base: TMR4→FFFE7000h, TMR5→FFFE8000h, TMR6→FFFE9000h, TMR7→FFFEA000h, TMR8→FFFEB000h) .......................................................................................126 Chapter 17: Universal Asynchronous Receiver/Transmitter (UART) ....................... 128 17.1 Functional Description ..................................................................................................................... 128 17.1.1 UART Transmitter .............................................................................................................128 17.1.2 UART Receiver.................................................................................................................128 17.1.3 UART Modem Control ....................................................................................................129 17.1.4 UART Interrupts ................................................................................................................129 17.2 UART Usage ........................................................................................................................................ 130 17.2.1 Control Transfers .............................................................................................................130 17.2.2 Data Transfers .................................................................................................................130 17.2.3 Poll Mode Transfers.........................................................................................................130 17.2.4 DMA mode Transfers ......................................................................................................131 17.3 Baud Rate Generator (BRG)........................................................................................................... 131 17.4 Infrared Encoder/Decoder (UART2 only)...................................................................................... 131 17.4.1 IR Transmit........................................................................................................................132 17.4.2 IR Receive .......................................................................................................................132 17.4.3 IR Narrow Pulse Detection .............................................................................................132 17.4.4 IR Jitter .............................................................................................................................133 17.4.5 IR Infrared Encoder/Decoder Signal Pins .....................................................................133 17.4.6 IR Loopback Testing .......................................................................................................133 17.5 Registers (Base: UART0→FFFE000h, UART1→FFFE100h, UART2→FFFE200h) .............................. 134 17.5.1 Baud Rate Generator Registers ....................................................................................134 17.5.2 UART Registers.................................................................................................................134 Chapter 18: Serial Peripheral Interface (SPI)............................................................ 143 18.1 Operation........................................................................................................................................... 144 18.2 Signals ................................................................................................................................................. 144 18.2.1 Master-In/Slave-Out (MISO)...........................................................................................144 18.2.2 Master-Out/Slave-In (MOSI)...........................................................................................144 18.2.3 Serial Clock (SCK) ...........................................................................................................144 18.2.4 Slave Select (nSS) ...........................................................................................................145 18.3 Clock Phase and Polarity Control.................................................................................................. 145 18.3.1 Transfer Format (SPI_CTL.PHASE = 0) .............................................................................145 18.3.2 Transfer Format (SPI_CTL.PHASE = 1) .............................................................................147 18.4 Multi-Master Operation.................................................................................................................... 147 18.5 Slave Operation ................................................................................................................................ 147 DS0200-003 Page vii Z32AN Series Data Sheet 18.6 Error Detection................................................................................................................................... 148 18.6.1 Transmit Overrun.............................................................................................................148 18.6.2 Mode Fault (Multi-Master Collision) ..............................................................................148 18.6.3 Slave Mode Abort ..........................................................................................................148 18.6.4 Receive Overrun ............................................................................................................148 18.7 SPI Interrupts ....................................................................................................................................... 148 18.8 SPI Baud Rate Generator (BRG)..................................................................................................... 149 18.9 SPI Registers (Base: SPI0→FFFEE00h, SPI1→FFFEF000h) ................................................................ 149 18.9.1 Offset 00h: SPI_DAT – SPI Data Register ........................................................................149 18.9.2 Offset 04h: SPI_CTL – SPI Control Register.....................................................................150 18.9.3 Offset 08h: SPI_STA – SPI Status Register .......................................................................151 18.9.4 Offset 0Ch: SPI_MOD – SPI Mode Register ...................................................................152 18.9.5 Offset 10h: SPI_DIAG – SPI Diagnostic State Register ..................................................152 18.9.6 Offset 14h: SPI_BRG – SPI Baud Rate Register ..............................................................153 18.9.7 Offset 18h: SPI_DMA – SPI DMA Register ......................................................................154 Chapter 19: Universal Serial Bus (USB) ...................................................................... 155 19.1 19.2 19.3 19.4 19.5 Buffer Descriptor Table..................................................................................................................... 155 Receive vs. Transmit ......................................................................................................................... 157 Buffer Descriptor Addressing........................................................................................................... 157 USB Transaction ................................................................................................................................. 157 Host Mode Operation ...................................................................................................................... 158 19.5.1 Discover a Connected Device.....................................................................................158 19.5.2 Perform a Control Transaction to Device ....................................................................158 19.5.3 Send a Full Speed Bulk Data to Target Device............................................................159 19.6 On-The-Go operation ...................................................................................................................... 159 19.6.1 OTG Dual Role “B” Device Operation..........................................................................159 19.6.2 OTG Dual Role “A” Device Operation .........................................................................160 19.7 External Configuration ..................................................................................................................... 161 19.8 Registers (Base → FFFBD000h)......................................................................................................... 162 19.8.1 Offset 000h: USB_PER_ID – Peripheral ID Register.........................................................162 19.8.2 Offset 004h: USB_ID_COMP – Peripheral ID Compliment Register.............................163 19.8.3 Offset 008h: USB_REV – Peripheral Revision Register ...................................................163 19.8.4 Offset 00Ch: USB_ADD_INFO – Peripheral Additional Info Register ...........................163 19.8.5 Offset 010h: USB_OTG_ISTAT – OTG Interrupt Status Register......................................164 19.8.6 Offset 014h: USB_OTG_IEN – OTG Interrupt Control Register ......................................164 19.8.7 Offset 018h: USB_OTG_STAT – OTG Status Register ......................................................165 19.8.8 Offset 01Ch: USB_OTG_CTL – OTG Control Register....................................................165 19.8.9 Offset 080h: USB_ISTAT – Interrupt Status Register ........................................................166 19.8.10 Offset 084h: USB_IEN – Interrupt Enable Register .........................................................166 19.8.11 Offset 088h: USB_ESTAT – Error Interrupt Status Register ..............................................167 19.8.12 Offset 08Ch: USB_EEN – Error Interrupt Enable Register...............................................167 19.8.13 Offset 090h: USB_STAT – USB Status Register .................................................................168 19.8.14 Offset 094h: USB_CTRL – USB Control Register..............................................................168 19.8.15 Offset 098h: USB_ADDR – USB Address Register...........................................................169 19.8.16 Offset 09Ch: USB_BDT_PAGE1 – Buffer Descriptor Table Page Register #1...............169 19.8.17 Offset 0A0h: USB_FRAMEL – USB Frame Number Register Low...................................169 19.8.18 Offset 0A4h: USB_FRAMEH – USB Frame Number Register High .................................169 19.8.19 Offset 0A8h: USB_TOKEN – USB Token Register.............................................................170 19.8.20 Offset 0ACh: USB_SOFT – USB SOF Threshold Register .................................................170 19.8.21 Offset 0B4h: USB_BDT_PAGE2 – Buffer Descriptor Table Page Register #2 ...............170 19.8.22 Offset 0B8h: USB_BDT_PAGE3 – Buffer Descriptor Table Page Register #3 ...............170 19.8.23 USB_ENDPTn_CTRL – Endpoint “N” Control Registers ..................................................171 Chapter 20: General-Purpose Input/Output (GPIO) ............................................... 172 20.1 GPIO Configuration .......................................................................................................................... 173 20.2 Multiplexed Pins................................................................................................................................. 174 DS0200-003 Page viii Z32AN Series Data Sheet 20.3 20.4 20.5 20.6 20.7 Registers (Base: GPIO0→FFFF5000h, GPIO1→FFFF6000h, GPIO2→FFFF7000h) ....................... 175 Using Output ...................................................................................................................................... 176 Configuring Interrupts....................................................................................................................... 176 Handling Interrupts............................................................................................................................ 176 Wake Function .................................................................................................................................. 176 Chapter 21: Electrical Characteristics ...................................................................... 177 21.1 21.2 21.3 21.4 21.5 21.6 Absolute Maximum Ratings ............................................................................................................ 177 DC Characteristics............................................................................................................................ 178 AC Characteristics............................................................................................................................ 179 External Memory Timing................................................................................................................... 180 SDRAM Timing .................................................................................................................................... 180 USB Electrical and Timing................................................................................................................. 181 Chapter 22: Packaging .............................................................................................. 182 22.1 Soldering Information ....................................................................................................................... 182 22.2 Top Mark............................................................................................................................................. 182 Chapter 23: Ordering Information............................................................................. 183 Chapter 24: Customer Support .................................................................................. 183 DS0200-003 Page ix Z32AN Series Data Sheet List of Figures Figure 2-1: Reset Module Block Diagram......................................................................................................... 7 Figure 3-1: Simplified PMU Block Diagram ....................................................................................................... 8 Figure 3-2: Main Crystal External Circuits ....................................................................................................... 10 Figure 3-3: System Clocking ............................................................................................................................. 10 Figure 7-1: CS1 as A[24] .................................................................................................................................... 30 Figure 7-2: Single Read/Write Timing Diagram ............................................................................................. 31 Figure 7-3: Asynchronous Page Read Timing Diagram............................................................................... 32 Figure 7-4: flclk Based Timing Diagram........................................................................................................... 33 Figure 7-5: External Memory Example ............................................................................................................ 37 Figure 7-6: Connection to an 8-bit SRAM Device ........................................................................................ 38 Figure 7-7: Connection to a 16-bit SRAM Device......................................................................................... 38 Figure 7-8: Connection to a 16-bit SRAM Device with Byte Enable.......................................................... 38 Figure 7-9: Connection to 2 x 8-bit SRAM Devices....................................................................................... 39 Figure 7-10: Connection to an 8-bit FLASH Device ...................................................................................... 39 Figure 7-11: Connection to a 16-bit FLASH Device ...................................................................................... 39 Figure 7-12: Sync Burst Flash Configuration (AM29BL802C)........................................................................ 40 Figure 7-13: Connection to two 4M byte x 8-bit FLASH Devices................................................................ 40 Figure 8-1: Acknowledge Waveform ............................................................................................................. 53 Figure 9-1: Magnetic Card Bit encoding ....................................................................................................... 60 Figure 9-2: Peak Detection Algorithm ............................................................................................................ 61 Figure 10-1: SPI Data Transfer ........................................................................................................................... 69 Figure 10-2: State Diagram for Smart Card Controller ................................................................................ 72 Figure 11-1: RTC Crystal External circuit ......................................................................................................... 94 Figure 11-2: APB Lock State Machine............................................................................................................. 99 Figure 15-1: LCD controller Read/Write Cycles .......................................................................................... 110 Figure 16-1: Interrupt and RESET Timing Diagram ....................................................................................... 113 Figure 16-2: Auto baud Timing Diagram...................................................................................................... 125 Figure 17-1: Infrared System Block Diagram................................................................................................ 131 Figure 17-2: Infrared Data transmission ........................................................................................................ 132 Figure 17-3: Infrared Data Reception........................................................................................................... 132 Figure 18-1: SPI Configured as a Master in a Single Master, Single Slave System................................. 143 Figure 18-2: SPI Configured as a Master in a Single Master, Multiple Slave system ............................. 143 Figure 18-3: SPI Configured as a Slave ......................................................................................................... 144 Figure 18-4: SPI Timing (PHASE = 0)................................................................................................................ 146 Figure 18-5: SPI Timing (PHASE = 1)................................................................................................................ 147 Figure 19-1: Buffer Descriptor Entry ............................................................................................................... 156 Figure 19-2: USB Token Transaction ............................................................................................................... 157 Figure 19-3: Dual Role "B" Device Flow Diagram ........................................................................................ 159 Figure 19-4: Dual Role "A" Device Flow Diagram........................................................................................ 160 Figure 20-1: 32-bit GPIO Detailed Block Diagram ...................................................................................... 173 Figure 21-1: External Memory I/O Timing ..................................................................................................... 180 Figure 21-2: SDRAM Interface I/O Timing ..................................................................................................... 180 Figure 21-3: USB Data Signal Timing .............................................................................................................. 181 DS0200-003 Page x Z32AN Series Data Sheet List of Tables Table 3-1: PMU Module Inputs and Outputs ................................................................................................... 8 Table 6-1: Interrupt Source to Channel Mapping ........................................................................................ 21 Table 7-1: Pin Functions vs. Control Style ....................................................................................................... 29 Table 7-2: Single Read/Write Timing (based on MEMC_TIMN)................................................................... 31 Table 7-3: Asynchronous Page Read Timing (based on MEMC_TIMN) .................................................... 32 Table 7-4: Extended Timing Parameters (based on MEMC_TIMN)............................................................ 33 Table 8-1: Source and Destination Address Construction .......................................................................... 50 Table 8-2: Inbound Data Alignment ............................................................................................................... 51 Table 8-3: Outbound Data Alignment ........................................................................................................... 51 Table 16-1: Watchdog Timer Approximate time Delays ........................................................................... 113 Table 16-2: Time Period Values for INT_PERIOD and RST_PERIOD ............................................................ 114 Table 19-1 : Buffer Descriptor - Word 0 ......................................................................................................... 156 Table 19-2 : Buffer Descriptor - Word 1 ......................................................................................................... 156 Table 19-3: Endpoint Enable / Direction Control........................................................................................ 171 Table 21-1: Absolute Maximum Ratings ....................................................................................................... 177 Table 21-2: AC Characteristics ...................................................................................................................... 179 Table 21-3: Power-On Reset Electrical Characteristics and Timing ........................................................ 179 Table 21-4: Analog-to-Digital Converter Electrical Characteristics ........................................................ 179 DS0200-003 Page xi Z32AN Series Data Sheet Chapter 1: Pin Description 1.1 1.2 1.3 System Pins Pin Name Dir Function nRSTIN I System Reset: Schmitt trigger input. nRSTOUT O Reset Out: 4mA drive. CLKXI I System Clock Oscillator Input CLKXO O System Clock Oscillator Output External Bus Interface Pin Name Dir Function nCS[9:6] O Memory Chip Selects [9:6]: 4mA drive. Multiplexed with GPIO_0[19:16] (nCS[9] multiplexed with GPIO_0[19], etc.). After reset, these pins default as chip selects. nCS[5:0] O Memory Chip Selects [5:0]: memory chip select. nWEU O Primary Write Strobe: 8mA drive. nWEL O Primary Write Strobe: 8mA drive. nOE O Primary Output Enable: 8mA drive. MA[23:0] O, I/O MD[15:0] I/O SDCLK O SDRAM Clock: 4mA drive. READY I Ready Input: 4mA drive. Multiplexed with GPIO_0[26]. At reset, this pin defaults to GPIO. 4mA drive. nCS[0] is used as the external boot Primary Address Bus: 8mA drive. MA[23:20] multiplexed with GPIO_0[23:20] (MA[23] multiplexed with GPIO_0[23], etc.). MA[23:20] are I/O when in GPIO mode. At reset, MA[23:20] default as address pins. Primary Data Bus: 8mA drive. Secondary External Bus Interface Pin Name Dir CKE O SDRAM Clock Enable for Secondary Bus: 4mA drive. nSWEU O Secondary Write Strobe: 4mA drive. nSWEL O Secondary Write Strobe: 4mA drive. nSOE O Secondary Output Enable: 4mA drive. SA[23:0] O Secondary Bus Address: 4mA drive. SD[15:0] I/O nRAS O SDRAM Row Address Strobe: 4mA drive. nCAS O SDRAM Column Address Strobe: 4mA drive. nWE O SDRAM Write Enable: 4mA drive. DQM[1:0] O SDRAM Data Mask: 4mA drive. DS0200-003 Function Secondary Bus Data: 4mA drive. Page 1 Z32AN Series Data Sheet 1.4 External DMA Interface After reset, all external DMA interface pins default to GPIO. 1.5 Pin Name Dir Function TxREQ I External DMA Transmit Request: Schmitt trigger input. 4mA drive. Multiplexed with GPIO_2[8]. TxACK O External DMA Transmit Acknowledge: 5V tolerant. 4mA drive. Multiplexed with GPIO_2[9]. RxREQ I External DMA Receive Request: Schmitt trigger input. 4mA drive. Multiplexed with GPIO_2[10]. RxACK O External DMA Receive Acknowledge: 5V tolerant. 4mA drive. Multiplexed with GPIO_2[11]. Timer/Counter Pin Name Pins PWM/TCLK[3:0] I/O 1.6 PWM/TCLK I/O for counters 3 to 0: Schmitt trigger input. 4mA drive. Multiplexed with GPIO_0[30:27]. (PWM/TCLK[3] multiplexed with GPIO_0[30], etc.) RTC Pin Name 1.7 Function Type Function RTCXI I RTC Oscillator Input: Expected frequency is 32.768kHz RTCXO O RTC Oscillator Output: UARTs At reset, all multiplexed UART pins default to GPIOs. 1.7.1 1.7.2 UART0 Pin Name Dir Function RxD[0] I UART0 Data Input: 5V tolerant. 4mA drive. TxD[0] O UART0 Data Output: 5V tolerant. 4mA drive. nCTS[0] I UART0 Clear to Send: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[1]. nRTS[0] O UART0 Request to Send: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[4]. nDCD[0] I UART0 Data Carrier Detect: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[7]. nDTR[0] O UART0 Data Terminal ready: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[8]. nDSR[0] I UART0 Data Set Ready: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[9]. nRI[0] I UART0 Ring Indicator: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[10]. UART1 Pin Name Dir RxD[1] I Function UART1 Data Input: 5V tolerant. 4mA drive. TxD[1] O UART1 Data Output: 5V tolerant. 4mA drive. nCTS[1] I UART1 Clear to Send: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[2]. nRTS[1] O UART1 Request to Send: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[4]. DS0200-003 Page 2 Z32AN Series Data Sheet 1.7.3 1.8 UART2 Pin Name Type Function RxD[2] I UART2 Data Input: 5V tolerant. 4mA drive. Multiplexed with GPIO_0[31]. TxD[2] O UART2 Data Output: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[0]. nCTS[2] I UART2 Clear to Send: 5V tolerant. 4mA drive. Mulitiplexed with GPIO_1[3]. nRTS[2] O UART2 Request to Send: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[6]. SPI After reset, all SPI pins default to GPIOs. Unless otherwise noted, the drive value of the GPIO is ‘0’. 1.8.1 1.8.2 1.9 Port 0 Pin Name Dir Function MISO[0] I SPI 0 Master DI, Slave DO: 5V tolerant. 4mA drive. Multiplexed with GPIO[11] MOSI[0] O SPI 0 Master DO, Slave DI: 5V tolerant. 4mA drive. Multiplexed with GPIO[13]. SCK[0] O SPI 0 Clock: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[15]. nSS[0] O SPI 0 Slave Select: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[17]. After reset, drives value of ‘1’. Port 1 Pin Name Dir Function MISO[1] I SPI 1 Master DI, Slave DO: 5V tolerant. 4mA drive. Multiplexed with GPIO[12] MOSI[1] O SPI 1 Master DO, Slave DI: 5V tolerant. 4mA drive. Multiplexed with GPIO[14]. SCK[1] O SPI 1 Clock: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[16]. nSS[1] O SPI 1 Slave Select: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[18]. After reset, drives value of ‘1’. USB Interface Pin Name Type USB0DN I/O USB Negative Transceiver: USB0DP I/O USB Positive Transceiver: USB0VBUS A USB0ID I/O USB ID: DRIVEBUS0 AO USB External Power Enable: 4mA drive. DS0200-003 Function USB VBUS: Page 3 Z32AN Series Data Sheet 1.10 SmartCard Interface All SmartCard pins default to GPIOs at reset. 1.10.1 Port 0 Pin Name Type SC_CLK[0] O SC_IO[0] I/O Function SmartCard Port 0 Clock: 4mA drive. Multiplexed with GPIO_1[19]. SmartCard Port 0 I/O: Internal Pull-up. 4mA drive. Multiplexed with GPIO_1[21]. 1.10.2 Port 1 Pin Name Type SC_CLK[1] O SC_IO[1] I/O Function SmartCard Port 1 Clock: 4mA drive. Multiplexed with GPIO_1[20]. SmartCard Port 1 I/O: Internal Pull-up. 4mA drive. Multiplexed with GPIO_1[22]. 1.10.3 SmartCard SPI Interface Pin Name Type Function SC_nALARM I SmartCard Alarm Interrupt: 4mA drive. Multiplexed with GPIO_1[23]. SC_SCK O SmartCard SPI Clock: 4mA drive. Multiplexed with GPIO_1[24]. SC_MOSI O SmartCard SPI MOSI: 4mA drive. Multiplexed with GPIO_1[25]. SC_MISO I SmartCard SPI MISO: 4mA drive. Multiplexed with GPIO_1[26]. SC_nSS[1:0] O SmartCard SPI Slave Select: 4mA drive. Internal Pull-up. GPIO_1[28:27] (SC_nSS[1] multiplexed with GPIO_1[28], etc.) Multiplexed with 1.11 LCD Display Interface At reset all LCD pins default to GPIOs, with a drive value of ‘0’. Pin Name Dir Function LCD_E O LCD Enable: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[29]. LCD_RS O LCD Register Select: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[30]. LCD_RnW O LCD Read/Write: 5V tolerant. 4mA drive. Multiplexed with GPIO_1[31]. LCD_D[7:0] I/O LCD Data: 5V tolerant. 4mA drive. multiplexed with GPIO_2[7], etc. Multiplexed with GPIO_2[7:0]. (LCD_D[7] 1.12 Dedicated General Purpose I/O Pin Name Type Function GPIO_0[25:24] I/O Dedicated GPIOs [25:24]: GPIO_0[15:1] I/O Dedicated GPIOs [15:1]: GPIO_0[0] I/O Dedicated GPIO [0]: 5V tolerant. Open drain capabile. 4mA drive. At reset, this is the “download” pin. See TBD for more details. Pin Name Type Function ADC_IN[4:1] AI ADC Analog in ADC_VREF AI ADC Connect to External Voltage Reference 5V tolerant. Open drain capabile. 4mA drive. 1.13 ADC DS0200-003 Page 4 Z32AN Series Data Sheet 1.14 Magnetic Card Reader Pin Name Type Function MCR_P[2:0] AI Memory Card Reader Positive Analog Inputs: MCR_N[2:0] AI Memory Card Reader Negative Analog Inputs: MCR_VREF A Memory Card Voltage Reference: Connect external 100nF (ceramic) to ground. 1.15 JTAG Pin Name Type Function ICE_TMS I Test Mode Select: Internal Pull-up ICE_TDI I Test Data Input: Internal Pull-up ICE_TDO OZ ICE_TCK I Test Clock: Internal Pull-up ICE_nTRST I Test Reset: Internal Pull-up Test Data Output: 4mA drive. Requires external pull-up 1.16 Power Pin Name 1.8V Core Power VSS[8:0] Core Ground VDDIO[11:0] 3.3V I/O Power VSSIO[12:0] I/O Ground VBAT DS0200-003 Function VDD[7:0] 3.0V Battery Power AVDD_RTC 3.3V RTC Module Power AVSS_RTC RTC Module Ground AVDD_PLL 1.8V PLL Power AVSS_PLL PLL Power AVDD_MCR 3.3V Mag Reader Power AVSS_MCR Mag Reader Ground AVDD_ADC 3.3V ADC Power AVSS_ADC ADC Ground VDD_USB 3.3V USB Power VSS_USB USB Ground Page 5 Z32AN Series Data Sheet 1.17 Pin Assignments, 256 BGA Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A MISO[0] MOSI[0] SCK[0] AVSS_ ADC AVSS_ USB ADC_ VREF VSSIO CLKXI CLKXO LCD_ D [3] LCD_ D [2] LCD_ D [1] LCD_ D [0] PWM_ TCLK[2] PWM_ TCLK[1] PWM_ TCLK[0] B nSS[0] MISO[1] SCK[1] AVDD_ ADC AVDD_ USB USB0 VBUS USB0 DP VSSIO VDDIO RxACK LCD_ D [6] LCD_ D [5] LCD_ D [4] PWM_ TCLK[3] nCTS[2] nRTS[2] C nCS[9] nOE MOSI[1] ADC_ IN[2] ADC_ IN{1] ADC_ IN[4] VDDIO VSSIO VDDIO TxACK TxREQ LCD_ RS LCD_ D [7] TxD[2] RxD[2] nCTS[1] D nCS[8] VSS VDD SD[0] ADC_ IN[3] USB0ID USB0DN AVSS_ PLL AVDD_ PLL VSS RxREQ LCD_ RnW LCD_E VSSIO VDDIO nRTS[1] E nCS[7] VDDIO DRIVE BUS0 SA[22] SA[21] nRSTIN VSSIO nSS[1] GPIO_0 [8] VDD SC_ CLK[1] SC_ IO [1] SC_ MISO GPIO_0 [14] GPIO_0 [15] TxD[1] F nCS[6] VSSIO SA[20] SA[19] SA[18] SD[2] SD[1] GPIO_0 [11] SC_ IO [0] SC_n ALARM VSS VDD GPIO_0 [13] RxD[1] G nCS[5] VSSIO SA[17] SA[16] SA[15] SD[4] SD[3] ICE_ nTRST ICE_ TDO GPIO_0 [10] SC_ CLK[0] GPIO_ [0] GPIO_0 [2] nRTS[0] H nCS[4] VDDIO SA[14] SA[13] SA[12] SD[6] SD[5] READY ICE_ TDI GPIO_0 [9] GPIO_0 [12] SC_ nSS[0] SC_ nSS[1] VDDIO VSSIO nRI0 J nCS[3] VSS SA[11] SA[10] SA[9] SD[8] SD[7] VSS GPIO_0 [7] GPIO_0 [1] GPIO_0 [4] MCR_ P[0] MCR_ N[0] VDD VSS nCTS[0] K nCS[2] VDD SA[8] SA[7] SA[6] SD[10] SD[9] VSS VSS GPIO_0 [3] GPIO_0 [5] MCR_ N[1] MCR_ P[1] AVDD_ MCR AVSS_ MCR nDTR[0] L MA[22] MA[23] SA[5] SA[4] SD[11] SD[12] VSS VSS VSS AVDD_ VBAT GPIO_0 [6] MCR_ N[2] MCR_ P[2] VSS MCR_ VREF RxD[0] M MA[20] MA[21] SA[3] SA[2] SD[13] SD[14] VSS nCS[1] RTCXO VDD VSS MD[14] nRST OUT VDDIO VSSIO TxD[0] N MA[19] VDD SA[1] SA[0] GPIO_0 [25] SD[15] VDDIO VSS RTCXI AVDD_ RTC CKE VSS MD[10] MD[6] MD[2] nDSR[0] P MA[18] VSS nCAS nRAS VSSIO GPIO_0 [24] VSSIO SDCLK nCS[0] AVSS_ RTC VSS VSS MD[11] MD[7] MD[3] nDCD[0] R MA[17] MA[14] MA[12] MA[10] MA[8] MA[6] MA[4] MA[2] MA[0] nWE DQM[0] nWEU MD[12] MD[8] MD[4] MD[0] T MA[16] MA[15] MA[13] MA[11] MA[9] MA[7] MA[5] MA[3] MA[1] nWEL DQM[1] MD[15] MD[13] MD[9] MD[5] MD[1] DS0200-003 ICE_ TMS ICE_ TCK SC_ SCK SC_ MOSI Page 6 Z32AN Series Data Sheet Chapter 2: Reset The Z32AN Series provides 3 types of reset operations: System Reset, Hard Reset, and Peripheral Reset Figure 2-1: Reset Module Block Diagram 2.1 System Reset A system reset is caused by a Hard Reset or a Soft Reset. A system reset resets all modules except the Power Management Unit (PMU) and Watchdog Timer. A system reset is driven out onto the nRSTOUT pin. 2.2 Hard Reset A hard reset is caused by the reset input pin, an internal Power-on reset or Watchdog time-out. A hard reset will reset all digital modules of the device. The hard reset is asserted asynchronously by any of its sources. The hard reset is released synchronously to the CLKXI oscillator input after all reset sources have been inactive for 16 clock cycles. 2.3 Peripheral Reset A peripheral reset is caused by a system or peripheral reset. This resets all APB peripherals, except the PMU, Watchdog Timer, and GPIO. This does not reset any AHB device (such as the CPU, Bridge, EBI, DMA, etc.). The source(s) of a reset are logged within PMURESET. nRSTIN is run through a glitch filter to improve noise immunity. DS0200-003 Page 7 Z32AN Series Data Sheet Chapter 3: System Clocks and Power Management The Z32AN Series contains a Power Management Unit (PMU) that controls system clocking and power management. The configuration of the PMU is performed through the PMU registers. Upon a hard reset, the PMU drives the main oscillator clock onto the system clock. All digital clock domains are enabled and most analog circuits are powered down. The PLL typically locks 100µs after it is enabled. The lock bit should be checked before switching clock source to the PLL. After the PLL has locked, the programmer can write to the PMU registers to control clock frequencies and clock gating. The PMU contains control circuits to allow for glitch-free, dynamic configuration of all clocks. The boot ROM configures the PLL at start up. Figure 3-1: Simplified PMU Block Diagram Table 3-1: PMU Module Inputs and Outputs Signal Name Dir CLKXI/CLKXO I Input/Output connection to the main external crystal. Any frequency from 14MHz-40MHz may be used. A clock must be present for the device to come out of reset. fclk O Main CPU clock. hclk[31:0] O System clocks. These clocks are driven to the AHB and APB devices as well as the AHB interface of the CPU. This clock can be enabled or disabled on a module-by-module basis. (See PMU Clock Enable Register (ADDR = 0xFFFF_E008) daaclk O Clock driven into the DAA. The DAA requires a 24.000MHz clock. sdclk O Clock eventually driven onto the CLKOUT pin. This signal first goes through the SDRAM Controller module where it may be subject to additional clock gating. gpio_wake I Signal from GPIO to wake system upon any GPIO input transition. See Using the GPIO Wake Function. Though shown as a single signal, there are wake signals from all GPIO modules. rtc_wake I Signal from RTC to wake system upon activation of the RTC alarm. See Real-Time Clock (RTC). DS0200-003 Description Page 8 Z32AN Series Data Sheet 3.1 Power Modes Mode Initiation Wake HALT ARM922T Wait-for-IRQ CP15 of ARM922T IRQ or FIQ active into ARM922T Clock must remain active to the INTC. The clocks of other modules can be deactivated in the PMU to reduce dynamic power consumption. Clocks for modules expected to generate interrupts should be left enabled. IDLE PMU_CFG and PMU_CLK_EN Transition on selected GPIO inputs or RTC Alarm or USB wake None. All clocks can be disabled but the PLL and Crystal continue to run. STOP PMU_CFG Battery Back Up Automatic when power is removed 3.1.1 Transition on selected GPIO inputs or RTC Alarm or USB wake POR Restrictions None. All clocks are disabled and the PLL and Crystal are disabled. None. Only the RTC remains active. Normal operation resumes when power is returned to the system. HALT - ARM922 Wait for Interrupt This is an intrinsic function of the ARM922T. The ARM922T contains a Wait for Interrupt mechanism within the CP15 registers to put the ARM922T in a low power state until the arrival of an IRQ or FIQ. More information can be found in the ARM922T Technical Reference Manual. Prior to placing the CPU in this state, turn off any unnecessary clocks in PMU_CLK_EN to further reduce power. In this mode, the INTC and any peripherals expected to generate interrupts should be left enabled. All other enables may be off. 3.1.1 IDLE In this mode all clocks are disabled. The PLL and crystal continue to run for fast return to full active operation. The return to active mode is achieved by transitions on selected GPIO, RTC alarm or USB wake. To enter this mode, power down the peripherals and select the wake mechanisms in PMUCFG and turn off the clocks in PMU_CLK_EN. 3.1.2 STOP In this mode, all the clocks, PLL, and Crystal are disabled. Return to active mode is achieved by transition on selected GPIO, RTC alarm or USB wake. This mode requires an additional delay to active mode while the crystal starts and PLL re-locks. To enter the this mode, power down the peripherals, select the wake mechanisms and disable XTAL with one write to PMUCFG. Once XTAL disabled, the clocks stop. Normal operation is resumed when the one of the selected wake mechanisms occurs and the delay for XTAL stabilization has elapsed. 3.1.3 Battery Back Up The system is in battery back up mode when all power is removed except the battery. In this mode, the RTC continues to operate. Return to active is achieved by applying valid system power. Resuming normal operation is automatic with the ROM boot sequence occurring. 3.2 Wake Mechanisms   DS0200-003 GPIO Wake: This can be used to return to active operation from Idle or Stop Modes. All GPIO modules can be configured to wake in the event of a GPIO input edge by setting GPIO_WAKE_EN. See section Chapter 20: for more details. RTC Wake: The RTC alarm can also be used to return to active operation from Idle or Stop Modes. The PMU can be configured to “wake” the PMU clocks upon activation of the RTC alarm. See section Chapter 11: for more details. Page 9 Z32AN Series Data Sheet  3.3 USB Wake: USB can return the SoC to active operation from Idle or Stop Modes. The lowest power for USB suspend is achieved through “stop” mode. The PMU can be configured to wake when USB activity is detected. Main Oscillator External Circuits The required crystal circuit for the main oscillator is shown below. Supported crystal frequencies are 14MHz - 40MHz.. Figure 3-2: Main Crystal External Circuits To allow the oscillator to stabilize, the PMU has a 16-bit ripple counter which will block the first 64k crystal clock cycles after a power on reset or when the crystal is re-enabled by a wake function. 3.4 System Clocking Notes The system outlined in Figure 4-3 isolates sysclk from any glitches or over/under-clocking:    Fast glitches (< 20ns) are prevented from entering the system by the 20ns Glitch Filter between the oscillator and the rest of the system. This limits the output of the oscillator from generating a signal faster than 50MHz. This is in effect whether or not sysclk is derived from the PLL. Fast frequency over-clocking is prevented by the PLL losing lock in the event of sudden changes to the input clock frequency. This is only operate when sysclk is derived from the PLL. Under-clocking is prevented by the PLL losing lock when the input clock is below the minimum requirement of the PLL. This will operate only when sysclk is derived from the PLL. Figure 3-3: System Clocking DS0200-003 Page 10 Z32AN Series Data Sheet 3.5 PMU Registers: (Base → FFFFE000h) The PMU registers are reset by a hard reset, unless otherwise noted in the register description. Most of the system and registers are reset by a system reset, but the PMU and Watchdog Timer are exceptions. 3.5.1 Offset Register Description 000h PMUPLL PMU PLL Register 004h PMUCLK PMU Clock Control Register 008h PMUCKEN PMU Clock Enable Register 00Ch PMURESET PMU Reset Register 014h PMUID 01Ch PMUCFG PMU ID Register PMU Configuration Register Offset 000h: PMUPLL – PMU PLL Register Bits Type Reset 31:28 RW 1h PLL Output Divider "P" (OUTDIVP): Determines how much the pll_clk is divided after frequency multiplication.  0000: pll_clk is divided by 1  0001: plll_clk is divided by 2  ...  1111: pll_clk is divided by 16 27:24 RW 0h PLL Input Divider “N” (INDIVN): Determines how much the crystal_clk is divided before frequency multiplication. This must result in a frequency above 12 MHz  0000: crystal_clk is divided by 1  0001: crystal_clk is divided by 2  ...  1111: crystal_clk is divided by 16 23:16 RW 13h PLL Multiplier “M” (MULTM): Determines how much the frequency is multiplied. This must result in a frequency below 500 MHz and greater than 225 MHz  00h: ILLEGAL SETTING  01h: frequency multiplier factor is 2  02h: frequency multiplier factor is 3  ...  FFh: frequency multiplier factor is 256 15:02 RO 0 Reserved 01 RO 0 PLL Lock (PLL_LOCK): When cleared, not locked. When set, locked. 00 RW 0 PLL Power Enable (PLL_ENJ): When cleared, power down. When set, power up. DS0200-003 Description Page 11 Z32AN Series Data Sheet 3.5.2 Offset 004h: PMUCLK – PMU Clock Control Register Bits Type Reset 31 RW 0 Crystal Disable (XTALDIS): When cleared, the crystal is disabled to put the device into low power sleep mode. This bit is automatically cleared by wake up. 30 RW 0 Source Clock Select (SRCCLKSEL): When cleared, select crystal clock as the source clock. When set, select PLL clock as the source clock. 29:25 RO 0 Reserved 24 RW 0 USB Clock Divider (USBCLKDIV): When cleared, use HCLK. When set, use HCLK divided by 2. 23:17 RO 0 Reserved 16 RW 0 External SDRAM Clock Enable (SDCLK): When cleared, SDCLK is disabled. When set, SDCLK is enabled. 15:08 RW 00h 07:05 RO 0 04:00 DS0200-003 RW 00000 DescriptionDS0200.docx HCLK Divider (HCLKDIV): This specifies how much to divide fclk to produce hclk.  00h: 1 (hclk = fclk)  01h: 2 (hclk = fclk / 2)  ...  FFh: 256 Reserved FCLK Divider (FCLKDIV): This specifies how much to divide source clock to produce fclk.  00000: 1 (fclk = source clock)  00001: 2 (fclk = source clock / 2)  ...  11111: 32 Page 12 Z32AN Series Data Sheet 3.5.3 Offset 008h: PMUCKEN – PMU Clock Enable Register Bits Type Reset Description 31 RW 1 CPU Clock Enable (CPU): Enables both CPU clocks (fclk and hclk). Forced to ‘1’ by wake up. 30 RW 1 USB Clock Enable (USB): Enables USB clock. Forced to ‘1’ by wake up. 29 RW` 1 Memory Controller Enable (MEMC): Enable hclk to the External Memory Controller and SDRAM controller. Forced to ‘1’ by wake up. 28 RW 1 SRAM/ROM Enable (SRAM_ROM): Forced to ‘1’ by wake up. 27 RW 1 Bridge Enable (BRDG): Enable hclk to the AHB bridge. Forced to ‘1’ by wake up. 26 RW 1 Interrupt Controller Clock Enable (INTC): Enable hclk to the Interrupt Controller. Forced to ‘1’ by wake up. 25 RW 1 Random Number Generator Clock Enable (RNG): Number Generator. 24 RO 0 Enable hclk to the Internal SRAM and ROM. Enable hclk to the Random Reserved GPIO “N” Enable (GPIOn): Enable hclk to GPIO “N”. Forced to ‘1’ by wake up. Bit 23 = GPIO2, bit 21 = GPIO0. 23:21 RW 111 20 RW 1 DMA Controller Clock Enable (DMA): Enable hclk to the DMA Controller 19 RW 1 MCR Enable (MCR): Enable hclk to MCR (all 3 channels) 18 RW 1 ADC Enable (ADC): Enable hclk to the ADC 17 RW 1 Reserved 16 RW 1 SmartCard Enable (SMC): Enable hclk to the SmartCard Interface 15:14 RW 11 SPI “N” Enable (SPIn): Enable hclk to SPI “n”. Bit 15 = SPI1, Bit 14 = SPI0. 13 RW 1 LCD Enable (LCD): Enable hclk to LCD Display Controller 12 RW 1 Watchdog Enable (WDOG): Enable hclk to the Watchdog Timer 11:03 RW FFh Timer “N” Enable (TMRn): Enable hclk to Timer “n”. Bit 11 = Timer 8, Bit 3 = Timer 0. 02:00 RW 111 UART “N” Enable (UARTn): Enable hclk for UART”n”. Bit 2 = UART2, Bit0 = UART0. DS0200-003 Page 13 Z32AN Series Data Sheet 3.5.4 3.5.5 Offset 00Ch: PMURESET – PMU Reset Register Bits Type Reset Description 31:20 RO 0 Reserved 19 WO 0 Manufacturing Access Disable (MAD): access. Writing a ‘0’ has no effect. 18 RW 0 Manufacturing Access Status: (MAS): When read, this bit indicates the status of manufacturing access. When written as ‘1’, this bit enables manufacturing access. Writes of ‘0’ have no effect. This bit is reset by a system reset (not just a hard reset). 17 WO 0 Peripheral Reset (PERI): When set, causes a reset of all APB peripherals except the PMU, WDT and GPIO. 16 WO 0 Soft Reset (SOFT): When set, causes a system reset. This includes a reset of all modules except the PMU and the WDT. 15:06 RO 0 Reserved 05 RW1C 0 Soft Reset Flag (SOFT_FLAG): When set, system was reset due to a soft reset. Reset only by a POR (not a hard reset). 04 RO 0 Reserved 03 RW1C 0 Watchdog Reset Flag (WDOG_FLAG): When set, the system was reset due to a Watchdog time-out. Reset only by a POR (not a hard reset). 02 RW1C 0 nRSTIN Pin Reset Flag (RST_PIN_FLAG): When set, the system was reset due to the nRSTIN pin being pulled low. Reset only by a POR (not a hard reset). 01 RW1C 0 Over-Voltage Reset Flag (VOVR_FLAG): When set, the system was reset due to a DVDD over voltage detection. Reset only by a POR (not a hard reset). 00 RW1C 0 POR Reset Flag (POR_FLAG): When set, the system was reset due to a DVDD Power-on-Reset condition. Reset only by a POR (not a hard reset). Writing to ‘1’ disables manufacturing Offset 014h: PMUID – PMU ID Register Bits Type Reset 31:16 RO 0 15:10 RO 000010 09:08 RO 01 Package Type (PACKAGE): Indicates BGA 07:00 RO 02h Version Number (VERSNUM): Indicates version AA DS0200-003 Description Reserved Part Number (PARTNUM): Indicates Z32AN series Page 14 Z32AN Series Data Sheet 3.5.6 Offset 01Ch: PMUCFG – PMU Configuration Register Bits Type Reset 31 RO 0 Reserved 30 RW 1 ADC Power Disable (ADC_DIS): When set, enables power to the ADC. 29:27 RW 000 MCR “N” Power Enable (MCRn_IEN): Bit 30 = MCR2, bit 28= MCR0. When set, enables power to the MCR “N” analog front end. Note: all MCR power enable bits must be set to use the MCR 26 RW 0 MCR ADC Power Enable (MCR_ADC_EN): When set, enables power to the MCR ADC. Note: All MCR Power Enable bits must be set to use the MCR 25 RW 0 MCR VREF Power Enable (MCR_VREF_EN): When set, enables power to the MCR voltage reference. Note: All MCR Power Enable bits must be set to use the MCR 24 RW 0 MCR IREF Power Enable (MCR_IREF_EN): When set, enables power to the MCR current reference. Note: All MCR Power Enable bits must be set to use the MCR 23 RW 0 USB Power Enable (USB_EN): When set, enables power to USB 22 RW 0 USB Suspend (USB_SUSP): When set, place USB in suspend mode 21:19 RO 0 Reserved 18 RW 0 USB Wake Enable (USB_WAKE): When set, enable wake when USB not IDLE. 17 RW 0 GPIO Wake Enable (GPIO_WAKE): When set, enables wake on GPIO wake. 16 RW 0 RTC Wake Enable (RTC_WAKE): When set, enables wake on RTC wake. 15:03 RO 0 Reserved DS0200-003 Description 02 RO 0 ROM MMU Table Write mode (ROM_MMU_BUFF): When set, disables the bufferable bit in the ROM MMU table. If the buffer-able bit is set, writes that hit in the cache are marked dirty and written back later. If the buffer-able bit is clear, writes that hit in the cache are written through and memory is updated immediately. The setting of this bit is the inverse of the buffer-able bit that appears in the cacheable region of the ROM MMU table. (See section 5.6.4) 01 RO 0 Reserved 00 RW 0 SRAM Re-Map (SRAM_REMAP): When cleared, ROM appears at the bottom of memory. When set, SRAM appears at the bottom of memory Page 15 Z32AN Series Data Sheet Chapter 4: ARM922T Core and Embedded ICE The ARM922T core of the Z32AN Series contains a JTAG interface and an embedded In-Circuit Emulator (ICE) interface. For more details on these features, refer to the ARM922T Technical Reference Manual. Big Endian handling is not supported by the Z32AN Series. All data is treated as Little Endian. The Z32AN Series supports the following ARM922T clocking modes:    FastBus (CPUCLK = hclk) Synchronous (CPUCLK = fclk, hclk = fclk/N where N = 2, 3, etc.) Asynchronous (CPUCLK = fclk, fclk ≥ hclk) The general restrictions are that fclk ≤ 200 MHz and hclk ≤ 100 MHz DS0200-003 Page 16 Z32AN Series Data Sheet Chapter 5: Memory Organization 5.1 Memory Map FFFFFFFFh FFFC0000h FFFBFFFFh FFFA0000h FFF9FFFFh 60000000h 5FFFFFFFh 40000000h 3FFFFFFFh 20000000h 1FFFFFFFh 1A000000h 19FFFFFFh 19000000h 18FFFFFFh 18000000h 17FFFFFFh 17000000h 16FFFFFFh 16000000h 15FFFFFFh 15000000h 14FFFFFFh 14000000h 13FFFFFFh 13000000h 12FFFFFFh 12000000h 11FFFFFFh 11000000h 10FFFFFFh 10000000h 0FFFFFFFh 00810000h 0080FFFFh 00800000h 007FFFFFh 00414000h 00413FFFh 00410000h 0040FFFFh 00408000h 00407FFFh 00400000h 003FFFFFh 00020000h 0001FFFFh 00010000h 0000FFFFh 00008000h 00007FFFh 00000000h DS0200-003 APB Peripherals AHB Peripherals 256 KB 64 KB Restricted External SDRAM Primary bus 512 MB External SDRAM Secondary bus 512 MB Restricted External nCS9 External nCS8 External nCS7 External nCS6 16 MB 16 MB 16 MB 16 MB External nCS5 16 MB External nCS4 16 MB External nCS3 External nCS0 External nCS2 External nCS1 External nCS0 External nCS0 Restricted External nCS0 CS1 EXT=1 Int SRAM 64KB Restricted Restricted Restricted MMU Table MMU Table Restricted Restricted Int ROM 32KB Int ROM 32KB Restricted Restricted Restricted Restricted Restricted Int ROM 32KB CS3 EXT=1 FFFFF000h Interrupt Controller INTC FFFFE000h Power Management Unit PMU FFFFD000h Reserved 4 KB 4 KB 4 KB FFFFC000h RTC Lock RTC 4 KB FFFFB000h FFFFA000h FFFF9000h FFFF8000h FFFF7000h FFFF6000h FFFF5000h FFFF4000h FFFF3000h FFFF2000h FFFF1000h FFFF0000h FFFEF000h FFFEE000h FFFED000h FFFEC000h FFFEB000h FFFEA000h FFFE9000h FFFE8000h FFFE7000h Real-Time Clock Reserved Reserved Memory Config Registers General Purpose I/O 2 General Purpose I/O 1 General Purpose I/O 0 DMA Controller Mag Card Reader A/D Converter Reserved SmartCard Interface SPI1 Interface SPI0 Interface LCD Controller Watchdog Timer Timer 8 Timer 7 Timer 6 Timer 5 Timer 4 RTC 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB SYSCFG GPIO2 GPIO1 GPIO0 DMAC MCR ADC SMC SPI1 SPI0 LCD WDT TMR8 TMR7 TMR6 TMR5 TMR4 FFFE6000h Timer 3 TMR3 4 KB FFFE5000h FFFE4000h FFFE3000h FFFE2000h FFFE1000h Timer 2 Timer 1 Timer 0 UART2 UART1 TMR2 TMR1 TMR0 UART2 UART1 4 4 4 4 4 FFFE0000h UART0 UART0 4 KB FFFDF000h FFFD0000h Reserved Reserved 4 KB 4 KB FFFDD000h Reserved 4 KB FFFDC000h FFFDB000h FFFDA000h FFFD9000h FFFD8000h Reserved Reserved Reserved Reserved Reserved 4 4 4 4 4 FFFD7000h FFFC0000h FFFBF000h Reserved Reserved USB OTG FFFBC000h FFFBB000h Reserved Reserved FFFA0000h KB KB KB KB KB Reserved FFFBE000h FFFBD000h FFFBA000h KB KB KB KB KB 4 KB 4 KB 4 KB Reserved Int SRAM 64KB (after remap) Page 17 Z32AN Series Data Sheet REMAP=0 5.2 REMAP=1 Accesses All AHB devices can be accessed with byte, halfword or word accesses. APB devices can be read as bytes or halfwords, but should only be written with word accesses. Byte or halfword writes to APB devices are executed as word writes with the defined data being repeated in the other byte lanes to form 32 bits of data. Example: a byte write of AFh results in a word write of AFAFAFAFh). Byte and halfword reads will operate properly on all APB devices, but some data may be lost (when reading a 32-bit wide FIFO register, for example). 5.3 Restricted / Reserved Addresses Accesses to restricted areas will result in a bus error to the requesting device (CPU or DMAC). Addresses shown as reserved will have no effect and will not result in a bus error. 5.4 ROM/SRAM Remapping Remapping is controlled by a bit in the PMU registers. ROM/SRAM remapping is shown below: 5.5 Address REMAP = 0 REMAP = 1 00000000h - 00007FFFh Internal ROM (32KB) 00008000h - 0000FFFFh Restricted 00400000h - 00407FFFh Internal ROM (32KB) Internal ROM (32KB) 00800000h - 0080FFFFh Internal SRAM (64KB) Restricted Internal SRAM (64KB) Internal SRAM The internal SRAM is 64 KB of 0 wait-state memory. 5.5.1 Clock Disable The clock to the SRAM can be disabled via PMU registers to reduce the power consumption of this module (see System Clocks and Power Management. This clock disable does not disrupt the contents of the memory. 5.5.2 Zeroization The internal SRAM can be automatically cleared by writing 1 to bit 0 in INT_SRAM_CLR.CLR. Clearing takes 64k hclks. During this time, reads of the SRAM are stalled. 5.5.3 Address FFFF8068h: INT_SRAM_CLR – Internal SRAM Clear Register Bits Type Reset 31:01 RO 0 Reserved 00 RW 0 Clear (CLR): When written to ‘1’, hardware writes 0’s to internal SRAM from top address to zero. When read as ‘0’, the internal clear-to-zero is done. While still set to ‘1’, the clear-to-zero is still in progress. A write of ‘0’ has no effect. DS0200-003 Description Page 18 Z32AN Series Data Sheet 5.6 Internal ROM and Boot Program After reset, the ARM CPU begins executing code out of the internal ROM at address 0h. 5.6.1 Boot locations After reset, boot code will search both the primary secondary busses for a valid image. It searches for a fixed constant at a specific memory location to determine if a valid image exists on that memory bus and chip select To facilitate initial programming and code updates, boot code is also capable of downloading an application using one of the UARTs. It checks GPIO[0] at startup. If ‘1’, it searches for an application to download using one of the UARTs. 5.6.2 External Memory Image Format Offset ... Application Start ... Contents Application Code Comments Code The space between the application info and application code can be any user defined data User defined Application Info Program to be executed Application Length Application Start Length of the application First non-zero word above the ECB 1Ch 00000000h Reserved 18h 00000000h Reserved 14h 00000000h Reserved 00000000h Reserved 10h 0Ch External Control Block (ECB) D3C2B1A0h Fixed constant for quick checking of the image 08h MEMC_GCFG Register value loaded by Boot ROM into MEMC 04h MEMC_TIM0 Register value loaded by Boot ROM into MEMC 00h MEMC_CFG0 Register value loaded by Boot ROM into MEMC The External Control Block contains:    DS0200-003 Memory bus width in MEMC_CFG0. The location of byte 0 appears at the same location in both 8-bit and 16-bit wide memories. Fixed constant with the value of D3C2B1A0h. This is used to check that a valid boot image exists in this external memory. MEMC and PMU register values. These are loaded into their corresponding registers by the boot code. This is to allow for optimal memory access time for the remainder of the load process. Page 19 Z32AN Series Data Sheet 5.6.3 5.6.3.1 Boot Sequence Download Pin (GPIO[0]) Before boot code begins searching external memory, it checks GPIO[0]. If this pin is high, boot code skips external memory checks and tries to download an image from a UART. 5.6.3.2 External Memory   5.6.3.3 Bus Search: Boot code searches for code in external memory on nCS[0]. It searches the secondary bus first followed by the primary bus. Bus Width: Boot code initially sets up the memory controller for the maximum timings. The boot code will first read the byte at offset 0 to determine the memory bus width. The boot code programs this value into MEMC_CFG0.  Fixed Constant: Boot code then reads the data word at offset 0Ch for the fixed constant D3C2B1A0h. If the boot code finds it, it reads the rest of the External Control Block (ECB) parameters and sets up the memory controller timings and PLL based upon the ECB settings.  Starting Address: If the External Control Block was found, the boot code will then search for the application start address immediately after the ECB. The application start address is the first non-zero word following the ECB. Once the application start pointer is found, boot code jumps to this application start address. Since ARM code must be word aligned, this address must be word aligned. The CPU is placed in its reset state (the MMU and caches are disabled) before branching to the start address. UART Download If an image was not found in external memory, or if the download pin GPIO[0] was asserted, the boot code tries to load an image from one of the UARTs. The boot code will search all of the UARTs for download activity. Since the operating frequency of the device is unknown, boot code uses the timers to perform automatic baud rate detection. It expects the first character received to be the ASCII carriage return character ‘\r’ 013. The timers will measure the length from the end of the start bit to the beginning of the stop bit to determine the baud rate. The UART is setup using 8 data bits, no parity,1 stop bit. The maximum baud rate is limited by the capability of the UART and system clock. A rate of 115k baud is achievable using a 24MHz clock. Once the baud rate is setup, boot code displays a prompt as confirmation that the baud rate is setup correctly. The boot code then expects an Intel hex file to be sent. This file is loaded at address 0. Once download is complete (end of file record found), boot code executes the application at address 0. 5.6.4 Boot ROM MMU Table A simple MMU table is implemented starting at address 00410000h. The Virtual to Physical mapping as well as the Cacheable/Bufferable settings are shown below. DS0200-003 Virtual Address Physical Address Cacheable/Bufferable Comments FFFFFFFFh ... C0000000h FFFFFFFFh ... C0000000h None APB Devices FFFFFFFFh ... C0000000h FFFFFFFFh ... C0000000h Non-Cacheable & Non-Bufferable Peripherals BFFFFFFFh ... 80000000h 3FFFFFFFh ... 00000000h Non-Cacheable & Non-Bufferable Non-cacheable view of lowest quadrant. 7FFFFFFFh ... 00000000h 7FFFFFFFh ... 00000000h Cacheable & Bufferable (write-back mode) Page 20 Z32AN Series Data Sheet Chapter 6: Interrupt Controller (INTC) The interrupt controller is an APB device that prioritizes and routes all interrupt channels from internal peripherals and external devices to the CPU. Features:     IRQ or FIQ generation for each interrupt source (programmable) Unique vectors for each interrupt channel Programmable priority for each channel (8 priority levels) Support for nesting and preemption by higher priority interrupts (IRQ only) Interrupts are first fed into a Priority Encoder. The highest priority enabled interrupt is passed on to either the IRQ or FIQ Processor. These are nearly identical and fully independent of each other – the INTC does not prioritize FIQ delivery over IRQ delivery. These blocks pass interrupt requests to the CPU and provide the proper vector when software reads the vector register. Additionally, the IRQ processor includes support for interrupt nesting (interruption of ISRs). 6.1 Interrupt Channels and Sources Table 6-1: Interrupt Source to Channel Mapping 6.2 # Source # Source # Source # Source 0 TMR6 8 TMR5 16 GPIO2 A 24 SPI1 1 WDT 9 SmartCard Alarm 17 GPIO2 B 25 UART1 2 UART0 10 SmartCard 0 18 DMAC 26 UART2 3 TMR0 11 SmartCard 1 19 MCR 27 Reserved 4 TMR1 12 GPIO0 A 20 USB 28 RNG 5 TMR2 13 GPIO0 B 21 Reserved 29 RTC 6 TMR3 14 GPIO1 A 22 ADC 30 TMR7 7 TMR4 15 GPIO1 B 23 SPI0 31 TMR8 Interrupt Priority Each interrupt channel can be assigned a priority level from 0 (highest) to 7 (lowest). This is done by programming the INTC_CFGN. The interrupt priority level is only effective if the channel is configured as an IRQ interrupt (not FIQ). All FIQ interrupts are considered to have a priority of 0. The priority has two effects:   DS0200-003 If two or more enabled interrupts of the same type (IRQ/FIQ) arrive at the same time, the higher priority interrupt will be serviced first. If two or more interrupts of the same priority arrive, the interrupt with the lower channel number will have priority. When using nested interrupts, only an interrupt of a higher programmed priority will generate a new (nested) interrupt to the CPU. Interrupts of the same or lower priority are masked until the CPU has indicated the completion of the ISR by writing to the INTC_IEND (or INTC_FEND for FIQ) Page 21 Z32AN Series Data Sheet 6.3 Configuring the Interrupt Controller Prior to configuring a particular channel, a number of settings must be made: 1. The ARM exception table should be set up. This typically is done by remapping the SRAM to appear at the bottom of memory and placing the following ARM instruction at locations 0x00000018 (IRQ Vector) and 0x0000001C (FIQ Vector) as shown in the example below: o LDR PC, [PC,#0xFFFFFF00 - (0x18+8)] ; IRQ Vector (located at A=0x0018) o LDR PC, [PC,#0xFFFFFF04 - (0x1C+8)] ; FIQ Vector (located at A=0x001C) 2. INTC_DFLT should be initialized to the address of an error handling ISR. This is to provide a vector for error handling in the case where INTC_IVEC or INTC_FVEC are read when there is no interrupt active. This usually indicates a spurious interrupt or a software error. Set up any or all of the interrupt channels. The following registers and fields are used: o INTC_CFGN → IRQ_FIQ, PRI o INT_VEC_N → All Bits o INTC_EN → Bit “N” 3. 4. 6.4 The “I” and/or “F” bits of the ARM922T CPSR register should be cleared to enable IRQ and/or FIQ interrupts. ISR Invocation Below is an example of how the CPU, ARM Exception Table, INTC_VECN’s, and INTC_IVEC operate together to invoke a Channel 1 ISR upon occurrence of a Channel 1 interrupt. Note the sequence of steps listed at the bottom of the table. FIQ ISR invocation is almost identical, except that the CPU will read the FIQ vector in the ARM exception table and this will cause INTC_FVEC to be read. 6.5 1. IRQ is set up: o The IRQ Vector, INTC_VEC_1 are initialized and the Channel 1 ISR is located as shown above. o Channel 1 is configured as an IRQ (as opposed to an FIQ), programmed to have the highest priority, and enabled. o A channel 1 interrupt enters the INTC, which is passed on to the CPU by activating IRQ. 2. An active IRQ causes the CPU to execute the IRQ vector instruction at 00000018h: o LDR PC, [PC, #0xFFFFFF00-(0x18+8)] 3. 4. 5. LDR instruction causes CPU to read memory location FFFFFF00h (INTC_IVEC). INTC provides the vector of the highest priority active interrupt (00000180h). CPU move the data 00000180h) into PC. Program execution then continues at this address. ISR Return from Interrupt Before returning from an IRQ or FIQ interrupt, the ISR must write to INTC_IEND or INTC_FEND. The data written is not important and is discarded. After this write is done, the final instruction of an IRQ or FIQ ISR must restore the PC and CPSR. When using nested interrupts, the interrupts should be disabled before writing to INTC_IEND. 6.6 Interrupt Nesting The IRQ processor nests interrupts (preemption of an ISR by a higher priority interrupt). The FIQ processor cannot nest interrupts. Active and enabled interrupt channels with a higher programmed priority always result in an interrupt being passed on to the CPU (via either IRQ or FIQ). To utilize this feature, software must clear the “I” bit of the ARM922T CPSR register within the ISR to re-enable interrupts, thereby “enabling” interrupt nesting. More information can be found in Chapter A2, Programmer’s Model of the ARM Architecture Reference Manual. To keep track of the nested interrupts, the IRQ Processor contains a priority stack. Since there are 8 priorities, the stack is 8 deep. A read of INTC_IVEC pushes the stack. A write to INTC_IEND pops the stack. During the time between push and pop, interrupts of the same or lower priority are masked. The programmer’s responsibility is to ensure there is a write to INTC_IEND every read of INTC_IVEC. DS0200-003 Page 22 Z32AN Series Data Sheet Certain registers within the ARM922T may be overwritten by nested interrupts, namely SPSR and LR(R14). These registers should be saved prior to re-enabling interrupts and restored after interrupts are re-disabled. Refer to the ARM Architecture Reference Manual for complete information. 6.7 Interrupt Latching Interrupts are not latched within the INTC and it is the responsibility of the ISR to perform whatever operations are necessary to clear the interrupt at the source peripheral where it is latched. An enabled interrupt into the INTC will be passed on to the CPU via the IRQ/FIQ signals. This interrupt will remain active until cleared at the source or the corresponding interrupt enable bit is cleared. 6.8 6.8.1 Registers: Base → FFFFF000h Offset Register Description 000h INTC_EN Interrupt Enable Register 004h INTC_ESET Interrupt Enable Set Register 008h INTC_ECLR Interrupt Enable Clear Register 00Ch INTC_DFLT Default Vector 010h INTC_ISTA Interrupt Status Register 014h INTC_RSTA Raw (Unmasked) Interrupt Status Register 018h INTC_IDBG IRQ Processor Debug Register 01Ch INTC_FDBG FIQ Processor Debug Register 020h INTC_SWINT 024h INTC_SWINT_SET Software interrupt register Software interrupt set register 028h INTC_SWINT_CLR Software interrupt clear register 080h - OFCh INTC_VECN Channel “N” Vector Register (N = 0 to 31) 100h – 17Ch INTC_CFGN Channel “N” Configuration Register (N = 0 to 31) F00h INTC_IVEC IRQ Vector Register F04h INTC_FVEC FIQ Vector Register F08h INTC_IEND IRQ End-of-Interrupt Register F0Ch INTC_FEND FIQ End-of-Interrupt Register Offset 000h: INTC_EN – Interrupt Controller Enable Register Bits 31:00 DS0200-003 Type RW Reset 0 Description Enable (EN): When set, enables the corresponding channel. Bit 0 enables channel 0, Bit 1 enables channel 1, etc. These bits can be set or cleared by writing directly to it, or by writing to INTC_ESET and INTC_ECLR. Page 23 Z32AN Series Data Sheet 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 Offset 004h: INTC_ESET – Interrupt Controller Enable Set Register Bits Type Reset 31:00 WO 0 Description Set (SET): Wires of ‘1’ set the corresponding bit in INTC_EN. Offset 008h: INTC_ECLR – Interrupt Controller Enable Clear Register Bits Type Reset 31:00 WO 0 Description Clear (CLR): Writes of ‘1’ clear the corresponding bit in INTC_EN. Offset 00Ch: INTC_DFLT – Default Vector Register Bits Type Reset 31:00 RW 0 Description Default Vector (VEC): Contains the value to appear in either INTC_IVEC or INTC_FVEC in the case that no IRQ or FIQ is active when that register is read. Should be loaded with a valid ISR address (to handle this error condition). Offset 010h: INTC_ISTA – Interrupt Status Register Bits Type Reset 31:0 RO 0 Description Status (STS): Indicates which enabled (non-masked) interrupts are active. Bit 0 corresponds to channel 0, Bit 1 enables channel 1, etc. When cleared, the interrupt is either not enabled or not active. When set, the interrupt is enabled and active. Offset 014h: INTC_RSTA – Raw Interrupt Status Register Bits Type Reset 31:00 RO 0 DS0200-003 Description Status (STS): Indicates which interrupts are active before masking. Bit 0 corresponds to channel 0, Bit 1 enables channel 1, etc. When cleared, the interrupt is active. When set, the interrupt is not active. Page 24 Z32AN Series Data Sheet 6.8.7 6.8.8 6.8.9 Offset 018h: INTC_IDBG – IRQ Processor Debug Register Bits Type Reset Description 31:12 RO 0 Reserved 11:08 RO 0h Stack Pointer (STACK): Holds the current stack pointer for the IRQ Processor Stack.  0000: Stack is empty; no entries are valid.  0001: Stack holds one value.  ....  1000: Stack is full (holds 8 values). 07:03 RO 0 Reserved 02:00 RO 0 Current Level (CURRLV): Indicates the current priority level. Offset 01Ch: INTC_FDBG – FIQ Processor Debug Register Bits Type Reset Description 31:12 RO 0 Reserved 11:08 RO 0h Stack Pointer (STACK): Holds the current stack pointer for the FIQ Processor Stack. Since nesting is not permitted for an FIQ, this field only holds only values of 0000 or 0001.  0000: Stack is empty; no entries are valid.  0001: Stack holds one value.  0010 – 1000: Invalid. 07:03 RO 0 Reserved 02:00 RO 0 Current Level (CURRLV): Indicates the current priority level. Offset 020h: INTC_SWINT – Software Interrupt Register Bits Type Reset 31:00 WO 0 Description Enable (EN): Each bit causes a software interrupt for each of the INTC channels. Bit 0 for channel 0, Bit 1 for channel 1, etc. These bits can be set or cleared by writing directly to it, of by writing to the INTC_SWINT_SET and INTC_SWINT_CLR. 6.8.10 Offset 024h: INTC_SWINT_SET – Software Interrupt Set Register Bits DS0200-003 Type Reset Description Page 25 Z32AN Series Data Sheet 31:00 WO 0 Set (SET): Writes of ‘1’ set the corresponding bit in INTC_SWINT. 6.8.11 Offset 028h: INTC_SWINT_CLR – Software Interrupt Clear Register Bits Type Reset 31:00 WO 0 Description Clear (CLR): Writes of ‘1’ clear the corresponding bit in INTC_SWINT 6.8.12 INTC_VECN – Channel N Vector Register Offset Channel Offset Channel Offset Channel Offset Channel 080h 0 0A0h 8 0C0h 16 0E0h 24 084h 1 0A4h 9 0C4h 17 0E4h 25 088h 2 0A8h 10 0C8h 18 0E8h 26 08Ch 3 0ACh 11 0CCh 19 0ECh 27 090h 4 0B0h 12 0D0h 20 0F0h 28 094h 5 0B4h 13 0D4h 21 0F4h 29 098h 6 0B8h 14 0D8h 22 0F8h 30 09Ch 7 0BCh 15 0DCh 23 0FCh 31 There is one register per interrupt channel, as shown in the table above. The bits in each register are described in the table below. Bits Type Reset 31:00 WO 0 DS0200-003 Description Vector (VEC): Contains the value to appear in either INTC_IVEC or INTC_FVEC when channel N is the highest priority active interrupt. Page 26 Z32AN Series Data Sheet 6.8.13 INTC_CFGN – Channel N Configuration Register Offset Channel Offset Channel Offset Channel Offset Channel 100h 0 120h 8 140h 16 160h 24 104h 1 124h 9 144h 17 164h 25 108h 2 128h 10 148h 18 168h 26 10Ch 3 12Ch 11 14Ch 19 16Ch 27 110h 4 130h 12 150h 20 170h 28 114h 5 134h 13 154h 21 174h 29 118h 6 138h 14 158h 22 178h 30 11Ch 7 13Ch 15 15Ch 23 17Ch 31 There is one register per interrupt channel, as shown in the table above. The bits in each register are described in the table below. Bits Type Reset 31:04 RO 0 Reserved 03 RW 0 IRQ/FIQ (IRQ_FIQ): When cleared, channel N produces an IRQ. When set, channel N produces an FIQ. 02:00 RW 000 Description Priority (PRI): Specifies the interrupt priority for channel N.  000: Priority 0 (highest priority)  ...  111: Priority 7 (lowest priority) 6.8.14 Offset F00h: INTC_IVEC – IRQ Vector Register Bits Type Reset Description 31:00 RO Undef Interrupt Vector (VEC): Contains the value of INTC_VECN associated with the highest priority IRQ interrupt. Reading this register pushes the priority of the associated interrupt onto the IRQ Processor Stack (see section 6.6). If no enabled IRQ is active, contains the value of INTC_DFLT. 6.8.15 Offset F04h: INTC_FVEC – FIQ Vector Register Bits 31:00 DS0200-003 Type RO Reset Description Undef Fast IRQ Vector (VEC): Contains the value of INTC_VECN associated with the highest priority FIQ interrupt. If no enabled FIQ is active, contains the value of INTC_DFLT. Page 27 Z32AN Series Data Sheet 6.8.16 Offset F08h: INTC_IEND – IRQ End-of-Interrupt Register Bits Type Reset Description 31:01 RO 0 Reserved 00 WO 0 End (END): A write to this register pops the IRQ Processor Stack. The written value is discarded and has no other effect. 6.8.17 Offset F0Ch: INTC_FEND – FIQ End-of-Interrupt Register Bits Type Reset 31:01 RO 0 Reserved 00 WO 0 End (END): No effect. FIQ cannot be nested. DS0200-003 Description Page 28 Z32AN Series Data Sheet Chapter 7: External Bus Interface (EBI) The EBI consists of the following blocks:   External Memory Controller (MEMC): The primary bus supports standard asynchronous memories (such as SRAM, ROM, Flash, etc.), I/O devices, and asynchronous PSRAM. SDRAM Controller: This provides direct interfacing to standard SDRAM. MA[23:0], MD[15:0], SA[22:0], and SD[15:0] are all actively driven low whenever idle. 7.1 Asynchronous Memory Controller This controller interfaces to up to 10 external memory or I/O devices. Features:      7.1.1 Asynchronous memory support (SRAM, ROM, Flash, PSRAM, Flash etc.) Support for I/O devices which utilize an asynchronous SRAM-like interface Programmable setup, hold, access and burst timings for each chip select Optional ready/wait line for each chip select Support for single asynchronous reads and writes, and asynchronous page reads. Programmable Features Each chip select has a number of programmable features which can be configured via MEMC_CFGN. Some are listed below. 7.1.1.1 Ready/Wait The READY pin can be used to extend the read and write access times until signaled by an external slave device. Two configuration bits are provided for each chip select: one enables or ignores the READY pin; the other sets the polarity as READY or nREADY. READY can only be used for the primary and not the secondary or the secondary and not the primary. This is because each bus has its own controller and can act independently of the other (Primary and Secondary accesses can occur at the same time). If HREADY is enabled for Chip Selects on both buses, conflicts can occur since accesses to peripherals which use the HREADY line could occur at the same time. There is no internal arbitration for the HREADY pin. Each Chip Select will respond to the HREADY if programmed to do so. 7.1.1.2 Device Data Width 8-bit and 16-bit devices are supported. Both can be accessed transparently over AHB with byte, half-word, word and burst accesses. 7.1.1.3 Byte Control Style 16-bit devices can be accessed with two write enables and no byte enable, or with a single write enable and two byte enables. The table below shows the muxing which can be done to support these cases. Table 7-1: Pin Functions vs. Control Style Byte Control Style Settings Width Style nWEU nWEL A[0] 0 (8-bit) 0 (no BE) 1 nWE A[0] 1 (BE) nBE nWE A[0] 0 (no BE) nWEU nWEL 0 1 (BE) nBEU nWE nBEL 1 (16-bit) DS0200-003 Z32AN Series Pin Function Page 29 Z32AN Series Data Sheet 7.1.1.4 Extending CS0 memory space The default memory range for CS0 is16MB or 128Mb is extended to 32MB by using the CS1 address space. MEMC_CFG_1.EXT has been added for CS1 and CS3 only. When ‘0’, CS0 is ‘0’ from address 10000000h – 10FFFFFFh (16MB) as presently specified. When EXT is ‘1’ for CS1, CS0 is ‘0’ for addresses 10000000h – 11FFFFFFh or 32MB (256Mb) and CS1 becomes the 25th address bit, A[24], for either the primary or secondary bus depending on programmable selection. The CS1 pin as A[24] is inverted. When EXT is ‘1’ for CS3, CS0 is ‘0’ for addresses 10000000h - 10FFFFFFh and 13000000h – 13FFFFFFh or 32MB (256Mb) and CS3 becomes the 25th address bit, A[24], for either the primary or secondary bus depending on programmable selection. The CS3 pin as A[24] is inverted. To use CS1 or CS3 as A[24], an inverter may be added to the output of this signal to address the larger 256Mb memory device. Figure 7-1: CS1 as A[24] Operation is the same for CS1 of CS3 except for the address space. CS1 is used here to explain the function. After reset, the boot ROM reads CS0 which sets CS0 =0 and CS1= 1 (default memory configuration). The inverter will drive A24 low, placing the start of the larger memory at 10000000h. The boot ROM checks memory for a valid boot image and if valid, control is turned over to this memory. When a larger memory device is used (256Mb) then the user code must set MEMC_CFG_1.EXT to ‘1’, to extend the memory range for CS0. This must be done within the first 16MB or 128Mbits of code space. After MEMC_CFG_1.EXT is set to ‘1’, CS0 is ‘0’ for the entire address space 10000000h – 11FFFFFFh. CS1 is ‘0’ for address spaces 11000000h – 11FFFFFFh. The rest of the time CS1 is ‘1’. Since CS1 behaves as an inverted address bit going into the memory, the external inverter on CS1 will cause correct behavior of A[24] for the address space 10000000h – 11FFFFFFh. DS0200-003 Page 30 Z32AN Series Data Sheet 7.1.2 Asynchronous Single Read and Write Transactions The programmable timing associated with the single reads and writes are shown below. The example provided here has settings of NRS=3, NRA=3, NRH=1, NWS=3, NWA=3, NWH=1, NRWI and READY ignored. hclk is the reference for cycle timing. Back-to-back accesses will be performed with the chip select remaining constantly active, if the timing of the requests and the programmed parameters allow it. Figure 7-2: Single Read/Write Timing Diagram Table 7-2: Single Read/Write Timing (based on MEMC_TIMN) Symbol Description tRS Read Cycle Setup Time: Specifies the number of half clock cycles of setup time before nOE goes active during a read cycle. Also, this specifies setup time for A and nCS as well as provides time for D to go high-Z. tRA Read Access Time: Specifies the number of clock cycles before data is samples and nOE returns to inactive. tRH - or - Read Cycle hold Time: Specifies the number of clocks that OEn is inactive before the end of the read cycle. This time is increased by a half clock if NRS[0]=1. tRWI Read/Write Idle Time: Specifies the minimum number of clocks after a read before a subsequent write cycle, access on a different chip select, or data bus clamping can occur. tWS Write Cycle Setup Time: Specifies the number of half clock cycles of setup time before nWE goes active during a write cycle. Also, this specifies setup time for A, D and nCS. tWA Write Access Time: Specifies the number of clock cycles before data is sampled and nOE returns to inactive. tWH DS0200-003 Equation - or - Write Cycle Hold Time: Specifies the number of clocks that OEn is inactive before the end of the write cycle. This time is increased by a half clock if NWS[0]=1. Page 31 Z32AN Series Data Sheet 7.1.3 Asynchronous Page Read Transactions The programmable timing of asynchronous page reads are shown below. For page reads, the burst is continued until the end of the request is reached, or until the page boundary is reached, whichever occurs first. The example provided here has settings of NRS=3, NRA=3, NRPA=2, NRH=1, NRWI=0 and READY is ignored. Figure 7-3: Asynchronous Page Read Timing Diagram Table 7-3: Asynchronous Page Read Timing (based on MEMC_TIMN) Symbol Formula Read Cycle Setup Time: Same as for single cycle access tRS Read Access Time: Same as for single cycle access tRA Read Page Access Time: Specifies the number of clocks to wait to sample read data again for a sequential page read. tRPA tRH DS0200-003 Description - or - Read Cycle Hold Time: Same as for single cycle access Page 32 Z32AN Series Data Sheet 7.1.4 Clock Divided Transactions MEMC_CFG.FCLK_DIV divides hclk to allow access to slow peripherals that do not have a READY pin. The example provided here has settings of NRS=1, NRA=3, NRH=1, NRWI=1, NWS=1, NWA=3, NWH=1 and READY ignored. Figure 7-4: flclk Based Timing Diagram Table 7-4: Extended Timing Parameters (based on MEMC_TIMN) Symbol tFLCLK DS0200-003 Formula Description Clock Division: Controls the frequency of flclk by dividing hclk. tRS Read Setup Time: Number of flclks before nOE goes active during a read. tRA Read Access Time: Number of flclks after nOE active before first data sampled. tRH Cycle Hold Time: Number of hclks between nOE inactive and end of the cycle. tRWI Read/Write Idle Time: Number of clocks after a read before a subsequent write cycle, access on a different chip select, or data bus clamping can occur. tWS Write Setup Time: Number of clocks before nWE, A, D, and nCS active on a write. tWA Write Access Time: Number of clocks before data is sampled and nOE inactive. tWH Write Hold Time: Number of clocks nOE is inactive before end of write cycle. Page 33 Z32AN Series Data Sheet 7.2 SDRAM Controller Key features of SDRAM Controller: 7.2.1   Support for 64 Mb, 128 Mb, 256 Mb and 512 Mb SDRAM devices Direct interface for two 16-bit SDRAM devices (if both interfaces are used, the SDRAM used must be the same on each interface)   Programmable timing parameters Support for entering and exiting power-down modes Operation Once configured, the SDRAM controller interfaces to a x16 SDRAM configuration and allows any AHB master to access memory transparently. Byte, half-word and word accesses are supported. In addition, burst accesses are supported. AUTO_REFRESH commands are issued automatically based on the user configuration. Power saving modes can be controlled by user commands and configuration. Address Mapping 10 11 1 00 11 11 10 11 DS0200-003 B[1:0] ROW[10:0] ROW[10:0] B[1:0] B[1:0] ROW[11:0] B[1:0] B[1:0] ROW[12:0] B[1:0] B[1:0] B[1:0] 0 1 2 3 4 5 6 COLUMN[8:0] COLUMN[10:0] B[1:0] ROW[12:0] COLUMN[7:0] COLUMN[9:0] B[1:0] ROW[12:0] ROW[12:0] COLUMN[8:0] COLUMN[10:0] B[1:0] ROW[11:0] COLUMN[7:0] COLUMN[9:0] B[1:0] ROW[11:0] ROW[11:0] 7 COLUMN[10:0] ROW[10:0] ROW[10:0] 8 9 10 11 12 15 16 13 COLUMN[8:0] COLUMN[9:0] ROW[12:0] 00 01 17 ROW[12:0] 00 10 COLUMN[7:0] ROW[12:0] 01 10 18 19 20 B[1:0] B[1:0] 01 01 COLUMN[10:0] ROW[12:0] 00 10 COLUMN[9:0] ROW[11:0] B[1:0] B[1:0] COLUMN[8:0] ROW[11:0] B[1:0] 01 COLUMN[7:0] ROW[11:0] B[1:0] 00 COLUMN[10:0] ROW[11:0] B[1:0] 10 COLUMN[9:0] ROW[10:0] B[1:0] 01 COLUMN[8:0] ROW[10:0] B[1:0] 00 COLUMN[7:0] ROW[10:0] B[1:0] 11 11 ROW[10:0] B[1:0] 10 10 21 B[1:0] 01 01 22 23 00 24 00 25 COL 0 26 ROW Memory Address INTER SDR_CFG 14 7.2.2 COLUMN[7:0] COLUMN[8:0] COLUMN[9:0] COLUMN[10:0] Page 34 Z32AN Series Data Sheet 7.2.3 7.2.4 Supported Configurations 64 Mb 128 Mb 256 Mb 512 Mb Configuration 4 Meg x 16 8 Meg x 16 16 Meg x 16 32 Meg x 16 Row Addressing 4K : A[11:0] 4K : A[11:0] 8K : A[12:0] 8K : A[12:0] Bank Addressing 4 : BA[1:0] 4 : BA[1:0] 4 : BA[1:0] 4 : BA[1:0] Column Addressing 256 : A[7:0] 512 : A[8:0] 512 : A[8:0] 1K : A[9:0] SDRAM Performance Access Type Single Read: Byte, Half-Word or Word 4-Burst Read 8-Burst Read AHB Clocks Bank Available 8 Page Hit 6 Page Miss 11 Bank Available 8-2-2-2 Page Hit 6-2-2-2 Page Miss 11-2-2-2 Bank Available 8-2-2-2-2-2-2-2 Page Hit 6-2-2-2-2-2-2-2 Page Miss 11-2-2-2-2-2-2-2 Bank Available 1 Page Hit 1 Page Miss 1 Bank Available 5-2-2-2 Page Hit 3-2-2-2 Page Miss 8-2-2-2 Bank Available 5-2-2-2-2-2-2-2 Page Hit 3-2-2-2-2-2-2-2 Page Miss 8-2-2-2-2-2-2-2 Single Read followed immediately by Single Write (same page) Bank Available 8-2 Page Hit 6-2 Page Miss 11-2 Single Write followed immediately by Single Read (same page) Bank Available 5-5 Page Hit 3-5 Page Miss 8-5 Single Write: Byte, Half-Word or Word 4-Burst Write 8-Burst Write 7.2.5 Page Status Notes D-Cache or I-Cache line fill D-Cache half-line dirty D-Cache or I-Cache line fill Open Bank Policy The SDRAM Controller leaves all pages open if possible. Banks are closed by page misses and refresh commands. DS0200-003 Page 35 Z32AN Series Data Sheet 7.2.6 Power Saving Modes 3 power savings modes are available to the SDRAM controller:    Pre-charge Standby: This state is the same as Active Standby, except that all banks are closed. In this case, nCS = 1 and CKE = 1. To close all banks, This is entered via a PRECHARGE_ALL command to SDR_CMD, or when the refresh timer times out. Apart from periodic refreshes generated by the SDRAM Controller, no commands are issued to the SDRAM. There is no penalty delay incurred when a memory access invokes Active Operation. Pre-charge Power Down: In this mode, all banks are closed and nCS = 1 and CKE = 0. This state is entered either by a POWER_DOWN command issued to SDR_CMD or by the powerdown timer of SDR_APD. In this mode, SDCLK may be configured to be properly disabled and re-enabled automatically. Self Refresh: In this mode, all banks are closed and nCS = 1 and CKE = 0. This state is entered either by a SELF_REFRESH command issued to SDR_CMD or by the power-down timer of SDR_APD. In this mode, SDCLK may be configured to be properly disabled and reenabled automatically. While the SDRAM controller is operating on the external memory (nCS = 0 and CKE = 1), SDRAM is not in a power saving mode. No matter what power down state is active, any access causes an immediate transition to this state. For the Active Standby and Auto Refresh states, there is no performance penalty associated with the access. For the Power-Down and Self-Refresh states, there is a delay to transition to the Active state. 7.2.7 Pin Multiplexing Multiplexing the bank, row and column bits is described in section 7.2.2. Within the EBI, additional pin multiplexing and de-multiplexing occurs. For more details, see section 7.1. ►Note: DQMU, DQML, nRAS, nCAS, and nWE are also multiplexed on Address pins 19-18 and 15-13 for the secondary interface. 7.2.8 7.2.8.1 Programmer’s Guide Initialization Initialization is achieved through a sequence of delays and SDRAM commands. This sequence is device dependent, but a general sequence is provided below; this is an example initialization only – refer to the SDRAM datasheet for a more specific initialization sequence. 1. 2. 3. 4. 5. 6. 7.2.8.2 Set the SDRAM clock enable and frequency via PMU registers (Power and SDRAM clocks). Configure the SDRAM Controller by writing to SDR_CFG and SDR_RFSH. Wait for 100 µs (time required for the SDRAM Controller to initialize). During this time, the SDRAM controller will drive CS inactive (COMMAND_INHIBIT). Initiate a PRECHARGE_ALL command to the SDRAM by writing to SDR_CMD. Initiate two AUTO_REFRESH commands to the SDRAM by writing twice to SDR_CMD. Initiate a LOAD_MODE_REGISTER command to the SDRAM by writing to SDR_CMD. By design, the SDRAM Controller waits at least two clocks before issuing a subsequent command. Refresh Control AUTO_REFRESH cycles are performed automatically at a period based upon SDR_RFSH. The setting of the timer register depends on SDCLK frequency as well as the number of rows and tREF for the SDRAM. The register must be set according to the following equation: Additionally, the user can perform a refresh by sending the AUTO_REFRESH command of SDR_CMD. DS0200-003 Page 36 Z32AN Series Data Sheet 7.2.8.3 Zeroization Command The SDRAM Controller is capable of clearing all SDRAM memory locations to 0 by issuing a ZEROIZATION command to SDR_CMD. During this operation, all locations are cleared at an approximate rate of one halfword per SDCLK cycle. Once started, you cannot stop this command before it is completed. 7.3 Example Configurations Below is a diag1./ram showing an example configuration, and the register settings for that configuration. The register programming for this configuration is:    SDR_CMD.SEC_SDRM_EN set to ‘1’ to enable use of the secondary bus and nCS[1] for SDRAM MEMC_CFG_2.PRI_SEC cleared to ‘0’ (primary bus) MEMC_CFG_0.PRI_SEC cleared to ‘0’ (primary bus) Figure 7-5: External Memory Example DS0200-003 Page 37 Z32AN Series Data Sheet Figure 7-6: Connection to an 8-bit SRAM Device Figure 7-7: Connection to a 16-bit SRAM Device Figure 7-8: Connection to a 16-bit SRAM Device with Byte Enable DS0200-003 Page 38 Z32AN Series Data Sheet Figure 7-9: Connection to 2 x 8-bit SRAM Devices Figure 7-10: Connection to an 8-bit FLASH Device Figure 7-11: Connection to a 16-bit FLASH Device DS0200-003 Page 39 Z32AN Series Data Sheet Figure 7-12: Sync Burst Flash Configuration (AM29BL802C) Figure 7-13: Connection to two 4M byte x 8-bit FLASH Devices DS0200-003 Page 40 Z32AN Series Data Sheet 7.4 Registers (Base → FFFF8000h) DS0200-003 Offset Register Description 000h SDR_CFG SDRAM Configuration Register 004h SDR_CMD SDRAM Command interfaces) 008h SDR_RFSH SDRAM Refresh Register 00Ch SDR_APD SDRAM Automatic Power-Down Register 010h MEMC_GCFG Global Configuration Register 014h – 038h MEMC_CFGn nCS[“n”] Configuration Register 03Ch – 060h MEMC_TIMn nCS[“n”] Timing Register 064h MEMC_STA Status Register Register (for both Page 41 Z32AN Series Data Sheet 7.4.1.1 Offset 000h: SDR_CFG – SDRAM Configuration Register Bits Type Reset Description 31:25 RO 0 Reserved 24 RW 0 Interleave Address (INTER): When cleared, bank address derived from MSBs. When set, bank address derived from address bits between the column (LSBs) and the row (MSBs). See section 7.2.2. 23:22 RO 00 Reserved 21:20 RW 00 Row Width (ROW): Row bits. See section 7.2.2.  00: 11 bits  01: 12 bits  10: 13 bits  11: reserved 19:18 RO 00 Reserved 17:16 RW 00 Column Width (COL): Column bits. See section 7.2.2.  00: 8 bits  01: 9 bits  10: 10 bits  11: 11 bits 15:08 RO 0 Reserved 11 Minimum PRECHARGE Delay (TRP): Minimum delay from PRECHARGE to any other command to the same bank: The SDRAM Controller will guarantee the specified number of SDCLK cycles between PRECHARGE and any subsequent command to the same bank.  00: 1 clock  01: 2 clocks  10: 3 clocks  11: 4 clocks 11 Minimum ACTIVE Delay (TRCD): Minimum delay from ACTIVE to READ or WRITE command. The SDRAM Controller will guarantee the specified number of SDCLK cycles between ACTIVE and READ/WRITE commands.  00: 1 clock  01: 2 clocks  10: 3 clocks  11: 4 clocks 9h Minimum AUTO_REFRESH Period (TRFC): The SDRAM Controller will guarantee the specified number of SDCLK cycles between AUTO REFRESH commands.  0000: 1 clock  0001: 2 clocks  ...  1001: 10 clocks  1010 - 1111: reserved 07:06 05:04 03:00 DS0200-003 RW RW RW Page 42 Z32AN Series Data Sheet 7.4.1.2 7.4.1.3 Offset 004h: SDR_CMD – SDRAM Command Register Bits Type Reset 31:27 RO 0 Reserved Description 26 RO 0 Primary Status (PSTAT): When set, SDRAM controller enabled 25 WO 0 Primary Controller Enable (PEN): When written to ‘1’, enables the primary SDRAM controller 24 WO 0 Primary Controller Disable (PDIS): SDRAM Controller. 23:21 RO 0 Reserved 20 RW 0 Primary Command Execute (PCMDX): When written to ‘1’, invokes the command specified in PCMD. Writes of ‘0’ have no effect. When read as ‘1’, command execution is pending. When read as ‘0’ command is completed. When written to ‘1’, disables the primary 19:16 RW 0h Primary Command (PCMD): Specifies the command to be executed PCMDX is set.  0000: Normal Operation  0001: NOP  0010: PRECHARGE_ALL  0011: LOAD_MODE_REGISTER  0100: SELF_REFRESH  0101: POWER_DOWN  0110: AUTO_REFRESH  0111: SDRAM_Zeroization  1000 - 1111: Reserved 15:11 RO 0 Reserved 10 RO 0 Secondary Status (SSTAT): See PSTAT. 09 WO 0 Secondary Controller Enable (SEN): See PEN. 08 WO 0 Secondary Controller Disable (SDIS): See PDIS. 07:05 RO 0 Reserved 04 RW 0 Secondary Command Execute (SCMDX): See PCMDX. 03:00 RW 0h Secondary Command (SCMD): See PCMD. Offset 008h: SDR_RFSH – SDRAM Refresh Register Bits Type Reset 31:16 RO 0 15:00 RW 0000h DS0200-003 Description Reserved Refresh Timer (TRFC): Sets the period for AUTO_REFRESH commands generated automatically by the SDRAM Controller in SDCLKs. Set to 0 to disable automatic refresh. Page 43 Z32AN Series Data Sheet 7.4.1.4 Offset 00Ch: SDR_APD – SDRAM Automatic Power-Down Bits Type Reset 31:05 RO 0 Reserved 0 SDCLK Disable (CLK_DIS): Specifies whether SDCLK must be disabled (gated) as part of the automatic power down sequence.  0: Do not disable SDCLK automatically  1: Disable SDCLK upon automatic power down time-out. 00 Mode (MODE): Selects type of power down mode of the SDRAM Controller.  00: Disable Automatic Power Down  01: Automatic Pre-charge Power Down  10: Automatic Active Power Down  11: Automatic Self Refresh 00 Timer (TIMER): Specifies the number of SDCLKs after an access of SDRAM before initiating the action specified in MODE.  00: 64 SDCLK cycles  01: 128 SDCLK cycles  10: 256 SDCLK cycles  11: 512 SDCLK cycles 04 03:02 01:00 7.4.1.5 RW RW RW Description Offset 010h: MEMC_GCFG – Memory Controller Global Configuration Bits Type Reset 31:28 RO 0 27:16 RW FFFh 15:05 RO 0 Reserved 0 Bus Zero Mode (BUS_ZERO): When set, MD[15:0] and SD[15:0] are driven “0” when SDRAM and Memory Controller state machines are idle. When cleared, MD[15:0] and SD[15:0] are floating when SDRAM and Memory Controller State Machines are idle. 04 RW Description Reserved Ready Time-out (READY_TIMEOUT): Global READY time-out limit. Time-out results in an AHB bus error. 0-4k hclk cycles. 0-4k hclk cycles. 03:02 RW 00 FLCLK Divider (FLCLK_DIV): Specifies the divider to derive flclk from hclk:  00: divide hclk by 2  01: divide hclk by 4  10: divide hclk by 6  11: divide hclk by 8 01:00 RO 0 Reserved DS0200-003 Page 44 Z32AN Series Data Sheet 7.4.1.6 MEMC_CFGn – Memory Controller nCS[“n”] Configuration Registers Offset Chip Select Offset Chip Select 014h 0 028h 5 018h 1 02Ch 6 01Ch 2 030h 7 020h 3 034h 8 024h 4 038h 9 There are 10 memory controller chip select configuration registers. The above table lists the offsets, and the table below describes the bits in each register. Bits Type Reset 31:11 RO 0 Description Reserved 10:08 RW 000 Page Boundary (PAGE_BDRY): Specifies the boundary limit for sync or async burst reads. This is defined in terms of the least significant AHB address bit which must remain constant for the burst to continue.  000: A[2]  001: A[3]  010: A[4]  011: A[5]  100: A[6]  101: A[7] 07 RW 0 Extend (EXT): When set, CS1 or CS3 becomes MA[24] and CS0 address space is 32MB. When cleared, CS1 or CS3 used normally. Note: Can use CS1 only if there is no SDRAM. 06 RO 0 Reserved 05 RW 0 Page Mode (PAGE_EN): When set, enables asynchronous page reads for this device. 04 RW 0 FLCLK Based Timing Enable (FLCLK_BTEN): When set, enables the clock divider for this external device. Uses the flclk divider to provide longer clock cycles for slow peripherals. When cleared, flclk Timing disabled. 03 RW 0 READY Pin Polarity (RDY_POL): When set, ‘1’ means ready. When cleared, VSS means ready. 02 RW 0 READY Pin Enable (RDY_EN): When set, READY indicates cycle completion. When cleared, READY pin ignored DS0200-003 01 RW 0 Byte Control Style (BYTE_STYLE): Specifies the style of the control bits used. This is used to provide a seamless solution for interfaces:  16-bit using 2xWE and no BE, 16-bit using 1xWE and 2xBE, 8-bit using 1xWE and no BE, 8-bit using 1xWE and 1xBE16-bit device:  When cleared, nWEU=nWEU, nWEL=nWEL, A[0] = unused, held low  When set, nWEU=nBEU, nWEL=nEW, A[0] = nBEL  8-bit device:  When cleared, nWEU= unused, held high, nWEL=nWE, A[0] = A0  When set, nWEU=nBE, nWEL=nWE, A[0] = A0 00 RW 1 Data Bus Width (WDTH): When cleared, external device width is 8 bits. When set, external device width is 16-bits. Page 45 Z32AN Series Data Sheet 7.4.1.7 MEMC_TIMn – Memory Controller nCS[“n”] Timing Registers Offset Chip Select Offset Chip Select 03Ch 0 050h 5 040h 1 054h 6 044h 2 058h 7 048h 3 05Ch 8 04Ch 4 060h 9 There are 10 memory controller chip select timing registers. The above table lists the offsets, and the table below describes the bits in each register. All timing parameters are based on hclk when FLCLKBTEN = ‘0’, and based on flclk when FLCLKBTEN = ‘1’. Bits Type Reset 31:30 RO 0 29:27 RW 111 NRWI: Number of hclks of the minimum time after a read before a subsequent write cycle, an access on a different chip select, or data bus clamping can occur.  FLCLKBTEN = ’0’ → 000: 0 hclk cycles, 001: 1 hclk cycles, … 111: 7 hclk cycles  FLCLKBTEN = ’1’ → 000: 1 flclk cycle, 001: 2 flclk cycles, … 111: 7flclk cycles 111 NWH: Number of clocks of the write cycle hold time.  FLCLKBTEN=0 & NWS[0] = 0 → 000: 0 hclks, 001: 1 hclk, … 111: 7 hclks  FLCLKBTEN=0 & NWS[0] = 1 → 000: 1/2 hclks, 001: 11/2 hclks, 010: 21/2 hclks, …, 111: 71/2 hclks  FLCLKBTEN=1 → 000: 1 flclk, 001: 2 flclks, …, 111: 8 flclks Fh Write Access Time (NWA): Number of clocks:  FLCLKBTEN = ’0’ → 0000: 1 hclk cycle, 0001: 2 hclk cycles, … 1111: 16 hclk cycles  FLCLKBTEN = ’1’ → 0000: 1 flclk cycle, 0001: 2 flclk cycles, … 1111: 16 flclk cycles 26:24 23:20 RW RW Description Reserved 19:16 RW Fh NWS: Number of clocks for write cycle setup time (before nWE goes active).  FLCLKBTEN=’0’ => 0h: 0 hclks, 1h: 1/2 hclks, 2h: 1 hclks, 3h: 11/2 hclks…, Fh: 71/2 hclk cycles  FLCLKBTEN=1 => 0000: 1 flclk cycle, 0001: 2 flclk cycles, …, 1111: 16 flclk cycles 15 RO 0 Reserved 14:11 NRPA: Number of clocks for read access time of sequential access of a page burst read.  0000: 1 cycle, 0001: 2 cycles, 0010: 3 cycles, … 1111: 16 cycles 10:08 RW 111 NRW: Number of hclks of the read cycle hold time.  FLCLKBTEN=0 & Page=0 & NRS[0]=0 → 000: 0 hclks, 001: 1 hclk, …, 111: 7 hclks  FLCLKBTEN=0 & Page=0 & NRS[0]=1 → 000: 1/2 hclk, 001: 11/2 hclks, 010: 21/2 hclks, …, 111: 71/2 hclks  FLCLKBTEN=0 and Page=1 → 000: 0 hclk cycle, 001: 1 hclk cycles, …, 111: 7 hclk cycles  FLCLKBTEN=1 → 000: 0 flclk cycle, 001: 1 flclk cycles, …, 111: 7 flclk cycles 07:04 RW Fh Read Access Number (NRA): Number of clocks for read access time.  FLCLKBTEN=0 → 0h: 1 hclk, 1h: 2 hclks, …, Fh: 16 hclks  FLCLKBTEN=1 → 0h: 1 flclk, 1h: 2 flclks, …, Fh: 16 flclks DS0200-003 Page 46 Z32AN Series Data Sheet 03:00 DS0200-003 RW Fh NRS: Number of clocks for read cycle setup time (before nOE goes active).  FLCLKBTEN=0 & Page=0 → 0h: 0 hclks, 1h: 1/2 hclk, 2h: 1 hclk, … Fh: 71/2 hclks  FLCLKBTEN=0 & Page=1 → 0h: 1 hclk, 1h: 2 hclks, …, 16h: 16 hclks  FLCLKBTEN=1 → 0h: 1 flclk, 1h: 2 flclks, …, Fh: 16 flclks Page 47 Z32AN Series Data Sheet 7.4.1.8 Offset 064h: MEMC_STA – Memory Controller Status Register Bits Type Reset 31:01 RO 0 Reserved 00 RW1C 0 Write Error Status (WR_ERR): When cleared, no write error was detected during Ready Mode. When set, indicates a write error was detected during Ready Mode. DS0200-003 Description Page 48 Z32AN Series Data Sheet Chapter 8: DMA Controller The DMA Controller is an AHB device that provides eight fully programmable, chaining capable DMA channels that can transfer from peripheral-to-memory, memory-to-memory, or memory-to-peripheral. All transactions consist of an AHB burst read into a DMA FIFO followed by an AHB burst write from the FIFO. Each channel has the following features:       8.1 Full 32-bit source and destination addresses with 24-bit (16 MB) address increment capability Up to 16 MB for each DMA buffer Programmable burst size Programmable priority Interrupt upon count-to-zero Abort on error Channel Arbitration and Bursts Once a channel has been programmed, it generates a request either immediately (memory-to-memory) or when its associated peripheral requests DMA (memory-to-peripheral or peripheral-to-memory). The arbiter grants on the basis of priority – a higher priority request is always granted. Within a priority level, requests are granted on a round-robin basis. Once a channel’s request has been granted, it executes two steps:   Burst movement of data from the source device into the FIFO. Burst movement of data from the FIFO to the destination device. Any required data alignment is achieved through the FIFO. Once granted, only an error condition interrupts execution. The occurrence of a higher priority request will not. Once both steps are complete, re-arbitration occurs. The fields EN, REQ, and PRI in DMA_CFGN are involved in arbitration. DS0200-003 Page 49 Z32AN Series Data Sheet 8.2 DMA Source and Destination Addressing For memory, DMA_SRCN/DMA_DESTN are addresses of the source and destination. For peripherals, all or part of the address is fixed based upon DMA_CFGN.REQ. The table below shows how the source and destination addresses as well as the address increment controls are constructed based on DMA_CFGN.REQ. A “P” in SINCR or DINCR indicates the field is programmable, while a ‘0’ indicates the field is forced to zero. REQ Transfer Source Address[31:0] 00h Mem-to-Mem 00b:DMA_SRC[29:0] P 01h Rx UART 0 FFFE0000h 0 02h Rx UART 1 FFFE1000h 0 03h Rx UART 2 FFFE2000h 0 04h Rx SPI 0 FFFEE000h 0 05h Rx Smart Card FFFF0h:DMA_SRC[11:0] 0 06h Destination Address[31:0] DINCR SINCR Table 8-1: Source and Destination Address Construction 00b:DMA_DEST[29:0] P 00b:DMA_DEST[29:0] P Reserved 07h Rx Ext Req 00b:DMA_SRC[29:0] P 08h Rx ADC FFFF2008h 0 09h Rx MCR FFFF300Ch 0 0Ah Rx SPI 1 FFFEF000h 0 0Bh – 10h Reserved 11h Tx UART 0 FFFE0000h 0 12h Tx UART 1 FFFE1000h 0 13h Tx UART 2 FFFE2000h 0 14h Tx SPI 0 FFFEE000h 0 15h Tx Smart Card FFFF0h:DMA_DEST[11:0] 0 00b:DMA_DEST[29:0] P FFFF9014h 0 00b:DMA_SRC[29:0] 16h P Reserved 17h Tx Ext Req 18h Tx SHA-1 19h Tx LCD 1Ah Tx SPI 1 00b:DMA_SRC[29:0] 1Bh – 1Fh P FFFED008h 0 FFFEF000h 0 Reserved The registers and fields involved with source data movement are:    DS0200-003 DMA_SRCN → All bits DMA_CNTN → All bits DMA_CFGN → BURST, SWIDTH, SINCR Page 50 Z32AN Series Data Sheet The table below depicts how data is moved into the DMA FIFO based on the settings of DMA_SRCN[1:0] and DMA_CFGN.SWIDTH. If the width of the device is larger than the current value of DMA_CNTN, the DMA Controller performs an AHB cycle to a smaller width. Table 8-2: Inbound Data Alignment Source Device Word Size Register Field Values Active Bytes 3 2 1 SWIDTH 0 1 0 X X 8 0 X 0 X 16 32 8.3 X X X X X X X X 0 1 1 0 Resulting AHB Burst DMA_SRCN 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 One AHB byte read for each byte moved. Only data from the indicated byte lane will be moved into the DMA FIFO (LS byte first). One AHB half-word read for each half-word moved. Only data from the indicated byte lanes will be moved into the DMA FIFO (least significant half-word first). One AHB word read for each word moved. The entire word is moved into the DMA FIFO. Data Movement from the DMA FIFO to the Destination The following registers and fields affect destination data movement of the DMA transfer:    DMA_DESTN → All bits DMA_CNTN → All bits DMA_CFGN → BURST, DWIDTH, DINCR The table below depicts how data is moved out of the FIFO based on the settings of DMA_FIFO_COUNTER, DMA_DESTN[1:0] and DMA_CFGN.DWIDTH. If the width of the device is larger than the number of bytes left in the FIFO, the DMA Controller performs an AHB cycle to a smaller width. Table 8-3: Outbound Data Alignment Destination Device Data Size Register Field Values Active Bytes 3 2 1 DWIDTH 0 1 0 X X 8 0 X 0 X 16 32 8.4 X X X X X X X X 0 1 1 0 DMA_DESTN 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 Resulting AHB Burst One AHB byte write for each byte moved. Bytes will be moved out of the DMA FIFO (LS byte first) onto the indicated byte lane. One AHB half-word write for each half-word moved. Half-words will be moved out of the DMA FIFO (least significant half-word first) onto the indicated byte lanes. One AHB word write for each word moved. The entire word is moved out of the DMA FIFO. Memory Buffer Alignment The DMA controller adjusts the transfer size to provide correct buffer alignment. DS0200-003 Page 51 Z32AN Series Data Sheet 8.5 Count-to-Zero Condition When a channel AHB burst completes, the DMA controller checks to see if DMA_CNTN has been decremented to 0. If so, there are two possible responses:   8.6 If DMA_CRLDN.EN is set, DMA_SRCN, DMA_DESTN, and DMA_CNTN are loaded from the reload registers and the channel remains active using the newly loaded address/count values and the previously programmed configuration values. If DMA_STAN.RLOAD is cleared, the channel is disabled and DMA_STAN.EN is cleared to ‘0’. Chaining Buffers The reload registers can be used for chaining buffers together. This allows the DMA to continue to service a request without immediate processing from the CPU. When a count-to-zero condition occurs with DMA_CRLDN.EN set to ‘1’, the channel remains active, the DMA_SRCN, DMA_DESTN, and DMA_CNTN is loaded with values from the reload registers, and the DMA operation continues with the new DMA buffer. To prevent improper operation, program the address before setting DMA_CRLDN.EN. The following fields affect buffer chaining.    8.7 DMA_SRLDN → All bits DMA_DRLDN → All bits DMA_CRLDN → EN, COUNT DMA Interrupts The following registers and fields control DMA interrupts.     8.8 DMA_CTRL → IENx DMA_ISTAT → PENDx DMA_CFGN → CTZ_IEN, STA_IEN DMA_STAN → EN, IPEND, CTZ, RLOAD, BUS_ERR, TO Channel Time-outs Each channel can be configured to generate an interrupt when its associated request line is inactive. An example of this feature is to determine an idle UART receive channel. The time-out mechanism consists of a single global 24-bit pre-scalar and per-channel programmable 8-bit timers. The global pre-scalar has 3 taps: a divide by 256, a divide by 64k, or a divide by 16M. Each channel’s 8-bit timer increments using a tap chosen by DMA_CFGN.PS. DMA_CFGN.TO selects how high the timer must count before generating an interrupt. The timer is reset whenever any of the following conditions occurs:   The DMA request line programmed for the channel is activated. The channel is disabled for any reason (DMA_STAN.EN is zero). Any timer can be disabled by clearing DMA_CFGN.PS to ‘00’. When all 8 channels are configured, the global pre-scalar is disabled. Normally, the timer starts counting as soon as the channel is enabled and DMA_CFGN.PS is non-zero. But if DMA_CFGN.WAIT is set, the timer starts counting only after the first DMA request is received from the peripheral. The time-out period can be calculated using the following equation: With hclk frequency of 90 MHz and PS=10b and TO=100b, the time-out period is: The following registers and fields control channel time-outs.    DS0200-003 DMA_CTRL → IENx DMA_CFGN → PS, TO, WAIT DMA_STAN → TO Page 52 Z32AN Series Data Sheet 8.9 Register Accesses Restrictions Any register can be written while a channel is disabled. When DMA_STAN.EN is set to ‘1’, the channel is enabled. As an active channel can be in the middle of read/write burst, DMA_SRCN, DMA_DESTN, or DMA_CNTN must not be written. A DMA channel can be disabled by clearing DMA_CFGN.EN. DMA_STAN.EN must be polled to verify that the channel is disabled. When clearing DMA_CFGN.EN, perform a read-modify-write to ensure that other bits of DMA_CFGN are not modified. A channel is automatically disabled if there is an AHB bus error, or a count-to-zero condition occurs with DMA_CRLDN.EN cleared. If these occur, EN and EN of DMA_CFGN are cleared automatically. 8.10 Memory-to-Memory DMA Memory-to-memory transfers are performed as if the request is always active. Therefore, assign a lower priority to channels executing memory-to-memory transfers to prevent starvation of other DMA channels. 8.11 External DMA An external DMA transfer is initiated by asserting nTxREQ. Figure 8-1 displays the nTxACK waveform to an external device. nTxACK is asserted at least 1 hclk before nCS, and de-asserts at least 4 hclks after the deassertion of nCS. The polarity is selected in DMA_CTRL. Figure 8-1: Acknowledge Waveform Note: The above figure assumes active low signals DS0200-003 Page 53 Z32AN Series Data Sheet 8.12 Registers (Base → FFFF4000h) 8.12.1 Global Registers 8.12.1.1 8.12.1.2 Offset Register Description 000h DMA_CTRL DMA Control Register 004h DMA_ISTAT DMA Interrupt Status Register Offset 000h: DMA_CTRL – DMA Control Register Bits Type Reset Description 31:17 RO 0 Reserved 16 RW 0 External DMA Polarity (EXTPOL): Sets the polarity for ALL external DMA inputs and outputs (TxREQ, TxACK, RxREQ, RxACK). When set, the polarity is active high. 15:08 RO 0 Reserved 07:00 RW 00h Channel “N” Interrupt Enable (IENx): When set, the interrupt for that channel is enabled. Bit 7 = channel 7, bit 0 = channel 0. Offset 004h: DMA_ISTAT – DMA Interrupt Status Register Bits Type Reset 31:08 RO 0 07:00 RO 00h DS0200-003 Description Reserved Channel Interrupt Pending (PENDx): When set, an interrupt is pending for the channel. More information in DMA_STAN, and all active bits of DMA_STAN must be cleared for this bit to clear. These bits are set only DMA_CTRL.IENx is set. Page 54 Z32AN Series Data Sheet 8.12.2 Per-Channel Registers Offsets 8.12.2.1 Ch0 Ch1 Ch2 Ch3 Ch4 Ch4 Ch6 Ch7 Register 100h 120h 140h 160h 180h 1A0h 1C0h 1E0h DMA_CFGN 104h 124h 144h 164h 184h 1A4h 1C4h 1E4h DMA_STAN 108h 128h 148h 168h 188h 1A8h 1C8h 1E8h DMA_SRCN 10Ch 12Ch 14Ch 16Ch 18Ch 1ACh 1CCh 1ECh DMA_DESTN 110h 130h 150h 170h 190h 1B0h 1D0h 1F0h DMA_CNTN 114h 134h 154h 174h 194h 1B4h 1D4h 1F4h DMA_SRLDN 118h 138h 158h 178h 198h 1B8h 1D8h 1F8h DMA_DRLDN 11Ch 13Ch 15Ch 17Ch 19Ch 1BCh 1DCh 1FCh DMA_CRLDN DMA_CFGn – DMA Channel “n” Config Register Bits Type Reset Description 31 RW 0 Count-to-Zero Interrupt Enable (CTZ_IEN): whenever a Count-to-Zero event occurs. 30 RW 0 Status Interrupt Enable (STA_IEN): DMA_STAN.EN transitions from 1 to 0. 29 RO 0 Reserved When set, the IPEND goes active When set, IPEND will go active whenever Burst Size (BURST): The number of bytes to be transferred into and out of the DMA FIFO in handling a single burst.  00000: 1 byte  00001: 2 bytes  ...  11111: 32 bytes 28:24 RW 00000 23 RO 0 Reserved 22 RW 0 Destination Increment Enable (DINCR): When set, enables incrementing of DMA_DESTN on every AHB transaction. Forced to 0 for DMA transmit to peripherals. 21:20 RW 00 Destination Width (DWIDTH): Indicates the width of the each AHB transaction to the destination peripheral or memory.  00: byte  01: half-word  10: word  11: reserved 19 RO 0 Reserved 18 RW 0 Source Increment Enable (SINCR): When set, enables incrementing of DMA_SRCN upon every AHB transaction. Forced to 0 for DMA receive from peripherals. DS0200-003 Page 55 Z32AN Series Data Sheet Bits 17:16 15:14 Type RW RW Reset Description 00 Source Width (SWIDTH): Indicates the width of the source device. In most cases, this will be the data width of each AHB transactions.  00: byte  01: half-word  10: word  11: reserved 00 Pre-Scale Select (PS): Selects the Pre-Scale divider to use for the channel timer.  00: Disable timer for this channel.  01: Pre-Scale is hclk divided by 256  10: Pre-Scale is hclk divided by 64k  11: Pre-Scale is hclk divided by 16M 13:11 RW 000 Time-Out Select (TO): Selects the number of pre-scale clocks seen by the channel timer before a time-out conditions is generated for this channel. Since the pre-scalar runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.  000: 3-4 Pre-Scale clocks  001: 7-8 Pre-Scale clocks  010: 15-16 Pre-Scale clocks  011: 31-32 Pre-Scale clocks  100: 63-64 Pre-Scale clocks  101: 127-128 Pre-Scale clocks  110: 255-256 Pre-Scale clocks  111: 511-512 Pre-Scale clocks 10 RW 0 Request Wait Enable (WAIT): When cleared, the channel timer is enabled as soon as the channel is enabled and PS is non-zero. Setting this bit delays the channel timer enabled until at least one request has been received from the peripheral. 09 RO 0 Reserved Request Select (REQ): channel. 08:04 RW 00000 Used to select which DMA request line is used for the REQ Definition REQ Definition 00h memory-to-memory 10h Reserved 01h Rx UART0 11h Rx UART0 02h Rx UART1 12h Rx UART1 03h Rx UART2 13h Rx UART2 04h Rx SPI 0 14h Rx SPI 0 05h Rx Smart Card 15h Rx Smart Card 06h N/A 16h N/A 07h Rx External Peripheral 17h Rx External Peripheral 08h Rx ADC 18h Tx SHA-1 09h Rx MCR 19h LCD Controller 0Ah Rx SPI 1 1Ah Tx SPI 1 0Bh – 0Fh Reserved 1Bh – 1Fh Reserved 03:02 RW 00 Priority (PRI): Channel DMA priority. 00 = Highest Priority. 11 = Lowest priority 01 RO 0 Reserved 00 RW 0 Enable (EN): When set, the channel is enabled. After clearing to ‘0’, DMA_STAN.EN determines when the channel is disabled. This bit is automatically cleared whenever DMA_STAN.EN transitions from 1 to 0. DS0200-003 Page 56 Z32AN Series Data Sheet 8.12.2.2 DMA_STAn – DMA Channel “n” Status Register Bits Type Reset 31:07 RO 0 Reserved 06 RW1C 0 Time-Out (TO): When set, a time-out has occurred for this channel. 05 RO 0 Reserved 04 RW1C 0 Bus Error (BUS_ERR): disabled. 03 RW1C 0 Reload Status (RLOAD): When set, indicates a reload has occurred on this channel. 02 RW1C 0 Count-to-Zero Status (CTZ): When set, a Count-to-Zero condition has occurred. 01 RO 0 Pending (PEND): When set, indicates that a DMA request is pending for this channel. 00 RO 0 Description When set, an AHB abort was received and the channel Enable Status (EN): When set, the channel is enabled. When cleared, the configuration, address, and count registers for the channel may be altered. This bit follows DMA_CFGN.EN. This bit automatically clears under the following conditions:  Bus error (cleared immediately)  Count-to-zero with RLOAD EN=0 (cleared at the end of the AHB R/W burst).  EN CTRL cleared by programmer (cleared at the end of the AHB R/W burst). When this bit transitions from 1 to 0, DMA_CFGN.EN also clears (if not cleared already). 8.12.2.3 DMA_SRCn – DMA Channel “n” Source Register Bits 31 30:00 DS0200-003 Type RO RW Reset Description 0 Reserved 0 Address (ADDR): For peripheral transfers, address bits are fixed (see Table 8-1). For memory transfers, if DMA_CFGN.SRC_INC is ‘1’, the counter is incremented by 1, 2, or 4, depending on the width of each AHB cycle. When a count-to-zero occurs and DMA_CRLDN.EN = ‘1’, this is reloaded with the contents of DMA_SRLDN. Page 57 Z32AN Series Data Sheet 8.12.2.4 8.12.2.5 DMA_DESTn – DMA Channel “n” Destination Register Bits Type Reset 31 RO 0 Reserved 30:00 RW 0 Address (ADDR): For peripheral transfers, address bits are fixed (see Table 8-1). For memory transfers, if DMA_CFGN.DEST_INC is ‘1’, the counter is incremented by 1, 2, or 4, depending on the width of each AHB cycle. When a count-to-zero occurs and DMA_CRLD.EN = ‘1’, this is reloaded with the contents of DMA_DRLD. DMA_CNTn – DMA Channel N Count Register Bits Type Reset 31:24 RO 0 Reserved 0 DMA Count (COUNT): Number of bytes to transfer. It decrements by 1, 2, or 4 depending on the width of each AHB cycle. When the counter reaches 0, a count-tozero condition occurs.  0000h: 0 bytes  0001h: 1 byte  0002h: 2 bytes  ...  FFFFh: 64K bytes 23:00 8.12.2.6 8.12.2.7 Description RW Description DMA_SRLDn – DMA Channel N Source Reload Register Bits Type Reset 31 RO 0 Description Reserved 30:00 RW 0 Address (ADDR): Reload value for DMA_SRCN. DMA_DRLDn – DMA Channel N Destination Reload Register Bits Type Reset 31 RO 0 Reserved 30:00 RW 0 Address (ADDR): Reload value for DMA_SRCN. DS0200-003 Description Page 58 Z32AN Series Data Sheet 8.12.2.8 DMA_CRLDn – DMA Channel N Count Reload Register Bits Type Reset 31 RO 0 Reload Enable (EN): When set, enable DMA_SRCN, DMA_DESTN and DMA_CNTN to be reloaded with their corresponding reload registers upon count-to-zero. This bit must be set after the address reload registers have been programmed. 30:24 RO 0 Reserved 23:00 RW 0 Counter Reload Value (COUNT): Reload value for DMA_CNTN. DS0200-003 Description Page 59 Z32AN Series Data Sheet Chapter 9: Magnetic Card Reader (MCR) The Magnetics Card Reader Module is depicted below. Features:           9.1 Support for 3 simultaneous tracks Direct mode operation supports direct connection to magnetic heads Bypass mode operation supports digital inputs from magnetic card readers Automatic peak detection and delta-time generation Accurate peak detection between 20mV and 400mV peak-to-peak Up to 266kHz sampling resolution per channel to support bit rates of 150bps to 12,000bps A single 8-deep, 32-bit FIFO Raw ADC sample access DMA support Interrupt support Magnetic Card Reading Overview Figure 9-1 shows an example of magnetic card bit encoding, derived from a single magnetic card track. The signal contains a series of alternating peaks occurring once or twice within a single bit time. Logic ‘0’ is encoded as one transition per bit; logic ‘1’ is encoded as two transitions. Although the bit rate will vary and distortions will occur for various reasons, the bit rate is relatively constant from bit-to-bit and the delta time between alternating peaks can be used to decode the series of ‘1’s and ‘0’s. The Z32AN Series MCR can be configured to generate a stream of delta-time integers which can be processed by the user to decode the magnetic card stripes. These delta time values appear in a FIFO along with the associated track number which can be processed by the user’s bit decoder application. A ‘1’ can be identified by the fact that it consists of two delta-time integers roughly equal to the single delta-time integer of a ‘0’. Figure 9-1: Magnetic Card Bit encoding DS0200-003 Page 60 Z32AN Series Data Sheet 9.2 9.2.1 Direct Mode Operation of MCR Peak Detection Algorithm The peak detection algorithm is rather simple and consists of this: 1. 2. 3. 4. 5. 6. 7. The user programs the positive and negative minimum threshold registers. Once the minimum positive threshold is crossed, the Peak Detector begins searching for a positive peak. This first value over the minimum is registered. Every incoming sample is compared to the registered value. If the incoming sample is greater, it is registered and the old value is discarded. Otherwise, the incoming sample is ignored. If the incoming sample falls below the negative threshold, the Peak Detector stores the positive peak information in the FIFO and begins the search for the negative peak. The negative peak search is analogous to the positive peak search. The Peak Detector alternates between the negative and positive peak searches until a timeout occurs. Figure 9-2 depicts the peak detection algorithm. Figure 9-2: Peak Detection Algorithm 9.2.2 Stored Peak Information Peak information stored in the FIFO is a 32-bit value with the following information:      Delta-time from previous peak Track number Polarity of current peak Whether a time-out caused this entry into the FIFO Amplitude of current peak The format of this can be found in MCR_FIFO. To save memory, using only 16-bits, discard the amplitude information held in the upper bits (for the case of manual read from the FIFO) or program the DMA to use only 16-bits (for the case of DMA operation). DS0200-003 Page 61 Z32AN Series Data Sheet 9.2.3 Peak Detection Timer and Time-out Each track has an internal 12-bit timer which is used to calculate the delta-time between peaks that increments with every sample of the ADC. In addition to calculating the delta-time, this timer is used to detect when peaks are no longer being received by the MCR (indicating the end of a card swipe). All three timers will only count up to the maximum value specified in the MCR_TMR. Should any timer count up to that value, a time-out condition will occur for that track. Under this condition, the last valid delta-time entry will be stored in the FIFO and the timer will be disabled (preventing further time-out interrupts). Once another threshold crossing occurs, the timer will be automatically re-enabled and the search for time-out conditions begins again. 9.2.4 Card Time-out and Track Timers As described above, each track has an internal 12-bit timer. An interrupt can be generated on the time-out of each track, or a single time-out can be generated on the time-out of the “last” track. This simplifies MCR interrupt handling. A time-out is considered to be the “last” if the other two timers are either: 1) not enabled; 2) already timed-out; or 3) have not encountered an initial peak (never started). The card time-out is enabled by setting MCR_CTRL.CART_TO_IEN. 9.2.5 Dynamic Minimum Thresholds There are two modes of operation for threshold values, selected by MCR_CTRL.THRESH. The first mode is static threshold mode. In this mode, the positive minimum threshold and the negative minimum threshold programmed by the user are always the thresholds used by the peak detector. The second mode is dynamic threshold mode. In this mode, the previous peak is scaled by 1/4, 1/8, or 1/16 to generate a temporary internal threshold for the next peak (the values in MCRn_THRS do not change). If the scaled value is ever computed to be less than the value of MCRn_THRS, then that minimum value is used instead of the scaled version (i.e. the thresholds can never be less than the programmed values). In the event of a time-out, both thresholds revert to the programmed value. 9.2.6 MCR Interrupts Below are the registers and fields which are used to control and handle DMA interrupts.        MCR_CTRL.CARD_TO_IEN → MCR_INT.CARD_TO MCR_CTRL.AUX_ADC_IEN → MCR_INT.AUX_ADC MCR_CTRL.UFLO_IEN → MCR_INT.UFLO MCR_CTRL.OFLO_IEN → MCR_INT.OFLO MCR_CTRL.LVL_IEN → MCR_INT.LVL MCR_CTRL.TOn_IEN → MCR_INT.TOn MCR_INT.STA Status bits are set whenever the corresponding event occurs whether or not the corresponding enable bit is set. These bits remain set (latched) until cleared by a write to MCR_INT. Whenever a status bit and corresponding enable bit are active, an interrupt is generated. DS0200-003 Page 62 Z32AN Series Data Sheet 9.2.7 Acquiring Raw ADC Samples Any of the three tracks can be used to generate raw ADC data. There are two means of accessing raw ADC samples and these are outlined below. 9.2.7.1 Using the Auxiliary ADC Register This method has the following advantages and restrictions:    Only one track can be sampled at a time. The track can be sampled while peak detection mode is active. There is no FIFO to hold data and DMA is not supported for this register, so response time is more restricted. Following are the registers and fields that must be configured to enable use of the MCR_AUX_ADC. Once configured, every new sample from the configured track is moved into MCR_AUX_ADC (provided that the previous sample has been read).    9.2.7.2 MCR_ADC → All fields MCR_CTRL → AUX_ADC_IEN, IENn MCR_AUX_ADC → NEW, SAMPLE, OFLO Using ADC Mode This method has the following advantages and restrictions:    Any number of tracks can be sampled at a time. Peak-Detection must be disabled while a track is in ADC mode. There is FIFO and DMA support. Below are the registers and fields that are used to configure a track for ADC mode. Once configured, ADC samples are streamed into the FIFO along with data from any other enabled channels.    9.2.8 MCR_ADC → All fields MCR_CTRL → MODEn, IENn MCR_FIFO → TRACK, TIME Programming Guide The MCR provides a stream of either delta time or ADC samples. The optimum parameters are strongly dependent upon system design. Some general guidelines are provided below. 9.2.8.1 Sample Rate Programming The ADC sample rate is configured by programming MCR_ADC. The sample rate for each track is dependent upon the number of active channels. The equation to determine the ADC divider is: For example, if hclk is 90MHz, the number of active MCR channels is 3, and the desired track sample rate is 250kHz, then: Thus, programming 7 into MCR_ADC.DIV produces a sample rate of 250kHz for each track. 9.2.8.2 DC Offset Programming The DC offset needs to be programmed for each track by writing to the MCRn_DCO. To determine value to use, the programmer should acquire a number of raw ADC samples and choose the average value. The DC offset should be close to the middle range of 800h. The variation between samples should be less than 00Fh DS0200-003 Page 63 Z32AN Series Data Sheet when no card swipe is active. MCR_AUX_ADC allows the programmer to sample the ADC while the track is still active. See section 9.2.7 for more details. 9.2.8.3 Programmable Gain Amplifier The reference voltage can be adjusted through the programmable gain amplifier for the voltage reference of the ADC. Increasing the peak to peak input range is achieved by changing MCR_ADC.REFCAL to adjust the ratio of input gain from 1 to 10. See section 9.2.7 for more details. 9.2.8.4 Threshold Programming The threshold settings should be such that the noise of the MCR does not exceed the threshold limits. 9.2.8.5 Max Delta Time Programming The maximum delta time can be safely set at the maximum value (FFFh), though the lowest bit rate (150bps) with the highest sample rate (266.7kHz) should imply that 7F2h should correspond to a “bit too wide” condition. 9.2.8.6 Enabling Channels and Handling FIFO Data Once the above parameters have been programmed the MCR channels can be enabled via MCR_CTRL.IENn. Once this is done, delta time information is moved into the FIFO as a card is swiped and the thresholds are crossed. A time-out interrupt will arrive when the swipe is completed. A channel may be disabled at any time by clearing its MCR_CTRL.IENn. Enabling tracks affects the sample rate. See section 9.2.8.1 for more details. The user can rely either upon FIFO and time-out interrupts or DMA to move data out of MCR_FIFO into a memory buffer. If multiple tracks are enabled, the buffer will contain data from one track interleaved with data from the other tracks, so it will be necessary to sort the data according to the track number stored with the delta time information. When a time-out occurs, the peak detector for that channel continues to search for another swipe and begins to move data into the FIFO as soon as more peaks begin to be detected. 9.2.9 Card Time-out and Track Timers Each track has an internal 12-bit timer. An interrupt can be generated on the time-out of each track, or a single time-out can be generated on the time-out of the “last” track. This simplifies MCR interrupt handling. A time-out is considered to be the “last” if the other two timers are either: 1) not enabled; 2) already timedout; or 3) have not encountered an initial peak (never started). The card time-out is enabled by setting MCR_CTRL.CARD_TO_IEN. 9.3 Registers (Base → FFFF3000h) DS0200-003 Offset Register Description 000h MCR_CTRL 004h MCR_INT MCR Interrupt Control and Status MCR Global Control Register 008h MCR_TMR MCR Timing Register 00Ch MCR_FIFO MCR FIFO Register 010h MCR_ADC MCR ADC Register 014h – 01Ch MCRn_DCO MCR”N” DC Offset Register (N = 0, 1, or 2) 020h – 028h MCRn_THRS MCR”N” DC Threshold Register (N = 0, 1, or 2) 02Ch MCR_AUX_ADC MCR Auxiliary ADC Register Page 64 Z32AN Series Data Sheet 9.3.1 Offset 000h: MCR_CTRL – MCR Control Register Bits Type Reset Description 31:24 RO 0 Reserved 27:24 RO 0h FIFO Count (COUNT): Number of valid entries are contained in the MCR FIFO.  0000: None, 0001: 1 entry, 0010: 2 entries, …, 1000: 8 entries  1001 - 1111: Invalid 23 RW 0 Card Time-out (CARD_TO_IEN): interrupt. 22 RW 0 Aux ADC (AUX_ADC_IEN): available in MCR_AUX_ADC. 21 RW 0 FIFO Underflow (UFLO_IEN): When set, enables interrupts on a FIFO underflow. 20 RW 0 FIFO Overflow (OFLO_IEN): When set, enables interrupts on a FIFO overflow. 19 RW 0 FIFO Level (LVL_IEN): When set, enables interrupts on the number of FIFO entries greater than or equal to the FIFO level. 18:16 RW 0 Track “N” Timeout (TOn_IEN): specified MCR track. 15 WO 0 Bypass ADC (BYPASS): When set, enables digital inputs to bypassing the ADC. 14:13 RO 0 Reserved 12:10 RW 0 Track “N” Mode (MODEn): When set, the track is in ADC mode. When cleared, the track is in peak-detection mode. 09 RW 0 Soft Reset (SOFT): When written to ‘1’, resets the MCR state machines and FIFOs. Does not affect analog or ADC registers. Writes of ‘0’ have no effect. When set, enables card time-outs to cause an When set, enables interrupts when a new sample is When set, enables time-out interrupts from the 08:07 RW 00 Threshold Mode (THRESH): Selects the threshold mode to use to all tracks:  00: Static thresholds  01: Enable 1/4 scaling thresholds  10: Enable 1/8 scaling thresholds  11: Enable 1/16 scaling thresholds 06 RW 0 DMA Enable (DMA): When set, enables DMA requests when FIFO level is reached or exceeded. 05:03 RW 000 FIFO Level (LVL): Sets the number of MCR FIFO entries required for a DMA request or FIFO interrupt.  000: 1 FIFO entry, 001: 2 FIFIO entries, …, 111: 8 FIFO entries 02:00 RW 0 Track “N” Enable (IENn): Enables each track. When cleared, the track is disabled. When set, the track is enabled. DS0200-003 Page 65 Z32AN Series Data Sheet 9.3.2 9.3.3 Offset 004h: MCR_INT – MCR Interrupt Register Bits Type Reset Description 31:24 RO 0 Reserved 23 RW1C 0 Card Time-out (CARD_TO): When set, indicates occurrence of a card time-out. This occurs when one of the tracks times out and both other tracks are either already timedout or were never started. 22 RW1C 0 AUX ADC (AUX_ADC): When set, indicates availability of a new AUX ADC sample. 21 RW1C 0 FIFO Underflow (UFLO): When set, indicates occurrence of a FIFO underflow 20 RW1C 0 FIFO Overflow (OFLO): When set, indicates occurrence of a FIFO overflow 19 RW1C 0 FIFO Level (LVL): When set, indicates that the number of entries in the FIFO is greater than or equal to the level specified in MCR_CTRL 18:16 RW1C 000 Track “N” Timeout (TOn): Indicates that the specified MCR track has encountered a peak search timeout. Bit 18 = MCR2, bit 17 = MCR1, and bit 16 = MCR0. 15:01 RO 0 Reserved 00 RO 0 Interrupt Status (STA): When set, indicates MCR is driving an interrupt Offset 008h: MCR_TMR – MCR Timing Register Bits Type Reset 31:12 RO 0 11:00 RW FFFh DS0200-003 Description Reserved Maximum Delta-Time (MAX_DELTA_TIME): Sets the number of samples before a time-out Page 66 Z32AN Series Data Sheet 9.3.4 9.3.5 Offset 00Ch: MCR_FIFO – MCR FIFO Register Bits Type Reset 31:28 RO 0 27:16 RO 000h Peak Amplitude (PEAK): In peak-detection mode, this provides the amplitude of the peak. In Raw ADC mode, these bits are always 0. 15 RO 0 Timeout (TO): In peak detection mode, indicates timeout (‘0’ = no timeout, ‘1’ = timeout). In ADC mode, this bit is always ‘0’. 14 RO 0 Peak Polarity (POL): In peak-detection mode, this provides the polarity of the peak (‘0’ = negative peak, ‘1’ = positive peak). In Raw ADC mode, this bit is set to zero. Track Number (TRACK): information.  00: Track 0  01: Track 1  10: Track 2  11: N/A 13:12 RO 00 11:00 RO 000h Description Reserved Provides the track number associated with the FIFO Delta-Time/ADC Sample (TIME): sample. Contains the delta-time value or raw ADC Offset 010h: MCR_ADC – MCR ADC Register Bits Type Reset 31:16 RO 0 15:13 RW 000 12 RW 1 11:00 DS0200-003 RW 004h Description Reserved ADC Reference Calibration (CAL): Selects the Peak to Peak differential input voltage range for full-scale output.  000 = 0.50  001 = 0.40  010 = 0.30  011 = 0.25  100 = 0.20  101 = 0.15  110 = 0.10  111 = 0.05 MCR Reset (RST): When set, resets the MCR ADC. ADC Clock Divider (DIV): Determines the divider for the ADC clock: See section 9.2.8.1 for details on how to create this value. Acceptable values:  000h: Illegal  001h: hclk divided by 2  002h: Illegal  003h: Illegal  004h: hclk divided by 5  …  FFFh: hclk divided by 256 Page 67 Z32AN Series Data Sheet 9.3.6 9.3.7 MCRn_DCO – MCR DC Offset Registers (MCR0: 014h, MCR1: 018h, MCR2: 01Ch) Bits Type Reset 31:12 RO 0 11:00 RW 000h DescriptionDS0200.docx Reserved DC Offset (OFFSET): Used to set the center point of the ADC. This should be set to the average raw ADC sample value for track N with no card swipe. MCRn_THRS – MCR Threshold Registers (MCR0: 020h, MCR1: 024h, MCR2: 028h) 9.3.8 Bits Type Reset 31:28 RO 0 27:16 RW 000h 15:12 RO 0 11:00 RW 000h Description Reserved Negative Minimum Threshold (NMT): Reserved Positive Minimum Threshold (PMT): Offset 02Ch: MCR_AUX_ADC – MCR Auxiliary ADC Register Bits Type Reset Description 31:18 RO 0 Reserved 17:16 RW 00 Track Number (TRACK): Configure which track is used to extract the samples.  00: Track 0  01: Track 1  10: Track 2  11: N/A 15 RO 0 New Sample (NEW): When set, indicates a sample has been loaded into ADC_SAMPLE. While this bit is set, ADC_SAMPLE will not be loaded with a new value. Cleared by a read of this register. 14 RO 0 Overflow (OFLO): When set, indicates one or more samples have been discarded due to the fact that NEW was set and ADC_SAMPLE could not be reloaded. Cleared by a read of this register. 14:12 RO 0 Reserved 11:00 RO 000h DS0200-003 ADC Sample (SAMPLE): Latest ADC sample from track specified in "Track Number". Page 68 Z32AN Series Data Sheet Chapter 10: Smart Card Controller The Smart Card Controller is an APB device that allows a seamless connection to external Smart Card Interface devices. Reference to the ON Semiconductor NCN6001 Smart Card Interface IC is made throughout this chapter which serves as an example interface for the Smart Card Controllers. The protocol layer is not implemented in hardware and must be managed by the software. The controller includes the following features:       Supports two interfaces: One for maincard and one for SIM card. Interrupt. DMA support. Master only SPI Interface Programmable Baud Rate Generator. Timing Checker. 10.1 SPI Interface The SPI port is able to serially send and receive 8-bit data to the external Smart Card Interface IC (MSB sent and received first). It is a master only interface. The SC_nSS0 and SC_nSS1 determine which external interface is being accessed. The clock is active high and idles low. The frequency is programmable through SC_SPI_CLK and allows discrete division ratios from the hclk frequency: all even numbers between 2 and 32 (inclusive). SPI clock frequency is calculated as per the below equation: The SPI data interface comprises of two unidirectional ports: SC_MOSI and SC_MISO. SC_MOSI is an output serial data line; SC_MISO is a concurrent input serial data line. Data is sent on SC_MOSI and received from SC_MISO and are clocked by the same clock SC_SCK. Each time a word is sent, another byte is received. When the CPU sends a byte through the SPI by writing the data in the SPIDATA register, it can get the concurrently received byte by reading SPIDATA. The received byte is valid once bit 8 (MSB) of the SPIDATA is set to 1. When an automatic RST or VCCON command is sent through the SPI (after a change of one of the 2 Card Reset or Card VCC lines), a byte is received, which is thrown away. This byte cannot be read by the processor as SPIDATA is not updated with this data. Figure 10-1 shows the waveforms of the SPI port. The SC_MISO input is sampled on the falling edge of SC_SCK, for example, OnSemi Smart Card interface chip (OnSemi NCN6001), must be programmed to operate in Special Mode. Refer to the datasheet for the OnSemi NCN6001 device or the specific device used in the application to determine SPI interface requirements. Figure 10-1: SPI Data Transfer 10.1.1 Smart Card Controller Interrupt Management An Interrupt indicates when an over current, overheating, card removal, or card insertion is detected on one of the Smart Card interfaces through SC_nALARM. Status is obtained by polling the Smart Card device. DS0200-003 Page 69 Z32AN Series Data Sheet 10.1.2 Reset and Power-up Management When reset or power-up commands are issued using the COMMAND register, the controller transfers the corresponding command words to the selected Smart Card through the SPI bus. The command request is queued and sent through the SPI bus as soon as the current SPI transfer is complete. The voltage information and clock division ratios must be programmed before the reset or power-up command is issued. The SPI command format is (most significant bit first) is given below: Where,     S[2:0]: target Smart Card interface address (INT1=000, INT2=001 INT3=010, INT4=011, EXT ASYNC=100). nRST: is the active-Low reset signal to be applied to the Smart Card. CK[1:0]: is the content of the CLKDIV register for the Smart Card. VCC[1:0]: is the content of the VCC register for the active Smart Card when the card must be powered on or 00 when the active card must be powered off. 10.1.3 Chip to Smart Card Interface Mapping Smart Card 0 is mapped to the Maincard. Smart Card 1 communicates with a SIM via the interface device. For the non-active Smart Card, the clock and I/O lines are held inactive. Which SIM to use is selected by SIM_SEL. At reset, Smart Card 1 is mapped to SIM0 (deactivated). 10.1.4 DMA Interface Each DMA channel can be independently assigned to either of the Smart Card RX or TX channels or deactivated. For example, the TX channel can be used with Smart Card 0 while the RX channel is used with Smart Card 1. At reset, the RX and TX DMA channels are not mapped and must be configured prior to use. ►Note: Ensure that Smart Card 0 and Smart Card 1 are not mapped onto the same DMA channel as it can lead to unpredictable operation. 10.1.5 Synchronous Smart Card Handling The SPI interface allows management of synchronous Smart Cards by sending corresponding commands to the interface devices to manually activate the clock and data signals. 10.1.6 Interrupt Generation Following are the interrupt sources:    SPI Interrupt: Occurs whenever an SPI collision occurs. For example, the CPU writes new data into the SPIDATA register while the previous transfer is not completed. Bit 8 of the SPIDATA register remains at 0 when the transfer is in process. ALARM Interrupt: Occurs whenever one of the Smart Card interfaces generates an interrupt indicating over current, overheating, card removal or card insertion is on one Smart Card socket. The interrupt lines from each Smart Card interface are combined to form the SC_nALARM. ALARM TRIG Interrupt: Generated whenever a High to Low transition is detected on the SC_nALARM input. These interrupt sources are combined to generate the Smart Card Alarm interrupt and can be individually masked in SC_IMASK. The Smart Card interfaces also provide interrupts. These interrupts cannot be masked in SC_IMASK. However, their status is available in SC_ISTAT. DS0200-003 Page 70 Z32AN Series Data Sheet 10.2 Blocks The Smart Card function contains two blocks: a UART, and a Controller and Timing Checker: 10.2.1 UART The UART is connected to APB and supports two DMA requests, one for receive and another for transmit. For receive, a DMA request indicates when a word is available in the receive data register. For transmit, a DMA request indicates when a word can be accepted by the UART for transmission. The receive channel supports a word register allowing the UART to function without DMA. The CPU can be informed it can read a word from the UART in the by an interrupt. Words to transmit can be written through single DMA transfers or through CPU direct accesses. 10.2.2 Programmable Baud Rate Generator (BRG) The BRG produces the Elementary Time Unit (ETU) timing reference which is the serial bit duration used for data transfer on SC_IO. The ETU is obtained by dividing SC_CLK, with a programmable factor defined in BRR. DS0200-003 Page 71 Z32AN Series Data Sheet 10.2.3 Controller There is one controller state machine in Smart Card 0 and four controller state machines in Smart Card 1 to manage card power on, card cold and warm reset, and card deactivation stages. The Smart Card 1 multiplexer must be configured before each command to select the appropriate controller state machine via SIM_SEL. The state diagram for the controller is shown below. Figure 10-2: State Diagram for Smart Card Controller The states are described below:   Idle: After card detection (DET_CMD), software sets COMMAND.PWR_CARD to ‘1’ to power up the card before changing to PowerCard. All outputs are in their inactive state. PowerCard: The controller applies power. Software sets COMMAND.DEAC_CARD to ‘1’. It is up to software to ensure power is stable before sending the CardReset command by reading SCSTATUS. If the card is removed, the controller automatically returns to the Idle state.  ResetCard: On entering this state, the card clock is started, the card IO is ‘0’, the card reset is asserted by the external interface device, and the reset duration counter is started. When the counter reaches the count programmed in RST_LEN, the controller changes to WaitCommand. If the card is removed anytime during the reset state the controller changes to WaitDeactivation.  WaitCommand: On entering this state, card reset is set inactive and data transfers may occur. When data transfer is complete, one of the following three commands can be issued. o o o    DS0200-003 StopCardClock: The Smart Card clock is stopped. DeactivateCard: The controller changes to WaitDeactivation. ResetCard: The controller performs a warm reset of the card by changing to ResetCard. If the card is removed during this state the controller automatically changes to the WaitDeactivation state. WaitDeactivation: On entering this state, the deactivation delay counter is started. When the counter reaches the count programmed in DEAC_DLY, the controller moves to DeacResetCard. It is up to the software to program the proper delay according to the protocol or the current card session stage. DeacResetCard: The external interface card reset is pulled ‘0’ and the controller moves to DeacStopClock. Page 72 Z32AN Series Data Sheet    DeacStopClock: The card clock is stopped and the controller moves to DeacLowerIO. DeacLowerIO: The IO line is pulled ‘0’ and the controller moves to DeacPowerOff. DeacPowerOff: The card is powered off and the controller moves to Idle. 10.2.4 Timing Checker This performs the mandatory checking on the Answer to Reset (ATR) delay, ATR length, Block Wait Timer (BWT), Character Wait Time (CWT), and Work Wait Time (WWT) parameters. 10.2.4.1 ATR The ATR is checked against 3 programmable parameters:    AtrMinDelay: Minimum delay between card reset end and ATR start in card clock units. AtrMaxDelay: Maximum delay between card reset end and ATR start in card clock units. AtrMaxLength: Maximum ATR length in ETU units. It is up to the software to notify the Smart Card block of the ATR end with an AtrEnd command. An ATR delay error is raised as a BWT error if a start bit is received before AtrMinDelay after the end of the card reset or if not start bit is received before AtrMaxDelay after the end of the card reset. An ATR length error is raised as a CWT error if the ATR end is not signaled within AtrMaxLength after the start of the ATR. The error is cleared during a card reset or when software reads INT_STAT. 10.2.4.2 Block Wait Time Error (INT_STAT.BWT) This is raised when the time between the last transmitted start bit and the next received start bit exceeds BWT.BWT_TO. COMMAND.ATR_TO_EN must be set to ‘1’ in order to be checked. The error is cleared during a card reset or when the software reads INT_STAT. 10.2.4.3 Character Wait Time Error (INT_STAT.CWT_ERR) This is raised when the time between two consecutive received start bits exceeds CWT.CWT_TO. COMMAND.ATR_TO_EN must be set to ‘1’ in order to be checked. The error is cleared during a card reset or when the software reads INT_STAT. 10.2.4.4 Work Wait Time Error (INT_STAT.WWT_ERR) This is raised when the time between the last received or transmitted start bit and the next received start bit exceeds WWT.WWT_TO. COMMAND.ATR_TO_EN must be set to ‘1’ in order to be checked. The error is cleared during a card reset or when the software reads INT_STAT. 10.2.4.5 Block Guard Time Error (INT_STAT.BGT_ERR) This is raised when the time between the last transmitted start bit and the next received start bit is less than BGT.BGT_TO. COMMAND.ATR_TO_EN must be set to ‘1’ in order to be checked. The error is cleared during a card reset or when the software reads INT_STAT. 10.2.5 Interrupt Generation Interrupt generation is governed by IER and INT_EN. When an interrupt is generated, the corresponding bit is set in LSR or INT_STAT. The status bits are cleared when the status register is read except for the TX Shift and TX Hold Empty. TO_EN.MST_INT_EN acts directly on the interrupt line. For ease of use, the status bits contained in the UART LSR are replicated in the controller’s INT_STAT. Reading this register also clears LSR status bits. DS0200-003 Page 73 Z32AN Series Data Sheet 10.3 Registers 10.3.1 Global Registers (Base → FFFF0000h) 10.3.1.1 Offset Register Description 000h SC_ISTAT Interrupt Status 004h SC_IMASK Interrupt Mask 008h SC_VCC_CFG 00Ch SC_IF_CLKDIV Interface Smart Cards Clock divisor configuration 010h SC_DET_CMD Smart Card detection command 014h SC_SPI_DATA Smart Card SPI Data Register 018h SC_SPI_CLK SPI clock division factor 01Ch SC_STATUS VCC and Reset status from Smart Card interface 024h SC_SPIDMASEL Smart Cards VCC configuration DMA channels to Smart Card and SPI block mapping Offset 000h: SC_ISTAT – Interrupt Status Register Bits Type Reset 31:05 RO 0 Reserved 04 RO 0 Alarm Trigger (ALARM_TRIG): SC_nALARM. 03 RO 0 Alarm (ALARM): When set, SC_nALARM is active. 02 RO 0 Smart Card 1 Interrupt (SC1_INT): When set, Smart Card 1 interrupt is active. This bit is cleared when the status register of the Smart Card 1 is read. 01 RO 0 Smart Card 0 Interrupt (SC0_INT): When set, Smart Card 0 interrupt is active. This bit is cleared when the status register of the Smart Card 1 is read. 00 RO 0 SPI Interrupt (SPI_INT): When set, a collision occurred on SPI. This bit is cleared when the register is read. DS0200-003 Description Set when there is a transition from ‘1’ to ‘0’ on Page 74 Z32AN Series Data Sheet 10.3.1.2 10.3.1.3 Offset 004h: SC_IMASK – Interrupt Mask Bits Type Reset Description 31:05 RO 0 Reserved 04 RW 0 Alarm Trigger Mask (ALARM_TRIG): When set, mask the interrupt when there is a transition from High to Low on the SC_nALARM input. 03 RW 0 Alarm Mask (ALARM): Masks SC_nALARM when this bit is set. 02:01 RO 0 Reserved 00 RW 0 SPI Interrupt Mask (SPI_INT): When set, mask the interrupt from SPI. Offset 008h: SC_VCC_CFG – Smart Cards VCC Configuration Bits Type Reset Description 31:10 RO 0 Reserved 09:08 RW 00 SC4 VCC configuration (SIM4): Configures VCC voltage  00 = 0 V  01 = 1.8 V  10 = 3 V  11 = 5 V 07:06 RW 00 SIM3 VCC configuration (SIM3): Configures VCC voltage. SIM4. Same encodings as 05:04 RW 00 SIM2 VCC configuration (SIM2): Configures VCC voltage. SIM4. Same encodings as 03:02 RW 00 SIM1 VCC configuration (SIM1): SIM4. Configures VCC voltage. Same encodings as 01:00 RW 00 Main VCC configuration (MAIN): SIM4. Configures VCC voltage. Same encodings as DS0200-003 Page 75 Z32AN Series Data Sheet 10.3.1.4 10.3.1.5 Offset 00Ch: SC_IF_CLKDIV – Interface Smart Cards Clock Divisor Configuration Bits Type Reset Description 31:10 RO 0 Reserved 09:08 RW 00 SIM4 CLK Divide Configuration (SIM4): These 2 bits are sent to the SIM4 card to configure clock division.  00: No Clock  01: CLK  10: CLK/2  11: CLK/4 07:06 RW 00 SIM3 Clock Divide Configuration (SIM3): Same encoding as SIM4. 05:04 RW 00 SIM2 Clock Divide Configuration (SIM2): Same encoding as SIM4. 03:02 RW 00 SIM1 Clock Divide Configuration (SIM1): Same encoding as SIM4. 01:00 RW 00 Main Clock Divide Configuration (MAIN): Same encoding as SIM4. Offset 010h: SC_DET_CMD – Detect Command Bits Type Reset 31:05 RO 0 Reserved 04 RW 0 SIM4 Card Detect (SIM4): When set, Smart Card Detected 03 RW 0 SIM3 Card Detect (SIM3): When set, Smart Card Detected 02 RW 0 SIM2 Card Detect (SIM2): When set, Smart Card Detected 01 RW 0 SIM1 Card Detect (SIM1): When set, Smart Card Detected 00 RW 0 Main Card Detect (MAIN): When set, Smart Card Detected DS0200-003 Description Page 76 Z32AN Series Data Sheet 10.3.1.6 10.3.1.7 Offset 014h: SC_SPI_DATA – Smart Card SPI Data Bits Type Reset 31:09 RO 0 Reserved Bypass / Bypass Done (BP_DONE): When written to ‘1’, the data is sent as it is on SPI. When written to ‘0’, bits 4:0 are replaced with programmed values for Card Reset, Card Clock Divisor and Card VCC (as defined by the OnSemi NCN6001 example interface). Card VCC register value is sent if the internal VCC is selected. When read When read as ‘1’, the previous transfer is complete. 08 RW 0 07:00 RW 00h Description SPI data (SPI_DATA): SPI Data Offset 018h: SC_SPI_CLK – SPI Clock Division Factor Register Bits Type Reset 31:04 RO 0 Reserved 03:00 RW 0h SPI Clock Divider (DIV): Clock used is hclk/DIV*2 DS0200-003 Description Page 77 Z32AN Series Data Sheet 10.3.1.8 10.3.1.9 Offset 01Ch: SC_STATUS – Smart Card Interface VCC and Reset Status Bits Type Reset 31:10 RO 0 Reserved Description 09 RO 0 SIM4 Card Reset Status (SIM4_RESET): When set, reset is valid 08 RO 0 SIM4 Card VCC Status (SIM4_VCC): When set, VCC is valid 07 RO 0 SIM3 Card Reset Status (SIM3_ RESET): When set, Reset is valid 06 RO 0 SIM3 Card VCC Status (SIM3_VCC): When set, VCC is valid 05 RO 0 SIM2 Card Reset Status (SIM2_RESET): When set, Reset is valid 04 RO 0 SIM2 Card VCC Status (SIM2_VCC): When set, VCC is valid 03 RO 0 SIM1 Card Reset Status (SIM1_RESET): When set, Reset is valid 02 RO 0 SIM1 Card VCC Status (SIM1_VCC): When set, VCC is valid 01 RO 0 Main Card Reset Status (MAIN_RESET): When set, Reset is valid 00 RO 0 Main Card VCC Status (MAIN_VCC): When set, VCC is valid Offset 024h: SC_SPIDMASEL – Smart Card DMA Channels and SPI Block Mapping ►Warning: Ensure that two Smart Card blocks do not map onto the same DMA channel as it can lead to unpredictable operation. Bits Type Reset 31:06 RO 0 Reserved 05 RW 0 CS Reset (CSR): When set, before each SPI transfer all the Chip Selects will be High for 2 hclk cycles. 04 RW 0 CS Memory (CSM): When set, the chip select which are not addressed will keep the same state as prior to SPI. That is, the 2 chip select can be asserted at the same time. 03 RW 0 SC1 RX (SC1_RX): When set, selects SC1 RX for DMA 02 RW 0 SC0 RX (SC0_RX): When set, selects SC0 RX for DMA 01 RW 0 SC1 TX (SC1_TX): When set, selects SC1 TX for DMA 00 RW 0 SC0 TX (SC0_TX): When set, selects SC0 TX for DMA DS0200-003 Description Page 78 Z32AN Series Data Sheet 10.3.2 Smart Card UART Mode Registers (Base: SC0 → FFFF0100h, SC1 → FFFF0200h) 10.3.2.1 Offset Register Description 000h SC_RBR Receiver Buffer Register 000h SC_THR Transmitter Holding Register 004h SC_IER Interrupt Enable Register 008h SC_IIR Interrupt Identification Register 00Ch SC_LCR Line Control Register 010h SC_BRR Baud Rate Register 014h SC_LSR Line Status Register 018h SC_GR Global Register 01Ch SC_GTIME 020h SC_NUM_REP Number of repetition in Tx Register 024h SC_REV_DLY Reverse delay Register 028h SC_CLK_DIV Clock Divide Register 02Ch SC_NUMTX Number of Data to Send 030h SC_NUMPE Number of Repetition in RX for parity error 034h SC_NUMRX Number of Data to Receive 038h SC_AUTO_PARITY Guard time Register Automatic Parity Offset 00h: SC_RBR – Receive Buffer ►Note: RBR and THR share the same address space. 10.3.2.2 Bits Type Reset 31:08 RO 0 07:00 RW 00h Description Reserved Data (DATA): Receive data. Offset 00h: SC_THR – Transmit Holding ►Note: RBR and THR share the same address space. Bits Type Reset 31:08 RO 0 07:00 RW 00h DS0200-003 Description Reserved Data (DATA): Transmit data. Page 79 Z32AN Series Data Sheet 10.3.2.3 10.3.2.4 Offset 04h: SC_IER – Interrupt Enable Bits Type Reset Description 31:03 RO 0 Reserved 02 RW 0 Rx Line Status Enable (LS): When set, line status interrupt is enabled. 01 RW 0 Tx Hold Register Empty Enable (THRE_EN): When set, THRE interrupt enabled 00 RW 0 Data Ready Enable (DR_EN): When set, data ready interrupt is enabled Offset 08h: SC_IIR – Interrupt Identification Bits Type Reset Description 31:03 RO 0 Reserved 02:01 RO 00 Interrupt source (INT_SRC): Interrupts are prioritized into three levels, as shown below:  00: Not used  01: THRE is source of interrupt  10: DR is source of interrupt  11: Line Status is source of interrupt, OE, PE, or FE. 00 RO 1 Interrupt (INT): When cleared, indicates an interrupt is pending. DS0200-003 Page 80 Z32AN Series Data Sheet 10.3.2.5 Offset 0Ch: SC_LCR – Line Control Bits Type Reset 31:08 RO 0 Reserved 07 RW 0 Data Convention for RX Data (CNV): cleared, normal convention. 06 RW 0 Repetitions Interrupt (REP_INT): When set, enables interrupt when the number of repetitions is reached. 05 RW 0 Sticky Parity (STKY_PAR): parity. 04 RW 0 Parity Select (PAR_SEL): When set, even parity. When cleared, odd parity. 03 RW 0 Parity Enable (PAR_EN): When set, parity bit is generated or checked between the last data word bit and Stop bit of the serial data. 02 RW 0 Stop Bits (STOP_BITS): When set, enables the guard time (stop bit). The minimum is 1 stop bit before sending a new character. The receiver checks the first Stop bit only, regardless of the number of Stop bits selected. When cleared, one stop bit only. 0 Character Length (CHAR_LEN): Specifies number of bits transmitted and received in each serial character.  00: 5 characters  01: 6 characters  10: 7 characters  11: 8 characters 01:00 10.3.2.6 RW Description When set, inverse convention. When set, sticky parity. When When cleared, non-sticky Offset 10h: SC_BRR – Baud Rate Register This holds the factor for dividing the Smart Card clock to produce an ETU timing reference. The formula is: Bits Type Reset 31:14 RO 0 13:04 RW 000h 3:0 RW 0h DS0200-003 Description Reserved Tuning (TUNING): Tuning value for ETU timing reference. Fine Tune (FINE_TUNE): Fine tune adder for ETU reference value 0h to 9h. Page 81 Z32AN Series Data Sheet 10.3.2.7 10.3.2.8 Offset 14h: SC_LSR – Line Status Register Bits Type Reset Description 31:07 RO 0 Reserved 06 RO 1 Transmitter Empty (TEMT): When set, THR and TSR are both empty. 05 RO 1 Transmitter Holding Register Empty (THRE): When set, THR is empty. 04 RO 0 Reserved 03 RO 0 Framing Error (FE): When set, received character did not have a valid stop bit. 02 RO 0 Parity Error (PE): When set, received data character does not have the correct even or odd parity, as selected by the even parity select bit. 01 RO 0 Overrun Error (OE): When set, CPU did not read data from RBR before the next character was transferred into RBR, destroying the previous character. 00 RO 0 Receive Data Ready (DR): When set, data is ready in the receive buffer. Offset 18h: SC_GR – Global Bits Type Reset 31:08 RO 0 Reserved DS0200-003 Description 07 RW 0 WWT Direction (WWT_DIR): When set, this timer can be used for generating an interrupt when the card is talking too early (based upon the value WWT_TO). When cleared, WWT timeout is used when the CARD is talking too late (based upon WWT_TO). 06 RW 0 T1 Enable (T1_EN): When set, during reception no parity error is made on the I/O line and no parity error is signaled, and during transmission parity bit is sent but no error on the I/O line will be taken into account. 05 RW 0 Reset Reception Counter (RST_REP_COUNT): NUM_RX in reading mode. 04 RW 0 Automatic Switch of RX to TX (RX_TO_TX): When set, and AUTO_SWT_EN is set to ‘1’, auto switches from RX to TX in the case of CWT error or an ATR length error. 03 RW 0 Automatic Switch TX to RX (TX_TO_RX): When set, auto switches from TX to RX just after the parity and 2-ETU of stop bit. When cleared, switches after total guard time. 02 RW 0 Automatic Switch from TX to RX (AUTO_SWT_EN): When set, the switch is made when the number of data to send is reached and after the second stop bit of the last send character. When cleared to ‘1’, see TX_TO_RX description. 01 RW 0 Software Reset (SW_RST): When set, generates a software rest. Automatically clears after the reset is complete. 00 RW 1 Communication Direction (DR_EN): When set, receive. When cleared, transmit. When set, automatically reset Page 82 Z32AN Series Data Sheet 10.3.2.9 Offset 1Ch: SC_GTIME – Guard Time Bits Type Reset 31:08 RO 0 07:00 RW 00h Description Reserved Guard Time (GUARD_TIME): Provides the Guard Time value in ETUs.  0x00: 11 ETU (1 stop bit)  0x01: 12 ETU  0x02: 13 ETU  …  0xFF: 266 ETU (256 stop bits) 10.3.2.10 Offset 20h: SC_NUM_REP – Number of Repetition Bits Type Reset 31:04 RO 0 Reserved 0h Number of repeated Parity Errors allowed in TX (RX?) Register (NUM_REP): Holds the maximum number of repetitions in case of receive parity errors.  0x0: 0 repetitions  0x1: 1 repetitions  …  0xF: 15 repetitions 03:00 RW Description 10.3.2.11 Offset 24h: SC_REV_DLY – Reverse Delay Bits Type Reset 31:08 RO 0 07:00 DS0200-003 RW 00h Description Reserved Number of Delay (DELAY_TIME):  0x00: 0 delay  0x01: 1 delay  …  0xFF: 255 delay Page 83 Z32AN Series Data Sheet 10.3.2.12 Offset 28h: SC_CLK_DIV – Clock Divider Bits Type Reset Description 31:16 RO 0 15:08 RW 00h SCI Clock Divider (SCI): Configures the programmable global clock divider situated before the Analog interface Chip. 07:00 RW 00h Card Clock Divider (CARD): Configures the programmable global clock divider. Reserved 10.3.2.13 Offset 2Ch: SC_NUMTX – Number of Data to Send Bits Type Reset 31:16 RO 0 15:00 RW 0000h Description Reserved Number (NUM): Defines the number of data transmissions. The number of transmission is the value in this register plus one. Automatic switch from transmission to reception will occur if IER register bit 13 is set. 10.3.2.14 Offset 30h: SC_NUMPE – Number of Repetition in Rx for Parity Error Before Interrupt Bits Type Reset 31:16 RO 0 15:00 RW 0000h Description Reserved Number (NUM): Defines the number of characters with parity error before generating an interrupt. The number of parity errors is the value in this register plus one. 10.3.2.15 Offset 34h: SC_NUMRX – Number of Receptions Before Interrupt Bits Type Reset 31:16 RO 0 15:00 RW 0000h DS0200-003 Description Reserved Number (NUM): Defines the number of characters to receive before generating an interrupt. RX interrupt must be enabled to use this register. The number of characters is the value in this register plus one. Page 84 Z32AN Series Data Sheet 10.3.2.16 Offset 38h: SC_AUTO_PARITY – Automatic Parity Bits Type Reset 31:09 RO 0 Reserved 08 WO 0 Automatic Parity Enable (AUTO_PAR_EN): When set, enables Auto Parity. 07:00 DS0200-003 WO 00h Description Number of Characters (NUMCHAR): If AUTO_PAR_EN is set, these bits are the value to detect in Rx data for the FIRST_ATR byte. Parity is equal to the bit written to LCR.STKY_PAR, and if not equal parity is changed. When AUTO_PAR_EN is cleared to ‘0’, parity is LCR.STKY_PAR. For configuring parity with LCR.STKY_PAR, you have to disable AUTO_PAR_EN and be idle state. Page 85 Z32AN Series Data Sheet 10.3.3 Smart Card Controller Registers (Base: SC0 → FFFF0100h, SC1 → FFFF0200h) DS0200-003 Offset Register Description 040h SC_COMMAND Command Register 044h SC_INT_STAT Interrupt Status Register 048h SC_INT_EN Interrupt Enable Register 04Ch SC_TO_EN Timeout Enable Register 060h SC_RST_LEN 064h SC_ATR_MIN_DLY Min ATR delay Register 068h SC_ATR_MAX_DLY Max ATR delay Register 06Ch SC_ATR_MAX_LEN Max ATR length Register 070h SC_WWT_TO WWT timeout Register 074h SC_CWT_TO CWT timeout Register 078h SC_BWT_TO BWT timeout Register 07Ch SC_BGT_TO BGT timeout Register 080h SC_DEAC_DLY 284h SC_SIM_SEL Reset length Register Card deactivation delay Register Selection of the SIM (Smart Card 1 Only) Page 86 Z32AN Series Data Sheet 10.3.3.1 Offset x40h: SC_COMMAND – Smart Card Command Bits Type Reset 31:09 RO 0 Reserved 07 RW 0 ATR Timing Interrupt Disable (ATR_TIM_INT_DIS): When set, disables all ATR timing and does not generate interrupt from ATR. 06 RW 0 Send Clock (SEND_CLK): When set, sends the clock without going through the states of the controller state machine. The sequence of activation of the Card Signals (VCC, Clock, IO and reset) must be made with the interface chip (ONSEMI) in parallel with the IP SIM. Not valid with Main Card. 05 RW 0 ATR Timeout Enable (ATR_TO_EN): When set, allows the use of the ATR timing without being in ATR. This bit is reset by writing 1 to ATR_END. 04 RW 0 ATR End (ATR_END): When set, signals the completion of the ATR reception. The bit is automatically reset when the command has been executed. 03 RW 0 Stop Card Clock (STOP_CARD_CK): When set, card clock is stopped. issued anytime during the WaitCommand state of the controller. 02 DS0200-003 RW 0 Description Can be De-activate Card (DEAC_CARD): When set, starts de-activiation sequence. Can be issued anytime during the WaitCommand state of the controller. DEAC_DLY must be loaded with the correct value. This bit is reset when the command has been executed. Note: In the case where the card is removed during the ResetCard Controller state, a deactivation sequence is automatically started. Therefore, DEAC_DLY must be loaded with the correct value prior to a ResetCard command. 01 RW 0 Reset Card Command (RST_CARD): When set, issues a cold or warm reset of the card. This bit is reset when the command has been executed. When issued, a timer is started to count RST_LEN. In the case of a cold reset, software must ensure the power is stable before issuing the command. A warm reset is performed when the controller is in the WaitCommand state. 00 RW 0 Power Card Command (PWR_CARD): When set, the card is powered-on. This bit is reset when the command has been executed. Page 87 Z32AN Series Data Sheet 10.3.3.2 Offset x44h: SC_INT_STAT – Smart Card Interrupt Status Status bits from SC_LSR are replicated in this register to allow software to identify the interrupt source. Reading this register clears LSR (except DR_INT which can only be reset by reading data). Bits Type Reset 31:16 RO 0 Reserved 15 RO 0 ATR Overlap (ATR_OVERLAP): When set, ATR length is reached and a data is overlapping. It is cleared upon reading the register. 14 RO 0 Number of Reception Reached (NB_RX_REACHED): When set, the number of received data has been reached. It is cleared upon reading the register. 13 RO 0 TX Data Sent (TX_DATA_SENT): When set, a byte has been sent by the UART. It is cleared upon reading the register, a soft reset, or when automatic switch is enabled and reception mode is activated. 12 RO 0 BGT Error (BGT_ERR): When set, a BGT error occurred. TO_EN.EN_BGT must be set to ‘1’. It is cleared on reading the register. 11 RO 0 BWT Error (BWT_ERR): When set, a BWT error occurred. TO_EN.EN_BWT must be set to ‘1’. Also occurs when an ATR delay error occurs. It is cleared on reading the register. 10 RO 0 CWT Error (CWT_ERR): When set, a CWT error occurred. TO_EN.EN_CWT must be set to ‘1’. Also occurs when an ATR length error occurs. It is cleared on reading the register. 09 RO 0 WWT Error (WWT_ERR): When set, a WWT error occurred. TO_EN.EN_WWT must be set to ‘1’. It is cleared on reading the register. 08 RO 0 PHY Error (PHY_ERR): When set, the number of character repetitions is reached (in transmission) due to continuous parity errors. It is cleared on reading the register 07 RO 0 Parity Error (PARITY_ERR): When set, a parity error occurred. 06 RO 0 Framing Error (FRAMING_ERR): When set, a framing error occurred. 05 RO 0 Overrun Error (OVERRUN_ERR): When set, an overrun error occurred. 04 RO 0 TX Hold Register Empty (TXHRE): When set, the TX Hold register is empty. 03 RO 0 TX Empty (TX_EMPTY): When set, TX is empty. 02 RO 0 RX Data Ready (DR_INT): When set, receive data is ready. 01 RO 0 Card Removed (CARD_REMOVED): When set, the Card Detect signal goes low. It is cleared on reading the register. No internal de-bouncing of the Card Detect signal is performed. 00 RO 0 Card Inserted (CARD_INSERTED): When set, the Card Detect signal goes high. It is cleared on reading the register. No internal de-bouncing of the Card Detect signal is performed. DS0200-003 Description Page 88 Z32AN Series Data Sheet 10.3.3.3 Offset x48h: SC_INT_EN – Smart Card Interrupt Enable Bits Type Reset 31:15 RO 0 Reserved 14 RW 0 Number of reception reach (NB_RX_REACHED): INT_STAT.NB_RX_REACHED to generate an interrupt. 13 RW 0 TX Data Sent interrupt (TX_DATA_SENT): INT_STAT.TX_DATA_SENT to generate an interrupt. 12 RW 0 BGT Error Interrupt (BGT_ERR): generate an interrupt. 11 RW 0 BWT Error Interrupt (BWT_ERR): When set, a BWT error occurred. BWT timeout checking must be enabled in the Command register or when an ATR delay error occurs. It is cleared on reading the register. 10 RW 0 CWT Error Interrupt (CWT_ERR): When set, a CWT error occurred. CWT timeout checking must be enabled in the Command register or when an ATR length error occurs. It is cleared on reading the register. 09 RW 0 WWT Error Interrupt (WWT_ERR): When set, a WWT error occurs. WWT timeout checking must be enabled in the Command register. It is cleared upon reading the register 08 RW 0 PHY Error Interrupt (PHY_ERR): When set, indicates the number of character repetitions is reached (in transmission) due to continuous parity errors. It is cleared upon reading the register 07:02 RO 0 Reserved 01 RW 0 Card Removed (CARD_REMOVED): Set whenever the Card Detect signal goes Low. It is cleared upon reading the register. No de-bouncing is performed. It must be done externally. 00 RW 0 Card Inserted (CARD_INSERTED): Set whenever the Card Detect signal goes High. It is cleared upon reading the register. No de-bouncing is performed. It must be done externally. DS0200-003 Description When When set, set, enables enables When set, enables INT_STAT.BGT_ERR to Page 89 Z32AN Series Data Sheet 10.3.3.4 10.3.3.5 10.3.3.6 10.3.3.7 Offset x4Ch: SC_TO_EN – Smart Card Timeout Enable Bits Type Reset Description 31:08 RO 0 Reserved 07 RW 0 Master Interrupt Enable (MST): When set, use Interrupt Enable register 06:04 RO 0 Reserved 03 RW 0 Enable BGT Timeout Checking (BGT): When set, BGT timeout checking enabled 02 RW 0 Enable BWT Timeout Checking (BWT): When set, BWT timeout checking enabled 01 RW 0 Enable CWT Timeout Checking (CWT): When set, CWT timeout checking enabled 00 RW 0 Enable WWT Timeout Checking (WWT): When set, WWT timeout checking enabled Offset x60h: SC_RST_LEN – Smart Card Reset Length Bits Type Reset 31:16 RO 0 15:00 RW 0000h Description Reserved Length (LENGTH): Defines the number of card clocks for reset from 0 to 65,535. Offset x64h: SC_ATR_MIN_DLY – Smart Card ATR Minimum Delay Bits Type Reset 31:18 RO 0 17:00 RW 00000h Description Reserved Value (VALUE): Defines number of card clocks for ATR minimum delay from 0 to 262,143 clocks. Offset x68h: SC_ATR_MAX_DLY – Smart Card ATR Maximum Delay Bits Type Reset 31:18 RO 0 17:00 RW 00000h DS0200-003 Description Reserved Value (VALUE): Defines number of card clocks for ATR maximum delay from 0 to 262,143 clocks. Page 90 Z32AN Series Data Sheet 10.3.3.8 10.3.3.9 Offset x6Ch: SC_ATR_MAX_LEN – Smart Card ATR Maximum Length Bits Type Reset 31:18 RO 0 17:00 RW 00000h Description Reserved Value (VALUE): 262,143. Defines number of ETUs for ATR maximum length from 0 to Offset x70h: SC_WWT_TO – Smart Card WWT Timeout Bits Type Reset 31:22 RO 0 21:00 RW 000000h Description Reserved Value (VALUE): Defines number of ETUs for WWT timeout from 0 to 4,194,303. 10.3.3.10 Offset x74h: SC_CWT_TO – Smart Card CWT Timeout Bits Type Reset 31:22 RO 0 21:00 RW Description Reserved Value (VALUE): 4,194,303. 000000h Defines the number of ETUs for CWT timeout from 0 to 10.3.3.11 Offset x78h: SC_BWT_TO – Smart Card BWT Timeout Bits Type Reset Description 31:26 RO 0 25:00 RW 0000000h Reserved Value (VALUE): Defines the number of ETUs for BWT TO from 0 to 33,554,432. 10.3.3.12 Offset x7Ch: SC_BGT_TO – Smart Card BGT Timeout Bits Type Reset 31:22 RO 0 DS0200-003 Description Reserved Page 91 Z32AN Series Data Sheet 21:00 RW 0000h Value (VALUE): Defines the number of ETUs for BGT timeout from 0 to 65,535. 10.3.3.13 Offset x80h: SC_DEAC_DLY – Smart Card Deactivate Delay Bits Type Reset 31:22 RO 0 21:00 RW 000000h Description Reserved DEAC_DLY: Defines number of ETUs for deactivation delay from 0 to 33,554,432. 10.3.3.14 Offset 284h: SC_SIM_SEL – Smart Card SIM Selection Each SIM has its own controller state machine. Bits Type Reset 31:02 RO 0 Reserved 00 Sim Selection (SIM_SEL): Selects the appropriate SIM card to receive command.  00: SIM1  01: SIM2  10: SIM3  11: SIM4 01:00 DS0200-003 RW Description Page 92 Z32AN Series Data Sheet Chapter 11: Real-Time Clock (RTC) The real-time clock (RTC) keeps time by maintaining a count of seconds, minutes, hours, day-of-the-month, month, and year. The current time is kept in 24-hour format. All count and alarm registers are in binary format. The calendar operation maintains the correct day of the month and automatically compensates for leap year. The RTC has a dedicated power supply and maintains operation through the external battery when main power is not available. It contains an alarm which can be used to generate an interrupt or to generate a wake condition. 11.1 Real-Time Clock Time/Counter Registers The time is accessible via a number of RTC registers. The seconds, minutes, hours, day-of-the-month, the month, and year can be read or written through the RTC_SEC, RTC_MIN, RTC_HRS, RTC_DOM, RTC_MON, and RTC_YR, respectively. An additional register, RTC_TIME can be used to read all the time registers in a single 32-bit value. However, only 6 LSB of the RTC_YR are available in this register. ►Note: All read and write operations to these registers must be followed by a read-verify operation. In the case of reads, a second read must be executed and verified as equal to the first read. For writes, the written register must be read back and verified as equal to the expected value. In both cases, this operation must be repeated until verified as correct. This is due to the asynchronous nature of the 32 kHz clock relative to the hclk. In rare cases, complete incorrect values may be read or written. If the RTC APB interface is locked, the RTC cannot be written to. 11.2 RTC Alarm An alarm can be programmed when the current count matches the alarm set-point registers. Alarm registers are available for seconds, minutes, hours, day-of-the-month, month, and year. Each alarm register can be independently enabled in RTC_ACTRL. For example, if the minute and hour alarms are both enabled (while the seconds, day-of-the-month, the month, and year registers are disabled), the alarm only occurs at the specified minute and hour. The alarm triggers an interrupt if RTC_CTRL.ALARM_EN is set to ‘1’. When this occurs, RTC_CTRL.ALARM_STATUS is set to ‘1’. It can be cleared by writing a ‘1’ to RTC_CTRL.ALARM_STATUS. Alarm value and control registers can be written at any time. The comparison of the alarm value to the time value is done once every second. 11.3 RTC Wake Whenever an RTC alarm is generated, a wake indication is also sent to the PMU. For the wake to result in activation of disabled clocks, the PMU must also be programmed. See section Chapter 3: for more details. 11.4 RTC Oscillator Source The RTC contains an internal oscillator which must be connected to an external 32.768 kHz crystal. The crystal must be connected to the RTCXI and RTCXO pins. 11.5 RTC Battery Backup The RTC derives its power from system power, when available. When system power is not available, the RTC derives its power from the battery power supply pin (VBAT). Irrespective of the power source, the RTC continues driving the oscillator and keeping accurate time while valid power remains on at least one of the power sources. 11.6 RTC Reset The alarm, control and time registers of the RTC are not reset in the event of a system reset. DS0200-003 Page 93 Z32AN Series Data Sheet 11.7 Oscillator External Circuit A 32.768 kHz crystal is required for operation of the RTC oscillator. Figure 11-1: RTC Crystal External circuit 11.8 RTC Registers (Base → FFFFB000h) These registers are unknown on initial power up of the battery voltage. 11.8.1 Current Time Registers 11.8.1.1 11.8.1.2 Offset Register Description 000h RTC_SEC Current Seconds 004h RTC_MIN Current Minutes 008h RTC_HRS Current Hours 00Ch RTC_DOM Current Day-of-the-month 010h RTC_MON Current Month 014h RTC_YR Current Year 018h RTC_TIME Current Time Offset 000h: RTC_SEC – Current Seconds Bits Type Reset 31:06 RO 0 05:00 RW Undef Description Reserved Value (VAL): Stores the current seconds count. Maximum value is 59. Offset 004h: RTC_MIN – Current Minutes Bits Type Reset 31:06 RO 0 05:00 RW Undef DS0200-003 Description Reserved Value (VAL): Stores the current minutes count. Maximum value is 59. Page 94 Z32AN Series Data Sheet 11.8.1.3 11.8.1.4 11.8.1.5 11.8.1.6 Offset 008h: RTC_HRS – Current Hours Bits Type Reset 31:05 RO 0 04:00 RW Undef Description Reserved Value (VAL): Stores the current hours count. Maximum value is 23. Offset 00Ch: RTC_DOM – Current Day-of-the-Month Bits Type Reset 31:05 RO 0 04:00 RW Undef Description Reserved Value (VAL): Stores the current day-of-the-month count, including leap year calculations. The counter does not correctly exclude leap days for the years 1900, 2100, i.e. every 200th year. 1 = 1st day, 2 = 2nd day, etc. Offset 010h: RTC_MON – Current Month Bits Type Reset 31:04 RO 0 03:00 RW Undef Description Reserved Value (VAL): December Stores the current month count. 0 = N/A. 1 = January, 12 = Offset 014h: RTC_YR – Current Year Bits Type Reset 31:08 RO 0 07:00 RW Undef DS0200-003 Description Reserved Value (VAL): Stores the current year count. The current year is 1900+YEAR. Valid for 1900–2155. Example: 0x65 = 2001 Page 95 Z32AN Series Data Sheet 11.8.1.7 Offset 018h: RTC_TIM – Current Time Bits Type Reset Description 31:26 RO Undef Year (YR): 6 least significant bits of the 8 bit year value. The current year is 1900+YEAR. Valid for 1900–2155. 25:22 RO Undef Month (MON): Stores the current month count. 1 = January, 12 = December. 0 = N/A 21:17 RO Undef Day of Month (DOM): Stores the current day-of-the-month count, including leap year calculations. The counter does not correctly exclude leap days for the years 1900, 2100, i.e. every 200th year. 1 = 1st day, 2 = 2nd day, etc. 16:12 RO Undef Hours (HRS): Stores the current hours count. Maximum value = 23 11:06 RO Undef Minutes (MIN): Stores the current minutes count. Maximum value = 59 05:00 RO Undef Seconds (SEC): Stores the current seconds count. Maximum value = 59 11.8.2 Alarm Registers 11.8.2.1 11.8.2.2 Offset Register Description 01Ch RTC_ASEC Alarm Seconds 020h RTC_AMIN Alarm Minutes 024h RTC_AHRS Alarm Hours 028h RTC_ADOM Alarm Day-of-the-month 02Ch RTC_AMON Alarm Month 030h RTC_AYR Alarm Year Offset 01Ch: RTC_ASEC – RTC Alarm Seconds Bits Type Reset 31:06 RO 0 05:00 RW Undef Description Reserved Value (VAL): Maximum value is 59. Offset 028h: RTC_AMIN – RTC Alarm Minutes Bits Type Reset 31:06 RO 0 05:00 RW Undef DS0200-003 Description Reserved Value (VAL): Maximum value is 59. Page 96 Z32AN Series Data Sheet 11.8.2.3 11.8.2.4 11.8.2.5 11.8.2.6 Offset 024h: RTC_AHRS – RTC Alarm Hours Bits Type Reset 31:05 RO 0 04:00 RW Undef Description Reserved Value (VAL): Maximum value is 23. Offset 028h: RTC_ADOM – RTC Alarm Day-of-the-Month Bits Type Reset 31:05 RO 0 04:00 RW Undef Description Reserved Value (VAL): Value must be between 1 and 31, inclusive. Offset 02Ch: RTC_AMON – RTC Alarm Month Bits Type Reset 31:04 RO 0 03:00 RW Undef Description Reserved Value (VAL): Value must be between 1 and 12, inclusive. Offset 030h: RTC_AYR – RTC Alarm Year Bits Type Reset 31:06 RO 0 07:00 RW Undef DS0200-003 Description Reserved Value (VAL): Value must be between 0 and 255, inclusive. Page 97 Z32AN Series Data Sheet 11.8.3 Control Registers 11.8.3.1 11.8.3.2 Offset Register Description 034h RTC_ACTRL Alarm Control 038h RTC_CTRL RTC Control Offset 034h: RTC_ACTRL – RTC Alarm Control Bits Type Reset Description 31:06 RO 0 05 RW Undef Year Alarm Enable (AYR_EN): When set, include year in alarm compare. 04 RW Undef Month Alarm Enable (AMON_EN): When set, include month in alarm compare. 03 RW Undef Day-of-the-Month Alarm Enable (ADOM_EN): compare. 02 RW Undef Hour Alarm Enable (AHRS_EN): When set, include hour in alarm compare. 01 RW Undef Minute Alarm Enable (AMIN_EN): When set, include min in alarm compare. 00 RW Undef Seconds Alarm Enable (ASEC_EN): When set, include sec in alarm compare. Reserved When set, Include day in alarm Offset 038h: RTC_CTRL – RTC Control Bits Type Reset 31:03 RO 0 Reserved 02 WO 0 Load Ripple (LOAD_RIPPLE): This bit is used only for manufacturing test. Writing one to this bit forces the RTC ripple counter to a value such that a 1 Hz clock positive edge is generated upon the next rising edge of the 32 kHz clock. Always returns ‘0’ on reads. 01 RW1C Undef RTC interrupt status (ALARM_STATUS): The interrupt is activated on an RTC alarm compare. When set, the interrupt is active. 00 RW Undef Interrupt on Alarm Condition (ALARM_EN): When set, enabled. DS0200-003 Description Page 98 Z32AN Series Data Sheet 11.9 RTC Locking Access to the RTC is locked upon a system reset of the main system, or an invalid write to the RTC_LCK2. While locked, writes are disabled to the RTC except to RTC_LCK1 and RTC_LCK2. APB may be identified as “unlocked” by reading RTC_APB_STA.APB_UNLOCKED. The lock is provided to prevent spurious writes during power up and down of the main system. Figure 11-2: APB Lock State Machine Address Register Description FFFFC00Ch RTC_APB_STA FFFFC694h RTC_LCK1 RTC Lock 1 Register FFFFC968h RTC_LCK2 RTC Lock 2 Register RTC APB Status Register 11.9.1 Address FFFFC00Ch: RTC_APB_STA – RTC APB Status Register Bits Type Reset 31 RO 1 APB Unlocked (APB_UNLOCKED): Indicates if the APB bus is locked or unlocked. Security accesses and secure memory are not possible if APB is locked. 30:00 RO 0 Reserved DS0200-003 Description Page 99 Z32AN Series Data Sheet 11.9.2 Address FFFFC694h: RTC_LCK1 – RTC Lock 1 Register Bits Type Reset 31:00 WO 0 Description Value (VAL): First of two registers which must be written to unlock accesses to the RTC registers. A write of 89ABCDEFh must be done to start the sequence, and a write of 76543210h to RTC_LCK2 completes the sequence. If any other write occurs to the RTC between these two writes, the RTC remains locked. 11.9.3 Address FFFFC698h: RTC_LCK2 – RTC Lock 2 Register Bits 31:00 DS0200-003 Type WO Reset 0 Description Value (VAL): Second of two registers which must be written to unlock accesses to the RTC registers. See description for RTC_LCK1. Once unlocked, APB remains unlocked until:  A hard reset of the main system  This register is written with a value other than 0x76543210.  A read access of this write only register Page 100 Z32AN Series Data Sheet Chapter 12: Random Number Generator (RNG) The Random Number Generator (RNG) is an APB device with the following features:     True 32-bit random number generation Interrupt Generation on completion of random number Generation rate of 1 number in less than 256 hclk cycles NIST 800-22 Compliant 12.1 Programming Guide 1. 2. 3. 4. 5. Ensure that RNG_CTRL.REQ and RNG_CTRL.GRANT are cleared to ‘0’. Set RNG_CTRL.REQ to ‘1’. If an interrupt is desired also set RNG_CTRL.IRQ_EN to ‘1’. RNG_CTRL.IRQ_CLR must be cleared to ‘0’. Wait for RNG_CTRL.GRANT to be set ‘1’, either by polling or receiving an IRQ (if RNG_CTRL.IRQ_EN was set). Clear RNG_CTRL.REQ and RNG_CTRL.IRQ_CLR to ‘0’. This action clears RNG_CTRL.GRANT bit as well as the contents of RNG_DATA. If active, the interrupt can be cleared by writing RNG_CTRL.IRQ_CLR to ‘1’. 12.2 RNG Registers (Base → FFFFA000h) Offset Register Description 000h RNG_DATA RNG Data Register 004h RNG_CTRL RNG Control Register 12.2.1 Offset 000h: RNG_DATA – Random Number Generator Data Register Bits 31:00 DS0200-003 Type RO Reset 0 Description Random Number (NUM): Valid when RNG_CTRL.GRANT is ‘1’. RNG_CTRL.REQ clears this register. Clearing Page 101 Z32AN Series Data Sheet 12.2.2 Offset 004h: RNG_CTRL – Random Number Generator Control Register Bits Type Reset 31:07 RO 0 Reserved 06 RO 0 IRQ Status (IRQ): Set when GRANT is set, and IRQ_EN was ‘1’. 05 RO 0 Grant (GRANT): When set, indicates a new random number is available in RNG_DATA. This goes active some time after REQUEST is set. Once set, it remains set until REQUEST is cleared. 04 RO 0 Reserved 03 WO 0 IRQ Clear (IRQ_CLR): Writing 1 to this bit causes the IRQ to be cleared. Any write with this bit set does not affect other bits of this register. Writes of ‘0’ have no effect. 02 RW 0 IRQ Enable (IRQ_EN): When set, enables IRQ to go active when a GRANT transitions to 1. Any write to RNG_CTRL with the IRQ CLR bit set do not affect this bit. DS0200-003 Description 01 RW 0 Request (REQUEST): When set, initiates generation of a new random number. After this bit is set, GRANT indicates a new random number is available. Once GRANT is set to ‘1’, this bit must be cleared. Clearing REQUEST will have following two effects:  GRANT is cleared.  The contents of RNG_DATA are cleared. Any write to RNG_CTRL with IRQ_CLR set do not affect this bit. 00 RO 0 Reserved Page 102 Z32AN Series Data Sheet Chapter 13: SHA-1 The SHA-1 module provides a message digest for given text of almost any length per the SHA-1 protocol. 13.1 Programming Guide To generate a hashed signature value, execute the following actions: 1. 2. 3. If the existing hash value is acceptable, set SHA1_CONTROL.INIT to ‘1’. Alternatively, write SHA1_WH with a hash value, and set SHA1_CONTROL.INIT and SHA1_CONTROL.INIT_SEL to ‘1’. Write a value to SHA1_DATA_IN.DATA. Sixteen writes to W_IN must be performed to provide data to the SHA-1. DMA can be used to provide these values. Wait for 65 clocks and read SHA1_STATUS.VALID. Once this bit is set, SHA1_H contains the output. SHA1_STATUS.VALID remains set until all 5 registers are read. 13.2 SHA-1 Registers (Base → FFFF9000h) Address Register Description 000h – 010h SHA1_H 014h SHA1_DATA_IN Data IN register 018h SHA1_CONTROL SHA-1 Control 01Ch SHA1_STATUS SHA-1 Status Control 020h – 030h SHA1_WH Initial hash value 0-4 Hashed value 0-4 from SHA-1 13.2.1 Offset 000h: SHA1_H – Hashed Value Bits Type Reset Description 159:127 RO C3D2E1F0h H-4 (H_4): This value is valid when STATUS.VALID is ‘1’. 127:96 RO 10325476h H-3 (H_3): This value is valid when STATUS.VALID is ‘1’. 95:64 RO 98BADCFEh H-2 (H_2): This value is valid when STATUS.VALID is ‘1’. 63:32 RO EFCDAB89h H-1 (H_1): This value is valid when STATUS.VALID is ‘1’. 31:00 RO 67452301h H-0 (H_0): This value is valid when STATUS.VALID is ‘1’. 13.2.2 Offset 014h: SHA1_DATA_IN – Data In Bits Type Reset 31:00 WO 00000000h DS0200-003 Description Data (DATA): 32-bit value for SHA-1. Page 103 Z32AN Series Data Sheet 13.2.3 Offset 018h: SHA1_CONTROL – SHA-1 Control Bits Type Reset DescriptionDS0200.docx 31:02 RO 0 Reserved 03 WO 0 Endian Select (END_SEL): Set to match the Endian type of data used. When written to ‘0’, little Endian data. When written to ‘1’, big Endian data 02 RO 0 Reserved 01 WO 0 Initialization Select (INIT_SEL): When set, WH_0 through WH_4 are copied to H_0 to H_4 when INIT is set to ‘1’. 00 WO 0 Initialize (INIT): Initializes to start the SHA-1. When written to ‘0’, no effect. When written to ‘1’, initializes SHA-1 registers 13.2.4 Offset 01Ch: SHA1_STATUS – SHA-1 Status Bits Type Reset Description 31:01 RO 0 Reserved 00 RO 0 Valid (VALID): When set, value is valid to read from H_0 through H_4. After H_0 through H_4 are read, the bit clears to ‘0’. 13.2.5 Offset 020h: SHA1_WH – SHA-1 Initialization Value DS0200-003 Bits Type Reset Description 159:128 RW 00000000h Initial H_4 Value (WH_4): Copied to H_4 when CONTROL.INIT_SEL is set. 127:96 RW 00000000h Initial H_3 Value (WH_3): Copied to H_3 when CONTROL.INIT_SEL is set. 95:64 RW 00000000h Initial H_2 Value (WH_2): Copied to H_2 when CONTROL.INIT_SEL is set. 63:32 RW 00000000h Initial H_1 Value (WH_1): Copied to H_1 when CONTROL.INIT_SEL is set. 31:00 RW 00000000h Initial H_0 Value (WH_0): Copied to H_0 when CONTROL.INIT_SEL is set. Page 104 Z32AN Series Data Sheet Chapter 14: Analog-to-Digital Converter (ADC) The ADC is an APB device with the following features:           10-bit resolution, 45 kHz, successive-approximation ADC Multiplexing to support 4 channel inputs 4 sample FIFO Support for DMA SINGLE SHOT or CONTINUOUS sample modes Programmable ADC clock 12 cycle conversion time (ADC clock cycles) Power down to AVDD_RTC ) ICCS ICCI Supply Currents in IDLE ICCA Supply Currents Active ICCMHA Supply Currents High Active Supply Current from (backup mode, VBAT only) ICCB Supply Current from Battery (with system power on) 1. DS0200-003 Battery RTC This condition excludes all pins that have on-chip pull-ups, when driven Low. Page 178 Z32AN Series Data Sheet 21.3 AC Characteristics Table 21-2: AC Characteristics VDDIO = 3.0 – 3.6V VDDCORE=1.71–1.89V TA = –400C to 850C Symbol Parameter System Clock Frequency FCLK Min Max Units Conditions — 200 MHz fclk — 100 MHz hclk, CLKOUT 14.0 40.0 MHz Without USB 24.0 24.0 MHz Required for USB operation FCLKXI Crystal Frequency TCLKXI CLKXI Clock Period 25.0 — ns TCLKXI = 1/FCLKXI TXINH CLKXI High Time 40%TCLKXI 60%TCLK_XI ns TCLKXI = 25ns TXINL CLKXI Low Time 40%TCLKXI 60%TCLK_XI ns TCLKXI = 25ns TXINR CLKXI Rise Time — 2 ns TCLKXI = 25ns TXINF CLKXI Fall Time — 2 ns TCLKXI = 25ns Table 21-3: Power-On Reset Electrical Characteristics and Timing Symbol TA = –400C to 850C Parameter Min Max Units Conditions VPOR POR Voltage Threshold for Core Power 1.62 1.71 V After UV POR TRIM. VDD = VPOR VOVR Over Voltage Reset Threshold for Core Power 1.89 1.98 V After OV POR TRIM. VDD = VPOR VPOR hysteresis 0 60 mV Starting VDD voltage to ensure valid PowerOn Reset. — — V 10 s TPORD Power-On Reset Delay TPOR Power-On Reset Digital Delay clocks Cycles after Crystal is stable. Table 21-4: Analog-to-Digital Converter Electrical Characteristics Symbol Parameter Full Scale Input Range VDDA = 3.0 – 3.6V TA = 00C to 850C Min Typ Max 0 — VREF V — 45 kSps Maximum Sample Rate Data Latency — 12 — cycles Input Clock Frequency — 540 — kHz Resolution — 10 — bits Differential Nonlinearity (DNL) –1.0 — 1.0 LSB Integral Nonlinearity (INL) –2.0 — 2.0 DC Offset Error VREF DS0200-003 Units ADC Reference Voltage ±2 — VDDADC LSB % FS — Conditions V Percent of Full Scale Should filter for best performance Page 179 Z32AN Series Data Sheet 21.4 External Memory Timing Figure 21-1: External Memory I/O Timing Parameter Description Symbol Output Delay Delay from internal hclk to output pin tPD Setup Time Setup time from input stable to internal hclk tSU Pins Min Max nCS[9:0], nWEU, nWEL, nOE 1.92ns 4.72ns MA[12:0], MD[15:0] 1.83ns 4.72ns MD[15:0] 5.78ns — 21.5 SDRAM Timing Figure 21-2: SDRAM Interface I/O Timing Parameter Description Symbol Pins Min Max Output Delay Delay from rising edge of SDCLK to output valid tPD CKE, nCS[1], nRAS, nCAS, nWE, DQM[1:0] 1.92ns 6.06ns MA[12:0], MD[15:0] 1.91ns 6.85ns Setup Time Setup time from input valid to rising edge of SDCLK tSU MD[15:0] 3.49ns — DS0200-003 Page 180 Z32AN Series Data Sheet 21.6 USB Electrical and Timing The Z32AN Series conforms to the Universal Serial Bus 2.0 standard specification. Figure 21-3: USB Data Signal Timing TA = –400C to 850C Symbol Parameter Min Max Units Conditions ICCUSB Supply Currents in STOP with USB Suspend — — µA No I/O switching, all blocks and oscillator disabled. USB Transceivers configured to wake with activity. tR Time for data to rise from 10% to 90% of rail values 4.0 20.0 ns tF Time for data to fall from 90% to 10% of rail values 4.0 20.0 ns DS0200-003 USB Full speed USB Full speed Page 181 Z32AN Series Data Sheet Chapter 22: Packaging 22.1 Soldering Information All Zilog products designated with as “Green” are RoHS compliant. 22.2 Top Mark The Top Mark contains 4 lines, as follows:      DS0200-003 Line 1: Zilog Logo and ARM Logo. Line 2: Denotes the SOC part number. Example: Z32AN12NW200XG Line 3: Denotes Customer ID or special lot number and type of lot (i.e. engineering sample). Line 4: Date code: Year (YY), week (XX), and lot coding (BB). Line 5: Country of origin. Page 182 Z32AN Series Data Sheet Chapter 23: Ordering Information Part Number RAM (KB) Smart Card Reader IF Magnetic Card Reader I/O UARTs SPI ADC Inputs USB Timers RTC 256 BGA package -40oC to 85oC Temp Range The table below lists the available packages for Z32AN Series ARM SOC and provides a brief description of each product. Z32AN00NW200SG 64 0 0 76 3 2 4 2 9 Yes X X Z32AN01NW200SG 64 0 1 76 3 2 4 2 9 Yes X X Z32AN10NW200SG 64 2 0 76 3 2 4 2 9 Yes X X Please contact your local Zilog® sales offices for assistance in ordering the part(s) required. The product represented by this document is newly introduced and Zilog has not completed the full characterization of the product. The document states what Zilog knows about this product at this time, but additional features or non-conformance with some aspects of the document may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. For more information, please visit www.zilog.com. Chapter 24: Customer Support For answers to technical questions about the Z32AN, documentation, or any other issues, please contact techsupport@zilog.com. DS0200-003 Page 183