Z32F06410AKS

ZNEO32! Cortex-M3 Z32F0641 MCU Product Specification PS034404-0417 PRELIMINARY Copyright ©2017 Zilog®, Inc. All rights reserved. www.zilog.com Z32F0641 MCU Product Specification ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2017 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. ZNEO32! is a trademark or registered trademark of Zilog, Inc. All other product or service names are the property of their respective owners. PS034404-0417 PRELIMINARY Z32F0641 MCU Product Specification iii Revision History Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Revision Level Description Page Apr 2017 04 Updated part numbers to include the Cortex M identifier. All Aor 2016 03 Added timing information for peripherals; global edits for clarity. All Feb 2016 02 Updated Figure 18.2 LQFP-32 Package Dimension. 178 Nov 2015 01 Original issue. Date PS034404-0417 PRELIMINARY Revision History Z32F0641 Product Specification 1. Overview Overview Introduction Zilog’s Z32F0641 MCU, a member of the ZNEO32! Family of microcontrollers, is a cost-effective and highperformance 32-bit microcontroller. The Z32F0641 MCU provides a 3-phase PWM generator unit which is suitable for inverter bridges, including motor drive systems. Two 12-bit high speed ADC units with 16-channel analog multiplexed inputs support feedback retrieval from the inverter bridge. Multiple powerful external serial interfaces help communicate with on-board sensors and devices. Figure 1.1 shows a block diagram of the Z32F0641 MCU. Figure 1.1 Block Diagram PS034404-0417 PRELIMINARY 1 Z32F0641 Product Specification Overview Figure 1.2 and Figure 1.3 show the pin layouts. Figure 1.2 Pin Layout (LQFP-48) PS034404-0417 PRELIMINARY 2 Z32F0641 Product Specification Overview Figure 1.3 Pin Layout (LQFP-32) PS034404-0417 PRELIMINARY 3 Z32F0641 Product Specification Overview Product Features The Z32F0641 MCU offers the following features:                 High Performance low-power Cortex-M3 core 64 KB code Flash memory with cache function 8 KB SRAM 3-Phase PWM with ADC triggering function 1.5Msps high-speed ADC with sequential conversion function o 2 units with 11 channel Inputs Watchdog timer Six general purpose timers o Periodic, One-shot, PWM, Capture mode o Multi-timer synchronization option External communication ports: o 2 UARTs o 1 I2C o 1 SPI Direct Memory Access (DMA) controller with 4 channels System fail-safe function by clock monitoring XTAL OSC fail monitoring Debug and emergency stop function Serial Wire Debug (SWD) and JTAG Debugger (JTAG is only for LQFP-48) Supports UART and SPI ISP Two types of package options o LQFP-48 (0.5mm pitch) o LQFP-32 (0.65mm pitch) Industrial grade operating temperature (-40 ~ +85℃) Table 1.1 Device Type Part Number Flash SRAM UART SPI I2C MPWM ADC I/O Ports Package Z32F06410AES 64KB 8KB 2 1 1 1 2-unit 11 ch 44 LQFP-48 Z32F06410AKS 64KB 8KB 2 1 1 1 2-unit 8 ch 30 LQFP-32 PS034404-0417 PRELIMINARY 4 Z32F0641 Product Specification Overview Architecture Block Diagram An internal block diagram of the Z32F0641 MCU is shown in Figure 1.4. JTAGS WD NMI DEBUG NVIC Cortex-M3 (Max. 48MHz) CODE FLASH (64KB) SRAM (8KB) POR Advanced High-Performance Bus (AHB) Matrix VDC LVD DMAC Advanced Peripheral Bus (APB) RingOSC MainOSC PLL UART x 2 SCU SPI x 1 16-bit WDT I2C x 1 16-bit TIMER x 6 1.5Msps 12-bit ADC 11 ch PA PB PC PD Figure 1.4 Internal Block Diagram PS034404-0417 PRELIMINARY 5 Z32F0641 Product Specification Overview Functional Description The following section provides an overview of the features of the Z32F0641 microcontroller. ARM Cortex-M3       ARM-powered Cortex-M3 core based on ARMv7M architecture, which is optimized for small-size and low-power systems. On core system timer (SYSTICK) provides a simple 24-bit timer that enables easy management of system operations Thumb-compatible Thumb-2 only instruction set processor core makes code high-density Hardware division and single-cycle multiplication Integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling JTAG and SWD debugging features Maximum 48 MHz operating frequency with zero wait execution Nested Vector-Interrupt Controller (NVIC)    The ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core handles all internal and external exceptions. When an interrupt condition is detected, the processor state is automatically stored to the stack and automatically restored from the stack at the end of interrupt service routine. The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which allows for back-to-back interrupts to be performed without the overhead of state saving and restoring 64 KB Internal Code Flash Memory   The Z32F0641 MCU provides internal 64 KB code Flash memory and its controller, which is sufficient to program the motor algorithm and control the system. Self-programming is available and ISP and JTAG programming is also supported in boot or debugging mode. Instruction and data cache buffer are present and overcome the low-bandwidth Flash memory. The CPU can execute from Flash memory with zero wait state up to 48 MHz bus frequency. 8 KB 0-wait Internal SRAM  On chip 8 KB 0-wait SRAM can be used for working memory space and program code can be loaded on this SRAM Boot Logic  Smart boot logic supports Flash programming. The Z32F0641 MCU can be accessed by an external boot pin; UART and SPI programming are available in Boot Mode System Control Unit  The System Control Unit (SCU) block manages internal power, clock, reset, and Operation Mode. The SCU also controls analog blocks (Oscillator Block, VDC and LVD) 32-bit Watchdog Timer  The Watchdog Timer (WDT) performs the system monitoring function. The WDT generates an internal reset or interrupt if the system is in abnormal state Multi-purpose 16-bit Timer  Six-channel 16-bit general purpose timers support the following functions o Periodic timer mode o Counter mode o PWM mode o Capture mode PS034404-0417 PRELIMINARY 6 Z32F0641 Product Specification  Overview Built-in timer also supports counter-synchronization mode which can generate synchronized waves and timing Motor PWM Generator    3-phase Motor PWM Generator is implemented. 16-bit up/down counter with prescaler supports triangular and saw tooth waveforms PWM has the ability to generate internal ADC trigger signals to measure the signal on time Dead time insertion and emergency stop functionality provide overcurrent protection for the chip and system Serial Peripheral Interface (SPI)   The Serial Peripheral Interface (SPI) block provides synchronous serial communication. The Z32F0641 MCU has 1 channel SPI module which includes the DMA function supported by a DMA controller. Transfer data is moved to/from the memory area without CPU operation Boot Mode uses this SPI block to download the Flash program Inter-Integrated Circuit Interface  The Z32F0641 MCU has 1 channel Inter-Integrated Circuit (I2C) block which supports up to 400 kHz I2C communication. Master and slave modes are supported Universal Asynchronous Receiver/Transmitter   The Z32F0641 MCU has 2 channels Universal Asynchronous Receiver/Transmitter (UART) block. For accurate baud rate control, the fractional baud rate generator is provided The UART features the DMA function, supported by a DMA controller. Transfer data is moved to/from the memory area without CPU operation General PORT I/Os    16-bit PA, PB, PC, and PD ports are available and provide multiple functionality: o General I/O port o Independent bit set/clear function o External interrupt input port Programmable pull-up and open-drain selection On-chip input debounce filter 12-bit Analog-to-Digital Converter (ADC)   2 built-in Analog-to-Digital Converters (ADC) can convert analog signals up to 1.5 Msps conversion rate. 11-channel analog MUX provides various combinations from external analog signals. The ADC features the DMA function, supported by a DMA controller. Transfer data is moved to/from the memory area without CPU operation. PS034404-0417 PRELIMINARY 7 Z32F0641 Product Specification Overview Pin Description Pin configurations are listed in Table 1.2. Table 1.2 Pin Description Pin Name LQFP48 LQFP32 1 2 3 4 5 6 7 8 9 10 1 2 3 4 - - 5 6 7 - Pin Name Type Description PA0* IOUS PORT A Bit 0 Input/Output AN0 IA Analog Input 0 PA1* IOUS PORT A Bit 1 Input/Output AN1 IA Analog Input1 PA2* IOUS PORT A Bit 2 Input/Output WDTO O Watchdog timer overflow output AN2 IA Comparator 2 Input PA3* IOUS PORT A Bit 3 Input/Output AN3 IA Analog Input 3 PA4* IOUS PORT A Bit 4 Input/Output SS1 I/O Slave Select 1 for SPI0 AN4 IA Analog Input 4 PA5* IOUS PORT A Bit 5 Input/Output SS2 I/O Slave Select 2 for SPI0 AN5 IA Analog Input 5 PA6* IOUS PORT A Bit 6 Input/Output T0IO I/O Timer 0 Input/Output T2IO I/O Timer 2 Input/Output AN6 IA Analog Input 6 PA7* IOUS PORT A Bit 7 Input/Output T1IO I/O Timer 1 Input/Output T3IO I/O Timer 3 Input/Output AN7 IA Analog Input 7 PA8* IOUS PORT A Bit 8 Input/Output T2IO I/O Timer 2 Input/Output T0IO I/O Timer 0 Input/Output AN8 IA Analog Input 8 PA9* IOUS PORT A Bit 9 Input/Output T3IO I/O Timer 3 Input/Output T1IO I/O Timer 1 Input/Output AN9 IA Analog Input 9 PA10* IOUS PORT A Bit 10 Input/Output SS3 Output ETM Trace Data 1 11 - AN10 IA Analog Input 10 12 8 VDD P VDD 13 9 GND P Ground 14 - PA11* IOUS PORT A Bit 11 Input/Output PA12* IOUS PORT A Bit 12 Input/Output T0IO I/O Timer 0 Input/Output 15 PS034404-0417 - PRELIMINARY Remark 8 Z32F0641 Product Specification 16 - 17 - 18 - 19 10 20 21 11 12 22 13 23 14 24 15 25 16 26 27 28 29 30 31 32 33 PS034404-0417 17 18 19 20 - - - - PA13* IOUS PORT A Bit 13 Input/Output T1IO I/O Timer 1 Input/Output PA14* IOUS PORT A Bit 14 Input/Output T2IO I/O Timer 2 Input/Output PA15* IOUS PORT A Bit 15 Input/Output T3IO I/O Timer 3 Input/Output PB0 IOUS PORT B Bit 0 Input/Output PWM0UH Output PWM0 UH Output PB1 IOUS PORT B Bit 1 Input/Output PWM0UL Output PWM0 UL Output PB2 IOUS PORT B Bit 0 Input/Output PWM0VH Output PWM0 VH Output PB3 IOUS PORT B Bit 1 Input/Output PWM0VL Output PWM0 VL Output PB4 IOUS PORT B Bit 4 Input/Output PWM0WH Output PWM0 WH Output PB5 IOUS PORT B Bit 5 Input/Output PWM0WL Output PWM0 WL Output PB6 IOUS PORT B Bit 6 Input/Output PRTIN0 Input PWM0 Protection Input signal 0 T0IO I/O Timer 0 Input/Output PB7 IOUS PORT B Bit 7 Input/Output OVIN0 Input PWM0 Over-voltage input signal 0 T1IO I/O Timer 1 Input/Output PC0 IOUS PORT C Bit 0 Input/Output T CK/SW C K Input JTAG TCK, SWD Clock Input RXD1 Input UART0 Rx Data Input PC1 IOUS PORT C Bit 1 Input/Output TMS/SWDI O I/O JTAG TMS, SWD Data Input/Output TXD1 Input UART0 Tx Data Output PC2 IOUS PORT C Bit 2 Input/Output TDO/SWO Output JTAG TDO, SWO Output T8IO I/O Timer 8 Input/Output PC3 IOUS PORT C Bit 3 Input/Output TDI Input JTAG TDI Input T9IO I/O Timer 9 Input/Output PC4 IOUS PORT C Bit 4 Input/Output nTRST Input JTAG nTRST Input T0IO Input Timer 0 input/Output PC5 IOUS PORT C Bit 5 Input/Output RXD1 Input UART1 RXD Input T1IO I/O Timer 1 input/Output PC6 IOUS PORT C Bit 6 Input/Output TXD1 Output UART1 TXD Output PRELIMINARY Overview 9 Z32F0641 Product Specification 34 21 T2IO I/O Timer 2 input/Output PC11 IOUS PORT C Bit 11 Input/Output BOOT Input Boot mode Selection Input T9IO I/O Timer 9 input/Output PC10 IOUS PORT C Bit 10 Input/Output nRESET Input External Reset Input 35 22 T8IO I/O Timer 8 input/Output 36 23 GND P Ground 37 24 VDD P VDD PC7 IOUS PORT C Bit 7 Input/Output SCL0 Output I2C Channel 0 SCL In/Out T3IO I/O Timer 3 input/Output PC8 IOUS PORT C Bit 8Input/Output SDA0 Output I2C Channel 0 SDA In/Out PC9 IOUS PORT C Bit 9 Input/Output CLKO Output System Clock Output PC15 IOUS PORT C Bit 14 Input/Output TXD0 Output UART0 TXD Output MISO0 I/O SPI0 Master-Input/Slave-Output PC14 IOUS PORT C Bit 14 Input/Output RXD0 Input UART0 RXD Input MOSI0 I/O SPI0 Master-Output/Slave-Input PC13 IOUS PORT C Bit 13 Input/Output XOUT OA External Crystal Oscillator Output PC12 IOUS PORT C Bit 12 Input/Output XIN IA External Crystal Oscillator Input PD0 IOUS PORT D Bit 0 Input/Output SS0 I/O SPI1 Slave Select T8IO I/O Timer 8 input/Output PD1 IOUS PORT D Bit 1 Input/Output SCK0 I/O SPI0 Clock Input/Output T9IO I/O Timer 9 input/Output PD2 IOUS PORT D Bit 2 Input/Output MISO0 I/O SCL0 Output I2C Channel 0 SCL In/Out PD3* IOUS PORT D Bit 3 Input/Output MOSI0 I/O SDA0 Output 38 - 39 - 40 - 41 42 25 26 43 27 44 28 45 29 46 47 48 30 31 32 Overview Pull-up SPI Channel 0 Master In / Slave Out SPI Channel 0 Master Out / Slave In I2C Channel 0 SDA In/Out *Notation: I=Input, O=Output, U=Pull-up, D=Pull-down, S=Schmitt-Trigger Input Type, C=CMOS Input Type, A=Analog, P=Power (*) Selected pin function after reset condition Pin order may be changed with revision notice. PS034404-0417 PRELIMINARY 10 Z32F0641 Product Specification Overview Memory Map Address Memories mapped 0x0000_0000 FLASH ROM (64KB) 0x0000_FFFF 0x0001_0000 RESERVED 0x0001_FFFF 0x0002_0000 RESERVED 0x1FFE_FFFF 0x1FFF_0000 BOOT ROM (2KB) 0x1FFF_07FF 0x1FFF_0800 RESERVED 0x1FFF_FFFF 0x2000_0000 SRAM (8KB) 0x2000_1FFF 0x2000_2000 RESERVED 0x2FFF_FFFF 0x3000_0000 FLASH ROM Mirrored (64KB) 0x3000_FFFF 0x3001_0000 RESERVED 0x3001_FFFF 0x3002_0000 BOOT ROM (2KB) Mirror 0x3002_07FF 0x3003_0000 OTP Mirror 0x3003_07FF 0x3004_0000 RESERVED 0x3FFF_FFFF 0x4000_0000 0x4000_FFFF PERIPHERALS 0x4001_0000 RESERVED 0x5FFF_FFFF 0x6000_0000 External RAM (Not support) 0x9FFF_FFFF 0xA000_0000 External DEVICE(Not support) 0xDFFF_FFFF 0xE000_0000 Private peripheral bus: Internal 0xE003_FFFF 0xE004_0000 Private peripheral bus: Debug/External 0xE00F_FFFF 0xE010_0000 0xFFFF_FFFF Vendor Specific Figure 1.5 Main Memory Map PS034404-0417 PRELIMINARY 11 Z32F0641 Product Specification Address Peripherals mapped 0x4000_0000 SCU 0x4000_00FF 0x4000_0100 FMC 0x4000_01FF 0x4000_0200 WDT 0x4000_02FF 0x4000_0300 Reserved 0x4000_03FF 0x4000_0400 DMAC 0x4000_04FF 0x4000_0500 Reserved 0x4000_05FF 0x4000_0600 Reserved 0x4000_0FFF 0x4000_1000 PCU 0x4000_1FFF 0x4000_2000 GPIO 0x4000_2FFF 0x4000_3000 TIMER 0x4000_3FFF 0x4000_4000 MPWM0 0x4000_4FFF 0x4000_5000 Reserved 0x4000_7FFF 0x4000_8000 UART0 0x4000_80FF 0x4000_8100 UART1 0x4000_81FF 0x4000_8200 Reserved 0x4000_8FFF 0x4000_9000 SPI0 0x4000_90FF 0x4000_9100 Reserved 0x4000_9FFF 0x4000_A000 I2C0 0x4000_A0FF 0x4000_A100 Reserved 0x4000_AFFF 0x4000_B000 ADC0 0x4000_B0FF 0x4000_B100 ADC1 0x4000_B1FF 0x4000_B200 0x4000_FFFF Reserved Overview Figure 1.6 Peripheral Memory Map PS034404-0417 PRELIMINARY 12 Z32F0641 Product Specification Address 0xE000_0000 Overview Core Memory Map ITM 0xE000_0FFF 0xE000_1000 DWT 0xE000_1FFF 0xE000_2000 FPB 0xE000_2FFF 0xE000_3000 Reserved 0xE000_DFFF 0xE000_E000 System Control 0xE000_EFFF 0xE000_F000 Reserved 0xE003_FFFF 0xE004_0000 TPIU 0xE004_0FFF 0xE004_1000 ETM 0xE004_1FFF 0xE004_2000 0xE00F_EFFF 0xE00F_F000 External PPB ROM Table 0xE00F_FFFF Figure 1.7 Cortex-M3 Private Memory Map Note: Refer to document number DDI337 from ARM for more information about the memory maps. PS034404-0417 PRELIMINARY 13 Z32F0641 Product Specification 2. CPU CPU Cortex-M3 Core The CPU core is supported by the ARM Cortex-M3 processor which provides a high-performance, low-cost platform. Document number DDI337 from ARM provides more information about Cortex-M3. Interrupt Controller Table 2.1 Interrupt Vector Map PS034404-0417 Priority Vector Address Interrupt Source -16 0x0000_0000 Stack Pointer -15 0x0000_0004 Reset Address -14 0x0000_0008 NMI Handler -13 0x0000_000C Hard Fault Handler -12 0x0000_0010 MPU Fault Handler -11 0x0000_0014 BUS Fault Handler -10 0x0000_0018 Usage Fault Handler -9 0x0000_001C Reserved -8 0x0000_0020 Reserved -7 0x0000_0024 Reserved -6 0x0000_0028 Reserved -5 0x0000_002C SVCall Handler -4 0x0000_0030 Debug Monitor Handle r -3 0x0000_0034 Reserved -2 0x0000_0038 PenSV Handler -1 0x0000_003C SysTick Handler 0 0x0000_0040 LVDDETECT 1 0x0000_0044 SYSCLKFAIL 2 0x0000_0048 XOSCFAIL 3 0x0000_004C WDT 4 0x0000_0050 Reserved 5 0x0000_0054 TIMER0 6 0x0000_0058 TIMER1 7 0x0000_005C TIMER2 8 0x0000_0060 TIMER3 9 0x0000_0064 Reserved 10 0x0000_0068 Reserved 11 0x0000_006C Reserved 12 0x0000_0070 Reserved 13 0x0000_0074 TIMER8 14 0x0000_0078 TIMER9 15 0x0000_007C Reserved 16 0x0000_0080 GPIOAE 17 0x0000_0084 GPIOAO 18 0x0000_0088 GPIOBE PRELIMINARY 14 Z32F0641 Product Specification PS034404-0417 19 0x0000_008C GPIOBO 20 0x0000_0090 GPIOCE 21 0x0000_0094 GPIOCO 22 0x0000_0098 GPIODE 23 0x0000_009C GPIODO 24 0x0000_00A0 MPWM0 25 0x0000_00A4 MPWM0PROT 26 0x0000_00A8 MPWM0OVV 27 0x0000_00AC Reserved 28 0x0000_00B0 Reserved 29 0x0000_00B4 Reserved 30 0x0000_00B8 Reserved 31 0x0000_00BC Reserved 32 0x0000_00C0 SPI0 33 0x0000_00C4 Reserved 34 0x0000_00C8 Reserved 35 0x0000_00CC Reserved 36 0x0000_00D0 I2C0 37 0x0000_00D4 Reserved 38 0x0000_00D8 UART0 39 0x0000_00DC UART1 40 0x0000_00E0 Reserved 41 0x0000_00E4 Reserved 42 0x0000_00E8 Reserved 43 0x0000_00EC ADC0 44 0x0000_00F0 ADC1 45 0x0000_00F4 Reserved 46 0x0000_00F8 Reserved 47 0x0000_00FC Reserved 48 0x0000_0100 Reserved 49 0x0000_0104 Reserved 50 0x0000_0108 Reserved 51 0x0000_010C Reserved 52 0x0000_0110 Reserved 53 0x0000_0114 Reserved 54 0x0000_0118 Reserved 55 0x0000_011C Reserved 56 0x0000_0120 Reserved 57 0x0000_0124 Reserved 58 0x0000_0128 Reserved 59 0x0000_012C Reserved 60 0x0000_0130 Reserved 61 0x0000_0134 Reserved 62 0x0000_0138 Reserved 63 0x0000_013C Reserved PRELIMINARY CPU 15 Z32F0641 Product Specification 3. Boot Mode Boot Mode Boot Mode Pins The Z32F0641 MCU includes a Boot Mode option to program internal Flash memory.To enter Boot Mode, set the BOOT pin to Low at reset timing. Note: The Normal state of the BOOT pin is High. Boot Mode supports UART boot and SPI boot.UART boot uses the UART0 port, and SPI boot uses SPI0.The pins used for Boot Mode are listed in Table 3.1. Table 3.1 Boot Mode Pins Block SYSTEM UART0 SPI0 PS034404-0417 Pin Name Dir Description nRESET/PC10 I Reset Input signal BOOT/PC11 I ‘0’ to enter Boot mode RXD0/PC14 I UART Boot Receive Data TXD0/PC15 O UART Boot Transmit Data SS0/PA12 I SPI Boot Slave Select SCK0/PA13 I SPI Boot Clock Input MOSI0/PA14 I SPI Boot Data Input MISO0/PA15 O SPI Boot Data Output PRELIMINARY 16 Z32F0641 Product Specification Boot Mode Boot Mode Connections Design the target board using either of the Boot Mode ports – UART or SPI. Figure 3.1 and Figure 3.2 display sample Boot Mode connections. 3.3 ~ 5V 10kΩ TARGET_RESET VDD nRESET BOOT_SW BOOT Z32F0641 HOST_TXD HOST_RXD RXD0 GND TXD0 Figure 3.1 UART Boot Connection Diagram 3.3 ~ 5V 10kΩ VDD nRESET TARGET_RESET BOOT_SW BOOT HOST_SS Z32F0641 SS0 HOST_SCK HOST_SDOUT SCK0 HOST_SDIN MOSI0 GND MISO0 Figure 3.2 SPI Boot Connection Diagram PS034404-0417 PRELIMINARY 17 Z32F0641 Product Specification 4. System Control Unit System Control Unit Overview The Z32F0641 microcontroller has an in-built intelligent power control block which manages the system analog blocks and operating modes. Internal reset and clock signals are controlled by the SCU block to maintain optimal system performance and power dissipation. APB BUS SCU MODE CONTROL SCU SCU CLOCK GEN HCLK PCLK RESET INTERRUPT SLEEP WAKE UP INTERRUPT VDC/LVD/PLL IntOSC CONTROL Wakeup Source Figure 4.1 SCU Block Diagram Clock System The Z32F0641 MCU has the following two main operating clocks: HCLK – Clock for the CPU and AHB bus system PCLK – Clock for peripheral systems Figure 4.2 and Figure 4.3 show the chip’s clock system. Table 4.1 lists the clock source descriptions. PS034404-0417 PRELIMINARY 18 Z32F0641 Product Specification System Control Unit Figure 4.2 Clock Source Configuration HCLK_FREE(4/8MHz) Figure 4.3 System Clock Configuration Each of the multiplexers for switching the clock source contains a circuit which allows glitch-free switching between clock modes. Table 4.1 Clock Sources Clock name Frequency Description MainOSC XTAL(4MHz~8MHz) External Crystal IOSC PLL Clock 8MHz ~ 80MHz On Chip PLL ROSC 1MHz Internal RING OSC The PLL can synthesize the PLLCLK clock up to 80 MHz with the FIN reference clock. It also has an internal pre-divider and post-divider. PS034404-0417 PRELIMINARY 19 Z32F0641 Product Specification System Control Unit HCLK Clock Domain The HCLK clock feeds the clock to the CPU and AHB bus. The Cortex-M3 CPU requires two clocks related with the HCLK clock: FCLK – FCLK is a free-running clock which runs continuously except during Power-Down Mode HCLK – HCLK can be stopped during Idle Mode Miscellaneous Clock Domain for Cortex-M3 RingOSC 0XX MCLK 100 XTAL 110 RingOSC 0XX MCLK 100 XTAL 110 RingOSC 0XX MCLK 100 XTAL 110 RingOSC 0XX MCLK 100 XTAL 110 RingOSC 0XX MCLK 100 XTAL 110 1/N SysTick CLK SYSTICKDIV (MCCR1) 1/N WDT CLK WDTDIV (MCCR3) WDTCSEL 1/N TIMER CLK TIMERDIV (MCCR3) TIMERCSEL 1/N MPWM0 C LK MPWM0DIV (MCCR2) MPWMCSEL 1/N RingOSC 0XX MCLK 100 XTAL 110 RingOSC 0XX MCLK 100 XTAL 110 RingOSC 0XX MCLK 100 XTAL 110 RingOSC 0XX MCLK 100 XTAL 110 1/N PA_DEBOUNCE PADDIV (MCCR4) PADCSEL 1/N PB_DEBOUNCE PBDDIV (MCCR4) PBDCSEL 1/N PC_DEBOUNCE PCDDIV (MCCR5) PCDCSEL 1/N PD_DEBOUNCE PDDDIV (MCCR5) PDDCSEL ADC_CLK ADCDIV (MCCR7) ADCCSEL Figure 4.4 Miscellaneous Clock Configuration PS034404-0417 PRELIMINARY 20 Z32F0641 Product Specification System Control Unit PCLK Clock Domain PCLK is the master clock of all the peripherals. It can be stopped in Power-Down Mode. Each peripheral clock is generated by the PCER register set. Clock Configuration After power up, the default system clock is fed by the RINGOSC (1 MHz) clock. RINGOSC is enabled by default at power up. The other clock sources are enabled by user controls with the RINGOSC system clock. The MOSC clock can be enabled by the CSCR register. Before enabling the MOSC block, the pin mux configuration should be set for XIN, XOUT function. PC12 and PC13 pins are shared with MOSC’s XIN and XOUT function - PCCMR and PCCCR registers should be correctly configured. After enabling the MOSC block, you must wait for more than 1 msec to ensure stable operation of crystal oscillation. The PLL clock can be enabled by the PLLCON register. After enabling the PLL block, you must wait for the PLL lock flag. When the PLL output clock is stable; you can select MCLK for your system requirement. Before changing the system clock, Flash access wait should be set to the maximum value. After the system clock is changed, you will need to set the desired Flash access wait time. An example flow chart outlining the steps to configure the system clock is shown in Figure 4.5. Power up MCLK == RING OSC (default set) Set PLL CON Set Flash wait control in FM.CFG.WAIT == Maximum wait N Check PLL LOCK bit in PLLCON Set MOSC PCCMR[27:24]←XIN,XOUT PCCCR[27:24]←analog CSCR.EOSCCON[1] = 1 Y Change MCLK from MOSC to PLL in SCCR (MCLK == PLL) N check EOSCSTS bit in CMR Set flash wait control in FM.CFG.WAIT Y Wait 5msec for MOSC crystal oscillation stabilizing END Change MCLK from RINGOSC to MOSC in SCCR (MCLK == MOSC) Figure 4.5. Clock Configuration Flow Chart When you speed up the system clock up to maximum operating frequency, you should check the Flash wait control configuration. Flash read access time is one of the limiting factors in performance. The wait control recommendation is provided in Table 4.2. PS034404-0417 PRELIMINARY 21 Z32F0641 Product Specification System Control Unit Table 4.2. Flash Wait Control Recommendation FM.CFG.WAIT FLASH Access Wait Available Max System Clock Frequency 000 0 clock wait ~16MHz 001 1 clock wait ~32MHz 010 2 clock wait ~48MHz 011 3 clock wait ~48MHz Reset The Z32F0641 MCU has two system resets:  Cold reset by POR, which is effective during power up or down sequence, and  Warm reset, which is generated by several reset sources. The reset event causes the chip to return to initial state. The cold reset has only one reset source, POR. The warm reset has the following reset sources:        nRESET pin WDT reset LVD reset MCLK Fail reset MOSC Fail reset S/W reset CPU request reset Cold Reset Cold reset is an important feature of the chip when power is up. This characteristic globally affects the system boot. Internal VDC is enabled when VDD power is turned on. The internal VDD level slope is followed by the external VDD power slope. The internal PoR trigger level is 1.4 V of internal VDC voltage out level. At this time, boot operation is started. The RINGOSC clock is enabled and counts to 4 msec for internal VDC level stabilizing. During this time, the external VDD voltage level should be greater than the initial LVD level (2.3 V). After counting 4 msec, the CPU reset is released and the operation is started. Figure 4.6 shows the power up sequence and internal reset waveform. PS034404-0417 PRELIMINARY 22 Z32F0641 Product Specification System Control Unit Figure 4.6. Power-up POR Sequence The RSSR register shows the POR reset status. The last reset comes from POR; RSSR.PORST is set to “1”. After power up, this bit is always “1”. If an abnormal internal voltage drop occurs during normal operation, the system will be reset and this bit is also set to “1”. When cold reset is applied, the chip returns to its initial state. Warm Reset The warm reset event has several reset sources. Some parts of the chip return to initial state when a warm reset condition occurs. The warm reset source is controlled by the RSER register and the status appears in the RSSR register. The reset for each peripheral block is controlled by the PRER register. The reset can be masked independently. PS034404-0417 PRELIMINARY 23 Z32F0641 Product Specification System Control Unit Figure 4.7. Reset Configuration PS034404-0417 PRELIMINARY 24 Z32F0641 Product Specification System Control Unit Operation Mode The INIT mode is the initial state of the chip when reset is asserted. The RUN mode is for maximum performance of the CPU with a high-speed clock system. The SLEEP mode can be used as the low- power consumption mode. Low-power consumption is achieved by halting the processor core and unused peripherals. Figure 4.8 shows the operating mode transition diagram. Power-on Reset INIT Reset Event Reset Event MCU Initialization Wake-up Event SLEEP RUN WFI SLEEPDEEP=0 Figure 4.8. Operating Mode RUN Mode In RUN mode, the CPU core and the peripheral hardware is operated by using the high-speed clock. After reset, followed by the INIT state, the chip enters RUN mode. SLEEP Mode In SLEEP mode, only the CPU is stopped. Each peripheral function can be enabled by the function enable and clock enable bit in the PER and PCER register. PS034404-0417 PRELIMINARY 25 Z32F0641 Product Specification System Control Unit Pin Description Table 4.3 SCU and PLL Pins Pin Name Type Description nRESET I External Reset Input XIN/XOUT OSC External Crystal Oscillator STBYO O Stand-by Output Signal CLKO O Clock Output Monitoring Signal Registers The base address of the system control unit is 0x4000_0000 and the register map is described in Table 4.4. Table 4.4 SCU Register Map Name Offset Type Description Reset Value CIDR 0x0000 R CHIP ID Register AC33_4064 SMR 0x0004 RW System Mode Register 0000_0000 SRCR 0x0008 RW System Reset Control Register 0000_0000 WUER 0x0010 RW Wake up source enable register 0000_0000 WUSR 0x0014 RW Wake up source status register 0000_0000 RSER 0x0018 RW Reset source enable register 0000_0049 RSSR 0x001C RW Reset source status register 0000_0080* PRER1 0x0020 RW Peripheral reset enable register 1 030F_0F3F* PRER2 0x0024 RW Peripheral reset enable register 2 0031_0311* PER1 0x0028 RW Peripheral enable register 1 0000_000F* PER2 0x002C RW Peripheral enable register 2 0000_0101* PCER1 0x0030 RW Peripheral clock enable register 1 0000_000F* PCER2 0x0034 RW Peripheral clock enable register 2 0000_0101* CSCR 0x0040 RW Clock Source Control register 0000_0020 SCCR 0x0044 RW System Clock Control register 0000_0000 CMR 0x0048 RW Clock Monitoring register 0000_0090 NMIR 0x004C RW NMI control register 0000_0000 COR 0x0050 RW Clock Output Control register 0000_000F PLLCON 0x0060 RW PLL Control register 0000_0000 VDCCON 0x0064 RW VDC Control register 0000_000F LVDCON 0x0068 RW LVD Control register 0000_0001 EOSCR 0x0080 RW External Oscillator control register 0000_0300 EMODR 0x0084 RW External mode pin read register 0000_000X DBCLK1 0x009C RW Debounce Clock Control register 1 0001_0001 DBCLK2 0x00A0 RW Debounce Clock Control register 2 0001_0001 MCCR1 0x0090 RW Misc Clock Control register 1 0000_0000 MCCR2 0x0094 RW Misc Clock Control register 2 0000_0000 MCCR3 0x0098 RW Misc Clock Control register 3 0000_0001 MCCR4 0x00A8 RW Misc Clock Control register 4 0001_0000 PS034404-0417 PRELIMINARY 26 Z32F0641 Product Specification System Control Unit CIDR Chip ID Register The CHIP ID Register shows chip identification information. This register is a 32-bit read-only register. CIDR=0x4000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHIPID 0xAC33_4064 RO 31 0 CHIPID Device ID 0xAC33_4064 CIDR=0x4000_000C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHIPID2 0x0000_0000 RO 31 0 CHIPID2 Revision ID 0x0000_0000 SMR System Mode Register The current operating mode is shown in this SCU mode register.The operating mode can be changed by writing a new mode in this register. The previous operating mode will be saved in this register after a reset event. The System Mode Register is a 16-bit register. SMR=0x4000_0004 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 0 PREVMODE 15 00 R 5 4 PS034404-0417 PREVMODE Previous operating mode before current reset event. 00 Previous operating mode was RUN mode 01 Previous operating mode was SLEEP mode 10 Previous operating mode was PowerDown mode 11 Previous operating mode was INIT mode PRELIMINARY 27 Z32F0641 Product Specification System Control Unit SRCR System Reset Control Register The System Reset Control Register allows the software to initate a reset. This register also provides the polarity for the STBYOP pin. SCR=0x4000_0008 7 6 5 4 3 2 1 0 SWRST 0 0 0 0 0 0 0 0 W 1 PS034404-0417 SWRST Internal soft reset activation bit 0 Normal operation 1 Internal soft reset is applied and auto cleared PRELIMINARY 28 Z32F0641 Product Specification WUER System Control Unit Wakeup Source Enable Register Enable the wakeup source when the chip is in Power-Down Mode. The source of chip wakeup should be enabled in each bit field for wakeup sources that will be used. If the source is used as a wakeup source, the corresponding bit should be written as 1. If the source is not used as a wakeup source, the bit should be written as 0. The Wakeup Source Enable Register is a 16-bit register. WUER=-0x4000_0010 0 0 PS034404-0417 9 8 0 0 0 0 RW RW RW RW 11 GPIODWUE 10 GPIOCWUE 9 GPIOBWUE 8 GPIOAWUE 1 WDTWUE 0 LVDWUE 7 6 5 4 3 2 0 0 0 0 0 0 Enable wakeup source of GPIOD port pin event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of GPIOC port pin event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of GPIOB port pin 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of GPIOA port pin 1 0 LVDWUE 0 10 WDTWUE 0 11 GPIOAWUE 12 GPIOBWUE 13 GPIOCWUE 14 GPIODWUE 15 0 0 RW RW change change change event change event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of watchdog timer event 0 Not used for wakeup source 1 Enable the wakeup event generation Enable wakeup source of LVD event 0 Not used for wakeup source 1 Enable the wakeup event generation PRELIMINARY 29 Z32F0641 Product Specification WUSR System Control Unit Wakeup Source Status Register When the system is woken up by any wakeup source, the wakeup source is identified by reading the Wakeup Source Status Register. When the bit is set to 1, the related wakeup source issues the wake-up signal to the SCU. The bit is cleared when the event source is cleared by the software. These bits show the interrupt flag in each peripheral. Examples: A GPIO wakeup status is cleared by clearing the interrupt flag in the PCn.ISR register of the PCU block. A WDTWU interrupt is cleared by clearing the overflow interrupt flag in the WDT block. The LVD flag is cleared when the low voltage condition is resolved. WUSR=0x4000_0014 0 0 9 8 0 0 0 0 R R R R 11 GPIODWU 10 GPIOCWU 9 GPIOBWU 8 GPIOAWU 1 WDTWU 0 LVDWU 6 5 4 3 2 0 0 0 0 0 0 1 0 0 0 R R Status of wakeup source of GPIOD port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of GPIOC port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of GPIOB port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of GPIOA port pin change event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of watchdog timer event 0 No wakeup event 1 Wakeup event was generated Status of wakeup source of LVD event 0 No wakeup event 1 PS034404-0417 7 LVDWU 0 10 WDTWU 0 11 GPIOAWU 12 GPIOBWU 13 GPIOCWU 14 GPIODWU 15 Wakeup event was generated PRELIMINARY 30 Z32F0641 Product Specification System Control Unit RSER Reset Source Enable Register The reset source to the CPU is selected by the Reset Source Enable Register. When 1 is written in the bit field of each reset source, the reset source event is transferred to the reset generator. When 0 is written in the bit field of each reset source, the reset source event is masked and does not generate a reset event. RSER=0x4000_0018 7 0 6 5 4 3 2 1 0 PINRST CORERST SWRST WDTRST MCKFRST XFRST LVDRST 1 0 0 1 0 0 1 RW RW RW RW RW RW RW 6 5 4 PS034404-0417 PINRST CPURST SWRST 3 WDTRST 2 MCKFRST 1 XFRST 0 LVDRST External pin reset enable bit 0 Reset from this event is 1 Reset from this event is CPU request reset enable bit 0 Reset from this event is 1 Reset from this event is Software reset enable bit 0 Reset from this event is 1 Reset from this event is Watchdog Timer reset enable 0 Reset from this event is 1 Reset from this event is MCLK Clock fail reset enable 0 Reset from this event is 1 Reset from this event is External OSC Clock fail reset 0 Reset from this event is 1 Reset from this event is LVD reset enable bit 0 Reset from this event is 1 Reset from this event is PRELIMINARY masked enabled masked enabled masked enabled bit masked enabled bit masked enabled enable bit masked enabled masked enabled 31 Z32F0641 Product Specification System Control Unit RSSR Reset Source Status Register The Reset Source Status Register displays the reset source information when a reset event occurs. 1 indicates that a reset event exists and 0 indicates that a reset event does not exist for a given reset source.When a reset source is found, write 1 to the corresponding bit to clear the reset status. This register is an 8-bit register. RSSR=0x4000_001C 7 6 5 4 3 2 1 0 PORST PINRST CPURST SWRST WDTRST MCKFRST XFRST LVDRST 1 0 0 0 0 0 0 0 RC1 RC1 RC1 RC1 RC1 RC1 RC1 RC1 7 PORST Power on reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 6 PINRST 5 CPURST 4 SWRST 3 WDTRST 2 MCLKFRST 1 XFRST 0 LVDRST Read :Reset from this event was occurred Write : Clear the status External pin reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status CPU request reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status Software reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status Watchdog Timer reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status MCLK Fail reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status Clock fail reset status bit 0 Read : Reset from this event was not exist Write : no effect 1 Read :Reset from this event was occurred Write : Clear the status LVD reset status bit 0 1 PS034404-0417 Read Write Read Write PRELIMINARY : Reset from this event was not exist : no effect :Reset from this event was occurred : Clear the status 32 Z32F0641 Product Specification PRER1 System Control Unit Peripheral Reset Enable Register 1 The reset of each peripheral by Event Reset can be masked by this user setting. The PRER1/PRER2 register controls enablement of the event reset. If the corresponding bit is 1, the peripheral corresponding to this bit accepts the reset event. Otherwise, the peripheral is protected from the reset event and maintains its current operation. PRER1=0x4000_0020 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 PS034404-0417 TIMER9 TIMER8 TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DMA PCU WDT FMC SCU FMC SCU 1 1 1 1 1 RW RW 0 WDT 1 RW RW 2 PCU 1 3 RW 1 4 DMA GPIOA 1 765 RW GPIOB 1 RW 0 0 0 0 GPIOC 1 RW 1 GPIOD 1 RW TIMER0 1 RW 0 0 0 0 TIMER1 1 RW 1 TIMER2 8 RW 9 TIMER3 10 RW 16 15 14 13 12 11 TIMER8 17 RW 18 TIMER9 0 0 0 0 0 0 24 23 22 21 20 19 RW 31 30 29 28 27 26 25 00 0 TIMER9 reset mask TIMER8 reset mask TIMER3 reset mask TIMER2 reset mask TIMER1 reset mask TIMER0 reset mask GPIOE reset mask GPIOE reset mask GPIOE reset mask GPIOA reset mask DMA reset mask Port Control Unit reset mask Watchdog Timer reset mask Flash memory controller reset mask System Control Unit reset mask PRELIMINARY 33 Z32F0641 Product Specification PRER2 System Control Unit Peripheral Reset Enable Register 2 The reset of each peripheral by Event Reset can be masked by this user setting. The PRER1/PRER2 register controls enablement of the event reset. If the corresponding bit is 1, the peripheral corresponding to this bit accepts the reset event. Otherwise, the peripheral is protected from the reset event and maintains its current operation. PRER2=0x4000_0024 21 20 16 9 8 4 0 PS034404-0417 0 ADC1 ADC0 MPWM0 UART1 UART0 I2C0 SPI0 0 0 1 0 0 0 0 0 0 1 0 0 0 4 3 2 1 1 0 0 0 0 SPI0 1 5 I2C0 1 MWPM0 1 6 1 RW 0 7 RW 0 UART0 0 RW 0 8 UART1 0 9 RW 0 RW 0 ADC0 0 RW 0 ADC1 0 RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADC1 reset enable ADC0 reset enable MPWM0 reset enable UART1 reset enable UART0 reset enable I2C0 reset enable SPI0 reset enable PRELIMINARY 34 Z32F0641 Product Specification System Control Unit PER1 Peripheral Enable Register 1 Prior to using a peripheral unit, it requires to be activated by writing 1 to the corresponding bit in the PER1/PER2 register. Until activation, the peripheral stays in Reset state. To disable the peripheral unit, write 0 to the corresponding bit in the PER0/PER1 register, after which the peripheral enters the Reset state. 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 PS034404-0417 TIMER9 TIMER8 TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DMA 0 0 1 1 1 1 R RW 1 R 0 2 R 0 3 R GPIOA 0 765 4 DMA GPIOB 0 RW 0 0 0 0 GPIOC 0 RW 0 GPIOD 0 RW TIMER0 0 RW 0 0 0 0 TIMER1 0 RW 0 TIMER2 8 RW 9 TIMER3 10 RW 16 15 14 13 12 11 TIMER8 17 RW 18 TIMER9 0 0 0 0 0 0 24 23 22 21 20 19 RW 31 30 29 28 27 26 25 RW PER1=0x4000_0028 000 TIMER9 function enable TIMER8 function enable TIMER3 function enable TIMER2 function enable TIMER1 function enable TIMER0 function enable GPIOD function enable GPIOC function enable GPIOB function enable GPIOA function enable DMA function enable Reserved PRELIMINARY 35 Z32F0641 Product Specification System Control Unit PER2 Peripheral Enable Register 2 Prior to using a peripheral unit, it requires to be activated by writing 1 to the corresponding bit in the PER1/PER2 register. Until activation, the peripheral stays in Reset state. To disable the peripheral unit, write 0 to the corresponding bit in the PER0/PER1 register, after which the peripheral enters the Reset state. PER2=0x4000_002C 21 20 16 9 8 4 0 PS034404-0417 0 ADC1 ADC0 MPWM0 UART1 UART0 I2C0 SPI0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 3 2 1 0 0 0 0 0 SPI0 0 5 I2C0 0 MWPM0 0 6 1 RW 0 7 RW 0 UART0 0 RW 0 8 UART1 0 9 RW 0 RW 0 ADC0 0 RW 0 ADC1 0 RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADC1 function enable ADC0 function enable MPWM0 function enable UART1 function enable UART0 function enable I2C0 function enable SPI0 function enable PRELIMINARY 36 Z32F0641 Product Specification PCER1 System Control Unit Peripheral Clock Enable Register 1 Prior to using a peripheral unit, its clock should be activated by writing 1 to the corresponding bit in the PCER1/PCER2 register. The peripheral will not operate correctly until its clock is enabled. To stop the clock of the peripheral unit, write 0 to the corresponding bit in the PCER1/PCER2 register. 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 PS034404-0417 TIMER9 TIMER8 TIMER3 TIMER2 TIMER1 TIMER0 GPIOD GPIOC GPIOB GPIOA DMA 0 0 1 1 1 1 R RW 1 R 0 2 R 0 3 R GPIOA 0 765 4 DMA GPIOB 0 RW 0 0 0 0 GPIOC 0 RW 0 GPIOD 0 RW TIMER0 0 RW 0 0 0 0 TIMER1 0 RW 0 TIMER2 8 RW 9 TIMER3 10 RW 16 15 14 13 12 11 TIMER8 17 RW 18 TIMER9 0 0 0 0 0 0 24 23 22 21 20 19 RW 31 30 29 28 27 26 25 RW PCER1=0x4000_0030 000 TIMER9 clock enable TIMER8 clock enable TIMER3 clock enable TIMER2 clock enable TIMER1 clock enable TIMER0 clock enable GPIOD clock enable GPIOC clock enable GPIOB clock enable GPIOA clock enable DMA clock enable Reserved PRELIMINARY 37 Z32F0641 Product Specification PCER2 System Control Unit Peripheral Clock Enable Register 2 Prior to using a peripheral unit, its clock should be activated by writing 1 to the corresponding bit in the PCER1/PCER2 register. The peripheral will not operate correctly until its clock is enabled. To stop the clock of the peripheral unit, write 0 to the corresponding bit in the PCER1/PCER2 register. PCER2=0x4000_0034 21 20 16 9 8 4 0 PS034404-0417 0 ADC1 ADC0 MPWM0 UART1 UART0 I2C0 SPI0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 3 2 1 0 0 0 0 0 SPI0 0 5 I2C0 0 MWPM0 0 6 1 RW 0 7 RW 0 UART0 0 RW 0 8 UART1 0 9 RW 0 RW 0 ADC0 0 RW 0 ADC1 0 RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADC1 clock enable ADC0 clock enable MPWM0clock enable UART1 clock enable UART0 clock enable I2C0 clock enable SPI0 clock enable PRELIMINARY 38 Z32F0641 Product Specification CSCR System Control Unit Clock Source Control Register The Z32F0641 MCU has multiple clock sources to generate internal operating clocks. Each clock source can be controlled by the Clock Source Control Register. This register is an 8-bit register. CSCR=0x4000_0040 7 6 5 4 3 2 1 0 - RINGOSCCON - EOSCCON 00 10 00 00 R RW R RW PS034404-0417 5 4 RINGOSCCON 1 0 EOSCCON Internal ring oscillator control 0 Stop internal sub oscillator X 10 Enable internal sub oscillator 11 Enable internal sub oscillator divide by 2 External crystal oscillator control 0 Stop External Ctystal oscillator X 10 Enable External Ctystal oscillator 11 Enable External Ctystal divide by 2 PRELIMINARY 39 Z32F0641 Product Specification SCCR System Control Unit System Clock Control Register The Z32F0641 MCU has multiple clock sources to generate internal operating clocks. Each clock source can be controlled by the System Clock Control Register. The MOSC MUST be running and stable before setting the FINSEL bit. SCCR=0x4000_0044 7 6 5 4 3 2 1 0 - FINSEL MCLKSEL 0000 0 00 R RW RW 2 FINSEL 1 0 MCLKSEL PLL input source FIN select register 0 IOSC clock is used as FIN clock 1 MOSC clock is used as FIN clock System clock select register 0 Internal sub oscillator X 10 PLL bypassed clock 11 PLL output clock Note: When changing FINSEL, both internal OSC and external OSC should be alive to prevent the chip from mal functioning. PS034404-0417 PRELIMINARY 40 Z32F0641 Product Specification System Control Unit CMR Clock Monitoring Register To monitor the internal clock and external oscillator, the MCLKMNT/EOSCMNT bits must be set before the MCLK and EOSC bits are valid. The Clock Monitoring Register is a 16-bit register. Note: The EOSC bit only checks for the EOSC oscillation, not its stability. When the system detects an MCLKFAIL interrupt, the MCLKREC bit determines if the system dies or will auto-recover using the ROSC. The system usually auto-recovers so that it can continue running. CMR=0x4000_0048 0 0 0 0 0 0 0 R 15 MCLKREC 7 MCLKMNT 6 MCLKIE 5 MCLKFAIL 4 MCLKSTS 3 EOSCMNT 2 EOSCIE 1 EOSCFAIL 0 EOSCSTS 6 5 4 3 2 1 0 EOSCSTS 0 7 EOSCFAIL 8 EOSCIE 9 EOSCMNT 10 MCLKSTS 11 MCLKFAIL 12 MCLKIE 13 MCLKMNT 14 MCLKREC 15 1 0 0 1 0 0 0 0 RW RW RC1 RC1 RW RW RC1 RC1 MCLK fail auto recovery 0 MCLK is changed to RINGOSC by default when MCLKFAIL issued 1 MCLK auto recovery is disabled MCLK monitoring enable 0 MCLK monitoring disabled 1 MCLK monitoring enabled MCLK fail interrupt enable 0 MCLK fail interrupt disabled 1 MCLK fail interrupt enabled MCLK fail interrupt 0 MCLK fail interrupt not occurred 1 Read : MCLK fail interrupt is pending Write : Clear pending interrupt MCLK clock status 0 No clock is present on MCLK 1 Clock is present on MCLK External oscillator monitoring enable 0 External oscillator monitoring disabled 1 External oscillator monitoring enabled External oscillator fail interrupt enable 0 External oscillator fail interrupt disabled 1 External oscillator fail interrupt enabled External oscillator fail interrupt 0 External oscillator fail interrupt not occurred 1 Read : External oscillator fail interrupt is pending Write : Clear pending interrupt External oscillator status 0 Not oscillate 1 External oscillator is working normally The clock monitoring function cannot cover all malfunction cases and is only used for reference. Figure 4.9 shows the operational diagram for clock monitoring function. PS034404-0417 PRELIMINARY 41 Z32F0641 Product Specification System Control Unit Figure 4.9. Clock Monitoring Function Diagram PS034404-0417 PRELIMINARY 42 Z32F0641 Product Specification NMIR System Control Unit Non-Maskable Interrupt Control Register The Non-Maskable Interrupt Control Register can be set with software. There are five kinds of interrupt sources from MPWM, WDT, and SCU. Write access key 0xA32C to NMR[31:16] is required before writing to this register. NMIR=0x4000_004C 31 16 12 11 10 9 8 PS034404-0417 ACCESSCODE PROTSTS OVPSTS WDTSTS MCLKFAILSTS LVDSTS 4 PROTEN 3 OVPEN 2 WDTEN 1 MCLKFAILEN 0 LVDEN 0 R R R R R 00 0 1 0 LVDEN 0 2 MCLKFAILEN 0 3 WDTEN 0 4 OVPEN 0 765 PROTEN 8 LVDSTS WO 9 MCLKFAILSTS 0 0 0 10 WDTSTS - 11 OVPSTS ACCESSCODE 12 PROTSTS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 0 0 0 0 1 RW RW RW RW RW This field enables writing access to this register. Writing 0xA32C is to enable writing. Protection condition status bit. This bit can’t invoke nmi interrupt without enable 0 Not occurred 1 Event occurred Over Voltage Protection condition status bit This bit can’t invoke nmi interrupt without enable 0 Not occurred 1 Event occurred WDT Interrrupt condition status bit This bit can’t invoke nmi interrupt without enable 0 Not occurred 1 Event occurred MCLK Fail condition status bit This bit can’t invoke nmi interrupt without enable 0 Not occurred 1 Event occurred LVD condition status bit This bit can’t invoke nmi interrupt without enable 0 Not occurred 1 Event occurred Protection condition enable for NMI interrupt 0 Disable 1 Enable Over Voltage Protection condition enable for NMI pt 0 Disable 1 Enable WDT Interrrupt condition enable for NMI interrupt 0 Disable 1 Enable MCLK Fail condition enable for NMI interrupt 0 Disable 1 Enable LVD Fail condition enable for NMI interrupt 0 Disable 1 Enable PRELIMINARY bit bit bit bit bit interru 43 Z32F0641 Product Specification COR System Control Unit Clock Output Register The Z32F0641 MCU can drive the clock from internal MCLK clock with a dedicated post divider. The Clock Output Register is an 8-bit register. COR=0x4000_0050 7 6 5 4 3 2 CLKOEN CLKODIV 000 0 1111 R RW RW 4 CLKOEN 3 0 CLKODIV 0 Clock output enable 0 CLKO is disabled and stay “L” output 1 CLKO Is enabled Clock output divider value CLKO = MCLK 𝐂𝐋𝐊𝐎 = PS034404-0417 1 - PRELIMINARY (CLKODIV = 0) 𝑴𝑪𝑳𝑲 (𝐂𝐋𝐊𝐎𝐃𝐈𝐕 𝟐∗ + 𝟏) (𝑪𝑳𝑲𝑶𝑫𝑰𝑽 > 𝟎) 44 Z32F0641 Product Specification PLLCON System Control Unit PLL Control Register Integrated PLL can synthesize the high speed clock for extremely high performance of the CPU from either the internal oscillator (IOSC) or the external oscillator (MOSC). The PLL Control register provides the configuration for the PLL system. By default, the PLL system is in reset mode and disabled. You must negate the reset and enable the PLL to operate (bits 14 and 15 must be set). The Bypass bit must be set to output the PLL clock. The active clock is defined in SCCR bit 2 (FIN). To calculate the PLL output: PLL Out = ((Active clock / PREDIV) * FBCTRL) / POSTDIV For example: Using MOSC (assuming it is running at 8 MHz and selected): PREDIV set to 1 (FIN / 2) FBCTRL set to 0x04 (M=12) POSTDIV set to 0x00 (N=1) ((8 MHz / 2) * 12) = 48 MHz PLLCON=0x4000_0060 0 0 RW RW RW R 9 0 0 0 15 PLLRSTB 14 PLLEN 13 BYPASS 12 LOCK 8 PREDIV 7 4 FBCTRL 3 0 PS034404-0417 POSTDIV 8 7 6 5 4 3 2 1 POSTDIV 0 10 FBCTRL 0 11 PREDIV LOCKSTS 12 BYPASS 13 PLLEN 14 PLLRSTB 15 0 0000 0000 RW RW RW PLL reset 0 PLL reset is asserted 1 PLL reset is negated PLL enable 0 PLL is disabled 1 PLL is enabled FIN bypass 0 FOUT is bypassed as FIN 1 FOUT is PLL output LOCK status 0 PLL is not locked 1 PLL is locked FIN predivider 0 FIN divided by 1 1 FIN divided by 2 Feedback control 0000 M = 4 1000 0001 M = 6 1001 0010 M = 8 1010 0011 M = 10 1011 0100 M = 12 1100 0101 M = 14 1101 0110 M = 16 1110 0111 M = 18 1111 Post divider control 000 N = 1 001 N = 2 010 N = 3 PRELIMINARY M M M M = = = = 0 20 24 26 34 Not available 45 Z32F0641 Product Specification 011 100 101 110 111 VDCCON N N N N N System Control Unit = 4 = 6 = 8 = 3 =16 VDC Control Register The on chip VDC control register, VDCTRIM, is used for the trim value of VDC output. To modify the VDCTRIM bit, 1 should be written to VDCTE simultaneously. The VDCWDLY value can be written by writing 1 to the VDCDE bit simultaneously. VDCCON=0x4000_0064 0 W PS034404-0417 0 0 RW W VDCTRIM 00 0 0 0 0000 0 0 0 RW 23 VDCTE 19 16 8 VDCTRIM 7 0 VDCWDLY VDCDE 0 0 0 0 8 7 6 5 4 3 VDCWDLY 0 22 21 20 19 18 17 16 15 14 13 12 11 10 9 VDCDE 0 VDCTE 0 23 RESERVED 30 29 28 27 26 25 24 RESERVE 31 0 0x7F W RW 2 1 0 VDCTRIM value write enable. Write only with VDCTRIM value. 0 VDCTRIM field is not updated by writing 1 VDCTRIM filed can be updated by writing VDC output voltage trim value VDCWDLY value write enable. Write only with VDCWD LY value 0 FOUT is PLL output 1 FOUT is bypassed as FIN VDC warm-up delay count value. When SCU is waked up from powerdown mode, the w arm-up delay is inserted for VDC output being stabilize d. The amount of delay can be defined with this register value 7F : 2msec PRELIMINARY 46 Z32F0641 Product Specification LVDCON System Control Unit LVD Control Register The LVD Control Register is an on chip brown-out detector control register. This register is a 32-bit register. LVDCON=0x4000_0068 0 0 0 0 PS034404-0417 0 0 23 LVDTE 17 16 15 LVDTRIM 9 8 LVDSEL 1 LVDLVL 0 LVDEN SELEN 4 3 2 0 0 0 0 0 0 LVDSEL 00 5 0 0 0 0 0 00 1 0 LVDEN 0 6 0 1 RW 0 7 LVDLVL 0 8 RO 0 9 RW 0 SELEN 0 RO 0 RW 0 RW 0 LVDTRIM LVDTE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LVDTRIM value write enable. Write only with LVDTRIM value. 0 LVDTRIM field is not updated by writing 1 LVDTRIM filed can be updated by writing LVD voltage level trim value It can writable when trim enable mode in FMC LVD level SEL value write enable. Write only. 0 SEL field is not updated by writing 1 SEL filed can be updated by writing LVD detect level select 00 LVD detect level is 1.8V- 50mV 01 LVD detect level is 2.2V – 50mV 10 LVD detect level is 2.7V -50mV 11 LVD detect level is 4.3V – 50mV LVD Status 0 VDDEXT level is over than LVD level 1 VDDEXT level is under than LVD level LVD Function enable 0 LVD is not enabled 1 LVD is enabled PRELIMINARY 47 Z32F0641 Product Specification EOSCR System Control Unit External Oscillator Control Register The external main crystal oscillator has two characteristics. For noise immunity, the NMOS amp type is recommended and for low power, the INV amp type is recommended. This register is a 16-bit register. EOSCR=0x4000_0080 14 13 12 11 10 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ISEL ISELEN 15 0 W 11 RW EMODR 15 ISELEN 9 8 ISEL Write enable of bit field ISEL. 0 Write access of ISEL field is masked 1 Write access of ISEL field is accepted Select current. 00 Minimum current driving option 01 Low current driving option 10 High current driving option 11 Maximum current driving option External Mode Status Register External Mode Status Register shows the external mode pin status while booting. This register is an 8-bit register. EMODR=0x4000_0084 7 6 5 4 3 2 1 0 BOOT 0 PS034404-0417 0x0 0 0 - R R R R BOOT BOOT pin level 0 BOOT(PC11) pin is low 1 BOOT(PC11) pin is high PRELIMINARY 48 Z32F0641 Product Specification DBCLK1 System Control Unit Debounce Clock Control Register 1 The Debounce Clock Control register 1 controls the debounce timing configuration for Port A and Port B. DBCLK1=0x4000_009C 0 PS034404-0417 0 000 0x01 RW RW 26 24 PBDCSEL 23 16 10 8 PBDDIV 7 0 PADDIV PADCSEL 0 0 0 0 0 8 7 6 5 4 3 PADDIV 0 9 PADCSEL 0 PBDDIV 0 PBDCSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 Debounce Clock for Port B source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 Reserved 110 External Main OSC (XTAL) 111 Reserved PORT B Debounce Clock N divider Debounce Clock for Port A source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 Reserved 110 External Main OSC (XTAL) 111 Reserved PORT A Debounce Clock N divider PRELIMINARY 49 Z32F0641 Product Specification DBCLK2 System Control Unit Debounce Clock Control Register 2 The Debounce Clock Control register 2 controls the debounce timing configuration for Port C and Port D. DBCLK2=0x4000_00A0 0 0 MCCR1 000 0x01 RW RW 0 26 24 PDDCSEL 23 16 10 8 PDDDIV 7 0 PCDDIV 0 0 0 0 8 7 6 5 4 3 PCDDIV 0 9 PCDCSEL 0 PDDDIV 0 PDDCSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 Debounce Clock for PORT D source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 Reserved 110 External Main OSC (XTAL) 111 Reserved PORT D Debounce Clock N divider PCDCSEL Debounce Clock for PORT C source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 Reserved 110 External Main OSC (XTAL) 111 Reserved PORT C Debounce Clock N divider Miscellaneous Clock Control Register 1 The Miscellaneous Clock Control register 1 controls the configuration for the System Tick clocks. MCCR1=0x4000_0090 0 0 0 PS034404-0417 0 0 0 0 0 0 0 0 0 10 8 STCSEL 7 0 STDIV 0 0 0 0 0 0 0 0 8 7 6 5 4 3 SYSTICKDIV 0 9 STCSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 SYSTIC Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 Reserved 110 External Main OSC (XTAL) 111 Reserved SYSTIC Clock N divider PRELIMINARY 50 Z32F0641 Product Specification MCCR2 System Control Unit Miscellaneous Clock Control Register 2 The Miscellaneous Clock Control register 2 controls the optional configuration of MPWM0 clocks. MCCR2=0x4000_0094 0 0 0 0 MCCR3 0 0 0 0 0 0 0 0 0 10 8 PWM0CSEL 7 0 PWM0DIV 0 0 0 0 PWM0 0xx 100 101 110 111 PWM0 0 0 0 8 7 6 5 4 3 PWM0DIV 0 9 PWM0CSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x00 RW RW 2 1 0 Clock source select bit RING OSC 1Mhz MCLK (bus clock) Reserved External Main OSC (XTAL) Reserved Clock N divider Miscellaneous Clock Control Register 3 The Miscellaneous Clock Control register 3 controls the configuration for the Timer EXT0 and WDT clocks. MCCR3=0x4000_0098 0 PS034404-0417 0 000 0x01 RW RW 26 24 TEXT0CSEL 23 16 10 8 TEXT0DIV 7 0 WDTDIV WDTCSEL 0 0 0 0 0 8 7 6 5 4 3 WDTDIV 0 9 WDTCSEL 0 TEXT0DIV 0 TEXT0CSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 2 1 0 Timer EXT0 Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 Reserved 110 External Main OSC (XTAL) 111 Reserved Timer EXT0 Clock N divider WDT Clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 Reserved 110 External Main OSC (XTAL) 111 Reserved WDT Clock N divider PRELIMINARY 51 Z32F0641 Product Specification MCCR4 System Control Unit Miscellaneous Clock Control Register 4 The Miscellaneous Clock Control Register 4 controls the clock setting for the ADC peripheral. MCCR7=0x4000_00A8 0 0 0 PS034404-0417 0 ADCCDIV 0 ADCCSEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 000 0x01 RW RW 26 24 ADCCSEL 23 16 ADCCDIV 9 8 7 6 5 4 3 2 1 0 ADC clock source select bit 0xx RING OSC 1Mhz 100 MCLK (bus clock) 101 Reserved 110 External Main OSC (XTAL) 111 Reserved ADC Clock N divider PRELIMINARY 52 Z32F0641 Product Specification Port Control Unit 5. Port Control Unit Overview The Port Control Unit (PCU) controls the external I/O configuration to:      Set the multiplex state of each pin (for alternative functions) Set external signal type (Analog / Push-Pull output /Open Drain output /Input) Set enable/monitor/trigger type for interrupts for each pin Set internal pull-up register control for each pin Set debounce for each pin Note: You must enable both the Port Periphreal and the Port Periphreal CLOCK in PER1/PCER1/ to use the pins of the port. APB BUS Function I/Os NVIC PORT CONTROL FUNCTION MUX PA/PB/PC PD/PE/PF PORTs INTERRUPT CONTROL Figure 5.1 Block Diagram PS034404-0417 PRELIMINARY 53 Z32F0641 Product Specification Port Control Unit VDDIO Pull-up Enable VDDIO VDDIO Open-drain Enable Input Mode Port MUX PIN GPIO output 00 Function 1 Output 01 Function 1 Output 10 Function 3 Output 11 Analog Disable 0 Function Input 1 Debounce Logic Debounce Enable Debounce Count Analog Input (AN0~AN15, XTALI,XTALO, SXIN,SXOUT) Figure 5.2 I/O Port Block Diagram (ADC and External Oscillator pins) VDDIO Pull-up Enable VDDIO VDDIO Open-drain Enable Input Mode Port MUX PIN GPIO output Function 1 Output 00 01 Function 1 Output 10 Function 3 Output 11 Analog Disable 0 Function Input 1 Debounce * Logic Debounce Enable Debounce Count Figure 5.3 I/O Port Block Diagram (General I/O pins) PS034404-0417 PRELIMINARY 54 Z32F0641 Product Specification Port Control Unit Pin Multiplexing GPIO pins have alternative function pins. Table 5.1 Table 5.1 GPIO Alternative functionshows pin multiplexing information. Table 5.1 GPIO Alternative function Port PA PB Pin Function 00 01 10 11 0 PA0* AN0 1 PA1* 2 PA2* 3 PA3* 4 PA4* SS1 5 PA5* SS2 6 PA6* T0IO T2IO AN6 7 PA7* T1IO T3IO AN7 8 PA8* T2IO T0IO AN8 9 PA9* T3IO T1IO AN9 10 PA10* SS3 11 PA11* 12 PA12* T0IO 13 PA13* T1IO 14 PA14* T2IO 15 PA15* T3IO 0 PB0* MP0UH 1 PB1* MP0UL 2 PB2* MP0VH 3 PB3* MP0VL 4 PB4* MP0WH 5 PB5* MP0WL 6 PB6* PRTIN0 T0IO 7 PB7* OVIN0 T1IO AN1 WDTO AN2 AN3 AN4 AN5 AN10 8 9 10 11 12 13 14 15 (*) indicates default pin setting (2) indicates secondary port PS034404-0417 PRELIMINARY 55 Z32F0641 Product Specification Port Control Unit Table 5.2 GPIO Alternative Function Port PC Pin Function 00 01 10 0 PC0 TCK/SWCLK* RXD1 1 PC1 TMS/SWDIO* TXD1 2 PC2 TDO/SWO* T8IO 3 PC3 TDI* T9IO 4 PC4 nTRST* T0IO 5 PC5* RXD1 T1IO 6 PC6* TXD1 T2IO 7 PC7* SCL0 T3IO 8 PC8* SDA0 9 PC9* CLKO 10 PC10 nRESET* 11 PC11/BOOT* 12 PC12* 13 PC13* 14 PC14* RXD0 MOSI0(2) 15 PC15* TXD0 MISO0(2) 0 PD0* SS0 T8IO 1 PD1* SCK0 T9IO 2 PD2* MOSI0 SCL0 3 PD3* MISO0 SDA0 11 T8IO T9IO XIN XOUT 4 5 6 PD 7 8 9 10 11 12 13 14 15 (*) indicates default pin setting. (2) indicates secondary port PS034404-0417 PRELIMINARY 56 Z32F0641 Product Specification Port Control Unit Registers The base address of the PCU block is 0x4000_1000. Table 5.3 Base Address of Port Port Name Address PCA 0x4000_1000 PCB 0x4000_1100 PCC 0x4000_1200 PCD 0x4000_1300 Table 5.4 PCU Register Map Name Offset Type Description PCn.MR 0x--00 RW Port n pin mux select register PCn.CR 0x--04 RW Port n pin control register PCn.PCR 0x--08 RW Port n internal pull-up control register PCn.DER 0x--0C RW Port n debounce control register PCn.IER 0x--10 RW Port n interrupt enable register PCn.ISR 0x--14 RW Port n interrupt status register PCn.ICR 0x--18 RW Port n interrupt control register 0x--1C PORTEN PS034404-0417 0x1FF0 Reserved RW Port Access enable PRELIMINARY 57 Z32F0641 Product Specification PCA.MR Port Control Unit PORT A Pin MUX Register This register is the PA Port Mode select register, and must be set up correctly before using the port to ensure that the port functions as designed. PCA.MR=0x4000_1000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Port PS034404-0417 Selection Bit 00 01 10 11 PA0 PA0* AN0 PA1 PA1* AN1 PA2 PA2* PA3 PA3* PA4 PA4* SS1 AN4 PA5 PA5* SS2 AN5 PA6 PA6* T0IO T2IO AN6 PA7 PA7* T1IO T3IO AN7 PA8 PA8* T2IO T0IO AN8 PA9 PA9* T3IO T1IO AN9 PA10 PA10* SS3 PA11 PA11* PA12 PA12* T0IO PA13 PA13* T1IO PA14 PA14* T2IO PA15 PA15* T3IO WDTO AN2 AN3 PRELIMINARY AN10 58 Z32F0641 Product Specification PCB.MR Port Control Unit PORT B Pin MUX Register This register is the PB Port Mode select register, and must be set up correctly before using the port to ensure that the port functions as designed. PCB.MR=0x4000_1100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Port PS034404-0417 Selection Bit 00 01 10 PB0 PB0* MP0UH PB1 PB1* MP0UL PB2 PB2* MP0VH PB3 PB3* MP0VL PB4 PB4* MP0WH PB5 PB5* MP0WL PB6 PB6* PRTIN0 T0IO PB7 PB7* OVIN0 T1IO PRELIMINARY 11 59 Z32F0641 Product Specification PCC.MR Port Control Unit PORT C Pin MUX Register This register is the PC Port Mode select register, and must be set up correctly before using the port to ensure that the port functions as designed. PCC.MR=0x4000_1200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 00 00 00 00 01 01 00 00 00 00 00 01 01 01 01 01 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Port PS034404-0417 Selection Bit 00 01 10 PC0 PC0 TCK/SWCLK* RXD1 PC1 PC1 TMS/SWDIO* TXD1 PC2 PC2 TDO/SWO* T8IO PC3 PC3 TDI* T9IO PC4 PC4 nTRST* T0IO PC5 PC5* RXD1 T1IO PC6 PC6* TXD1 T2IO PC7 PC7* SCL0 T3IO PC8 PC8* SDA0 PC9 PC9* CLKO PC10 PC10 nRESET* PC11 PC11/BOOT* PC12 PC12* PC13 PC13* 11 T8IO T9IO XIN XOUT (2) PC14 PC14* RXD0 MOSI0 PC15 PC15* TXD0 MISO0(2) PRELIMINARY 60 Z32F0641 Product Specification PCD.MR Port Control Unit PORT D Pin MUX Register This register is the PD Port Mode select register, and must be set up correctly before using the port to ensure that the port functions as designed. PCD.MR=0x4000_1300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Port PCn.CR Selection Bit 00 01 10 11 PD0 PD0* SS0 T8IO PD1 PD1* SCK0 T9IO PD2 PD2* MOSI0 SCL0 PD3 PD3* MISO0 SDA0 PORT n Pin Control Register (Except for PCCR) This register controls the input or output of each port pin. Each pin can be configured as input pin, output pin, or open-drain pin. PCA.CR=0x4000_1004, PCB.CR=0x4000_1104, PCD.CR=0x4000_1304 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Pn PS034404-0417 Port 00 01 10 11 control Push-pull output Open-drain output Input Analog PRELIMINARY 61 Z32F0641 Product Specification PCCCR Port Control Unit PORT C Pin Control Register This register controls the input or output of each port pin. Each pin can be configured as input pin, output pin, or open-drain pin. PCC.CR=0x4000_1204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 11 11 11 11 10 10 11 11 11 11 11 10 10 00 10 10 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Pn PCn.PCR Port 00 01 10 11 control Push-pull output Open-drain output Input Analog PORT n Pull-up Resistor Control Register Every pin in the port has on-chip pull-up resistors which can be configured by the PnPCR registers. PCA.PCR=0x4000_1008, PCB.PCR=0x4000_1108 PUE14 PUE13 PUE12 PUE11 PUE10 PUE9 PUE8 7 6 5 4 3 2 1 0 PUE0 8 PUE1 9 PUE2 10 PUE3 11 PUE4 12 PUE5 13 PUE6 14 PUE7 15 PUE15 PCC.PCR=0x4000_1208, PCD.PCR=0x4000_1308 0000 RW n PS034404-0417 PUEn Port pull-up control 0 Disable pull-up resistor 1 Enable pull-up resister PRELIMINARY 62 Z32F0641 Product Specification PCn.DER Port Control Unit PORT n Debounce Enable Register Every pin in the port has a digital debounce filter which can be configured by the PnDER registers. . The Debounce clock can be configured in the DBCLKx registers. PCA.DER=0x4000_100C, PCB.DER=0x4000_110C PDE14 PDE13 PDE12 PDE11 PDE10 PDE9 PDE8 7 6 5 4 3 2 1 0 PDE0 8 PDE1 9 PDE2 10 PDE3 11 PDE4 12 PDE5 13 PDE6 14 PDE7 15 PDE15 PCC.DER=0x4000_120C, PCD.DER=0x4000_130C 0000 RW PDEn PCn.IER Pin debounce enable 0 Disable debounce filter 1 Enable debounce filter PORT n Interrupt Enable Register Each individual pin can be an external interrupt source. The edge trigger interrupt and level trigger interrupt are both supported. The interrupt mode can be configured by setting the PnIER registers. PCA.IER=0x4000_1010, PCB.IER=0x4000_1110 PCC.IER=0x4000_1210, PCD.IER=0x4000_1310 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PIE15 PIE14 PIE13 PIE12 PIE11 PIE10 PIE9 PIE8 PIE7 PIE6 PIE5 PIE4 PIE3 PIE2 PIE1 PIE0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PIEn PS034404-0417 Pin 00 01 10 11 8 7 6 5 4 3 2 1 0 interrupt enable Interrupt disabled Enable interrupt as level trigger mode Reserved Enable interrupt as edge trigger mode PRELIMINARY 63 Z32F0641 Product Specification PCn.ISR Port Control Unit PORT n Interrupt Status Register When an interrupt is delivered to the CPU, the interrupt status can be detected by reading the PnISR register. PnISR register reports an interrupt source pin and an interrupt type. PCA.ISR=0x4000_1014, PCB.ISR=0x4000_1114 PCC.ISR=0x4000_1214, PCD.ISR=0x4000_1314 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PIS15 PIS14 PIS13 PIS12 PIS11 PIS10 PIS9 PIS8 PIS7 PIS6 PIS5 PIS4 PIS3 PIS2 PIS1 PIS0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PISn PS034404-0417 8 7 6 5 4 3 2 1 0 Pin interrupt status 00 No interrupt event 01 Low level interrupt or Falling edge interrupt event i s present 10 High level interrupt or rising edge interrupt event i s present 11 Both of rising and falling edge interrupt event is p resent in edge trigger interrupt mode. Not available in level trigger interrupt mode PRELIMINARY 64 Z32F0641 Product Specification PCn.ICR Port Control Unit PORT n Interrupt Control Register This is the Interrupt Mode control register. PCA.ICR=0x4000_1018, PCB.ICR=0x4000_1118 PCC.ICR=0x4000_1218, PCD.ICR=0x4000_1318 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PIC15 PIC14 PIC13 PIC12 PIC11 PIC10 PIC9 PIC8 PIC7 PIC6 PIC5 PIC4 PIC3 PIC2 PIC1 PIC0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PICn PORTEN Pin 00 01 10 11 8 7 6 5 4 3 2 1 0 interrupt mode Prohibit external interrupt Low level interrupt or Falling edge interrupt mode High level interrupt or rising edge interrupt mode Both of rising and falling edge interrupt mode. Not support for level trigger mode Port Access Enable Port Access Enable provides register writing permission for all PCU registers. PORTEN=0x4000_1FF0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PORTEN -WO 7 0 PS034404-0417 PORTEN Writing the sequence of 0x15 and 0x51 in this register enables writing to PCU registers, and writing other valu es protects all PCU registers from writing. PRELIMINARY 65 Z32F0641 Product Specification Port Control Unit Functional Description All the GPIO pins can be configured for different operations – inputs, outputs, and triggered interrupts (both level and edge) through the PDU. The system is also able to disable ports by setting the PER1 and PCER1 registers in the SCU. By default, all pins are disabled (except for UART0/SPI0) so the developer must enable these to operate. All configuration parameters are protected by the Port Access Enable register. You must write the sequence in order (0x15, 0x51) to the PORTEN register to configure any pin(s). Once the configuration is complete, write any other value to the PORTEN register to lock it. Note: Do not read in between the sequence; it will prevent the configuration registers from being unlocked. When the input function of I/O port is used by the Pin Control Register, the output function of I/O port is disabled. The Port function differs according to the Pin Mux Register. The Input Data Register captures the data present on the I/O pin or debounced input data at every GPIO Clock cycle. INPUT CONTROL LOGIC R/W GPIO IN FUNC 2 IN FUNC 3 IN De-Bounce Enable Register P-MOS 00 0 DEMUX FUNC 1 IN Pull Up Register R/W VDD 01 1 10 200 Ohm 200 Ohm De-Bounce Logic 11 APB AIN5V R/W VDD Pin Mux Register DIODE 00 DIODE PAD GPIO OUT FUNC 1 OUT FUNC 2 OUT FUNC 3 OUT 01 VSS 10 11 R/W VDD Pin Control Register Control Logic P-MOS N-MOS VSS OUTPUT CONTROL LOGIC Figure 5.4. Port Diagram PS034404-0417 PRELIMINARY 66 Z32F0641 Product Specification Port Control Unit De-bounce CLK External Input 1 1 1 0 1 0 0 0 1 1 0 1 1 0 CNT[1:0] 01 00 11 FF=1 FF=1 FF=1 FF=1 10 De-bounced Input FF=0 1 1 1 0 1 Figure 5.5. Debounce Function When the Debounce function of input data is used by the Debounce Enable Register, the external input data is captured by the Debounce CLK. - If CNT Value is “01”, Debounced Input Data is “1”. - If CNT Value is “10”, Debounced Input Data is “0” The Debounce CLK of each port group can be configured by the DBCLK Registers. PS034404-0417 PRELIMINARY 67 Z32F0641 Product Specification 6. General Purpose I/O General Purpose I/O Overview Most pins, except the dedicated function pins, can be used as general I/O ports. General input/output ports are controlled by the GPIO block.    Output signal level (H/L) select Input signal level Output Set/Clear pin by writing a 1 GPIO Port PSEL PnSRR PnODR DOUT[31:0] PCU DIN[31:0] PINs PnIDR Figure 6.1 Block Diagram Pin Description Table 6.1 External Signal Pin Name PS034404-0417 Type Description PA IO PA0 - PA15 PB IO PB0 – PB7 PC IO PC0 - PC15 PD IO PD0 – PD3 PRELIMINARY 68 Z32F0641 Product Specification General Purpose I/O Registers The base address of GPIO is 0x4000_2000 and the register map is described in Table 6.2 and Table 6.3. Table 6.2 Base Address of Each Port Port Address PA PORT 0x4000_2000 PB PORT 0x4000_2100 PC PORT 0x4000_2200 PD PORT 0x4000_2300 Table 6.3 GPIO Register Map Name Offset Type Description Reset Value Pn.ODR 0x--00 RW Port n Output data register 0x00000000 Pn.IDR 0x--04 RO Port n Input data register 0x00000000 Pn.BSR 0x--08 WO Port n Pin set register 0x00000000 Pn.BCR 0x—0C WO Port n Pin clear register 0x00000000 Pn.ODR PORT n Output Data Register When the pin is set as output and GPIO Mode, the pin output level is defined by Pn.ODR registers. PA.ODR=0x4000_2000, PB.ODR=0x4000_2100 PC.ODR=0x4000_2200, PD.ODR=0x4000_2300 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODR 0000 RW ODR Pn.IDR Pin output level 0 Output low level 1 Output high level PORT n Input Data Register Each pin level status can be read in the Pn.IDR register. Even if the pin is a mode other than Analog Mode, the pin level can be detected in the PnIDR register. PA.IDR=0x4000_2004, PB.IDR=0x4000_2104 PC.IDR=0x4000_2204, PD.IDR=0x4000_2304 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PnIDR 0000 RO IDR PS034404-0417 Pin current level 0 The pin is low level 1 The pin is high level PRELIMINARY 69 Z32F0641 Product Specification Pn.BSR General Purpose I/O PORT n Bit Set Register Pn.BSR is a register for controlling each bit of the PnODR register. Writing a 1 into the specific bit will set a corresponding bit of PnODR to 1. Writing 0 in this register has no effect. PA.BSR=0x4000_2008, PB.BSR=0x4000_2108 PC.BSR=0x4000_2208, PD.BSR=0x4000_2308 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BSR 0000 WO BSR Pn.BCR Pin current level 0 Not effect 1 Set correspondent bit in PnODR register PORT n Bit Clear Register Pn.BRR is a register for controlling each bit of the PnODR register. Writing a 1 into the specific bit will set a corresponding bit of PnODR to 0. Writing 0 in this register has no effect. PA.BCR=0x4000_200C, PB.BCR=0x4000_210C PC.BCR=0x4000_220C, PD.BCR=0x4000_230C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PnBCR 0000 WO BCR PS034404-0417 Pin current level 0 Not effect 1 Clear correspondent bit in PnODR register PRELIMINARY 70 Z32F0641 Product Specification General Purpose I/O Functional Description The GPIO registers provide the input/output condition of the GPIO pins. The input data registers give the states of the pins of the ports. The output data register is for setting the port pins. The Set and Clear registers control the pins at the individual level. When configured as output, the value written to the GPIO Ouput Data Register is output on the I/O Pin. When setting the Bit Set Register, the GPIO Output Data Register sets the high. When setting the Bit Clr Register, the GPIO Output Data Register sets the Low. The Input Data Register captures the data present on the I/O pin or debounced input data at every GPIO clock cycle. GPIO BLOCK PAD PORT CONTROL UNIT BIT CLR REGISTER ( WRITE ONLY ) OUTPUT DATA REGISTER ( READ WRITE ) BIT SET REGISTER ( WRITE ONLY ) APB INPUT DATA REGISTER ( READ ONLY ) Figure 6.2. GPIO Diagram PS034404-0417 PRELIMINARY 71 Z32F0641 Product Specification Flash Memory Controller 7. Flash Memory Controller Introduction The Flash Memory Controller is an internal Flash memory interface controller with the following features:       64KB Flash code memory 32-bit read data bus width Code cache block for fast access mode 128-byte page size Support page erase and macro erase 128-byte unit program Note: Programming the Flash requires the execution to occur in RAM. Once the Program mode is selected, Flash is no longer able to be read for instructions. Table 7.1 Internal Flash Specification PS034404-0417 Item Description Size 64KB Start Address 0x0000_0000 End Address 0x0000_FFFF Page Size 128-byte Total Page Count 512 pages PGM Unit 128-byte Erase Unit 128-byte PRELIMINARY 72 Z32F0641 Product Specification Flash Memory Controller B U S AHB BUS C O N T R O L Read CACHE APB BUS Register file CODE FlashROM 64KB (16K x 32bit) M U X Figure 7.1 Block Diagram Pin Description The Flash Memory Controller has no external interface pins. Registers The base address of the Flash Memory Controller is 0x4000_0100. PS034404-0417 PRELIMINARY 73 Z32F0641 Product Specification Flash Memory Controller Table 7.2 shows the register memory map. Table 7.2 Flash Memory Controller Register Map Name Offset Type Description Reset Value FM.MR 0x0004 RW Flash Memory Mode Select register 0x01000000 FM.CR 0x0008 RW Flash Memory Control register 0x00000000 FM.AR 0x000C RW Flash Memory Address register 0x00000000 FM.DR 0x0010 RW Flash Memory Data register 0x00000000 FM.TMR 0x0014 RW Flash Memory Timer register 0x000000bb FM.DRTY 0x0018 RW Flash Memory Dirty bit FM.TICK 0x001C RO Flash Memory Tick Timer FM.CRC 0x0020 RO Flash Memory Read CRC Value FM.BOOTCR 0x0074 RW Boot ROM Remap Clear register 0x00000000 FM.PROT 0x0078 RW Flash Page protection register 0x00000000 FM.JTAGEN 0x007C RW Jtag protection register 0x00000001 FM.MR 0x00000000 Flash Memory Mode Register The Flash Memory Mode Register is an internal Flash memory mode 32-bit register. FM.MR=0x4000_0104 PS034404-0417 31 BOOT 24 IDLE 23 VERIFY 22 AMBAEN 17 TRMEN 16 TRM 9 FEMOD 8 FMOD 7 0 ACODE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5A  A5 A5  5A 0 0 0 0 0 0 4 3 ACODE 0 5 0 0 0x00 RW 0 6 FMOD 0 7 R 0 8 FEMOD 0 9 R 0 TRM 0 RW 0 TRMEN 1 RW 0 AMBAEN 0 RW 0 VERIFY 0 RW 0 IDLE 0 R 0 R BOOT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 2 1 0 Boot mode enable status(read only) Boot mode enable status(read only) Flash Verify mode enable status(read only) AMBA mode disable AMBA mode enable (can change wait state and etc) Trim mode entry status(read only) Trim mode status(read only) Flash mode entry status(read only) Flash mode status(read only) Flash mode Trim mode PRELIMINARY 74 Z32F0641 Product Specification FM.CR Flash Memory Controller Flash Memory Control Register The Flash Memory Control Register is an internal Flash memory control register. FM.CR=0x4000_0108 20 TIMER 17 16 TEST 15 14 13 11 10 9 VPPOUT EVER PVER OTPBE OTPAE PPGM 8 5 4 3 2 1 AE PMODE WE PBLD PGM ERS 0 PBR PGM ERS PBR 0 0 0 0 0 0 RW 0 RW 1 RW 2 PBLD 0 3 RW 0 4 WE 0 5 RW 0 6 PMOD AE 0 7 RW PPGM 0 RW OTPAE 0 OTPBE 0 8 RW 0 9 RW PVER 0 0 0 1 00 01 01 10 11 0 1 0 RW 0 EVER 0 RW 0 VPPOUT 0 R 0 TEST0 RW 0 TEST1 RW 0 RW RW 0 RW RW PS034404-0417 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW TIMER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Program/Erase timer enable (timer can be enable by PGM or ERS bit) Normal operation (read) Row voltage mode (write) ODD Row program Even Row program All Row program Enable charge-pump Vpp output Set erase verify mode Set program verify mode OTP area B enable OTP area A enable Pre PGM enable Page buffer set automatically All erase enable PMODE enable(Address path changing) Write enable Page buffer load(WE should be set) Program enable Program mode enable Erase mode enable Page buffer reset PRELIMINARY 75 Z32F0641 Product Specification FM.AR Flash Memory Controller Flash Memory Address Register The Flash Memory Address Register is an internal Flash memory program, erase address register. FM.AR=0x4000_010C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FADDR 0 0x0000 RW 13 0 FM.DR FADDR 16K words address (one word = 4 bytes) Flash Memory Data Register This is an internal Flash memory program data register. FM.DR=0x4000_0110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FDATA 0x0000_0000 RW 31 0 FM.TMR FDATA Flash PGM data (32-bit) Flash Memory Timer Register The Flash Memory Timer Register is an internal Flash memory Timer value register (16-bit). Erase/Program timer runs up to TMR[15:0] FM.TMR=0x4000_0114 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMR 0x09C4 RW 7 0 PS034404-0417 TMR Erase/PGM timer (default, 0x09C4) Timer counts up to TMR[15:0] by 1MHz int. OSC cloc k or External OSC clock. It can be selected in TMR CK bit. PRELIMINARY 76 Z32F0641 Product Specification FM.DRTY Flash Memory Controller Flash Memory Dirty Bit Register This is an internal Flash memory dirty bit clearing register. FM.DRTY=0x4000_0118 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FDRTY Write Only 31 0 FDRTY Write any value here, cache line fill flag will be clear ed. Note: This device has a small internal cache. All cache lines are cleared when any data is written to this register. FM.TICK Flash Memory Tick Timer Register The Flash Memory Tick Timer Register is an internal Flash memory Burst Mode channel selection register. FM.TICK=0x4000_011C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTICK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 RW 17 0 FM.CRC FTICK TICK goes to 0x3FFFF from written TICK value while T RM runs by PCLK clock Flash Memory CRC Value Register The Flash Memory CRC Value Register is the Cyclic Redundancy Check (CRC) value resulting from read access on internal Flash memory. FM.CRC=0x4000_0120 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xFFFF RO 15 0 PS034404-0417 CRC CRC16 value PRELIMINARY 77 Z32F0641 Product Specification FM.CFG Flash Memory Controller Flash Memory Config Value Register The Flash Memory Config Value Register is the Flash configuration register. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 WAIT 1 9 0 1 1 7 6 CRCEN 0 TMRCK WRITE KEY HRESPD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CRCINIT FM.CFG=0x4000_0130 5 4 3 2 1 TRIM 0 0 0 0 RW FM.BOOTCR 31 15 15 WRITE KEY KEY Value : 0x7858 HRESPD 12 TMRCK 0 10 8 WAIT 7 CRCINIT 000 001 010 011 0 1 6 CRCEN 3 0 TRIM Disable HRESP(error response function) of Data or System bus (HRESP is AMBA AHB signal) PGM/ERASE timer source is 1MHz RINGOSC PRM/ERASE timer source is External Clock No wait access for flash memory 1-wait inserted for flash access 2-wait inserted for flash access 3-wait inserted for flash access CRC register winll be initialized. It should be reset again before read flash to generate CRC16 calculation (Initial value of FMCRC is 0xFFFF) CRC16 enable CRC value will be calculated at every flash read timing FLASH TRIM Value (trim_mode_entry) 0 1 Boot ROM Remap Clear Register This is the Boot ROM remap clear register. This register is an 8-bit register. FM.BOOTCR=0x4000_0174 7 6 5 4 3 2 1 0 BOOTROM 0 0 0 0 0 0 0 1 R 0 PS034404-0417 BOOTROM Boot Mode (only can be written in boot loader mode) This bit is used to clear boot loader mode at end of boot code (when BOOTROM low, external BOOT pin si gnal is masked) PRELIMINARY 78 Z32F0641 Product Specification FM.PROTECT Flash Memory Controller Write Protection Control Register The Write Protection Control Register is an internal Flash memory control register. FM.PROTECT=0x4000_0178 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FM.JTAGEN WP15 WP14 WP13 WP12 WP11 WP10 WP9 WP8 WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW 0 0 0xF000 0xE000 0xD000 0xC000 0xB000 0xA000 0x9000 0x8000 0x7000 0x6000 0x5000 0x4000 0x3000 0x2000 0x1000 0x0000 0 RW 0 RW 0 WP8 0 0 RW 0 1 WP9 0 2 RW 0 3 WP10 0 4 WP11 0 5 RW 0 6 RW 0 7 WP12 0 8 RW 0 9 WP13 0 RW 0 WP14 0 RW 0 WP15 WRITE_KEY RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 0xFFFF, write_key is 0x87 0xEFFF, write_key is 0x87 0xDFFF, write_key is 0x87 0xCFFF, write_key is 0x87 0xBFFF, write_key is 0x87 0xAFFF, write_key is 0x87 0x9FFF, write_key is 0x87 0x8FFF, write_key is 0x87 0x7FFF, write_key is 0x87 0x6FFF, write_key is 0x87 0x5FFF, write_key is 0x87 0x4FFF, write_key is 0x87 0x3FFF, write_key is 0x87 0x2FFF, write_key is 0x87 0x1FFF, write_key is 0x98 0x0FFF, write_key is 0x98 JTAG Protection Control Register The JTAG Protection Control Register is a debug access control register. FM.JTAGEN=0x4000_017C 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 WRITE_KEY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RW 0 0 JTAGEN 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 PS034404-0417 JTAGEN 0 1 Debug access port is disabled, write access code is 0xC7 Debug access port is enabled PRELIMINARY 79 Z32F0641 Product Specification Flash Memory Controller Functional Description Flash Memory Controller is an internal Flash memory interface controller. It mainly controls the program Flash memory operation and prepares read data for requesting from the bus. Flash Organization The 64 Kbytes code Flash memory consists of 1,024 pages which have a uniform 128-bytes page size. The Flash controller allows for reading or writing a data of the Flash memory. Read access can be performed by 8, 16, and 32 bits wide. This momory is located at 0x0000_0000 address on the system memory map. The system boot address is 0x0000_0000, so this Flash memory is boot memory. The code data which is programmed in the Flash memory will boot up the device after the boot ROM sequence is completed. Flash Read Operation The Flash data read operation is requested from the bus. The Flash controller responds to the request by itself. The wait time should be correctly defined because the bus speed is usually faster than Flash data access time. The normal read operation is not available in FLASH MODE in the ACODE.FM.MR field. Flash Program Operation The erase and program access of Flash memory is available only in FLASH MODE in the ACODE.FM.MR field. Therefore, self-programming is not supported. The Flash program/erase operation should be performed by the execution program on the SRAM memory. The Flash program operation writes one page to the target address selected by the FM.AR register. At first, users should write the program data into the page buffer. Page buffer write is pefromed by word write access to the FM.DR register on the FM.AR address. After filling the page buffer, users can start the Flash write operation and should wait for the IDLE bit to be set. Figure 7.2 shows the page buffer loading operation. Figure 7.2. Page Buffer Load Timing Diagram The Flash write of page buffer data is performed by the PRGM.FM.CR command. Safe writing operation requires correct program time. The program time tPGM is defined by the FM.TMR register. This timer counts the number of HCLK clock to the FM.TMR value. When the timer count starts, the IDLE.FM.MR register is cleared. When the timer count is completed, the IDLE.FM.MR register is set. In this page write operation, the target page address should be written in the FM.AR register. PS034404-0417 PRELIMINARY 80 Z32F0641 Product Specification Flash Memory Controller Figure 7.3 shows the page write operation. Figure 7.3.Page Erase Timing Diagram The Flash erase of page data is done by the ERS.FM.CR command. Safe writing operation requires correct program time. The erase time tERS is defined by the FM.TMR register. This timer counts the number of HCLK clock to the FM.TMR value. When the timer count starts, the IDLE.FM.MR register is cleared. When the timer count is completed, the IDLE.FM.MR register is set. Figure 7.4 shows the bulk erase operation. Figure 7.4. Bulk Erase Timing Diagram PS034404-0417 PRELIMINARY 81 Z32F0641 Product Specification Internal SRAM 8. Internal SRAM Overview The Z32F0641 MCU has a block of 0-wait on-chip SRAM. The size of SRAM is 8 KB. The SRAM base address is 0x2000_0000. The SRAM memory area is usually used for data memory and stack memory. Sometimes the code is dumped into the SRAM memory for fast operation or Flash erase/PGM operation. This device does not support a memory remap strategy; therefore, jump and return is required to execute the code in the SRAM memory area. 0x0000_0000 Code Flash (64KB) 0x0000_FFFF 0x2000_0000 SRAM (8KB) 0x2000_1FFF Figure 8.1 SRAM Block Diagram PS034404-0417 PRELIMINARY 82 Z32F0641 Product Specification Direct Memory Access Controller 9. Direct Memory Access Controller Introduction Features of the Direct Memory Access Controller (DMAC) include:      Four channels Single transfer only Supports 8/16/32-bit data size Supports multiple buffers with same size Interrupt condition is transferred through peripheral interrupt A block diagram of the DMAC is shown in Figure 9.1. Figure 9.1 Block Diagram Pin Description The DMAC has no external interface pins. PS034404-0417 PRELIMINARY 83 Z32F0641 Product Specification Direct Memory Access Controller Registers The base address of the DMA controller is shown in Table 9.1. Table 9.1 DMA Controller Base Address Channel Base Address DMACH0 0x4000_0400 DMACH1 0x4000_0410 DMACH2 0x4000_0420 DMACH3 0x4000_0430 Table 9.2 shows the register map of the DMA controller. Table 9.2 DMAC Register Map Name Offset Type Description Reset Value DCn.CR 0x0000 RW DMA Channel n Control Register 0x0000_0000 DCn.SR 0x0004 RW DMA Channel n Status Register 0x0000_0000 DCn.PAR 0x0008 R DMA Channel n Peripheral Address 0x0000_0000 DCn.MAR 0x000C RW DMA Channel n Memory Address 0x2000_0000 DCn.CR DMA Controller Configuration Register This DMA operation control register is a 32-bit register. DC0.CR=0x4000_0400 , DC1.CR=0x4000_0410 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TRANSCNT 0 0 0 0 0x000 0 0 0 0 0 RW 27 16 TRANSCNT 11 8 PERISEL 3 2 SIZE 1 DIR 8 7 6 5 4 PERISEL RW PS034404-0417 9 0 0 0 0 2 1 SIZE DIR DC2.CR=0x4000_0420 , DC3.CR=0x4000_0430 3 00 0 RW RW 0 0 Number of DMA transfer remained Required transfer number should be written before ena ble DMA transfer. 0 DMA transfer is done. N N transfers are remained Peripheral selction N Associated peripheral selection. Refer to DMA Peripheral connection table Bus transfer size. 00 DMA transfer is byte size transfer 01 DMA transfer is half word size transfer 10 DMA transfer is word size transfer 11 Reserved Select transfer direction. 0 Transfer direction is from memory to peripheral. (T X) 1 Transfer direction is from peripheral to memory (R X) PRELIMINARY 84 Z32F0641 Product Specification Direct Memory Access Controller A DMA channel is connected to the selected peripheral. Table 9.3 shows the peripheral selections. This PERISEL field must be configured with the correct number of peripherals that will be connected to the DMA interface. Table 9.3 DMAC PERISEL Selection PERISEL[3:0] Associatec Peipheral 0 CHANNEL IDLE 1 UART0 RX 2 UART0 TX 3 UART1 RX 4 UART1 TX 5 SPI0 RX 6 SPI0 TX 7 ADC0 RX 8 ADC1 RX 9 - 15 N.A. Note: PERISEL cannot have the same value in different channels. If the same PERISEL value is wriiten in more than one channel, proper operation is not guaranteed. Unused channels must contain CHANNEL IDLE value in PERISEL bit postions. DCn.SR DMA Controller Status Register The DMA Controller Status Register is an 8-bit register. This register represents the current status of the DMA Controller and enables DMA function. DC0.SR=0x4000_0404 , DC1.SR=0x4000_0414 DC2.SR=0x4000_0424 , DC3.SR=0x4000_0434 7 6 5 4 3 2 1 EOT 1 DMAEN 0 0 0 0 0 0 RO PS034404-0417 0 0 RW 7 EOT 0 DMAEN End of transfer. 0 Data to be transferred is existing. TRANSCNT shows non zero value 1 All data is transferred. TRANSCNT shows now 0 DMA Enable 0 DMA is in stop or hold state 1 DMA is running or enabled PRELIMINARY 85 Z32F0641 Product Specification Direct Memory Access Controller DCn.PAR DMA Controller Peripheral Address Register This register represents the peripheral addresses. DC0.PAR=0x4000_0408 , DC1.PAR=0x4000_0418 DC2.PAR=0x4000_0428 , DC3.PAR=0x4000_0438 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Peripheral BASE OFFSET PAR 0x4000 0x0000 RO RW 31 0 PAR 6 5 4 3 2 1 0 Target Peripheral address of transmit buffer or receive buffer. User must set exact target peripheral buffer address in this field. If DIR is “0” this address is destination address of data transfer. If DIR is “1”, this address is source address of data transfer. DCn.MAR DMA Controller Memory Address Register This register represents the memory addresses. DC0.MAR=0x4000_040C , DC1.MAR=0x4000_041C DC2.MAR=0x4000_042C , DC3.MAR=0x4000_043C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR 0x2000 0x0000 RO RW 31 0 PS034404-0417 MAR Target memory address of data transfer. Address is automatically incremented according to SIZE bits when each transfer is done. If DIR is “0” this address is source address of data tra nsfer. If DIR is “1”, this address is destination address of dat a transfer. PRELIMINARY 86 Z32F0641 Product Specification Direct Memory Access Controller Functional Description The DMA controller performs direct memory transfer by sharing the system bus with the CPU core. The system bus is shared by 2 AHB masters following the round-robin priority strategy. Therefore, the DMA controller can share half of the system bandwidth. The DMA controller is triggered only with a peripheral request. When a peripheral requests the transfer to the DMA controller, the associated channel is activated and accesses the bus to transfer the requested data from memory to the peripheral data buffer or from the peripheral data buffer to memory space. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. User sets the peripheral address and memory address. User configures DMA operation mode and transfer count. User enables the DMA channel. Peripheral sends a DMA request. DMA activates the channel that was requested. DMA reads data from the source address and saves it to the internal buffer. DMA writes the buffered data to the destination address. Transfer count number is decreased by 1. When Transfer count is 0, the EOT flag is set and a notice sent to peripheral to issue the interrupt. DMA does not have an interrupt source; the interrupt related DMA status can be shown from the assigned peripheral interrupt. Figure 9.2. Block Diagram Figure 9.2 shows the functional timing diagram of the DMA controller. The transfer request from the peripheral is pended internally and it invokes source data read transfer on the AHB bus. The read data from the source address is stored in the internal buffer. This data will then be transferred to the destination address when the AHB bus is available. The timing diagram for a DMA transfer from the peripheral to memory is shown in Figure 9.3. A 4-clock cycle latency exists when accessing the peripheral. If the bus is occupied by a different bus master, the number of bus waiting cycles increase until the bus is available. PS034404-0417 PRELIMINARY 87 Z32F0641 Product Specification Direct Memory Access Controller Figure 9.3. DMA Transfer from Peripheral to Memory The timing diagram for a DMA transfer from memory to the peripheral is shown in Figure 9.4. 4-clock cycle latency exists during accessing the peripheral. If the bus is occupied by a different bus master, there are amount of bus waiting cycles. Figure 9.4. DMA Transfer from Memory to Peripheral The figure is an example N data transfers with the DMA. The DMA transfer is started when DCnSR.DMAEN is set and will be cleared when all the number of transfer is completed. Figure 9.5. N DMA Transfer Example PS034404-0417 PRELIMINARY 88 Z32F0641 Product Specification Watchdog Timer 10. Watchdog Timer Overview The Watchdog Timer can monitor the system and generate an interrupt or a reset. It has a 32-bit down-counter. The Miscellaneous Clock Control Register 3 provides base clock options with clock dividers to drive the WDT clock. This can be selected in the WDTCON register. To prevent the WDT from firing, reload the LR register with the appropriate value before the WDT times out. 32-bit down counter (WDTCVR) Features include:  Select reset or periodic interrupt  Count clock selection  Dedicated pre-scaler  Watchdog overflow output signal Figure 10.1 Block Diagram PS034404-0417 PRELIMINARY 89 Z32F0641 Product Specification Watchdog Timer Registers The base address of the watchdog timer is 0x4000_0200 and the register map is described in Table 10.1. The initial watchdog time-out period is set to 2,000-miliseconds. Table 10.1 Watchdog Timer Register Map NAME OFFSET TYPE WDT.LR 0x0000 W WDT Load register 0x00000000 WDT.CNT 0x0004 R WDT Current counter register 0x0000FFFF WDT.CON 0x0008 RW WDT Control register 0x0000805C WDT.LR DESCRIPTION RESET VALUE Watchdog Timer Load Register The WDTLR register is used to update the WDTCVR register. To update the WDTCVR register, the WEN bit of WDTCON should be set to 1 and written to the WDTLR register with a target value of WDTCVR. WDT.LR=0x4000_0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLR 0x0000_0000 RW 31 0 WDT.CNT WDTLR Watchdog timer load value register Keeping WEN bit as ‘1’, write WDTLR register will upd ate WDTCVR value with written value Watchdog Timer Current Counter Register The WDTCNT register represents the current count value of 32-bit down counter .When the counter value reaches 0, an interrupt or reset occurs. WDT.LR=0x4000_0204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTCNT 0x0000_FFFF RW 31 0 PS034404-0417 WDTCNT Watchdog timer current counter register 32-bit down counter will run from the written value. PRELIMINARY 90 Z32F0641 Product Specification Watchdog Timer WDT.CON Watchdog Timer Control Register WDT module should be configured properly before running. When target purpose is defined, the WDT can be configured in the WDTCON register WDT.CON=0x4000_0208 1 0 0 0 0 0 0 RW PS034404-0417 15 WDBG 8 WUF 7 WDTIE 6 WDTRE 4 WDTEN 3 CKSEL 2 0 WPRS 8 7 6 0 0 1 RW RW RW 5 0 4 3 2 1 WPRS 9 CKSEL 10 WDTEN 11 WDTRE 12 WDTIE 13 WUF 14 WDBG 15 1 1 100 RW RW RW 0 Watchdog operation control in debug mode 0 Watchdog counter running when debug mode 1 Watchdog counter stopped when debug mode Watchdog timer underflow flag 0 No underflow 1 Underflow is pending Watchdog timer counter underflow interrupt enable 0 Disable interrupt 1 Enable interrupt Watchdog timer counter underflow interrupt enable 0 Disable reset 1 Enable reset Watchdog Counter enable 0 Watch dog counter disabled 1 Watch dog counter enabled WDTCLKIN clock source select 0 PCLK 1 External clock ( RINGOSC 1MHz ) Counter clock prescaler WDTCLK = WDTCLKIN/WPRS 000 WDTCLKIN 001 WDTCLKIN / 4 010 WDTCLKIN / 8 011 WDTCLKIN / 16 100 WDTCLKIN / 32 101 WDTCLKIN / 64 110 WDTCLKIN / 128 111 WDTCLKIN / 256 PRELIMINARY 91 Z32F0641 Product Specification Watchdog Timer Functional Description The watchdog timer count can be enabled by setting WDTEN (WDT.CON[4]) to 1. When the watchdog timer is enabled, the down counter starts counting from the Load Value. If WDTRE (WDT.CON[6]) is set as 1, WDT reset will be asserted when the WDT counter value reaches 0 (underflow event) from the WDTLR value. Before WDT counter goes down to 0, the software can write a certain value to the WDTLR register to reload the WDT counter. Timing Diagram Figure 10.2. Timing Diagram in Interrupt Mode Operation when WDT Clock is the External Clock In WDT Interrupt mode, after WDT underflow occurs, a certain count value is reloaded to prevent the next WDT interrupt in a short time period and this reloading action can only be activated when the watchdog timer counter is set to Interrupt mode (set WDTIE of WDT.CON). It takes up to 5 cycles from the Load value to the CNT value. The WDT interrupt signal and the CNT value data might be delayed by a maximum of 2 system bus clocks in synchronous logic. Prescale Table The Watchdog Timer includes a 32-bit down counter with programmable pre-scaler to define different time-out intervals. The clock sources of watchdog timer can be peripheral clock (PCLK) or one of 3 external clock sources. The external clock source can be enabled by CKSEL (WDT.CON[3]) set to ‘1’. The external clock source is selected in the MCCR3 register of the System Control Unit block. To make the WDT counter base clock, users can control the 3-bit pre-scaler WPRS [2:0] in the WDT.CON register and the maximum pre-scaled value is “clock source frequency/256”. The pre-scaled WDT counter clock frequency values are listed in Table 10.2. Selectable clock source (40 kHz ~ 16 MHz) and the time out interval when 1 count Time out period = {(Load Value) * (1/pre-scaled WDT counter clock frequency) + max 5Text} + max 4Tclk *Time out period (time out period from load Value to interrupt set ‘1’) PS034404-0417 PRELIMINARY 92 Z32F0641 Product Specification Watchdog Timer Table 10.2. Pre-scaled WDT Counter Clock Frequency Clock Source Ring OSC MCLK EOSC WDTCLKIN WDTCLKIN /4 WDTCL KIN/8 WDTCL KIN/16 WDTCL KIN/32 WDTCL KIN/64 WDTCL KIN/128 WDTCL KIN/256 1Mhz 250khz 125khz 62.5khz 31.25khz 15.625khz 7.8125khz 3.90625kh z MCLK (BUS CLK) MCLK/4 MCLK/8 MCLK/16 MCLK/32 MCLK/64 MCLK/128 MCLK/256 XTAL XTAL/4 XTAL/8 XTAL/16 XTAL/32 XTAL/64 XTAL/128 XTAL/256 PS034404-0417 PRELIMINARY 93 Z32F0641 Product Specification 16-Bit Timer 11. 16-Bit Timer Overview The timer block consists of six channels of 16-bit general-purpose timers. They support periodic timer, PWM pulse, one-shot timer, and capture mode. The 16-bit timer has the following features:        16-bit up-counter Periodic timer mode One-shot timer mode PWM pulse mode Capture mode 10-bit prescaler Synchronous start and clear function Figure 11.1 shows the block diagram of a unit timer block. Figure 11.1 Block Diagram PS034404-0417 PRELIMINARY 94 Z32F0641 Product Specification 16-Bit Timer Pin Description Table 11.1 External Pin Pin Name Type TnIO I Description External clock/capture input and PWM/one-shot output Registers The base address of the timer is 0x4000_3000 and the register map is described in Table 11.3. Table 11.2 Base Address of Each Channel Channel Base Address T0 0x4000_3000 T1 0x4000_3020 T2 0x4000_3040 T3 0x4000_3060 T8 0x4000_3100 T9 0x4000_3120 Table 11.3 Timer Register Map Name Offset Type Description Reset Value Tn.CR1 0x--00 RW Timer control register 1 0x00000000 Tn.CR2 0x--04 RW Timer control register 2 0x00000000 Tn.PRS 0x--08 RW Timer prescaler register 0x00000000 Tn.GRA 0x--0C RW Timer general data register A 0x00000000 Tn.GRB 0x--10 RW Timer general data register B 0x00000000 Tn.CNT 0x--14 RW Timer counter register 0x00000000 Tn.SR 0x--18 RW Timer status register 0x00000000 Tn.IER 0x--1C RW Timer interrupt enable register 0x00000000 PS034404-0417 PRELIMINARY 95 Z32F0641 Product Specification Tn.CR1 16-Bit Timer Timer n Control Register 1 The Timer Control Register 1 is a 16-bit register. The timer module should be accurately configured prior to operating it. When a target purpose is defined, the timer can be configured in the TnCR1 register. T0.CR1=0x4000_3000, T1.CR1=0x4000_3020 T2.CR1=0x4000_3040, T3.CR1=0x4000_3060 0 RW RW RW RW PS034404-0417 0 0 0 8 7 0 SSYNC 14 CSYNC 13 UAO 12 OUTPOL 8 ADCTRGEN 7 STARTLVL 6 4 CKSEL[2:0] 3 2 CLRMOD 1 0 MODE 5 4 3 2 1 0 0 000 00 00 RW RW RW RW 15 6 MODE 0 9 CLRMOD 0 10 CKSEL 0 11 STARTLVL OUTPOL 12 UAO 13 CSYNC 14 SSYNC 15 ADCTRGEN T8.CR1=0x4000_3100, T9.CR1=0x4000_3120 Synchronize start counter with other synchronized timer s 0 Single counter mode 1 Synchronized counter start mode Synchronize clear counter with other synchronized timer s 0 Single counter mode 1 Synchronized counter clear mode Select GRA, GRB update mode 0 Writing GRA or GRB takes effect after current period 1 Writing GRA or GRB takes effect in current peri od Timer output polarity 0 Normal output 1 Negated output ADC Trigger enable control 0 Disable adc trigger 1 Enable adc trigger Timer output polarity control 0 Default output level is HIGH 1 Defulat output level is LOW Counter clock source select 000 PCLK/2 001 PCLK/4 010 PCLK/16 011 PCLK/64 10X MCCR3 clock setting 11X TnIO pin input (TnIO pin must be set as input mode) Clear select when capture mode 00 Rising edge clear mode 01 Falling edge clear mode 10 Both edge clear mode 11 None clear mode Timer operation mode control 00 Normal periodic operation mode 01 PWM mode 10 One shot mode 11 Capture mode PRELIMINARY 96 Z32F0641 Product Specification Tn.CR2 16-Bit Timer Timer Control Register 2 The Timer Control Register 2 is an 8-bit register. T0.CR2=0x4000_3004, T1.CR2=0x4000_3024 T2.CR2=0x4000_3044, T3.CR2=0x4000_3064 T8.CR2=0x4000_3104, T9.CR2=0x4000_3124 7 6 5 4 3 2 1 0 TCLR TEN 0 0 0 0 0 0 0 0 R R R R R R WO RW 1 TCLR 0 TEN Timer register clear 0 Normal operation 1 Clear count register. (This bit will be cleared after next timer clock) Timer enable bit 0 Stop timer counting 1 Start timer counting Note: It is recommended that the timer is started with TCLR bit setting at 1. Tn.PRS Timer n Prescaler Register The Timer Prescaler Register is a 16-bit register designed to prescale the counter input clock. T0.PRS=0x4000_3008, T1.PRS=0x4000_3028 T2.PRS =0x4000_3048, T3.PRS=0x4000_3068 T8.PRS=0x4000_3108, T9.PRS=0x4000_3128 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRS 0 0 0 0 0 0 000 RW 9 0 PS034404-0417 PRS Pre-scale value of count clock TCLK = CLOCK_IN/(PRS+1) (CLOCK_IN is a selected timer input clock) PRELIMINARY 97 Z32F0641 Product Specification Tn.GRA 16-Bit Timer Timer General Register A The Timer General Register A is a 16-bit register. T0.GRA=0x4000_300C, T1.GRA=0x4000_302C T2.GRA =0x4000_304C, T3.GRA=0x4000_306C T8.GRA=0x4000_310C, T9.GRA=0x4000_312C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRA 0x0000 RW 15 0 Tn.GRB GRA General Register A (Duty/Interrupt Register) Periodic mode / PWM / One-shot mode - In PWM mode this register is used as duty value. - When the counter value is matched with this value, GRA Match interrupt is requested Capture mode - Falling edge of TnIO port will capture the count valu e when rising edge clear mode - Rising edge of TnIO port will capture the count value when falling edge clear mode Timer n General Register B The Timer General Register B is 16-bit register. T0.GRB=0x4000_3010, T1.GRB=0x4000_3030 T2.GRB=0x4000_3050, T3.GRB=0x4000_3070 T8.GRB=0x4000_3110, T9.GRB=0x4000_3130 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRB 0x0000 RW 15 0 PS034404-0417 GRB General Register B (Period Register) Periodic mode / PWM / One-shot mode - In periodic mode or PWM mode, this register is used as Period value. The counter will count up to (GRB-1) value. - When the counter value is matched with this value, GRB Match interrupt is requested only in PWM and on e-shot modes. Capture mode - Rising edge of TnIO port will capture the count value when rising edge clear mode - Falling edge of TnIO port will capture the count value when falling edge clear mode PRELIMINARY 98 Z32F0641 Product Specification Tn.CNT 16-Bit Timer Timer Count Register. The Timer Count Register is a 16-bit register. T0.CNT=0x4000_3014, T1.CNT=0x4000_3034 T2.CNT=0x4000_3054, T3.CNT=0x4000_3074 T8.CNT=0x4000_3114, T9.CNT=0x4000_3134 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 0x0000 RW 15 0 Tn.SR CNT Timer count value register R Read current timer count value W Set count value Timer n Status Register The Timer Status Register is an 8-bit register. This register indicates the current status of timer module. T0.SR=0x4000_3018, T1.SR=0x4000_3038 T2.SR=0x4000_3058, T3.SR=0x4000_3078 T8.SR=0x4000_3118, T9.SR=0x4000_3138 7 0 6 5 0 4 0 0 2 MFA 1 MFB 0 OVF 3 0 2 1 0 MFA MFB OVF 0 0 0 RW RW RW GRA Match flag 0 No direction change 1 Match flag with GRA GRB Match flag 0 No direction change 1 Match flag with GRB Counter overflow flag 0 No direction change 1 Counter overflow flag Note: The OVF flag occurs only when the counter rolls from 0xFFFF to 0. PS034404-0417 PRELIMINARY 99 Z32F0641 Product Specification Tn.IER 16-Bit Timer Timer Interrupt Enable Register The Timer Interrupt Enable Register is an 8-bit register. Each status flag of the timer block can issue the interrupt. To enable the interrupt, write 1 in the corresponding bit in the TnIER register. T0.IER=0x4000_301C, T1.IER=0x4000_303C T2.IER=0x4000_305C, T3.IER=0x4000_307C T8.IER=0x4000_311C, T9.IER=0x4000_313C 7 6 5 4 3 0 0 0 0 0 PS034404-0417 2 MAIE 1 MBIE 0 OVIE 2 1 0 MAIE MBIE OVIE 0 0 0 W RW W GRA Match interrupt enable 0 Not effect 1 Enable match register A interrupt GRB Match interrupt enable 0 Not effect 1 Enable match register B interrupt Counter overflow interrupt enable 0 Not effect 1 Enable counter overflow interrupt PRELIMINARY 100 Z32F0641 Product Specification 16-Bit Timer Functional Description Timer Basic Operation In Figure 11.2, TMCLK is a reference clock for operation of the timer. When this clock is divided by the prescaler setting, the counting clock will work. (a) Timer initialization is performed by the TCLR command and the timer is started by the TEN command. (b) Timer is reset by matching GRB timing and counting again from 00. Figure 11.2. Basic Start and Match Operation The period of timer count can be calculated as shown in the following equation: The period = TMCLK Period * Tn.GRB value Match A interrupt time = TMCLK Period * Tn.GRA value If the Tn.CR1.UAO bit is “0”, the Tn.CR2.TCLR command will initialize all the registers in the timer block and load the GRA and GRB values into the Data0 and Data1 buffer. When you change the timer setting and restart the timer with the new setting, it is recommended that you write the CR2.TCLR command before the CR2.TEN command. PS034404-0417 PRELIMINARY 101 Z32F0641 Product Specification 16-Bit Timer The update timing of the Data0 and Data1 buffer in dynamic operation is different in each operating mode and depends on the Tn.CR1.UAO bit. Normal Periodic Mode Figure 11.3 shows the timing diagram in normal periodic mode. Tn.GRB value decides the timer period. One more compare point is provided with Tn.GRA register value. Figure 11.3. Normal Periodic Mode Operation The period of timer count can be calculated as shown in the following equation: The period = TMCLK Period * Tn.GRB value Match A interrupt time = TMCLK Period * Tn.GRA value If Tn.GRB = 0, the timer cannot be started even if TnCR2.TEN is “1” because the period is “0”. The value in Tn.GRA and Tn.GRB is loaded into the internal compare data buffers 0 and 1 when the loading condition occurs. In this periodic mode with TnCR1.UAO =0, the Tn.CR2.TCLR write operation and the GRB match event will load the compare data buffers. When TnCR1.UAO is 1, the internal compare data buffer is updated whenever the Tn.GRA or Tn.GRB data is updated. The TnIO output signal will be toggled at every Match A condition time. If the value of TnGRA is 0, the TnIO output does not change its previous level. If TnGRA is the same as TnGRB, the TnIO ouput will toggle at same time as the counter start time. The initial level of the TnIO signal is decided by the TnCR1.STARTLVL value. One Shot Mode Figure 11.4 shows the timing diagram in one shot mode. Tn.GRB value decides the one shot period. One more compare point is provided with Tn.GRA register value. PS034404-0417 PRELIMINARY 102 Z32F0641 Product Specification 16-Bit Timer Figure 11.4. One Shot Mode Operation The period of one shot count can be calculated as shown in the following equation: The period = TMCLK Period * Tn.GRB value Match A interrupt time = TMCLK Period * Tn.GRA value If Tn.GRB = 0, the timer cannot be started even if TnCR2.TEN is “1” because the period is “0”. The value in Tn.GRA and Tn.GRB is loaded into the internal compare data buffer 0 and 1 when the loading condition occurs. In this periodic mode with TnCR1.UAO =0, the Tn.CR2.TCLR write operation and the GRB match event will load the compare data buffers. When TnCR1.UAO is 1, the internal compare data buffer is updated whenever the Tn.GRA or Tn.GRB data is updated. The TnIO output signal format is the same as PWM mode. Tn.GRB value defines the output pulse period and the Tn.GRA value defines the pulse width of one shot pulse. PWM Timer Output Figure 11.5 shows the timing diagram in PWM output mode. The Tn.GRB value decides the PWM pulse period. An additional comparison point is provided by the Tn.GRA register value which defines the pulse width of PWM output. PS034404-0417 PRELIMINARY 103 Z32F0641 Product Specification 16-Bit Timer Figure 11.5. PWM Output Operation The period of PWM pulse can be calculated as shown in the following equation: The period = TMCLK Period * Tn.GRB value Match A interrupt time = TMCLK Period * Tn.GRA value If Tn.GRB = 0, the timer cannot be started even TnCR2.TEN is “1” because the period is “0”. The value in Tn.GRA and Tn.GRB is loaded into the internal compare data buffer 0 and 1 when the loading condition occurs. In this periodic mode with TnCR1.UAO =0, the Tn.CR2.TCLR write operation and the GRB match event will load the compare data buffers. When TnCR1.UAO is 1, the internal compare data buffer is updated whenever the Tn.GRA or Tn.GRB data is updated. The TnIO output signal generates a PWM pulse. The Tn.GRB value defines the output pulse period and the Tn.GRA value defines the pulse width of one shot pulse.The active level of the PWM pulse can be controlled by the Tn.CR1.STARTLVL bit value. ADC Trigger generation is available at Match A interrupt time. PS034404-0417 PRELIMINARY 104 Z32F0641 Product Specification 16-Bit Timer PWM Synchronization Function 2-PWM outputs are usually used as synchronous PWM signal control. This function is provided with a synchronous start function. Figure 8.6 shows the synchronous PWM generation function. T0.GRB T0.GRA T0.CNT Timer0 was cleared by start event of Timer1 (SSYNC=‘1’) Timer0 starts Timer0 restarts T1.GRB T1.CNT T1.GRA Timer1 starts T0IO output T1IO output T0.CR2 TEN=1 (SSYNC=0) T1.CR2 TEN=1 (SSYNC=1) T0.CNT=T0.GRA T1.CNT=T1.GRA Figure 11.6. Example of Timer Synchronization Function (SSYNC=’0’) PS034404-0417 PRELIMINARY 105 Z32F0641 Product Specification 16-Bit Timer Figure 11.7. Example of Timer Synchronization Function (CSYNC=’1’) The TnCR1.SSYNC bit controls start synchronization with other timer blocks. The TnCR1.CSYCN bit controls clear sync with other timer blocks. The SSYNC and CSYNC bits are only effective when used with two or more timers. For example, timer0 and timer1 set the SSYNC and CCSYNC bits in each CR1 register; both timers are started whenever one of them is enabled and both timers will cleared with a short period match value. However, others are not affected by these two timers, and they can be operated independently because their SYNC control bit is 0. Capture Mode Figure 11.8 shows the timing diagram in the Capture mode operation. The TnIO input signal is used for capturing the pulse.Rising and falling edges can capture the counter value in each capture codition. PS034404-0417 PRELIMINARY 106 Z32F0641 Product Specification 16-Bit Timer Figure 11.8. Capture Mode Operation A 5 PCLK clock cycle is required internally. Therefore, the actual capture point is after 5 PCLK clock cycles from the rising or falling edge of the TnIO input signal. The internal counter can be cleared in multiple modes. The TnCR1.CLRMD field controls the counter clear mode. The following clear modes are supported: Rising edge, Falling edge, Both edges, and None. The example in Figure 11.8 is of Rising edge clear mode. ADC Trigger Function The timer module can generate ADC start trigger signals. One timer can be one trigger source of the ADC block. Trigger source control is performed by the ADC control register. Figure 11.9 shows the ADC trigger function. The conversion rate must be shorter than the timer period, else an overrun situation can occur. ADC acknowledge is not required because the trigger signal is automatically cleared after 3 PCLK clock pulses. PS034404-0417 PRELIMINARY 107 Z32F0641 Product Specification 16-Bit Timer Figure 11.9. ADC Trigger Function Timing Diagram PS034404-0417 PRELIMINARY 108 Z32F0641 Product Specification UART 12. UART Overview 2-Channel Universal Asynchronous Receiver/Transmitter (UART) modules are included. Dedicated DMA support to transfer data between the Memory buffer and the Transmit/Receive buffer of the UART block is also provided. The UART operation status, including error status, can be read from the status register. The prescaler, which generates proper baud rate, exists for each UART channel. This prescaler divides the UART clock source which is PCLK/2, from 1 to 65535. The baud rate is generated using the clock with a prescaler of 16, and an 8-bit precision clock tuning function. Programmable interrupt generation function helps control communication via the UART channel. Features of the UART include:           Compatible with 16450 UART Supports DMA transfer Standard asynchronous control bit (start, stop, and parity) configurable Programmable 16-bit fractional baud rate generator Programmable serial communication o 5-, 6-, 7- or 8- bit data transfer o Even, odd, or no-parity bit insertion and detection o 1-, 1.5- or 2-stop bit-insertion and detection 16-bit baud rate generation with 8-bit fraction control Hardware inter-frame delay function Stop bit error detection Detail status register Loop-back control PS034404-0417 PRELIMINARY 109 Z32F0641 Product Specification UART Figure 12.1 Block Diagram PS034404-0417 PRELIMINARY 110 Z32F0641 Product Specification UART Pin Description Table 12.1 External Signal Pin Name Type Description TXD0 O UART Channel 0 transmit output RXD0 I UART Channel 0 receive input TXD1 O UART Channel 1 transmit output RXD1 I UART Channel 1 receive input Registers The base address of UART is shown in Table 12.2 and the register map is described in and Table 12.3. Table 12.2 Base Address of Each Port Name Base Address UART 0 0x4000_8000 UART 1 0x4000_8100 Table 12.3 UART Register Map Name Offset Type Description Reset Value Un.RBR 0x00 R Receive data buffer register 0x00 Un.THR 0x00 W Transmit data hold register 0x00 Un.IER 0x04 RW Interrupt enable register 0x00 Un.IIR 0x08 R Interrupt ID register 0x01 - 0x08 - reserved - Un.LCR 0x0C RW Line control register 0x00 Un.DCR 0x10 RW Data Control Register 0x00 Un.LSR 0x14 R Line status register 0x00 - 0x18 - reserved - Un.SCR 0x1C RW Scratch pad register 0x00 Un.BDR 0x20 RW Baud rate Divisor Latch Register 0x0000 Un.BFR 0x24 RW Baud rate Fractional Counter Value 0x00 Un.IDTR 0x30 RW Inter-frame Delay Time Register 0x00 PS034404-0417 PRELIMINARY 111 Z32F0641 Product Specification Un.RBR UART Receive Buffer Register The UART Receive Buffer Register is an 8-bit Read-Only register. U0.RBR=0x4000_8000, U1.RBR=0x4000_8100 7 6 5 4 3 2 1 0 RBR[7:0] RO 7 0 Un.THR RBR Receive Buffer Register Transmit Data Hold Register The UART Transmit Data Hold Register is an 8-bit Write-Only register. U0.THR=0x4000_8000, U1.THR=0x4000_8100 7 6 5 4 3 2 1 0 THR WO 7 0 PS034404-0417 THR Transmit Data Hold Register PRELIMINARY 112 Z32F0641 Product Specification Un.IER UART UART Interrupt Enable Register The UART Interrupt Enable Register is an 8-bit register. U0.IER=0x4000_8004, U1.IER=0x4000_8104 7 6 5 4 3 2 1 0 - - DTXIEN DRXIEN TXIE RLSIE THREIE DRIE 0 0 0 0 0 0 0 0 RW RW RW RW RW Un.IIR 5 DTXIEN 4 DRXIEN 3 TXIE 2 RLSIE 1 THREIE 0 DRIE DMA transmit done interrupt enable 0 Receive line status interrupt is disabled 1 Receive line status interrupt is enabled DMA receive done interrupt enable 0 DMA receive done interrupt is disabled 1 DMA receive done interrupt is enabled Transmit register empty interrupt enable 0 Transmit register empty interrupt is disabled 1 Transmit register empty interrupt is enabled Receiver line status interrupt enable 0 Receive line status interrupt is disabled 1 Receive line status interrupt is enabled Transmit holding register empty interrupt enable 0 Transmit holding register empty interrupt is disable d 1 Transmit holding register empty interrupt is enable d Data receive interrupt enable 0 Data receive interrupt is disabled 1 Data receive interrupt is enabled UART Interrupt ID Register The UART Interrupt ID Register is an 8-bit register. U0.IIR=0x4000_8008, U1.IIR=0x4000_8108 7 0 PS034404-0417 6 5 0 4 0 4 TXE 3 1 0 IID IPEN 3 2 1 0 TXE IID IPEN 0 000 0 R R R Interrupt source ID See interrupt source ID table Interrupt source ID See interrupt source ID table Interrupt pending bit 0 Interrupt is pending 1 No interrupt is pending. PRELIMINARY 113 Z32F0641 Product Specification UART The UART supports 3-priority interrupt generation. The Interrupt Source ID register shows one interrupt source which has the highest priority among pending interrupts. This priority is defined in the following order:     Receive line status interrupt Receive data ready interrupt/Character timeout interrupt Transmit hold register empty interrupt Tx/Rx DMA complete interrupt Table 12.4 Interrupt ID and Control TXE Priority IID IPEN Interrupt Sources Bit4 Bit3 Bit2 Bit1 Bit0 Interrupt Interrupt Condition Interrupt Clear - 0 0 0 0 1 None - - 1 0 0 1 1 0 Receiver Line Status Overrun, Parity, Framing or Break Error Read LSR register 2 0 0 1 0 0 Receiver Data Available Receive data is available. Read receive register or read IIR register 0 Transmitter Holding Register Empty Transmit buffer empty Write transmit hold register or read IIR register Transmit registerr empty Write transmit hold register or read IIR register 3 0 0 0 1 4 1 X X X X Transmitter Register Empty 5 0 1 1 0 0 Rx DMA done Rx DMA completed. Read IIR register 6 0 1 0 1 0 Tx DMA done Tx DMA completed. Read IIR register X Transmitter register Empty and DMA done Transmitter regiser Empty and Tx DMA completed. Read IIR register 7 PS034404-0417 1 X X X PRELIMINARY 114 Z32F0641 Product Specification Un.LCR UART UART Line Control Register The UART Line Control Register is an 8-bit register. U0.LCR=0x4000_800C, U1.LCR=0x4000_810C 7 0 6 5 4 3 2 BREAK STICKP PARITY PEN STOPBIT 0 0 0 0 0 0 0 RW RW RW RW RW RW RW 6 BREAK 5 STICKP 4 PARITY 3 PEN 2 STOPBIT 1 0 DLEN 1 0 DLEN When this bit is set, TxD pin will be driven at low state in orde r to notice the alert to the receiver. 0 Normal transfer mode 1 Break transmit mode Force parity and it will be effective when PEN bit is set. 0 Parity stuck is disabled 1 Parity stuck is enabled and parity always the bit of PARI TY. Parity mode selection bit and stuck parity select bit 0 Odd parity mode 1 Even parity mode Parity bit transfer enable 0 The parity bit disabled 1 The parity bit enabled The number of stop bit followed by data bits. 0 1 stop bit 1 1.5 / 2 stop bit In case of 5 bit data case, 1.5 stop bit is added. In cas e of 6,7 or 8 bit data, 2 stop bit is added The data length in one transfer word. 00 5 bit data 01 6 bit data 10 7 bit data 11 8 bit data Parity bit is generated according to bit 3, 4, 5 of UnLCR register. The following table shows the variation of parity bit generation. PS034404-0417 STICKP PARITY PEN Parity X X 0 No Parity 0 0 1 Odd Parity 0 1 1 Even Parity 1 0 1 Force parity as “1” 1 1 1 Force parity as “0” PRELIMINARY 115 Z32F0641 Product Specification Un.DCR UART UART Data Control Register The UART Data Control Register is an 8-bit register. U0.DCR=0x4000_8010, U1.DCR=0x4000_8110 7 0 PS034404-0417 6 5 0 0 4 LBON 3 RXINV 2 TXINV 4 3 2 LBON RXINV TXINV 0 0 0 RW RW 1 0 0 0 Local loopback test mode enable 0 Normal mode 1 Local loopback mode (TxD connected to RxD internally) Rx Data Inversion Selection 0 Normal RxData Input 1 Inverted RxData Input Tx Data Inversion Selection 0 Normal TxData Output 1 Inverted TxData Output PRELIMINARY 116 Z32F0641 Product Specification Un.LSR UART UART Line Status Register The UART Line Status Register is an 8-bit register. U0.LSR=0x4000_8014, U1.LSR=0x4000_8114 7 6 5 4 3 2 1 0 - TEMT THRE BI FE PE OE DR 0 1 1 0 0 0 0 0 R R R R R R R 6 TEMT 5 THRE 4 BI 3 FE 2 PE 1 OE 0 DR Transmit empty. 0 Transmit register has the data is now transferring 1 Transmit register is empty. Transmit holding empty. 0 Transmit holding register is not empty. 1 Transmit holding register empty Break condition indication bit 0 Normal status 1 Break condition is detected Frame Error. 0 No framing error. 1 Framing error. No valid stop bit in receive charact ert Parity Error 0 No parity error 1 Parity error. The receive character does not have correct parity information. Overrun error 0 No overrun error 1 Overrun error. Additional data arrives when the R HR is full Data received 0 No data in receive holding register. 1 Data received and saved in receive holding registe r This register provides the status of data transfers between the transmitter and receiver. Users can get the line status information from this register and handle the next process. Bits 1,2,3, and 4 will cause the line status Interrupt when RLSIE bit in UnIEN register is set. Other bits generate an interrupt when their interrupt enable bit in UnIEN register is set. PS034404-0417 PRELIMINARY 117 Z32F0641 Product Specification Un.BDR UART Baud Rate Divisor Latch Register The UART Baud Rate Divisor Latch Register is a 16-bit register. U0.BDR=0x4000_8020, U1.BDR=0x4000_8120 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDR 0x0000 RW 15 0 BDR Baud rate Divider latch value To establish communication with the UART channel, the baud rate should be set. The baud rate for the baud rate generator is determined using divider values from 1 to 65535 The 16 bit divider register (UnBDR) is written for desired baud rate.The baud rate calculation formula is shown below. BDR = 𝑈𝐴𝑅𝑇𝑃𝐶𝐿𝐾 32 × 𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒 For a speed of 48 MHz UART_PCLK, the divider value and error rate is described in table Table 12.5. Table 12.5 Example of Baud Rate Calculation (without BFR) UART_PCLK=48 MHz PS034404-0417 Baud Rate Divider Error (%) 1200 1250 0.00% 2400 625 0.00% 4800 312 0.16% 9600 156 0.16% 19200 78 0.16% 38400 39 0.16% 57600 26 0.16% 115200 13 0.16% PRELIMINARY 118 Z32F0641 Product Specification Un.BFR UART Baud Rate Fraction Counter Register The Baud Rate Fraction Counter Register is an 8-bit register. U0.BFR=0x4000_8024, U1.BFR=0x4000_8124 7 6 5 4 3 2 1 0 BFR 0x00 RW 7 0 BFR Fractions counter value. 0 Fraction counter is disabled N Fraction counter enabled. Fraction compensation m ode is operating. Fraction counter is incremented by FCNT. Table 12.6 Example of Baud Rate Calculation UART_PCLK=48 MHz Baud Rate Divider FCNT Error (%) 1200 1250 0 0.0% 2400 625 0 0.0% 4800 312 128 0.0% 9600 156 64 0.0% 19200 78 32 0.0% 38400 39 16 0.0% 57600 26 10 0.01% 115200 13 5 0.01% BFR = Float ∗ 256 The FCNT value can be calculated using the equation above. For example, if the target baud rate is 4800 bps and UART_PCLK is 48 MHz, the BDR value is 312.5. Using the integer 312 as the BDR value and the floating number 0.5, the FNCT value will be 128, as shown in the following calculation: FCNT = 0.5 * 256 = 128 The 8-bit fractional counter will count up by the BFR value every (baud rate)/16 periods and whenever the fractional counter overflows, the divisor value will increment by 1. Therefore, this period will be compensated. In the next period, the divisor value will return to the original set value. PS034404-0417 PRELIMINARY 119 Z32F0641 Product Specification Un.IDTR UART Inter-frame Delay Time Register The UART Inter-frame Time Register is an 8-bit register. A dummy delay can be inserted between two continuous transmits. U0.IDTR=0x4000_8030, U1.IDTR=0x4000_8130 7 6 5 4 3 2 1 0 0 0 WAITVAL 0 0 0 000 RW 2 0 WAITVAL Wait time is decided by this value 𝐖𝐚𝐢𝐭 𝐓𝐢𝐦𝐞 = PS034404-0417 PRELIMINARY 𝑾𝑨𝑰𝑻𝑽𝑨𝑳 𝑩𝑨𝑼𝑫𝑹𝑨𝑻𝑬 120 Z32F0641 Product Specification UART Functional Description General Operation The UART module is compatible with 16450 UART. Additionally, dedicated DMA channels and fractional baud rate compensation logic are provided. This UART module does not have an internal FIFO block. Therefore, data transfers are established either interactively or with DMA support. The DMA operation is described in this section. Two DMA channels are provided for each UART module – one channel is for TX transfer and the other one is for RX transfer. Each channel has a 32-bit memory address register and a 16-bit transfer counter register. Prior to DMA operation, the DMA Memory Address Register and the Transfer Count Register should be configured. For the RX operation, the memory address is the destination memory address and for the TX operation, the memory address is the source memory address. The transfer counter register stores the number count of transfer data. Each time a single transfer is done, the counter is decremented by 1. When the counter reaches zero, the DMA done flag is delivered to the UART control block. If the interrupt is enabled, this flag generates the interrupt. Receiver Sampling Timing The UARTs operates with the following timing. If the falling edge is on the receive line, the UART determines it to be the start bit. From the start timing, UART oversamples 16 times of 1-bit and detects the bit value at the 7th sample of 16 samples. START bit UnRXD STOP bit 0 1 0 0 0 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 0 1 0 Bit 6 Bit 7 Bit Samples Start bit Bit 5 Stop bit UnRXD SubSample 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Sampling Position (7/16) Figure 12.2. Sampling Timing of UART Receiver Note: Enable the debounce settings in the PCU block to reinforce the immunity of external glitch noise. PS034404-0417 PRELIMINARY 121 Z32F0641 Product Specification UART Transmitter The transmitter’s function is to transmit data transmit. The start bit, data bits, optional parity bit, and stop bit are serially shifted, with the least significant bit first. The number of data bits is selected in the DLAN[1:0] field in the Un.LCR register. The parity bit is set according to the PARITY and PEN bit field in the Un.LCR register. If the parity type is even, the parity bit depends on the one bit sum of all data bits. For odd parity, the parity bit is the inverted sum of all data bits. The number of stop bits is selected in the STOPBIT field in the Un.LCR register. An example of transmit data format is shown Figure 12.3. Transmit Data Format Example Inter-frame Delay Transmission The inter-frame delay function allows the transmitter to insert an idle state on the TXD line between two characters. The width of the idle state is defined in the WAITVAL field of the Un.IDTR register. When this field is set to 0, zero time-delay is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted character during the number of bit periods defined in the WATIVAL field. Figure 12.4. Inter-frame Delay Timing Diagram Transmit Interrupt The transmit operation generates interrupt flags. When the transmitter holding register is empty, the THRE interrupt flag will be set. When the transmitter shifter register is empty, the TXE interrupt flag will be set. Users can select the interrupt timing that is best for the application. PS034404-0417 PRELIMINARY 122 Z32F0641 Product Specification UART Figure 12.5. Transmit Interrupt Timing Diagram DMA Transfers The UART supports the DMA interface function. It is provided as an option, depending on the device. The start memory address for transfer data and the length of transfer data are programmed in the registers in the DMA block. The end of transfer is notified via the related transfer done flag. The Transmit with DMA operation invokes the DMA TX done flag DTX.UnIIR and sets the DMA TX done interrupt ID when all the transmit data are written to the transmit holding register.Two transmit data are remain in registers in the UART block after the DMA transfer done interrupt. The Receive with DMA operation invokes the RXT.UnIIR DMA RX done flag and sets the DMA RX done interrupt ID when all the receive data are written to the destination memory. Therefore, the UART RXD signal is already in IDLE state when the DMA RX done interrupt is issued. PS034404-0417 PRELIMINARY 123 Z32F0641 Product Specification Serial Peripheral Interface 13. Serial Peripheral Interface Overview One-channel serial Interface is provided for synchronous serial communications with external peripherals. The Serial Peripheral Interface (SPI) block supports both master and slave modes. Four signals are used for SPI communication – SS, SCK, MOSI, and MISO.        Master or Slave operation. Programmable clock polarity and phase. 8, 9, 16, 17-bit wide transmit/receive register. 8, 9, 16, 17-bit wide data frame. Loop-back mode. Programmable start, burst, and stop delay time. DMA transfer operation. Figure 13.1 SPI Block Diagram PS034404-0417 PRELIMINARY 124 Z32F0641 Product Specification Serial Peripheral Interface Pin Description Table 13.1 External Pins Pin Name Type Description SS0 I/O SPI0 Slave select input / output SCK0 I/O SPI0 Serial clock input / output MOSI0 I/O SPI0 Serial data ( Master output, Slave input ) MISO0 I/O SPI0 Serial data ( Master input, Slave output ) Registers The base address of SPI is 0x4000_9000 and the register map is described in Table 13.3. Table 13.2 SPI Base Address Name Base Address SPI0 0x4000_9000 Table 13.3 SPI Register Map SP0.TDR Name Offset Type Description Reset Value SP0.TDR 0x00 W SPI0 Transmit Data Register - SP0.RDR 0x00 R SPI0 Receive Data Register 0x000000 SP0.CR 0x04 RW SPI0 Control Register 0x001020 SP0.SR 0x08 RW SPI0 Status Register 0x000006 SP0.BR 0x0C RW SPI0 Baud rate Register 0x0000FF SP0.EN 0x10 RW SPI0 Enable register 0x000000 SP0.LR 0x14 RW SPI0 delay Length Register 0x010101 SPI Transmit Data Register SP0.TDR is a 17-bit read/write register. It contains serial transmit data. SP0.TDR=0x4000_9000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 RW 16 0 PS034404-0417 TDR Transmit Data Register PRELIMINARY 125 Z32F0641 Product Specification SP0.RDR Serial Peripheral Interface SPI Receive Data Register SP0.RDR is a 17-bit read/write register. It contains serial receive data. SP0.RDR=0x4000_9000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 RW 16 0 RDR SP0.CR Receive Data Register SPI Control Register SP0.CR is a 20-bit read/write register which can be set to configure SPI operation mode. SP0.CR=0x4000_9004 20 19 18 17 16 15 14 13 PS034404-0417 TXBC RXBC TXDIE RXDIE SSCIE TXIE RXIE SSMOD 0 0 0 RW RW RW RW RW RW 0 0 BITSZ 0 1 0 0 0 00 RW 1 0 CPOL 0 1 RW 0 2 CPHA SSPOL 0 3 RW SSMO 0 4 MSBF LBE SSMASK 0 5 RW SSOUT 0 6 MS SSMOD 0 0 7 RW RXIE 0 RW 0 TXIE 0 SSCIE 0 RW 0 RW 0 RXDIE 0 RW 0 RW 0 TXBC 0 RW 0 TXDIE 8 RW 9 RXBC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Tx buffer clear bit. 0 No action 1 Clear Tx buffer Rx buffer clear bit 0 No action 1 Clear Rx buffer DMA Tx Done Interrupt Enable bit. 0 DMA Tx Done Interrupt is disabled. 1 DMA Tx Done Interrupt is enabled. DMA Rx Done Interrupt Enable bit. 0 DMA Rx Done Interrupt is disabled. 1 DMA Rx Done Interrupt is enabled. SS Edge Change Interrupt Enable bit. 0 nSS interrupt is disabled. 1 nSS interrupt is enabled for both edges (LH, HL) Transmit Interrupt Enable bit. 0 Transmit Interrupt is disabled. 1 Transmit Interrupt is enabled. Receive Interrupt Enable bit.. 0 Receive Interrupt is disabled. 1 Receive Interrupt is enabled. SS Auto/Manual output select bit. PRELIMINARY 126 Z32F0641 Product Specification 0 1 12 11 10 SSOUT LBE SSMASK Serial Peripheral Interface SS output is not set by SSOUT (SPnCR[12]). SS signal is in normal operation mode. SS output signal is set by SSOUT. SS output signal select bit. 0 SS output is ‘L.’ 1 SS output is ‘H’. Loop-back mode select bit in master mode. 0 Loop-back mode is disabled. 1 Loop-back mode is enabled. SS signal masking bit in slave mode. 0 9 8 SSMO SSPOL 7 6 5 4 3 2 1 0 SS signal masking is disabled. Receive data when SS signal is active. 1 SS signal masking is enabled. Receive data at SCLK edges. SS signal is ignored. SS output signal select bit. 0 SS output signal is disabled. 1 SS output signal is enabled. SS signal Polarity select bit. 0 SS signal is Active-Low. 1 SS signal is Active-High. Reserved MS MSBF CPHA CPOL BITSZ Master/Slave select bit. 0 SPI is in Slave mode. 1 SPI is in Master mode. MSB/LSB Transmit select bit. 0 LSB is transferred first. 1 MSB is transferred first. SPI Clock Phase bit. 0 Sampling of data occurs at odd edges (1,3,5,…,15). 1 Sampling of data occurs at even edges (2,4,6,…,16). SPI Clock Polarity bit. 0 Active-high clocks selected. 1 Active-low clocks selected. Transmit/Receive Data Bits select bit. 00 8 bits 01 9 bits 10 16 bits 11 17 bits CPOL=0, CPHA=0 : data sampling at rising edge, data changing at falling edge CPOL=0, CPHA=1 : data sampling at falling edge, data changing at rising edge CPOL=1, CPHA=0 : data sampling at falling edge, data changing at rising edge CPOL=1, CPHA=1 : data sampling at rising edge, data changing at falling edge PS034404-0417 PRELIMINARY 127 Z32F0641 Product Specification SP0.SR Serial Peripheral Interface SPI Status Register SP0.SR is a 10-bit read/write register. It contains the status of the SPI. SP0.SR=0x4000_9008 0 0 0 9 8 TXDMAF RXDMAF 7 6 5 4 3 2 1 0 0 0 RC1 RC1 5 4 3 2 1 0 0 0 0 0 1 1 0 RC1 RC1 RC1 RC1 R R R 0 DMA Transmit Operation Complete flag. (DMA to SPI) 0 DMA Transmit Op is working or is disabled. 1 DMA Transmit Op is done. DMA Receive Operation Complete flag. (SPI to DMA ) 0 DMA Receive Operation is working or is disabled. 1 DMA Transmit Op is done. Reserved SSDET SSON OVRF UDRF TXIDLE TRDY RRDY The rising or falling edge of SS signal Detect flag. 0 SS edge is not detected. 1 SS edge is detected. The bit is cleared when it is written as “0”. SS signal Status flag. 0 SS signal is inactive. 1 SS signal is active. Receive Overrun Error flag. 0 Receive Overrun error is not detected. 1 Receive Overrun error is detected. This bit is cleared by writing or reading SPnRDR. Transmit Underrun Error flag. 0 Transmit Underrun is not occurred. 1 Transmit Underrun is occurred. This bit is cleared by writing or reading SPnTDR. Transmit/Receive Operation flag. 0 SPI is transmitting data 1 SPI is in IDLE state. Transmit buffer Empty flag. 0 Transmit buffer is busy. 1 Transmit buffer is ready. This bit is cleared by writing data to SPnTDR. Receive buffer Ready flag. 0 Receive buffer has no data. 1 Receive buffer has data. - PS034404-0417 6 RRDY 0 7 TRDY 0 8 TXIDLE 0 9 UDRF 10 OVRF 11 SSON 12 SSDET 13 RXDMAF 14 TXDMAF 15 This bit is cleared by writing data to SPnRDR. PRELIMINARY 128 Z32F0641 Product Specification SP0.BR Serial Peripheral Interface SPI Baud Rate Register SP0.BR is a16-bit read/write register. Baud rate is set by writing the register. SP0.BR=0x4000_900C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR 0x00FF RW 15 BR Baud rate setting bits Baud Rate = PCLK / (BR + 1) (BR must be bigger than “0”, BR >= 2 ) 0 SP0.EN SPI Enable Register SP0.EN is a bit read/write register. It contains the SPI enable bit. SP0.EN=0x4000_9010 7 6 5 4 3 2 1 0 ENABLE 0 0 0 0 0 0 0 0 RW 0 ENABLE SPI Enable bit 0 1 - SPI is disabled. SPnSR is initialized by writing “0” to this bit but other registers ar en’t initialized. SPI is enabled. When this bit is written as “1”, the dummy data of transmit buffer will be shifted. To prevent this, write data to SPTDR before this b it is active. Note: When in SPI Slave mode, ensure that you disable the SPI prior to loading the TDR register, then enable it to prevent an extra byte from being sent. PS034404-0417 PRELIMINARY 129 Z32F0641 Product Specification SP0.LR Serial Peripheral Interface SPI Delay Length Register SP0.LR is a 24-bit read/write register. It contains start, burst, and stop length value. SP0.LR=0x4000_9014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 0 23 0 SPL 15 BTL 7 0 STL 7 6 5 4 3 BTL STL 0x01 0x01 0x01 RW RW RW 2 1 0 StoPLength value (SPL ≥ 1) BursTLength value 0x01 ~ 0xFF : 1 ~ 255 SCLKs. 8 8 SPL 0x01 ~ 0xFF : 1 ~ 255 SCLKs. 16 9 (BTL ≥ 1) STart Length value 0x01 ~ 0xFF : 1 ~ 255 SCLKs. (STL ≥ 1) Figure 13.2 SPI Waveform (STL, BTL and SPL) PS034404-0417 PRELIMINARY 130 Z32F0641 Product Specification Serial Peripheral Interface Functional Description The SPI Transmit block and Receive block share the Clock Gen Block; however, they are independent of each other. The Transmit and Receive blocks contain double buffers and SPI is available for back to back transfer operation. SPI Timing The SPI has four modes of operation. These modes essentially control the way data is clocked in or out of an SPI device. The configuration is done by two bits in the SPI control register (SPnCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock. The clock phase (CPHA) control bit selects one of the two fundamentally different transfer formats. To ensure proper communication between master and slave, both devices must run in the same mode. This may require a reconfiguration of the master to match the requirements of different peripheral slaves. The clock polarity has no significant effect on the transfer format. Switching this bit causes the clock signal to be inverted (active high becomes active low and idle low becomes idle high). The settings of the clock phase, however, select one of the two different transfer timings, which are described in detail in the following two chapters. Because the MOSI and MISO lines of the master and the slave are directly connected to each other, the diagrams show the timing of both devices. The nSS line is the slave select input of the slave. The nSS pin of the master is not shown in the diagrams. It has to be inactive by a high level on this pin (if configured as input pin) or by configuring it as an output pin. The timing of a SPI transfer where CPHA is zero is shown in Figure 13.3 and Figure 13.4. Two wave forms are shown for the SCK signal: one for CPOL equals zero and another for CPOL equals one. When the SPI is configured as a slave, the transmission starts with the falling edge of the /SS line. This activates the SPI of the slave and the MSB of the byte stored in its data register (SPnTDR) is output on the MISO line. The actual transfer is started by a software write to the SPnTDR of the master. This causes the clock signal to be generated. In cases where the CPHA equals zero, the SCLK signal remains zero for the first half of the first SCLK cycle. This ensures that the data is stable on the input lines of both the master and the slave. The data on the input lines is read with the edge of the SCLK line from its inactive to its active. The edge of the SCLK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL equals one) causes the data to be shifted one bit further so that the next bit is output on the MOSI and MISO lines. SCK MOSI D0 D1 D2 D3 D4 D5 D6 D7 MISO D0 D1 D2 D3 D4 D5 D6 D7 Figure 13.3 Transfer Timing 1/4 (CPHA=0, CPOL=0, MSBF=0) PS034404-0417 PRELIMINARY 131 Z32F0641 Product Specification Serial Peripheral Interface SS SCK MOSI D7 D6 D5 D4 D3 D2 D1 D0 MISO D7 D6 D5 D4 D3 D2 D1 D0 Figure 13.4 SPI Transfer Timing 2/4 (CPHA=0, CPOL=1, MSBF=1) The timing of a SPI transfer where CPHA is one is shown in Figure 13.5 and Figure 13.6. Two wave forms are shown for the SCLK signal -one for CPOL equals zero and another for CPOL equals one. Similar to the previous cases, the falling edge of the nSS lines selects and activates the slave. Compared to the previous cases, where CPHA equals zero, the transmission is not started and the MSB is not output by the slave at this stage. The actual transfer is started by a software write to the SPnTDR of the master which causes the clock signal to be generated. The first edge of the SCLK signal from its inactive to its active state (rising edge if CPOL equals zero and falling edge if CPOL equals one) causes both the master and the slave to output the MSB of the byte in the SPnTDR. As shown in Figure 13.3 and Figure 13.4, there is no delay of half a SCLK-cycle. The SCLK line changes its level immediately at the beginning of the first SCLK-cycle. The data on the input lines is read with the edge of the SCLK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL equals one). After eight clock pulses, the transmission is completed. PS034404-0417 PRELIMINARY 132 Z32F0641 Product Specification Serial Peripheral Interface SS SCKSS MOSI D0 D1 D2 D3 D4 D5 D6 D7 MISO D0 D1 D2 D3 D4 D5 D6 D7 Figure 13.5 SPI Transfer Timing 3/4 (CPHA=1, CPOL=0, MSBF=0) SS SCK MOSI D7 D6 D5 D4 D3 D2 D1 D0 MISO D7 D6 D5 D4 D3 D2 D1 D0 Figure 13.6 SPI transfer Timing 4/4 (CPHA=1, CPOL=1, MSBF=1) PS034404-0417 PRELIMINARY 133 Z32F0641 Product Specification Serial Peripheral Interface DMA Handshake SPI supports the DMA handshaking operation. In order to operate a DMA handshake, DMA registers should first be set. (Refer to Chapter 6, Direct Memory Access Controller). As the transmitter and receiver are independent of each other, SPI can operate the two channels at the same time. After the DMA channel for the receiver is enabled and the receive buffer is filled, SPI sends an Rx request to the DMA to empty the buffer and waits for an ACK signal from DMA. If the Receive buffer is filled again after the ACK signal, SPI sends an Rx request. If DMA Rx DONE becomes high, RXDMAF (SPnSR[8]) becomes 1 and an interrupt is serviced when RXDIE (SPnCR[17]) is set. Similarly, if the transmit buffer is empty after the DMA channel for the transmitter is enabled, SPI sends a Tx request to the DMA to fill the buffer and waits for an ACK signal from DMA. If the transmit buffer is empty again after the ACK signal, SPI sends a Tx request. If DMA Tx DONE becomes high, TXDMAF(SPnSR[9]) becomes 1 and an interrupt is serviced when TXDIE(SPnCR[18]) is set. The slave transmitter sends dummy data at the first transfer (8~17 SCLKs) in DMA handshake mode. Figure 13.7 DMA Handshake Flow Chart PS034404-0417 PRELIMINARY 134 Z32F0641 Product Specification I2C Interface 14. I2C Interface Overview Inter-Integrated Circuit (I2C) bus serves as an interface between the microcontroller and the serial I2C bus. It provides two wires, serial bus interface to a large number of popular devices and allows parallel-bus systems to communicate bidirectionally with the I2C-bus.         Master and slave operation Programmable communication speed Multi-master bus configuration 7-bit addressing mode Standard data rate of 100/400 kbps STOP signal generation and detection START signal generation ACK bit generation and detection Debounce Slave Addr. Register1 enable SDA Noise Canceller (debounce ) (I2CSAR1) SDAIN 1 F/F 0 SDAOU T SDA Out Controller Debounce enable SCL Noise Canceller (debounce ) 8-bit Shift Register (SHFTR) SCLI N 1 SCL Out Controller 0 Data Out Register (I2CDR) SCL High Period Register (I2CSCLHR) SCL Low Period Register (I2CSCLLR) SDAHoldTimeRegister (I2CDAHR) I n t e r n a l B u s L i n e SCLOU T Figure 14.1 I2C Block Diagram PS034404-0417 PRELIMINARY 135 Z32F0641 Product Specification I2C Interface Pin Description Table 14.1 I2C Interface External Pins Pin Name Type Description SCL0 I/O I2C channel 0 Serial clock bus line (open-drain) SDA0 I/O I2C channel 0 Serial data bus line (open-drain) Registers The base address of I2C0 is 0x4000_A000. The register map is described in Table 14.3. Table 14.2 I2C Interface Base Address Name Base Address 2 I C0 0x4000_A000 Table 14.3 I2C Register Map PS034404-0417 Name Offset Type Description Reset Value ICn.DR 0x00 RW I2C0 Data Register 0xFF 2 ICn.SR 0x08 R, RW I C0 Status Register 0x00 ICn.SAR 0x0C RW I2C0 Slave Address Register 0x00 2 ICn.CR 0x14 RW I C0 Control Register 0x00 ICn.SCLL 0x18 RW I2C0 SCL LOW duration Register 0xFFFF 2 ICn.SCLH 0x1C RW I C0 SCL HIGH duration Register 0xFFFF ICn.SDH 0x20 RW I2C0 SDA Hold Register 0x7F PRELIMINARY 136 Z32F0641 Product Specification ICn.DR I2C Interface I2C Data Register ICn.DR is an 8-bit read/write register. It contains a byte of serial data to be transmitted or a byte which has just been received. IC0.DR=0x4000_A000 7 6 5 4 3 2 1 0 DR 0xFF RW 7 0 ICn.SR DR The most recently received data or data to be transmitted. I2C Status Register 2 ICn.SR is an 8-bit read/write register. It contains the status of I C bus interface. Writing to the register clears the status bits except for IMASTER. IC0.SR=0x4000_A008 7 6 5 4 3 2 1 0 GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW 7 6 5 4 3 2 1 0 PS034404-0417 GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK General call flag 0 General call is not detected. 1 General call detected or slave address (ID byte) was sent. 1 Byte transmission complete flag 0 The transmission is working or not completed. 1 The transmission is completed. STOP flag 0 STOP is not detected. 1 STOP is detected. Slave flag 0 Slave is not selected. 1 Slave is selected. Mastership lost flag 0 Mastership is not lost. 1 Mastership is lost. BUSY flag 0 I2C bus is in IDLE state. 1 I2C bus is busy. Transmitter/Receiver mode flag 0 Receiver mode. 1 Transmitter mode. Rx ACK flag 0 Rx ACK is not received. 1 Rx ACK is received. PRELIMINARY 137 Z32F0641 Product Specification I2C Interface I2C Slave Address Register ICn.SAR ICn.SAR is an 8-bit read/write register. It shows the address in Slave Mode. IC0.SAR=0x4000_A00C 7 6 5 4 3 2 1 0 SVAD GCEN 0x00 0 RW RW 7 1 SVAD 7-bit Slave Address 0 GCEN General call enable bit 0 General call is disabled. 1 General call is enabled. I2C Control Register ICn.CR ICn.CR is an 8-bits read/write register. The register can be set to configure I2C operation mode and simultaneously allowed for I2C transactions to be kicked off. IC0.CR=0x4000_A014 0 0 0 0 0 9 8 7 5 4 3 1 INTDEL IIF SOFTRST INTEN ACKEN STOP 7 00 0 RW R 6 5 4 3 0 0 0 RW RW RW 0 2 0 1 0 0 0 RW RW Interval delay value between address and data transfer (or DATA and DATA) 0 1 * ICnSCLL 1 2 * ICnSCLL 2 4 * ICnSCLL 3 8 * ICnSCLL Interrupt status bit 0 Interrupt is inactive 1 Interrupt is active Soft Reset enable bit. 0 Soft Reset is disabled. 1 Soft Reset is enabled.. Interrupt enabled bit. 0 Interrupt is disabled. 1 Interrupt is enabled. ACK enable bit in Receiver mode. 0 ACK is not sent after receiving data. 1 ACK is sent after receiving data. Stop enable bit. When this bit is set as “1” in transmitter mode, next transmission will be stopped even though ACK signal has been received. 0 PS034404-0417 8 START 0 9 STOP 10 ACKEN 11 INTEN 12 SOFTRST 13 IIF 14 INTDEL 15 Stop is disabled. PRELIMINARY 138 Z32F0641 Product Specification 1 0 START I2C Interface Stop is enabled. When this bit is set, transmission will be stopped. Transmission start bit in master mode. 0 Waits in slave mode. 1 Starts transmission in master mode. Figure 14.2 INTDEL in Master Mode ICn.SCLL I2C SCL LOW Duration Register ICnSCLL is a 16-bit read/write register. SCL LOW time can be set by writing this register in Master Mode. IC0.SDLL=0x4000_A018 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLL 0xFFFF RW 15 0 SCLL SCL LOW duration value. SCLL = ( PCLK * SCLL[15:0] ) + 2*PCLKs Default value is 0xFFFF. Figure 14.3 SCL LOW Timing PS034404-0417 PRELIMINARY 139 Z32F0641 Product Specification ICn.SCLH I2C Interface I2C SCL HIGH Duration Register ICnSCLH is a 16-bit read/write register. SCL HIGH time will be set by writing this register in Master Mode. IC0.SDLH=0x4000_A01C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLH 0xFFFF RW 15 SCLH 0 SCL HIGH duration value. SCLH = ( PCLK * SCLH[15:0] ) + 3 PCLKs Default value is 0xFFFF. Figure 14.4 SCL LOW Timing ICn.SDH SDA Hold Register ICnSDH is a 15-bit read/write register. SDA HOLD time is set by writing this register in Master Mode. IC0.SDH=0x4000_A020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDH 0x3FFF RW 14 0 PS034404-0417 SDH SDA HOLD time setting value. SDH = ( PCLK * SDH[14:0] ) + 4 PCLKs Default value is 0x3FFF. PRELIMINARY 140 Z32F0641 Product Specification I2C Interface Figure 14.5 SDA HOLD Timing PS034404-0417 PRELIMINARY 141 Z32F0641 Product Specification I2C Interface Functional Description I2C Bit Transfer The data on the SDA line must be stable during the “H” period of the clock. The “H” or “L” state of the data line can only change when the clock signal on the SCL line is “L”; see Figure 14.6. SDA SCL Figure 14.6 I2C Bus Bit Transfer PS034404-0417 PRELIMINARY 142 Z32F0641 Product Specification I2C Interface START/Repeated START/STOP Within the procedure of the I2C-bus, unique situations arise which are defined as START(S) and STOP(P) conditions; see Figure 14.7. An “H” to “L” transition on the SDA line while SCL is “H” is one such unique case. This situation indicates a START condition. An “L” to “H” transition on the SDA line while SCL is “H” defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus is busy if a repeated START(Sr) is generated instead of a STOP condition. In this respect, the START(S) and repeated START(Sr) conditions are functionally identical. For the remainder of this document therefore, the S symbol will be used as a generic term to represent both the START and repeated START conditions, unless Sr is particularly relevant. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition. SDA SCL S P START Condition STOP Condition Figure 14.7 START and STOP Condition PS034404-0417 PRELIMINARY 143 Z32F0641 Product Specification I2C Interface Data Transfer Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first; see Figure 14.8. If a slave can’t receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL “L” to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL. A message which starts with such an address can be terminated by generation of a STOP condition, even during the transmission of a byte. In this case, no acknowledgement is generated. P SDA MSB Acknowledgemen Acknowledgement t Signal from Signal from Slave Byte Complete, Clock line held low Slave SCL S Interrupt Device 1 or within 9 ACK while served. 1 interrupts 9 ACK Sr Sr are Sr or P STOP or Repeated START Condition START or Repeated START Condition Figure 14.8 I2C Bus Data Transfer PS034404-0417 PRELIMINARY 144 Z32F0641 Product Specification I2C Interface Acknowledge Data transfer with acknowledgement is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable “L” during the “H” period of this clock pulse; see Figure 14.9. Set-up and hold times must also be taken into account. When a slave doesn’t acknowledge the slave address (for example, it’s unable to receive or transmit because it’s performing some real-time function), the data line must be left “H” by the slave. The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a slave-receiver acknowledges the slave address but cannot receive any more data bytes later during the transfer, the master must again abort the transfer. This is indicated by the slave generating the notacknowledge on the first byte to follow. The slave leaves the data line “H” and the master generates a STOP or a repeated START condition. If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line to allow the master to generate a STOP or repeated START condition. Data Output By Transmitter NAC K Data Output By Receiver SCL MASTER From 1 2 8 AC K 9 Clock ACK pulse for Figure 14.9 I2C Bus Acknowledgement PS034404-0417 PRELIMINARY 145 Z32F0641 Product Specification I2C Interface Synchronization All masters generate their own clock on the SCL line to transfer messages on the I2C-bus. Data is only valid during the “H” period of the clock. A defined clock is therefore needed for the bit-by-bit arbitration procedure to take place. Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that an “H” to “L” transition on the SCL line will cause the devices concerned to start counting off their “L” period and, once a device clock has gone “L”, it will hold the SCL line in that state until the clock “H” state is reached; see Figure 14.10. However, the “L” to “H” transition of this clock may not change the state of the SCL line if another clock is still within its “L” by the device with the longest “L” period. Devices with shorter “L” periods enter an “H” wait-state during this time. When all devices concerned have counted off their “L” period, the clock line will be released and go “H”. There will then be no difference between the device clocks and the state of the SCL line, and the devices will start counting their “H” periods. The first device to complete its “H” period will again pull the SCL line “L”. Wait High Counting Fast Device SCLOUT Slow Device SCLOUT Start High Counting High Counter Reset SCL Figure 14.10 Clock Synchronization During the Arbitration Procedure PS034404-0417 PRELIMINARY 146 Z32F0641 Product Specification I2C Interface Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time of the START condition which results in a defined START condition to the bus. Arbitration takes place on the SDA line, while the SCL line is at the “H” level, in such a way that the master which transmits “H” level, while another master is transmitting “L” level will switch off its DATA output stage because the level on the bus doesn’t correspond to its own level. Arbitration can continue for many bits. Its first stage is comparison of the address bits. If the masters are each trying to address the same device, arbitration continues with comparison of the data-bits if they are mastertransmitter or acknowledge-bits if they are master-receiver. Because address and data information on the I2Cbus is determined by the winning master, no information is lost during the arbitration process. A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration. If a master also incorporates a slave function and it loses arbitration during the addressing stage, it’s possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave mode. Figure 14.11 shows the arbitration procedure for two masters. Of course, more may be involved (depending on how many masters are connected to the bus). As soon as there is a difference between the internal data level of the master generating Device1 Dataout and the actual level on the SDA line, its data output is switched off, which means that a “H” output level is then connected to the bus. This will not affect the data transfer initiated by the winning master. Arbitration adapted Process not Device Arbitration 1 loses Device1 outputs High Device1 DataOut Device2 DataOut SDA on BUS SCL on BUS S Figure 14.11 Arbitration Procedure Between Two Masters PS034404-0417 PRELIMINARY 147 Z32F0641 Product Specification I2C Interface I2C Operation I2C supports the interrupt operation. After interrupt is serviced, IIF(ICnSR[10]) flag is set. ICnSR shows I2Cbus status information and SCL line stays “L” before the register is written as a certain value. The status register can be cleared by writing a zero. Master Transmitter The master transmitter shows the flow of the transmitter in Master Mode (see Figure 14.12). Master Receiver SLA+R S or Sr SLA+W ACK N STOP P Y LOST DATA ACK Rs N STOP LOST Cont? Lost? LOST& STOP Y Y LOST P Other master continues From master to slave / Master command or Data Write Y N From slave to master STOP ACK Interrupt, SCL line is held low P Interrupt after stop command P LOST & Arbitration lost as master and addressed as slave Figure 14.12 Transmitter Flowchart in Master Mode PS034404-0417 PRELIMINARY 148 Z32F0641 Product Specification I2C Interface Master Receiver The master receiver shows the flow of the receiver in Master Mode (see Figure 14.13). IDLEIDLE Master Transmitter S or SrData SLA+W Chang e of Data allowed line Stable: SLA+R Data valid exept S, Sr, P ACK N STOP P Y LOST DATA Rs LOST LOST& Sr ACK N STOP P Y LOST From master to slave / Master command or Data Addr. Register FromWrite slaveSlave to master (I2CSAR) Other master continues ACK Interrupt, SCL line is held low ACK P LOST & Interrupt after stop command Arbitration lost as master and addressed as slave Figure 14.13 Receiver Flowchart in Master Mode PS034404-0417 PRELIMINARY 149 Z32F0641 Product Specification I2C Interface Slave Transmitter The slave transmitter shows the flow of the transmitter in Slave Mode (see Figure 14.14). IDLE S or Sr SLA+R GCALL ACK LOST& Y DATA Y N ACK STOP P Y IDLE From master to slave / Master command or Data Write From slave to master ACK Interrupt, SCL line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave GCALL General Call Address Figure 14.14 Transmitter Flowchart in Slave Mode PS034404-0417 PRELIMINARY 150 Z32F0641 Product Specification I2C Interface Slave Receiver The slave receiver shows the flow of the receiver in Slave Mode (see Figure 14.15). IDLE S or Sr SLA+W ACK LOST& GCALL N Y DATA Y ACK N STOP P Y IDLE From master to slave / Master command or Data Write From slave to master ACK Interrupt, SCL line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave GCALL General Call Address Figure 14.15 Receiver Flowchart in Slave Mode PS034404-0417 PRELIMINARY 151 Z32F0641 Product Specification Motor Pulse Width Modulator 15. Motor Pulse Width Modulator Introduction The Motor Pulse Width Modulator (MPWM) is a 16-bit programmable motor controller with the following features:        6-channel outputs for motor control 16-bit counter Dead-time supports Protection event and over voltage event handling 6 ADC trigger outputs Interval interrupt mode Up-down count mode Figure 15.1 Block Diagram PS034404-0417 PRELIMINARY 152 Z32F0641 Product Specification Motor Pulse Width Modulator Pin Description Table 15.1 External Signals Pin Name Type Description MP0UH O MPWM 0 Phase-U H-side output MP0UL O MPWM 0 Phase-U L-side output MP0VH O MPWM 0 Phase-V H-side output MP0VL O MPWM 0 Phase-V L-side output MP0WH O MPWM 0 Phase-W H-side output MP0WL O MPWM 0 Phase-W L-side output PRTIN0 I MPWM 0 Protection Input OVIN0 I MPWM 0 Over-voltage Input Registers The base address of MPWM is 0x4000_4000. Table 15.2 shows the register memory map. Table 15.2 MPWM Register Map Name Offset Type Description Reset Value MP0.MR 0x0000 RW MPWM Mode register 0x0000_0000 MP0.OLR 0x0004 RW MPWM Output Level register 0x0000_0000 MP0.FOLR 0x0008 RW MPWM Force Output register 0x0000_0000 MP0.PRD 0x000C RW MPWM Period register 0x0000_0002 MP0.DUH 0x0010 RW MPWM Duty UH register 0x0000_0001 MP0.DVH 0x0014 RW MPWM Duty VH register 0x0000_0001 MP0.DWH 0x0018 RW MPWM Duty WH register 0x0000_0001 MP0.DUL 0x001C RW MPWM Duty UL register 0x0000_0001 MP0.DVL 0x0020 RW MPWM Duty VL register 0x0000_0001 MP0.DWL 0x0024 RW MPWM Duty WL register 0x0000_0001 MP0.CR1 0x0028 RW MPWM Control register 1 0x0000_0000 MP0.CR2 0x002C RW MPWM Control register 2 0x0000_0000 MP0.SR 0x0030 R MPWM Status register 0x0000_0000 MP0.IER 0x0034 RW MPWM Interrupt Enable 0x0000_0000 MP0.CNT 0x0038 R MPWM counter register 0x0000_0001 MP0.DTR 0x003C RW MPWM dead time control 0x0000_0000 MP0.PCR0 0x0040 RW MPWM protection 0 control register 0x0000_0000 MP0.PSR0 0x0044 RW MPWM protection 0 status register 0x0000_0080 MP0.PCR1 0x0048 RW MPWM protection 1 control register 0x0000_0000 MP0.PSR1 0x004C RW MPWM protection 1 status register 0x0000_0000 - 0x0054 - Reserved - MP0.ATR1 0x0058 RW MPWM ADC Trigger reg1 0x0000_0000 MP0.ATR2 0x005C RW MPWM ADC Trigger reg2 0x0000_0000 MP0.ATR3 0x0060 RW MPWM ADC Trigger reg3 0x0000_0000 MP0.ATR4 0x0064 RW MPWM ADC Trigger reg4 0x0000_0000 MP0.ATR5 0x0068 RW MPWM ADC Trigger reg5 0x0000_0000 MP0.ATR6 0x006C RW MPWM ADC Trigger reg6 0x0000_0000 PS034404-0417 PRELIMINARY 153 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.MR MPWM Mode Register The PWM Operation Mode register is a 16-bit register. MP0.MR=0x4000_4000 9 8 7 6 5 4 3 2 1 0 UPDOWN 10 MCHMOD 11 BUP 12 TUP 13 UAO 14 MOTORB 15 0 0 0 0 00 0 RW RW RW RW RW RW 15 7 5 4 2 1 0 MOTORB UAO TUP BUP MCHMOD UPDOWN 0 Motor mode 1 Normal mode 0 Update will be executed at designated timing. 1 Update all duty, period register at once. When UPDATE set, Duty and Period registers are updated after two PWM clocks 0 Period, duty values are not updated at every period match. 1 Period, duty values are updated at every period match. 0 Period, duty values are not updated at every bottom match 1 Period, duty values are updated at every bottom match 00 2 channels symmetric mode Duty H decides toggle high/low time of H-ch Duty L decides toggle high/low time of L-ch 01 1 channel asymmetric mode Duty H decides toggle high time of H-ch Duty L decides toggle low time of H-ch L channel become the inversion of H channel 10 1 channel symmetric mode Duty H decides toggle high/low time of H-ch L channel become the inversion of H channel 11 Not valid (same with 00) 0 PWM Up count mode (only available when MOTORB=’1’) 1 PWM Up/Down count mode (This bit should be ‘1’ if MOTORB=’0’) After initial PWM period and duty setting is completed, the UAO bit should be set once for updating the setting value into the internal operating registers. This action will help to transfer the setting data from the user interface register to the internal operating register. The UAO bit should stay at set state for at least 2-PWM clock periods. Otherwise, the update command can be missed and the internal registers will keep the previous data. MCHMOD in the MP0.MR field is only effective when MOTORB in MP0.MR is a clear “0”. Otherwise, the MCHMOD field value will be ignored internally and will retain a “00” value. UPDOWN in the MP0.MR field is only effective when MOTORB in MP0.MR is set to “1”. Otherwise, the UPDOWN field value will be ignored internally and will retain a “1” value. In the motor mode, the counter is always an up-down count operation. PS034404-0417 PRELIMINARY 154 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.OLR MPWM Output Level Register The PWM Port Mode register is a 16-bit register. MP0.OLR=0x4000_4004 7 6 0 0 5 4 3 2 1 0 5 4 3 2 1 0 WHL VHL UHL WLL VLL ULL 0 0 0 0 0 0 RW RW RW RW RW RW WHL VHL UHL WLL VLL ULL 0 Default Level 1 Inverted Level 0 Default Level 1 Inverted Level 0 Default Level 1 Inverted Level 0 Default Level 1 Inverted Level 0 Default Level 1 Inverted Level 0 Default Level 1 Inverted Level The normal level is defined in each operating mode as shown in Table 15.3. Table 15.3. MPWM Register Map PWM Output WH WL VH VL UH UL Level NORMAL mode MOTOR mode UP mode UPDOWN mode Default level LOW HIGH LOW Active level HIGH LOW HIGH Default level LOW LOW HIGH Active level HIGH HIGH LOW Default level LOW HIGH LOW Active level HIGH LOW HIGH Default level LOW LOW HIGH Active level HIGH HIGH LOW Default level LOW HIGH LOW Active level HIGH LOW HIGH Default level LOW LOW HIGH Active level HIGH HIGH LOW The polarity control block is shown in Figure 15.2. The example shown is for WH signal polarity control. PS034404-0417 PRELIMINARY 155 Motor Pulse Width Modulator Z32F0641 Product Specification Figure 15.2. Polarity Control Block MP0.FOLR MPWM Force Output Level Register The PWM Force Output register is an 8-bit register. The PWM output level can be forced by an abnormal event occurring externally or from a user-intended condition. When the forced condition occurs, each PWM output level which is programmed in the FOLR register will be forced. MP0.FOLR=0x4000_4008 7 0 6 0 5 5 4 3 2 1 0 WHFL VHFL UHFL WLFL VLFL ULFL 0 0 0 0 0 0 RW RW RW RW RW RW WHFL Select WH Output Force Level 0 1 4 VHFL Select VH Output Force Level 0 1 3 UHFL WLFL VLFL ULFL Output Force Level is ‘L’ Output Force Level is ‘H’ Select UL Output Force Level 0 1 PS034404-0417 Output Force Level is ‘L’ Output Force Level is ‘H’ Select VL Output Force Level 0 1 0 Output Force Level is ‘L’ Output Force Level is ‘H’ Select WL Output Force Level 0 1 1 Output Force Level is ‘L’ Output Force Level is ‘H’ Select UH Output Force Level 0 1 2 Output Force Level is ‘L’ Output Force Level is ‘H’ Output Force Level is ‘L’ Output Force Level is ‘H’ PRELIMINARY 156 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.CR1 MPWM Control Register 1 The PWM Control Register 1 is a 16-bit register. MP0.CR1=0x4000_4028 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PWMEN 14 IRQN 15 000 0 RW RW 10 8 IRQN IRQ interval number (Every 1~8th PRDIRQ,BOTIRQ,ATRn) 0 PWMEN PWM enable When this bit set 0, the PWM block stay in reset state but user interface can be accessed. To operate the PWM block, this bit should be set 1. Basically, PRDIRQ and BOTIRQ are generated every period. However, the interrupt interval can be controlled from 0 to 8 periods. When IRQN.CR1 = 0, the interrupt is requested every period; otherwise, the interrupt is requested every (IRQN+1) times of period. MP0.CR2 MPWM Control Register 2 The PWM Control Register 2 is an 8-bit register. MP0.CR2=0x4000_402C 7 6 5 4 3 2 1 HALT 0 0 PSTART 0 0 0 0 0 0 RW 0 RW 7 HALT PWM HALT (PWM counter stop but not reset) PWM outputs keep previous state 0 PSTART 0 PWM counter stop and clear 1 PWM counter start (will be resynced @PWM clock twice) PWMEN should be “1” to start PWM counter PS034404-0417 PRELIMINARY 157 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.PRD MPWM Period Register The PWM Period Register is a 16-bit register. MP0.PRD=0x4000400C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PERIOD 0x0002 RW 15 0 MP0.DUH PERIOD 16-bit PWM period. It should be larger than 0x0010 (If Duty is 0x0000, PWM will not work) MPWM Duty UH Register The PWM U channel duty register is a 16-bit register. MP0.DUH=0x4000_4010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY UH 0x0001 RW 15 0 PS034404-0417 DUTY UH 16-bit PWM Duty for UH output. It should be larger than 0x0001 (If Duty is 0x0000, PWM will not work) PRELIMINARY 158 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.DVH MPWM Duty VH Register The PWM V channel duty register is a 16-bit register. MP0.DVH=0x4000_4014 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY VH 0x0001 RW 15 0 DUTY VH 16-bit PWM Duty for VH output. It should be larger than 0x0001 (If Duty is 0x0000, PWM will not work) MP0.DWH MPWM Duty WH Register The PWM W channel duty register is a 16-bit register. MP0.DWH=0x4000_4018 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY WH 0x0001 RW 15 0 PS034404-0417 DUTY WH 16-bit PWM Duty for WH output. It should be larger than 0x0001 (If Duty is 0x0000, PWM will not work) PRELIMINARY 159 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.DUL MPWM Duty UL Register The PWM U channel duty register is a 16-bit register. MP0.DUL=0x4000_401C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY UL 0x0001 RW 15 0 MP0.DVL DUTY UL 16-bit PWM Duty for UL output. It should be larger than 0x0001 (If Duty is 0x0000, PWM will not work) MPWM Duty VL Register The PWM V channel duty register is a 16-bit register. MP0.DVL=0x4000_4020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY VL 0x0001 RW 15 0 PS034404-0417 DUTY VL 16-bit PWM Duty for VL output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) PRELIMINARY 160 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.DWL MPWM Duty WL Register The PWM W channel duty register is a 16-bit register. MP0.DWL=0x4000_4024 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DUTY WL 0x0001 RW 15 0 MP0.IER DUTY WL 16-bit PWM Duty for WL output. It should be larger than 0x0001 (if Duty is 0x0000, PWM will not work) MPWM Interrupt Enable Register The PWM Interrupt Enable Register is an 8-bit register. MP0.IER=0x4000_4034 7 6 5 4 3 2 1 0 PRDIEN BOTIEN WHIE VHIE UHIE WLIE VLIE ULIE 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW 7 PRDIEN PWM Counter Period Interrupt enable 0 1 6 BOTIEN PWM Counter Bottom Interrupt enable 0 1 5 4 3 2 1 0 PS034404-0417 interrupt disable interrupt enable interrupt disable interrupt enable WHIE ATR6IE WH Duty or ATR6 Match Interrupt enable VHIE ATR5IE VH Duty or ATR5 Match Interrupt enable UHIE ATR4IE UH Duty or ATR4 Match Interrupt enable WLIE ATR3IE WL Duty or ATR3 Match Interrupt enable VLIE ATR2IE VL Duty or ATR2 Match Interrupt enable ULIE ATR1IE UL Duty or ATR1 Match Interrupt enable 0 1 0 1 0 1 0 1 0 1 0 1 interrupt disable interrupt enable interrupt disable interrupt enable interrupt disable interrupt enable interrupt disable interrupt enable interrupt disable interrupt enable interrupt disable interrupt enable PRELIMINARY 161 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.IER[5:0] control bits are shared by duty match interrupt event and ADC trigger match interrupt event. When ADC trigger mode is disabled, the interrupt is generated by the duty match condition. In other cases, the interrupt is generated by the ADC trigger counter match condition. The ADC trigger mode is selected by the ATMOD bit field in the ATRm register. MP0.SR MPWM Status Register The PWM Status Register is a 16-bit register. MP0.SR=0x4000_4030 15 DOWN 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW Current PWM Count mode is Up 1 Current PWM Count mode is Down IRQCNT Interrupt count number of period match (Interval PRDIRQ mode) 7 PRDIF PWM Period Interrupt flag(write “1” to clear flag) No interrupt occurred Interrupt occurred PWM duty VL interrupt flag(write “1” to clear flag) (Duty interrupt is enabled if ATR2 was disabled) DVLIF ATR2F 0 1 0 No interrupt occurred Interrupt occurred PWM duty WL interrupt flag(write “1” to clear flag) (Duty interrupt is enabled if ATR3 was disabled) DWLIF ATR3F 0 1 1 No interrupt occurred Interrupt occurred PWM duty UH interrupt flag(write “1” to clear flag) (Duty interrupt is enabled if ATR4 was disabled) DUHIF ATR4F 0 1 2 No interrupt occurred Interrupt occurred PWM duty VH interrupt flag(write “1” to clear flag) (Duty interrupt is enabled if ATR5 was disabled) DVHIF ATR5F 0 1 3 No interrupt occurred Interrupt occurred PWM duty WH interrupt flag(write “1” to clear flag) (Duty interrupt is enabled if ATR6 was disabled) DWHIF ATR6F 0 1 4 No interrupt occurred Interrupt occurred PWM Bottom Interrupt flag(write “1” to clear flag) BOTIF 0 1 5 DULIF 0 DVLIF 0 14 12 6 ATR1F 1 ATR2F 2 0 0 1 No interrupt occurred Interrupt occurred PWM duty UL interrupt flag(write “1” to clear flag) (Duty interrupt is enabled if ATR1 was disabled) DULIF ATR1F 0 1 PS034404-0417 3 DWLIF 0 4 ATR3F 0 5 DUHIF 0 6 ATR4F 0 7 ATR5F 8 DVHIF RW 9 ATR6F RW 10 DWHIF 000 11 BOTIF 0 12 PRDIF 13 IRQCNT 14 DOWN 15 No interrupt occurred Interrupt occurred PRELIMINARY 162 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.SR[5:0] status bits are shared by the duty match interrupt event and the ADC trigger match interrupt event. When ADC trigger mode is disabled, the interrupt is generated by the duty match condition. In other cases, the interrupt is generated by the ADC trigger counter match condition. The ADC trigger mode is selected by the ATMOD bit field in the ATRm register. MP0.CNT MPWM Counter Register The PWM Counter register is a 16-bit Read-Only register. MP0.CNT=0x4000_4038 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 0x0000 RW CNT MP0.DTR PWM Counter Value MPWM Dead Time Register The PWM Dead Time register is a 16-bit register. PSHRT 0 0 13 12 11 10 9 0 0 0 0 0 RW 15 DTEN 8 PSHRT 0 PS034404-0417 DT 3 RW 2 1 0 Dead-time function enable 2-channel symmetric mode does not support dead time function. It should be disabled in 2 channel symmetric mode. Disable Dead-time function Enable Dead-time function Protect short condition This function is effective only for 2 channel symmetric mode. For 1 channel mode, never activated on both H-side and Lside at same time. L-side is always opposite of H-side. Enable output short protection function. (Turn off both output when both H-side and L-side are active.) Disable output short protection function. Dead-time prescaler 0 1 7 4 RW 1 DTCLK 5 0x00 0 8 6 0 0 1 14 7 DT 14 DTCLK 15 DTEN MP0.DTR=0x4000_403C Dead time counter uses PWM CLK/4 Dead time counter uses PWM CLK/16 Dead Time value (Dead time setting makes output delay of ‘low to high transition’ in normal polarity) 0x01 ~0xFF : Dead time PRELIMINARY 163 Motor Pulse Width Modulator Z32F0641 Product Specification Protect short condtion is only for internal PWM level, not for external PWM level. When the internal signal of H-side and L-side are the same high level, the protection short function operates to force both H-side and Lside to low level. MP0.PCR MPWM Protection 0,1 Control Register The PWM Protection Control register is a 16-bit register. MP0.PCR0=0x4000_4040,MP0.PCR1=0x4000_4048 5 4 3 2 1 0 ULPROTM 6 VLPROTM 7 WLPROTM 8 UHPROTM 9 VHPROTM 10 WHPROTM 11 PROTIE 12 PROTD 13 PROT0POL 14 PROT0EN 15 0 0 000 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW 15 PROT0EN Enable Protection Input 0 14 PROT0POL Select Protection Input Polarity 0: Low-Active 1: High-Active 10 8 PROTD Protection Input debounce 0 – no debounce 1~7 – debounce by (MPWMCLK * PROTD[2:0]) 7 PROTIE Protection Interrupt enable 0 1 5 WHPROTM Activate W-phase H-side protection output 0 1 4 VHPROTM UHPROTM WLPROTM VLPROTM ULPROTM Disable Protection Output Enable Protection Output with FOR value Activate U-phase L-side protection output 0 1 PS034404-0417 Disable Protection Output Enable Protection Output with FOR value Activate V-phase L-side protection output 0 1 0 Disable Protection Output Enable Protection Output with FOR value Activate W-phase L-side protection output 0 1 1 Disable Protection Output Enable Protection Output with FOR value Activate U-phase H-side protection output 0 1 2 Disable Protection Output Enable Protection Output with FOR value Activate V-phase H-side protection output 0 1 3 Disable protection interrupt Enable protection interrupt Disable Protection Output Enable Protection Output with FOR value PRELIMINARY 164 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.PSR MPWM Protection 0,1 Status Register The PWM Protection Status register is a 16-bit register. This register indicates which outputs are disabled. Users can set the output masks manually. When writing a value, if PROTKEY is not written, the written values are ignored. MP0.PSR0=0x4000_4044,MP0.PSR1=0x4000_404C 8 7 6 5 4 3 2 1 0 PROTKEY ULPROT 9 VLPROT 10 WLPROT 11 UHPROT 12 VHPROT 13 WHPROT 14 PROTIF 15 - 0 0 0 0 0 0 0 WO RC RW RW RW RW RW RW 15 8 PROTKEY Protection Clear Access Key To clear flags, write the key with protection flag (PSR0 key is 0xCA and PSR1 key is 0xAC) Writing without PROTKEY prohibited. 7 PROTIF Protection Interrupt status 0 1 5 WHPROT Activate W-phase H-side protection flag 0 1 4 VHPROT UHPROT WLPROT VLPROT ULPROT Protection not occurred. Protection occurred or protection output enabled Activate V-phase L-side protection flag 0 1 0 Protection not occurred. Protection occurred or protection output enabled Activate W-phase L-side protection flag 0 1 1 Protection not occurred. Protection occurred or protection output enabled Activate U-phase H-side protection flag 0 1 2 Protection not occurred. Protection occurred or protection output enabled Activate V-phase H-side protection flag 0 1 3 No Protection Interrupt Protection Interrupt occurred Protection not occurred. Protection occurred or protection output enabled Activate U-phase L-side protection flag 0 1 Protection not occurred. Protection occurred or protection output enabled If the PROTEN bit in MP.PCR register is enabled, on any asserting signal on the external protection pins, the PWM output is prohibited with output values defined in MP.FOLR register. Additionally, users can prohibit the output manually by writing the designated value into the MP.PSR register. PS034404-0417 PRELIMINARY 165 Motor Pulse Width Modulator Z32F0641 Product Specification MP0.ATRm MPWMn ADC Trigger Counter m Register MP0.ATR1 MPWM ADC Trigger Counter 1 Register MP0.ATR2 MPWM ADC Trigger Counter 2 Register MP0.ATR3 MPWM ADC Trigger Counter 3 Register MP0.ATR4 MPWM ADC Trigger Counter 4 Register MP0.ATR5 MPWM ADC Trigger Counter 5 Register MP0.ATR6 MPWM ADC Trigger Counter 6 Register The PWM ADC Trigger Counter register is a 32-bit register. MP0.ATR1=0x4000_4058 MP0.ATR2=0x4000_405C MP0.ATR3=0x4000_4060 MP0.ATR4=0x4000_4064 MP0.ATR5=0x4000_4068 MP0.ATR6=0x4000_406C 0 0 0 0 0 0 0 0 0 0 0 0 RW 0 PS034404-0417 19 ATUDT 17 16 ATMOD 15 0 ATCNT 0 9 8 7 ATMOD 18 17 16 15 14 13 12 11 10 ATCNT 0 0x0000 RW 19 ATUDT 31 30 29 28 27 26 25 24 23 22 21 20 RW 6 5 4 3 2 1 0 Trigger register update mode 0 ADC trigger value applied at period match event (at the same time with period and duty registers update) 1 Trigger register update mode When this bit set, written Trigger register values are sent to trigger compare block after two PWM clocks (through synchronization logic) ADC trigger Mode register 00 ADC trigger Disable 01 Trigger out when up count match 10 Trigger out when down count match 00 Trigger out when up-down count match ADC Trigger counter (it should be less than PWM period) PRELIMINARY 166 Z32F0641 Product Specification Motor Pulse Width Modulator Functional Description The MPWM includes 3 channels, each of which controls a pair of outputs. In normal PWM mode, each channel runs independently. Six PWM outputs can be generated. Each PWM output is built with various settings. Figure 15.3 shows the diagram for generating PWM. Figure 15.3. PWM Output Generation Chain Normal PWM UP Count Mode Timing In normal PWM mode, each channel runs independently. Six PWM outputs can be generated. An example of the waveform is shown in Figure 15.4. Before PSTART is activated, the PWM output stays at the default value L. When PSTART is enabled, the period counter starts up count up to the MP0.PRD count value. In the first period, the MPWM does not generate a PWM pulse. The PWM pulse is generated from the second period. The active level is derived at the start of the counter value during duty value time. PS034404-0417 PRELIMINARY 167 Z32F0641 Product Specification Motor Pulse Width Modulator Figure 15.4. UP Count Mode Waveform (MOTORB=1, UPDOWN=0) Normal PWM UP/DOWN Count Mode Timing The basic operation of UP/DOWN count mode is the same as UP count mode except the one period is twice that in UP count mode. The default active level is opposite in a pair PWM output. This output polarity can be controlled by the MP0.OLR register. Figure 15.5. UP/DOWN Count Mode Waveform (MOTORB=0, MCHMOD=0, UPDOWN=1) Motor PWM 2-Channel Symmetric Mode Timing The motor PWM operation has three types of operating modes – 2-channel symmetric mode, 1-channel symmetric mode, and 1-channel asymmetric mode. Figure 15.6 shows an example of a 2-channel symmetric mode waveform. PS034404-0417 PRELIMINARY 168 Z32F0641 Product Specification Motor Pulse Width Modulator Figure 15.6. 2-Channel Symmetric Mode Waveform (MOTORB=0,MCHMOD=00) The default start level of both H-side and L-side is low. For the H-side, PWM ouput level is changed to active level when the duty level is matched in up count period and is returned to the default level when the duty level is matched in down count period. The symmetrical feature appears in each channel which is controlled by the corresponding DUTY register value. Motor PWM 1-Channel Asymmetric Mode Timing The 1 channel asymmetric mode makes asymmetric duration pulses which are defined by the H-side and Lside DUTY register. Therefore, the L-side signal is always the negative signal of the H-side. During up count period, the H-side DUTY register matching condition generates the active level pulse and during down count period, the L-side DUTY register matiching condition generates the default level pulse. Figure 15.7. 1-Channel Asymmetric Mode Waveform (MOTORB=0,MCHMOD=01) PS034404-0417 PRELIMINARY 169 Z32F0641 Product Specification Motor Pulse Width Modulator The default start level of both H-side and L-side is low. For the H-side, PWM ouput level is changed to active level when the H-side duty level is matched in up count period and is returned to the default level when the Lside duty level is matched in down count period. When the PSTART is set, the L-side PWM output is changed to the active level, then the L-side PWM output is the inverse output of the H-side output. Motor PWM 1-Channel Symmetric Mode Timing The 1-channel symmetric mode generates a symmetric duration pulse which is defined by the H-side DUTY register. Therefore, the L-side signal is always the negative signal of H-side. During up count period, the Hside DUTY register matching condition generates the active level pulse and during down count period, the Hside DUTY register matiching condition also generates the default level pulse. Figure 15.8. 1-Channel Symmetric Mode Waveform (MOTORB=0,MCHMOD=10) The default start level of both H-side and L-side is low. For the H-side, PWM ouput level is changed to active level when the H-side duty level is matched in up count period and is returned to the default level when the Hside duty level is matched again in down count period. When the PSTART is set, the L-side pwm output is changed to the active level, then the L-side PWM output is the inverse output of H-side output. PWM Dead-Time Operation To prevent an external short condition, the MPWM provides a dead-time function. This function is only available in the Motor PWM mode. When either theH-side or L-side output changes to active level, an amount of dead-time is inserted if the DTEN.MP.DTR bit is enabled. The duration of dead-time is decided by the value in the DT.MP.DTR[7:0] field. When DTCLK = 0, the dead-time duration = DT[7:0] * (PWM clock period * 4) When DTCLK = 1, the dead-time duration = DT[7:0] * (PWM clock period * 16) When the PWM counter reaches the duty value, the PWM output is masked and the dead-time counter starts to run. When the dead-time counter reaches the value in the DT[7:0] register, the output mask is disabled. PS034404-0417 PRELIMINARY 170 Motor Pulse Width Modulator Z32F0641 Product Specification Figure 15.9 is an example of dead-time operation in 1 channel symmetric mode. MP.CNT MP.DUH/V/W MP.DTR MP0UH MP0VH MP0WH MP.DTR MP0UH MP0VH MP0WH Figure 15.9. PWM Dead-time Operation Timing Diagram (Symmetric Mode) Figure 15.10 displays an example of dead-time operation in 1-channel asymmetric mode. MP.CNT MP.DUL/V/W MP.DUH/V/W MP.DTR MP0UH MP0VH MP0WH MP.DTR MP0UH MP0VH MP0WH Figure 15.10. PWM Dead-Time Operation Timing Diagram (Asymmetric Mode) The dead-time function is not available for 2-channel symmetric mode. Therefore, the dead condition is generated by each channel’s duty control. MPWM Dead-time Timing Examples for Special Conditions Figure 15.11 shows the operation of dead-time. In normal dead-time, dead-time masking is activated at duty match time and the dead-time counter runs. When the dead-time counter reaches the dead time value, the mask is disabled. PS034404-0417 PRELIMINARY 171 Z32F0641 Product Specification Motor Pulse Width Modulator Figure 15.11. Normal Dead-Time Operation (TDUTY>TDT) The following figures display special-case scenarios of dead time configurations. MP.CNT 2 x TDUTY MP.PRD MP.DUH/V/W DT-Rising Mask DMP.CNT ng Mask MASKED MASKED TDT-Risng MP0UH MP0VH MP0WH TDT-Falling MP0UH MP0VH MP0WH Figure 15.12. Minimum H-Side Pulse Timing (TDUTY